JP2002353799A - Semiconductor integrated circuit and its drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that prevents malfunction and is operated at a high-speed even when the operating characteristics of the circuit are changed and to provide its drive method. SOLUTION: The semiconductor integrated circuit is provided with a flip-flop 14a, a combination logic circuit 16a, a combination logic circuit 16v, a clock signal generating circuit 20 and a malfunction detection circuit 15a, and the clock signal generating circuit 20 has a mechanism of generating a check signal Sch. The malfunction detection circuit 15a compares an input signal Sin1 to the flip-flop 14a with an output signal Sou1 from the flip-flop 14a, generates a malfunction signal Ser1 when the both differ from each other and delays the clock signal by one clock period. Thus, the malfunction of semiconductor integrated circuit is prevented and high-speed operations can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit and a method of driving the same, and more particularly to a semiconductor integrated circuit having a malfunction detector and a method of driving the same.

[0002]

2. Description of the Related Art In recent years, a large number of portable devices powered by batteries have become widespread, and semiconductor integrated circuits used in these devices have been required to have lower power consumption in order to extend the operation time of batteries. Is strongly required. Also,
The demand for higher performance of semiconductor integrated circuits that leads to improved functions of portable devices is increasing year by year.

[0003] The processing performance of a semiconductor integrated circuit depends on the operating frequency of a clock signal in a circuit designed to store data in a latch circuit in synchronization with the clock signal. That is, in order to improve the processing performance of the semiconductor integrated circuit, the operating frequency of the clock signal may be increased.

On the other hand, in order for the circuit to operate properly, the one with the largest delay time when data is transmitted between the latch circuits needs to be smaller than the clock cycle which is the reciprocal of the operating frequency. However, the setup time and the hold time of the latch circuit are not considered here.

However, the data transmission speed in a semiconductor integrated circuit varies depending on various factors. The main factors are changes in the temperature and power supply voltage of the semiconductor chip, and variations during manufacturing. In a normal design, a circuit is designed on the assumption that the variation in these characteristics is the worst.

In recent years, a method of mounting a temperature detecting function on a chip to change a clock cycle or a power supply voltage in accordance with the change, or a circuit for generating a maximum delay time between a latch circuit and a latch circuit. Create a circuit equivalent to
There has been proposed a configuration in which the operation speed of the circuit is detected and the power supply voltage is changed to a power supply voltage suitable for the clock cycle.

FIG. 9 is a block circuit diagram of a semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. 11-234113. In the figure, signal 1 is applied to combinational circuit 106a.
When the signals 09c and 109d are input, a signal 108a is output.
Is input to The internal clock 107 is also input to the flip-flop 105a.
The signal 110a is output from 05a. Next, when the signal 110a and the signal 109a are input to the combination circuit 106b, the signal 108b is output. Then, the signal 108b and the internal clock 1 are supplied to the flip-flop 105b.
When 07 is input, a signal 110b is output. The signal 110b and the signal 109b are combined with the combinational circuit 106.
c, the signal 108c is output, and the signal 108c and the internal clock 107 are output from the flip-flop 10c.
5c, the signal 110c is output. Next, when the signal 110c and the output clock 112 are input to the output device 111, the signal 113 is output.

Further, the clock 102 is used for the delay measuring device 10.
1, the clock correction signal 104 is output. When the clock correction signal 104 and the clock 102 are input to the clock correction device 103, the internal clock 107 and the output clock 112 are output.

According to the present invention, the delay of the combinational circuits 106a, 106b, and 106c designed in advance is determined by the delay measuring device 101, and the internal clock 107 suitable for the operation speed of the circuit based on the determination is used. Can work. As a result, malfunction of the circuit is prevented, the operation speed is increased, and the number of circuits is reduced. As a result, the manufacturing cost of the semiconductor device can be reduced. These conventional techniques can be used when the actual operating circuit environment can be inferred from an externally provided circuit.

[0010]

However, there are cases where the operating speed of a circuit varies with the history of the circuit and cannot be estimated from the outside. As an example, there is a case where a circuit is designed using a MOSFET using an SOI (Silicon on Insulator) substrate which has been developed in recent years. The SOI MOSFET is characterized in that the MOSFET is formed on a thick insulating film and the source and drain bottom surfaces are in contact with the insulating film, so that the junction capacitance is smaller than that of a normal bulk MOSFET. In addition, since the MOSFETs are completely insulated and separated from each other, there is an advantage that latch-up does not occur and higher integration can be achieved. FD (Fully-Dep) in which the region under the channel is completely depleted in SOI MOSFET
Let-type) and PD (Partially-Depleted) type where there is an area called body that is not depleted.
In the FET, the potential of the body region below the electrically floating channel changes during circuit operation, and the threshold voltage changes.
Therefore, the operation characteristics change depending on the operation history of the circuit up to that time.

In the conventional synchronous design, it is necessary to give the change width of the characteristic variation due to the operation history as a timing margin, and there is a problem that the operation speed is reduced.

As a prior art which can cope with this, there is a technique of detecting the stillness of the operation of the combinational logic circuit unit and generating the next clock (Japanese Patent Laid-Open No. 08-288822). However, in order to completely detect a quiescent state, it is necessary to attach a quiescent detection circuit to all internal nodes of the combinational logic circuit unit.

An object of the present invention is to provide a semiconductor integrated circuit whose operating speed is improved and power consumption is small even when there is an unpredictable variation in delay time from an external circuit, and a driving method thereof. .

[0014]

A semiconductor integrated circuit according to the present invention includes a clock generation circuit for generating a clock signal, a combinational logic circuit, and an output of the combinational logic circuit latched and output according to the clock signal. A latch circuit, which detects an input signal to the latch circuit and an output signal from the latch circuit when a check period, which is a fixed period, has elapsed since the clock signal was applied to the latch circuit, and a logical value of both signals was detected. And a malfunction detection circuit that outputs a malfunction signal if the two do not match, wherein the latch circuit latches the input signal again and outputs an output signal when the malfunction signal is output. ,
The clock signal generation circuit generates a clock signal at a fixed clock cycle when the malfunction signal is not output, and generates the clock signal after delaying the clock signal by the check period or more when the malfunction signal is output.

Thus, even if the delay time of the circuit becomes longer than the clock cycle, malfunction of the circuit can be prevented. In addition, the clock cycle can be set shorter than the latest time (maximum path delay time) among the times when the signal travels through the combinational logic circuit, so that the circuit can be operated at high speed.

Further, the clock signal generation circuit outputs the check signal with a delay of the check period from the clock signal for each clock cycle, so that each flip-flop reliably compares the input and the output at the same timing. Therefore, malfunction of the circuit can be reliably prevented.

When the output signal from the combinational logic circuit is latched by the latch circuit at the time of rising or falling of the clock signal, and when the clock signal transits in the opposite direction to when the latch circuit performs a latch operation. The malfunction detection circuit compares the input signal to the latch circuit with the output signal from the latch circuit, and outputs a malfunction signal if the logical values of both signals do not match, thereby generating a check signal. Since there is no need, the circuit configuration can be simplified, which leads to a reduction in manufacturing cost.

Further, in the semiconductor integrated circuit according to the present invention, if the frequency per time at which the malfunction signal is detected is higher than a certain malfunction upper limit frequency, the combinational logic circuit, the latch circuit, and the malfunction detection circuit can be used. A power supply having a function of increasing an operating voltage to be supplied and decreasing an operating voltage to be supplied to the combinational logic circuit, the latch circuit, and the malfunction detecting circuit if the frequency of the malfunction signal per time is lower than a certain malfunction lower limit frequency. A voltage control circuit is further provided.

As a result, an optimum power supply voltage can be set, so that power consumption can be effectively reduced. Since the power consumption of the circuit is proportional to the square of the power supply voltage, it is effective for power saving of a device using the semiconductor integrated circuit.

Further, in the semiconductor integrated circuit according to the present invention, if the frequency per time at which the malfunction signal is detected is higher than a certain malfunction upper limit frequency, the clock cycle is lengthened,
A clock cycle control circuit having a function of shortening the clock cycle if the frequency per time at which the malfunction signal is detected is smaller than a certain malfunction lower limit frequency.

As a result, the circuit can be operated at the optimum clock cycle, and malfunction of the circuit can be prevented. Further, since the circuit can be operated at an optimum clock cycle, the operation speed of the circuit can be improved.

A method for driving a semiconductor integrated circuit according to the present invention is a method for driving a semiconductor integrated circuit configured to transmit a signal between a first combinational circuit and a second combinational circuit via a latch circuit, Step (a) of outputting a clock signal having a fixed clock cycle from the clock signal generation circuit, and comparing the signal input to the latch circuit with the signal output from the latch circuit to determine whether the two signals are different. (B) outputting a malfunction signal;
In response to the malfunction signal, the latch circuit latches the signal from the first combinational circuit again, and
(C) outputting the clock signal to the combinational circuit after the above operation, and (d) outputting the clock signal after delaying the clock signal by a check period or more when the malfunction signal is output.

According to this method, malfunction of the circuit can be prevented even when the delay time of the circuit becomes longer than the clock cycle. In addition, the clock cycle can be set shorter than the latest time (maximum path delay time) of the time that the signal travels through the combinational logic circuit, so that the circuit can operate at high speed.

After the step (a) and before the step (b), the method further comprises a step (e) of outputting a check signal from the clock signal generation circuit with a delay of a check period from the clock signal. Input and output can be reliably compared at the same timing in each flip-flop, and malfunction of the circuit can be reliably prevented.

Before step (b),
An output signal from a combinational logic circuit is latched by the latch circuit at the time of rising or falling of the clock signal, and the clock signal transits in a direction opposite to that when the latch circuit performs a latch operation (e).
, It is not necessary to generate a check signal, so that the circuit configuration can be simplified, which leads to a reduction in manufacturing cost.

If the frequency of detection of the malfunction signal per time is higher than a certain malfunction upper limit frequency, the operating voltage supplied to the combinational logic circuit, the latch circuit and the malfunction detection circuit is increased, If the frequency of the malfunction signal per unit time is lower than the malfunction lower limit frequency, the method further includes the step (f) of reducing the operating voltage supplied to the combinational logic circuit, the latch circuit, and the malfunction detection circuit.

According to this method, the optimum power supply voltage can be set, so that the power consumption of the circuit can be effectively reduced. Since the power consumption of the circuit is proportional to the square of the power supply voltage, it is very effective for power saving of a device using the semiconductor integrated circuit.

Further, in the method of driving a semiconductor integrated circuit according to the present invention, the frequency per time at which the malfunction signal is detected is as follows:
The method further includes a step (g) of lengthening the clock cycle if the frequency is higher than a certain malfunction upper limit frequency, and shortening the clock cycle if the frequency per time at which the malfunction signal is detected is smaller than the certain malfunction lower limit frequency. It is.

According to this method, the circuit can be operated at the optimum clock cycle, so that the operation can be speeded up and the circuit can be prevented from malfunctioning.

[0030]

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram schematically showing a semiconductor integrated circuit according to the present embodiment. Referring to FIG. 1, reference numerals 14a and 14b denote flip-flops serving as latch circuits, 15a and 15b denote malfunction detection circuits, and 16a and 16b.
Is a combinational logic circuit, Ser1 and Ser2 are malfunction signals, 18 is a check signal line, 19 is a clock signal line, a check signal is Sch, a clock signal is Sck, 20 is a clock signal generation circuit, S1 is an input signal, and S2 is a combination circuit. Sin1 is an input signal to the flip-flop 14b, Sin1 is an input signal to the flip-flop 14b, and Sou1 is an input signal to the flip-flop 14b.
The output signal Sou2 from the flip-flop 14b
This is the output signal from.

In the semiconductor integrated circuit of this embodiment, a flip-flop 14a and a flip-flop 14b are arranged between a combinational logic circuit 16a and a combinational logic circuit 16b.
5a has the malfunction detection circuit 1 in the flip-flop 14b.
5b are respectively connected. Further, a first circuit composed of a flip-flop 14a and a malfunction detection circuit 15a
And the second circuit B composed of the flip-flop 14b and the malfunction detection circuit 15b have the same configuration. In the semiconductor integrated circuit of this embodiment, a plurality of similar circuits are connected in parallel. , Each of which is provided with a combinational logic circuit 16a, 16b and a clock generation circuit 20.
And are connected to each other.

The semiconductor integrated circuit of the present embodiment includes a malfunction detection circuit 15a in addition to the configuration of a normal synchronous circuit (flip-flop 14a, combination logic circuit 16a, combination logic circuit 16b, clock signal generation circuit 20, etc.). The clock signal generation circuit 20 outputs the check signal S
It also has a mechanism for generating channels. The malfunction detection circuit 15a outputs the input signal Sin to the flip-flop 14a.
1 and the output signal Sou1 are compared at the time of transition of the check signal Sch (here, at the time of rising transition), and when they are different from each other, a malfunction signal Ser1 is generated.

Next, the operation (driving method) of the semiconductor integrated circuit of this embodiment will be described with reference to the drawings. Hereinafter, the first circuit A including the flip-flop 14a and the malfunction detection circuit 15a will be described as an example.

FIGS. 2A and 2B are timing charts showing the operation of the semiconductor integrated circuit of this embodiment. As shown in the figure, the check signal Sch is a clock signal Sc.
It is generated later than k by the check period tc.

Here, the flip-flop 14a operates when the malfunction signal Ser1 is generated.
The function of re-storing the data of the input signal Sin1 to a and outputting the output signal Sou1 from the flip-flop 14a.

Further, the mechanism for generating the clock signal Sck and the check signal Sch is such that when the malfunction signal Ser1 is generated, both of the next generated pulse of the clock signal Sck and the pulse of the check signal Sch are compared with the normal period of the check period tc. Generated with a delay above. Here, it is delayed by one clock cycle.

Further, the delay time of the minimum delay path of the combinational logic circuit 16a is longer than the above-mentioned tc ("tc + clock skew + hold time of flip-flop 14a when clock skew and hold time are considered"). Shall be designed to be

As shown in FIG. 2A, when the maximum path delay time is shorter than the clock cycle, a clock signal is generated for each predetermined clock cycle as in a normal synchronous circuit.

On the other hand, as shown in FIG. 2B, when the maximum path delay time is longer than the clock cycle, first, the malfunction signal Ser1 changes from low (low voltage) to high (high voltage). Subsequently, after the input signal Sin1 to the flip-flop 14a is stored in the flip-flop 14a, the output signal Sou1 from the flip-flop 14a is output. Subsequently, pulses of the next clock signal 18 and check signal 19 are generated with a delay of one clock cycle.

As described above, in the semiconductor integrated circuit of the present embodiment, the clock cycle at normal time can be set shorter than the absolute maximum path delay time. It can operate at a higher speed than a conventional semiconductor integrated circuit that has been set long. Further, in the semiconductor integrated circuit of the present embodiment, even when a path delay longer than the clock cycle occurs and a timing shift occurs, a malfunction of the entire circuit can be avoided. However, if the maximum path delay time is longer than the clock period + the check period tc, it is difficult to avoid malfunction.

As described above, according to the semiconductor integrated circuit of the present embodiment, the operation speed can be improved as compared with the conventional semiconductor integrated circuit, and malfunction of the semiconductor integrated circuit can be suppressed. In particular, the above-described effect is remarkable in a circuit including an semiconductor device using SOI or the like as a substrate and in which the operation speed varies depending on the operation history.

In this embodiment, the flip-flop 1
Although the first circuit A including the first circuit 4a and the malfunction detection circuit 15a has been described as an example, other flip-flops such as the second circuit B connected in parallel with these circuits and the malfunction detection circuit are also described. The operation is similar to that of the loop 14a and the malfunction detection circuit 15a.

It is preferable that the malfunction detection circuit shown in this embodiment is connected only to a flip-flop circuit in which an input signal may arrive later than the clock cycle. That is, even if a signal transmitted through the combinational circuit connected to the input arrives as late as possible due to operation fluctuation, the malfunction detection device is not connected to the flip-flop arriving within the clock cycle from the beginning. This allows
The number of circuits can be reduced as compared with the case where a malfunction detection circuit is connected to all flip-flop circuits, and the manufacturing cost can be reduced.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
FIG. 3 is a block circuit diagram schematically showing a semiconductor integrated circuit according to the embodiment. As shown in the figure, the semiconductor integrated circuit of the present embodiment is configured by integrating a latch circuit and a malfunction detection circuit in the semiconductor integrated circuit of the first embodiment.

Referring to FIG. 14, reference numeral 14 denotes a flip-flop which is a latch circuit, 15 denotes a malfunction detection circuit, Ser denotes a malfunction signal, 18 denotes a check signal line, 19 denotes a clock signal line, a check signal is Sch, and a clock signal is Sck, 2
0 is a clock signal generation circuit, Sin is an input signal to the flip-flop, Sou is an output signal from the flip-flop, 25 is a CK master latch, 26 is a CH master latch, 27 is a slave latch, Clk is an external clock signal, and Che is An external check signal, ON is a clock generation signal, and 30 is a multiplexer.

The flip-flop 14 integrated with the malfunction detection circuit according to the present embodiment has two master latches (CK master latch 25 and CH master latch 26).
, One slave latch 27 and the malfunction detection circuit 15
And a multiplexer 30. The malfunction detection circuit 15 has a function of comparing the output signal from the CK master latch 25 and the output signal from the CH master latch 26 and, when they are different from each other, setting the malfunction signal Ser to high. It has a function of selecting one of an output signal from the master latch 25 and an output signal from the CH master latch 26.

The CK master latch 25 and the CH master latch 26 transmit a signal applied to the data input terminal to the output terminal when the enable signal is low, and hold the output data when the enable signal is high. Slave latch 27
Transmits the signal applied to the data input terminal to the output terminal when the enable signal is high, and holds the output data when the enable signal is low. When the clock signal Sck changes from low to high, the output signal from the CK master latch 25 is held, this output signal is transmitted to the input terminal of the slave latch 27, and the output signal Sou from the flip-flop is output. When the check signal Sch changes from low to high, the output signal from the CH master latch 26 is held.

Here, when the output signal from the CK master latch 25 and the output signal from the CH master latch 26 are the same, the malfunction signal Ser becomes low by the malfunction detection circuit 15, and the output signal of the CK master latch 25 becomes the slave latch. It is transmitted to 27 input terminals. When the output signal from the CK master latch 25 and the output signal from the CH master latch 26 are different from each other, the malfunction signal Ser changes to high by the malfunction detection circuit 15, and the output signal from the CH master latch 26 When input to the input terminal, an output signal from the flip-flop 14 is output.

In the clock signal generation circuit 20, when the malfunction signal Ser is high, the external check signal Che
Falls, the clock generation signal ON goes low, and even if the external clock signal Clk changes, both the clock signal Sck, which is the output signal from the clock generation circuit 20, and the check signal Sch remain low. When the check signal Sch becomes low, the malfunction signal Ser changes to low. Therefore, when the external check signal Che next changes from high to low, the clock generation signal ON in the clock signal generation circuit 20 becomes high, and the next clock signal and the pulse of the check signal are output. From the above,
The timing operation as shown in FIG. 2 can be performed.

With the above configuration, in the semiconductor integrated circuit of the present embodiment, the number of elements and the number of wirings constituting the semiconductor integrated circuit can be reduced as compared with the first embodiment. That is, a semiconductor integrated circuit can be manufactured at low cost.

Further, by including a latch circuit having a malfunction detection function in the standard cell library, it is possible to easily design a semiconductor integrated circuit having a malfunction detection function using a conventional logic synthesis and layout / wiring design technique. become able to.

It is preferable that the malfunction detection circuit shown in this embodiment is connected only to a flip-flop circuit in which an input signal may arrive later than the clock cycle. That is, even if a signal transmitted through the combinational circuit connected to the input arrives as late as possible due to operation fluctuation, the malfunction detection device is not connected to the flip-flop arriving within the clock cycle from the beginning. This allows
The number of circuits can be reduced as compared with the case where a malfunction detection circuit is connected to all flip-flop circuits, and the manufacturing cost can be reduced.

(Third Embodiment) FIG. 4 shows a third embodiment of the present invention.
FIG. 3 is a block circuit diagram schematically showing a semiconductor integrated circuit according to the embodiment.

Referring to FIG. 14, reference numerals 14a and 14b denote flip-flops as latch circuits, 15a and 15b denote malfunction detection circuits, 16a and 16b denote combinational logic circuits, and Se.
r1 and Ser2 are malfunction signals, 19 is a clock signal line,
20 is a clock signal generation circuit, S1 is an input signal, S2 is an output signal, Sin1 is an input signal input to the flip-flop 14a, Sin2 is an input signal input to the flip-flop 14b, and Sou1 is a flip-flop 14a.
And Sou2 is an output signal from the flip-flop 14b.

The semiconductor integrated circuit according to the present embodiment includes a malfunction detection circuit 15 in addition to the flip-flops 14a and 14b, the combination logic circuit 16a, the combination logic circuit 16b, and the clock signal generation circuit 20 which constitute a normal synchronous circuit. Further provisions. The first circuit A including the flip-flop 14a and the malfunction detection circuit 15a has the same configuration as the second circuit B including the flip-flop 14b and the malfunction detection circuit 15b. In the semiconductor integrated circuit of the embodiment, a plurality of similar circuits are arranged in parallel, and each of them is mutually connected to the combinational logic circuits 16a and 16b and the clock generation circuit 20.

Hereinafter, the first circuit A including the flip-flop 14a and the malfunction detection circuit 15a will be described as an example. The clock signal Sc is applied to the flip-flop 14a.
Data is stored when k rises and makes a transition. The malfunction detection circuit 15a compares the input signal Sin1 to the flip-flop 14a with the output signal Sou1 from the flip-flop 14a when the clock signal Sck makes a falling transition, and generates a malfunction signal Ser1 when the two are different from each other. . The clock signal generation circuit 20
Has a mechanism for generating a clock signal Sck.
The difference from the first embodiment is that the clock signal generation circuit 2
0 means that the check signal is not generated and the check signal is substituted at the falling edge of the clock signal Sck.

FIGS. 5A and 5B are timing charts for explaining the operation of the semiconductor integrated circuit according to the present embodiment.

As shown in FIG.
Is generated so as to perform a falling transition after a check period tc after performing a rising transition. The flip-flop 14a has a function of, when the malfunction signal Ser1 is generated, storing the data of the input signal Sin1 to the flip-flop 14a again and outputting the output signal Sou1. Further, when the malfunction signal Ser1 is generated, the mechanism for generating the clock signal Sck delays the pulse of the clock signal Sck to be generated next by a check period tc or more than normal. In this embodiment, it is delayed by one clock cycle.

The delay time of the minimum delay path of the combinational logic circuit 16a is longer than the above-described tc ("tc + clock skew + hold time of flip-flop 14a when clock skew and hold time are considered"). Shall be designed to be

In the semiconductor integrated circuit of the present embodiment, when the maximum path delay time is shorter than the clock cycle, the clock signal Sck is generated for each clock cycle determined in the same manner as in a normal synchronous circuit.

When the maximum path delay time becomes longer than the clock cycle, first, the malfunction signal Ser1 changes from low to high, and the input signal Sin to the flip-flop 14a is changed.
1 is stored again in the flip-flop 14a, and the output signal Sou1 is output. Then, the next clock signal S
The pulse of ck is generated with a delay of one clock cycle.

As described above, by setting the clock cycle at the normal time shorter than the absolute maximum path delay time, the circuit can be operated at a higher speed, and even if a timing shift occurs, the circuit malfunctions. Can be avoided. However, if the maximum path delay time is longer than the clock period + the check period tc, it is difficult to avoid malfunction.

Further, according to the configuration of the semiconductor integrated circuit of the present embodiment, since it is not necessary to generate a check signal, the number of wirings can be reduced as compared with the semiconductor integrated circuit of the first embodiment. That is, the manufacturing cost can be reduced as compared with the semiconductor integrated circuit of the first embodiment.

In this embodiment, the flip-flop 1
Although the first circuit A composed of the circuit 4a and the malfunction detection circuit 15a has been described as an example, other flip-flops and the malfunction detection circuit such as the second circuit B connected in parallel with these circuits are also described. It operates similarly to the flip-flop 14a and the malfunction detection circuit 15a.

It is preferable that the malfunction detection circuit shown in the present embodiment is connected only to a flip-flop circuit in which an input signal may arrive later than the clock cycle. That is, even if a signal transmitted through the combinational circuit connected to the input arrives as late as possible due to operation fluctuation, the malfunction detection device is not connected to the flip-flop arriving within the clock cycle from the beginning. This allows
The number of circuits can be reduced as compared with the case where a malfunction detection circuit is connected to all flip-flop circuits, and the manufacturing cost can be reduced.

(Fourth Embodiment) FIG. 6 shows a fourth embodiment of the present invention.
FIG. 3 is a block circuit diagram schematically showing a semiconductor integrated circuit according to the embodiment. As shown in the figure, the semiconductor integrated circuit of the present embodiment is configured by integrating a latch circuit and a malfunction detection circuit of the semiconductor integrated circuit of the third embodiment.

Referring to FIG. 14, 14 is a flip-flop which is a latch circuit, 15 is a malfunction detection circuit, Ser is a malfunction signal, 19 is a clock signal line, 20 is a clock signal generation circuit, and Sin is an input to the flip-flop. , Sou
Is the output of the flip-flop, Clk is the external clock signal, 30 is the multiplexer, 31 is the master latch,
32 is a CK slave latch, 33 is a CH slave latch, 34 is a toggle flip-flop, and ON is a clock generation signal.

In the semiconductor integrated circuit of this embodiment, the flip-flop 14 including the malfunction detection circuit 15
Master latches 31 and two slave latches (C
K slave latch 32, CH slave latch 33),
It comprises a multiplexer 30 and a malfunction detection circuit 15. The malfunction detection circuit 15 has a function of comparing the output signal from the CK slave latch 32 and the output signal from the CH slave latch 33, and setting the malfunction signal Ser to high if they differ from each other.
Has a function of selecting one of an output signal from the CK slave latch 32 and an output signal from the CH slave latch 33.

The master latch 31 transmits the signal input to the data input terminal to the output terminal when the enable signal is low, and holds the output data when the enable signal is high. CK slave latch 32 and CH
The slave latch 33 transmits a signal applied to the data input terminal to the output terminal when the enable signal is high, and holds the output signal when the enable signal is low. When the clock signal Sck changes from low to high, the output signal from the master latch 31 is held, transmitted to the input terminal of the CK slave latch 32, and the output signal Sou is output from the output terminal of the flip-flop.

When the clock signal Sck changes from high to low, the output signal from the CH slave latch 33 is held. At this time, the CK slave latch 32
If the output signal from the CK slave latch 33 is the same as the output signal from the CH slave latch 33, the malfunction detection circuit 15 turns the malfunction signal Ser to low, and the output signal from the CK slave latch 32 becomes the output signal Sou from the flip-flop 14.
Is output as

On the other hand, when the output signal from the CK slave latch 32 is different from the output signal from the CH slave latch 33, the malfunction detection circuit 15
Changes to high, and the output signal from the CH slave latch 33 is output as the output signal Sou from the flip-flop 14.

The clock generation signal ON output from the toggle flip-flop 34 in the clock signal generation circuit 20 is initialized to high. The toggle flip-flop 34 holds the output signal when the malfunction signal Ser is low, and inverts the output signal when the external clock signal Clk rises when the malfunction signal Ser is high. That is, when the malfunction signal Ser changes to high and the external clock signal Clk subsequently rises, the clock generation signal ON changes from high to low. This allows
Even if the external clock signal Clk changes, the clock signal Sck output from the clock generation circuit 20 remains low.

Next, when the external clock signal Clk rises, the malfunction signal Ser remains high, so that the output signal (clock generation signal ON) from the toggle flip-flop 34 changes from low to high again. And
The clock signal Sck rising from low to high is input to the flip-flop 14. At this time, the malfunction signal Se
r changes to low. Thus, the timing operation shown in FIG. 5 can be performed.

In the semiconductor integrated circuit of the present embodiment, the number of elements and the number of wirings constituting the semiconductor integrated circuit can be reduced as compared with the semiconductor integrated circuit of the third embodiment. That is, the manufacturing cost can be reduced as compared with the semiconductor integrated circuit of the third embodiment.

Also, by including a latch circuit having a malfunction detection function in the standard cell library, it is possible to easily design a semiconductor integrated circuit having a malfunction detection function using a conventional logic synthesis and layout / wiring design technique. become able to.

(Fifth Embodiment) FIG. 7 shows a fourth embodiment of the present invention.
FIG. 3 is a block circuit diagram schematically showing a semiconductor integrated circuit according to the embodiment. As shown in the figure, the semiconductor integrated circuit of the present embodiment is obtained by further adding a power supply voltage control circuit and a power supply circuit to the semiconductor integrated circuit of the first embodiment.

Referring to FIG. 14, reference numerals 14a and 14b denote flip-flops as latch circuits, 15a and 15b denote malfunction detection circuits, 16a and 16b denote combinational logic circuits, and Se.
r1 and Ser2 are malfunction signals, 18 is a check signal line,
19 is a clock signal line, 20 is a clock signal generation circuit,
S1 is an input signal, S2 is an output signal, Sin1 is an input signal to the flip-flop 14a, Sin2 is an input signal to the flip-flop 14b, Sou1 is an output signal from the flip-flop 14a, and Sou2 is a flip-flop 1
4b, an output signal from 4b, a power supply circuit 35, a power supply line 36,
37 is a power supply voltage control circuit. Further, a first circuit composed of a flip-flop 14a and a malfunction detection circuit 15a
And the second circuit B composed of the flip-flop 14b and the malfunction detection circuit 15b have the same configuration. In the semiconductor integrated circuit of this embodiment, a plurality of similar circuits are connected in parallel. And each is connected to the combinational logic circuits 16a and 16b and the clock signal generation circuit 20. Hereinafter, the first circuit A including the flip-flop 14a and the malfunction detection circuit 15a will be described as an example.

In the semiconductor integrated circuit of this embodiment, both the clock signal Sck and the malfunction signal Ser1 are input to the power supply voltage control circuit 37, and the number of pulses of the clock signal Sck and the malfunction signal Ser1 are measured.
Then, the power supply voltage control circuit 37 supplies the clock signal Sck
When the number of pulses per time reaches a certain number, if the number of pulses per time of the malfunction signal Ser1 exceeds a certain number (upper limit of malfunction), a control signal for increasing the power supply voltage is supplied to the power supply circuit 35. If it is less than a certain number of times (the lower limit of malfunction), a signal for increasing the power supply voltage is transmitted to the power supply circuit 35. Note that the power supply voltage used here means an operating voltage that actually flows through the circuit.

Thus, the circuit can be operated at an optimum power supply voltage. In a conventional semiconductor integrated circuit, it is necessary to set a higher power supply voltage in consideration of a variation in the maximum path delay time. However, in the semiconductor integrated circuit of the present embodiment, an optimum power supply voltage can be set. Therefore, power consumption can be effectively reduced. Since the power consumption of the circuit is proportional to the square of the power supply voltage, the semiconductor integrated circuit of the present invention is very effective for power saving of a device using the same.

The malfunction detection circuit shown in this embodiment is preferably connected only to a flip-flop circuit in which an input signal may arrive later than the clock cycle. That is, even if a signal transmitted through the combinational circuit connected to the input arrives as late as possible due to operation fluctuation, the malfunction detection device is not connected to the flip-flop arriving within the clock cycle from the beginning. This allows
The number of circuits can be reduced as compared with the case where a malfunction detection circuit is connected to all flip-flop circuits, and the manufacturing cost can be reduced.

In the semiconductor integrated circuit of this embodiment, the clock signal generation circuit has a function of generating a check signal. However, the clock signal generation circuit does not generate a check signal, and the clock signal falls. In this case, the input signal to the flip-flop may be compared with the output signal from the flip-flop.

(Sixth Embodiment) FIG. 8 shows a fifth embodiment of the present invention.
FIG. 3 is a block circuit diagram schematically showing a semiconductor integrated circuit according to the embodiment. As shown in the figure, the semiconductor integrated circuit of the present embodiment is obtained by further adding a clock cycle control circuit to the semiconductor integrated circuit of the first embodiment.

Referring to FIG. 14, reference numerals 14a and 14b denote flip-flops as latch circuits, 15a and 15b denote malfunction detection circuits, 16a and 16b denote combinational logic circuits, and Se.
r1 and Ser2 are malfunction signals, 18 is a check signal line,
19 is a clock signal line, 20 is a clock signal generation circuit,
S1 is an input signal, S2 is an output signal, Sin1 is an input signal to the flip-flop 14a, Sin2 is an input signal to the flip-flop 14b, Sou1 is an output signal from the flip-flop 14a, and Sou2 is a flip-flop 1
Reference numeral 38 denotes an output signal from 4b, which is a clock cycle control circuit. Here, in the semiconductor integrated circuit of the present embodiment,
Since the same circuit composed of a flip-flop and a malfunction detection circuit is arranged in parallel, the flip-flop 14a and the malfunction detection circuit 15a will be described below as an example.

In the semiconductor integrated circuit of this embodiment, both the clock signal Sck and the malfunction signal Ser1 are input to the clock cycle control circuit 38, and the clock signal Sck
And the number of pulses of the malfunction signal Ser1 are measured. The clock cycle control circuit 38 controls the clock signal Sck
When the number of pulses per time reaches a certain number of times and the number of pulses per time of the malfunction signal Ser1 exceeds a certain number (upper limit of malfunction), a control signal for lengthening the clock cycle is generated as a clock signal. The signal is transmitted to the circuit 20, and a signal for shortening the clock cycle is transmitted to the clock signal generation circuit 20 when the frequency is smaller than a certain number of times (the lower limit of malfunction).

Thus, the circuit can be operated at the optimum clock cycle. That is, the operation speed of the semiconductor integrated circuit of the present embodiment can be improved in accordance with the operation environment.

The malfunction detection circuit shown in this embodiment is preferably connected only to a flip-flop circuit to which an input signal may arrive later than the clock cycle. That is, even if a signal transmitted through the combinational circuit connected to the input arrives as late as possible due to operation fluctuation, the malfunction detection device is not connected to the flip-flop arriving within the clock cycle from the beginning. This allows
The number of circuits can be reduced as compared with the case where a malfunction detection circuit is connected to all flip-flop circuits, and the manufacturing cost can be reduced.

In the semiconductor integrated circuit of the present embodiment, the clock signal generation circuit has a function of generating a check signal. However, the clock signal generation circuit does not generate the check signal, and the clock signal falls. In this case, the input signal to the flip-flop may be compared with the output signal from the flip-flop.

Further, the semiconductor integrated circuit of the present embodiment may have a structure further including the above-described power supply circuit and power supply voltage control circuit.

As the structure of the clock cycle control circuit used in this embodiment, a structure using a ring oscillator can be considered. At this time, the clock period can be varied by controlling, for example, a voltage applied to the ring oscillator by a signal from the clock period control circuit.

[0091]

According to the semiconductor integrated circuit and the method of operation of the present invention, the provision of the malfunction detection circuit enables the operation speed of the circuit to be reduced even when there is an unpredictable fluctuation in the delay time from an external circuit. The power consumption of the semiconductor integrated circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram schematically showing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIGS. 2A and 2B are timing charts showing the operation of the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a block circuit diagram schematically showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a block circuit diagram schematically showing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIGS. 5A and 5B are timing charts for explaining the operation of the semiconductor integrated circuit according to the third embodiment of the present invention.

FIG. 6 is a block circuit diagram schematically showing a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 7 is a block circuit diagram schematically showing a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 8 is a block circuit diagram schematically showing a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 9 is a block circuit diagram schematically showing a conventional semiconductor integrated circuit.

[Explanation of symbols]

14, 14a, 14b Flip-flop 15, 15a, 15b Malfunction detection circuit 16a, b Combinational logic circuit 18 Check signal line 19 Clock signal line 20 Clock signal generation circuit 25 CK master latch 26 CH master latch 27 Slave latch 30 Multiplexer 31 Master latch 32 CK slave latch 33 CH slave latch 34 toggle flip-flop 35 power supply circuit 36 power supply line 37 power supply voltage control circuit 38 clock cycle control circuit ON clock generation signal S1 input signal S2 output signal Ser, Ser1, Ser2 malfunction signal Sin, Sin1, Sin2 Input signal to flip-flop Sou, Sou1, Sou2 Output signal from flip-flop Clk External clock signal Che External check signal Sch Check signal Sck clock signal

Claims (10)

[Claims] A clock generation circuit for generating a clock signal; a combinational logic circuit; a latch circuit for latching and outputting an output of the combinational logic circuit in accordance with the clock signal; and a clock signal added to the latch circuit. A malfunction that detects an input signal to the above-mentioned latch circuit and an output signal from the above-mentioned latch circuit when a check period which is a fixed period has elapsed since then, and outputs a malfunction signal if the logical values of both signals do not match. A semiconductor integrated circuit having a detection circuit, wherein the latch circuit outputs the malfunction signal.
The input signal is latched again and an output signal is output. The clock signal generation circuit generates a clock signal at a constant clock cycle when the malfunction signal is not output, and generates the clock signal when the malfunction signal is output. A semiconductor integrated circuit that is generated with a delay of more than the check period. 2. The semiconductor integrated circuit according to claim 1, wherein said clock signal generation circuit further outputs a check signal with a delay of a check period from a clock signal for each clock cycle. . 3. The semiconductor integrated circuit according to claim 1, wherein an output signal from said combinational logic circuit is latched by said latch circuit when said clock signal rises or falls, and said latch circuit performs a latch operation. When the clock signal makes a transition in the opposite direction to when the operation is performed, the malfunction detection circuit compares the input signal to the latch circuit with the output signal from the latch circuit, and if the logical values of both signals do not match, A semiconductor integrated circuit which outputs a malfunction signal. 4. The combinational logic circuit according to claim 1, wherein a frequency per time at which the malfunction signal is detected is higher than a certain malfunction upper limit frequency. The operating voltage supplied to the latch circuit and the malfunction detection circuit is increased, and if the frequency of the malfunction signal per time is lower than a certain malfunction lower limit frequency, the combination logic circuit, the latch circuit, the malfunction detection circuit, A semiconductor integrated circuit, further comprising a power supply voltage control circuit having a function of reducing an operation voltage supplied to the semiconductor integrated circuit. 5. The semiconductor integrated circuit according to claim 1, wherein the frequency of the malfunction signal per unit time is higher than a certain malfunction upper limit frequency. A semiconductor integrated circuit, further comprising a clock cycle control circuit having a function of shortening the clock cycle if the frequency per time at which the malfunction signal is detected is smaller than a certain malfunction lower limit frequency. 6. A method for driving a semiconductor integrated circuit configured to send a signal between a first combinational circuit and a second combinational circuit via a latch circuit, the method comprising the steps of: (A) outputting a clock signal having: and comparing a signal input to the latch circuit and a signal output from the latch circuit, and outputting a malfunction signal if both signals are different ( b) receiving the malfunction signal, causing the latch circuit to re-latch the signal from the first combinational circuit,
And (d) outputting the clock signal after a delay of at least a check period when the malfunction signal is output. 7. The method of driving a semiconductor integrated circuit according to claim 6, wherein after said step (a) and before said step (b), said clock signal generation circuit is delayed from said clock signal by a check period. A method for driving a semiconductor integrated circuit, further comprising a step (e) of outputting a check signal. 8. The method for driving a semiconductor integrated circuit according to claim 6, wherein before the step (b), when the clock signal rises or falls, the latch circuit is combined with a logic circuit. A method for driving a semiconductor integrated circuit, further comprising a step (e) in which an output signal is latched and the clock signal transits in a direction opposite to a direction in which the latch circuit performs a latch operation. 9. The method of driving a semiconductor integrated circuit according to claim 6, wherein a frequency per time at which the malfunction signal is detected is higher than a certain malfunction upper limit frequency. The operating voltage supplied to the logic circuit, the latch circuit, and the malfunction detection circuit is increased. If the frequency of the malfunction signal per time is lower than a certain malfunction lower limit frequency, the combination logic circuit, the latch circuit, and the malfunction detection are performed. A method for driving a semiconductor integrated circuit, further comprising the step (f) of lowering an operating voltage supplied to the circuit. 10. The driving method of a semiconductor integrated circuit according to claim 6, wherein a frequency per time at which the malfunction signal is detected is higher than a certain malfunction upper limit frequency. A method of driving a semiconductor integrated circuit, further comprising the step of: (g) increasing the clock cycle and shortening the clock cycle if the frequency per time at which the malfunction signal is detected is smaller than a certain malfunction lower limit frequency.