JP4712785B2 - Pulse modulator and D / A converter - Google Patents

Description

  The present invention relates to a pulse modulator that receives digital data and outputs a pulse signal, and a D / A converter using the pulse modulator.

  In various industrial fields such as optical equipment and motor control, D / A converters using pulse modulation such as pulse width modulation (PWM) and delta-sigma (ΔΣ) modulation are used from the viewpoint of low power consumption. It has been. Such a D / A converter generates, for example, a pulse signal in which the duty ratio and pulse density are adjusted in accordance with input digital data, performs amplification and offset adjustment on the pulse signal, and then transmits low-frequency transmission. By smoothing with a smoothing circuit such as a filter (Low Pass Filter, LPF), a desired analog signal is output.

  However, when PWM is used as the modulation method, if the resolution of the signal is increased without changing the reference clock frequency, the basic frequency of PWM is reduced, that is, the period is increased. As a result, in order to sufficiently smooth the pulse, the time constant of the LPF must be increased, and there is a problem that the response speed as the D / A converter becomes slow. On the other hand, when ΔΣ modulation is used, for example, a pulse signal including a high frequency component of several MHz to several tens of MHz is output. If the pulse signal contains a high-frequency component in this way, there is a problem that it is difficult to design a signal transmission path and to prevent noise.

  A pulse width modulator that solves the problems that occur when using such ΔΣ modulation is disclosed (see Patent Document 1). According to this pulse width modulator, the output of the pulse modulation signal generated by ΔΣ modulation (hereinafter referred to as ΔΣ output) is accumulated for a certain predetermined period, and the number of High states included in the accumulated period is obtained. A new pulse signal having a corresponding time width is generated and output. This reduces the frequency of a high-frequency pulse signal having a short time width as a pulse signal having a long time width, thereby reducing the generation of a high-frequency component that becomes a problem when ΔΣ modulation is used.

  FIG. 16 is a diagram illustrating an example of a pulse signal output from a conventional pulse width modulator. In FIG. 16, when the input digital data is 4 bits, “9” is input as the digital data, and the period for accumulating ΔΣ output is set to “8” with one system clock as a time unit. Is shown. As shown in FIG. 16, the ΔΣ output has four and five high states in periods T1 and T2, respectively, but the pulse width modulator is a pulse signal in which four high states are consecutive in period T1. In the period T2, a high-frequency component in the output pulse signal is reduced by outputting a pulse signal having five consecutive high states.

Japanese Patent Laid-Open No. 7-22861

  However, the above-described technique also has a problem that a high frequency component is generated in a pulse signal when the value of digital data is small. FIG. 17 is a diagram illustrating a pulse signal output when “1” is input as digital data to a conventional pulse width modulator. In FIG. 17 as well, the period in which the ΔΣ output is accumulated is “8”. As shown in FIG. 17, when “1” is input as digital data, the number of high states in the 4 bits is only 1, so that the number of pulses output in the period T3 is 0. Since the number is 1, only high-frequency components are generated because only the pulse signals with the number of High states being 1 are output even if accumulated within the period. Similarly, when “15”, which is the upper limit value, is input as digital data, the number of High states in 4 bits is 15. Therefore, a pulse including only one Low state in the periods T3 and T4. As a result, a high-frequency component is generated.

  The present invention has been made in view of the above, and an object of the present invention is to provide a pulse modulator and a D / A converter that can output a pulse signal with reduced high-frequency components.

  In order to solve the above-described problems and achieve the object, a pulse modulator according to the present invention receives digital data, delta-sigma modulates the digital data, and outputs a delta-sigma modulated signal; and Counting means for accepting the delta-sigma modulation signal and counting either the high state or the low state of the delta-sigma modulation signal, and when the number of the counted states reaches a set number, the count is performed by the set number. And a pulse conversion means having a pulse output means for outputting a pulse signal in a continuous state.

  Further, the pulse modulator according to the present invention receives delta-sigma modulation means for receiving digital data, delta-sigma modulating the digital data and outputting a delta-sigma modulation signal, and receiving the digital data and the delta-sigma modulation signal, When the digital data is greater than ½ of the upper limit value of the digital data, the Low state of the delta sigma modulation signal is counted, and when the digital data is less than ½ of the upper limit value, the delta sigma modulation signal Counting means for counting the high state of the output signal, and pulse output means for outputting a pulse signal in which the low state or the high state continues for the set number when the counted number of the low state or the high state reaches the set number. And a pulse conversion means.

  In the pulse modulator according to the present invention as set forth in the invention described above, the delta-sigma modulation means adds an offset value to the digital data and converts the digital data into digital data having a number of bits larger than the number of bits of the digital data. Conversion means is provided, wherein the converted digital data is delta-sigma-modulated with the number of bits after conversion, and the delta-sigma modulation signal is output.

  A D / A converter according to the present invention receives a pulse modulator according to any one of the above inventions and a pulse signal output from the pulse modulator, and smoothes the pulse signal to convert an analog signal. Smoothing means for outputting.

  According to the present invention, it is possible to realize a pulse modulator that can output a pulse signal with reduced high-frequency components.

  Hereinafter, embodiments of a pulse modulator and a D / A converter according to the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. Further, in the description of each embodiment, the same portions are denoted by the same reference numerals as appropriate, and the overlapping description is omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing an overall configuration of a D / A converter according to Embodiment 1 of the present invention. As shown in FIG. 1, the D / A converter 10 is an n-bit D / A converter where n is an integer of 2 or more, and includes a pulse modulator 1, an amplification / offset circuit 2, and an LPF 3. Is provided. The pulse modulator 1 includes a ΔΣ modulator 11 and a pulse converter 12.

  In this D / A converter 10, the pulse modulator 1 accepts input of n-bit digital data and outputs a predetermined pulse signal, and the amplifying / offset circuit 2 accepts input of the pulse signal, and amplifying circuit Amplifies the pulse signal and adjusts and outputs the offset of the pulse signal by the offset circuit, and the LPF 3 smoothes the amplified and offset-adjusted pulse signal and outputs an analog signal.

  Next, the ΔΣ modulator 11 and the pulse converter 12 will be described in detail. FIG. 2 is a block diagram showing a configuration of the ΔΣ modulator 11 shown in FIG. As shown in FIG. 2, the ΔΣ modulator 11 includes an n-bit adder 111 and a flip-flop circuit 112 connected to the adder 111. In the ΔΣ modulator 11, the adder 111 receives digital data input, adds the received digital data and the integrated value one clock before output from the flip-flop circuit 112, and outputs a carry of the added value. Is output as a ΔΣ modulation signal.

  FIG. 3 is a block diagram showing a configuration of the pulse converter 12 shown in FIG. As shown in FIG. 3, the pulse converter 12 includes a reception unit 121, a control unit 122, a storage unit 123, an integrated value counter 124, a pulse counter 125, and a pulse output unit 126.

  In this pulse converter 12, when the receiving unit 121 receives the ΔΣ modulation signal, the control unit 122 counts the High state of the ΔΣ modulation signal, and when the number of counted High states reaches the set number, the pulse output unit 126 , A pulse signal in which the high state continues for the set number is output.

  FIG. 4 is a diagram illustrating an example of a pulse signal output from the pulse converter 12 illustrated in FIG. FIG. 4 shows a case where the set number is “3” and “7” is input as digital data when the input digital data is 4 bits. FIG. 4 also shows an integrated value that is the number of High states counted by the integrated value counter 124 and a pulse counter value of the pulse counter 125. As shown in FIG. 4, when the High state of the ΔΣ modulation signal is input, the pulse converter 12 counts it and counts up the integrated value counter 124. When the integrated value reaches the set number “3”, the pulse counter 125 counts up until the pulse counter value reaches the set number, and the pulse output unit 126 outputs a high-level pulse signal. As a result, the pulse output unit 126 outputs a pulse signal having three consecutive high states. Therefore, the pulse signal output from the pulse converter 12 always has a set number of high states that are continuous. Therefore, by appropriately setting the set number, generation of high-frequency components is reduced.

  FIG. 5 is a diagram illustrating another example of the pulse signal output from the pulse converter 12 illustrated in FIG. 3. In FIG. 5, the set number is “3” and “1” is input as digital data. As shown in FIG. 5, even when “1”, which is a small value, is input as digital data, the pulse converter 12 is configured when the counted value in the high state reaches the set number “3”. Since a pulse signal having three consecutive high states is output, the generation of high-frequency components is reduced.

  The specific operation of the pulse converter 12 is not particularly limited, but an example thereof will be described below. FIG. 6 is a flowchart for explaining an example of a specific operation of the pulse converter 12 shown in FIG. First, the reception unit 121 receives a ΔΣ output (step S101). Next, the control unit 122 determines whether or not the ΔΣ output is in a high state. If the control unit 122 determines that the ΔΣ output is in a high state (step S102: Yes), the integrated value counter 124 is counted up (step S103). .

  Next, the control unit 122 reads the set number from the storage unit 123 and also reads the integrated value from the integrated value counter 124 to determine whether the integrated value matches the set number. If they match (step S104: Yes), the control unit 122 sets the integrated value of the integrated value counter 124 to zero (step S105), sets the pulse counter value of the pulse counter 125 to 1 (step S106), and outputs a pulse output unit. A high state pulse signal is output to 126 (step S107), and the process returns to step S101.

  On the other hand, when the integrated value does not match the set number (step S104: No), the control unit 122 reads the pulse counter value from the pulse counter 125, and determines whether the pulse counter value matches the set number. To do. If they match (step S108: Yes), the control unit 122 sets the pulse counter value of the pulse counter 125 to 0 (step S109), and causes the pulse output unit 126 to output a low state pulse signal (step S110). Return to step S101.

  On the other hand, when the pulse counter value does not match the set number (step S108: No), the control unit 122 determines whether the pulse counter value is zero. When the pulse counter value is zero (step S111: Yes), the control unit 122 sets the pulse counter value of the pulse counter 125 to 0 (step S109), and causes the pulse output unit 126 to output a low state pulse signal ( Step S110) and return to Step S101.

  On the other hand, when the pulse counter value is not zero (step S111: No), the control unit 122 counts up the pulse counter 125 (step S112), and causes the pulse output unit 126 to output a high state pulse signal (step S112). S107), the process returns to step S101. As described above, the pulse converter 12 operates according to the flowchart shown in FIG. 6, so that the pulse signals shown in FIGS. 4 and 5 can be output.

  As described above, according to the first embodiment, even when the value of the input digital data is small, the pulse modulator 1 can output a pulse signal with reduced high-frequency components. As a result, the D / A converter 10 can easily design a signal transmission path and take measures against noise, and can output an analog signal with reduced high-frequency components. The D / A converter 10 can be particularly suitably used for an apparatus that performs control mainly near the lower limit value of digital data.

  In the case of the conventional pulse width modulator, as shown in FIG. 16, the basic period of the pulse signal is fixed to a predetermined period to be accumulated, that is, a period of 8 clocks in the case of FIG. Therefore, in the output pulse signal, only a specific switching frequency corresponding to this period appears on the spectrum with a strong intensity, which is not preferable. However, in the case of the first embodiment, since the period is not fixed, for example, in the case of FIG. 4, the period of the pulse output seems to be a mixture of 9 clocks and 10 clocks. Since the fundamental period of the pulse signal is dispersed, a strong spectrum is not generated at a specific frequency, which is preferable.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. The D / A converter according to the second embodiment has the same configuration as the D / A converter according to the first embodiment, but the pulse converter operates differently depending on the value of the digital data. It is configured.

  FIG. 7 is a block diagram showing the overall configuration of the D / A converter according to the second embodiment. As shown in FIG. 2, the D / A converter 20 is an n-bit D / A converter, like the D / A converter 10, and includes a pulse modulator 4, an amplification / offset circuit 2, LPF3. The pulse modulator 4 includes a ΔΣ modulator 11 and a pulse converter 42.

  Similarly to the D / A converter 10, the D / A converter 20 also receives an input of n-bit digital data, the pulse modulator 4 outputs a predetermined pulse signal, and the amplification / offset circuit 2 The input of the pulse signal is accepted, the pulse signal is amplified and offset adjusted, and then output, and the LPF 3 smoothes the amplified and offset adjusted pulse signal and outputs an analog signal.

  However, unlike the D / A converter 10, the D / A converter 20 receives the input of digital data and performs different operations depending on the value of the digital data, as shown in FIG. To do.

  FIG. 8 is a block diagram showing a configuration of the pulse converter 42 shown in FIG. As shown in FIG. 8, the pulse converter 42 includes a reception unit 421, a control unit 422, a storage unit 123, an integrated value counter 124, a pulse counter 125, and a pulse output unit 126.

  In the pulse converter 42, the reception unit 421 receives a ΔΣ modulation signal and digital data. Then, the control unit 422 determines whether or not the received digital data is larger than ½ of the upper limit value of the digital data. If the received digital data is ½ or less, the ΔΣ modulation signal is the same as the pulse converter 12. When the high state is input, it is counted and the integrated value counter 124 is counted up. When the integrated value reaches the set number, the pulse counter 125 counts up until the pulse counter value reaches the set number, and the pulse output unit 126 outputs a high-state pulse signal.

  On the other hand, when the digital data is larger than ½ of the upper limit value, when the low state of the ΔΣ modulation signal is inputted, it is counted and the integrated value counter 124 is counted up. When the integrated value reaches the set number, the pulse counter 125 counts up until the pulse counter value reaches the set number, and the pulse output unit 126 outputs a low state pulse signal.

  Hereinafter, a case where the input digital data is 4 bits and the set number is “3” will be described as an example. In this case, the upper limit of digital data is 15. First, when “1” to “7” are input as digital data, since it is ½ or less of the upper limit value “15”, the pulse output unit 126 is high as in the case of the first embodiment. Outputs a pulse signal with a set number of consecutive states.

  On the other hand, when “8” to “15” are input as digital data, it is larger than ½ of the upper limit “15”, so the pulse output unit 126 outputs a pulse signal in which the Low state continues for the set number. Is output.

  FIG. 9 is a diagram showing an example of a pulse signal output from the pulse converter 42 shown in FIG. FIG. 8 shows a case where the set number is “3” and “15” is input as digital data. As shown in FIG. 9, in the case of “15” as digital data, the pulse converter 42 counts when the low state of the ΔΣ modulation signal is input, and counts up the integrated value counter 124. When the integrated value reaches the set number “3”, the pulse counter 125 counts up until the pulse counter value reaches the set number, and the pulse output unit 126 outputs a pulse signal in the low state. As a result, the pulse output unit 126 outputs a pulse signal having three consecutive Low states.

  In other words, the pulse converter 42 outputs a pulse signal having three consecutive high states when “1” to “7” are input as digital data, and when “8” to “15” are input. A pulse signal having three consecutive Low states is output. As a result, even if the digital data is small or close to the upper limit value, the set number of High or Low states are always continuous. Is reduced.

  The specific operation of the pulse converter 42 is not particularly limited, but an example thereof will be described below. FIG. 10 is a flowchart for explaining an example of a specific operation of the pulse converter 42 shown in FIG. First, the reception unit 421 receives digital data input and ΔΣ output (step S201). Next, the control unit 422 reads the upper limit value from the storage unit 123 and determines whether or not the digital data input value is greater than ½ of the upper limit value.

  If it is determined that the output is greater than ½ (step S202: Yes), it is determined whether the ΔΣ output is in a low state. If it is determined that the ΔΣ output is in a low state (step S203: Yes), The integrated value counter 124 is counted up (step S204).

  Next, the control unit 422 reads the set number from the storage unit 123 and also reads the integrated value from the integrated value counter 124 to determine whether the integrated value matches the set number. If they match (step S205: Yes), the control unit 422 sets the integrated value of the integrated value counter 124 to zero (step S206), sets the pulse counter value of the pulse counter 125 to 1 (step S207), and outputs a pulse output unit. The low state pulse signal is output to 126 (step S208), and the process returns to step S201.

  On the other hand, when the integrated value and the set number do not match (step S205: No), the control unit 422 reads the pulse counter value from the pulse counter 125 and determines whether the pulse counter value and the set number match. To do. If they match (step S209: Yes), the control unit 422 sets the pulse counter value of the pulse counter 125 to 0 (step S210), causes the pulse output unit 126 to output a high-state pulse signal (step S211), The process returns to step S201.

  On the other hand, when the pulse counter value does not match the set number (step S209: No), the control unit 422 determines whether the pulse counter value is zero. When the pulse counter value is zero (step S212: Yes), the control unit 422 sets the pulse counter value of the pulse counter 125 to 0 (step S210), and causes the pulse output unit 126 to output a high state pulse signal ( Step S211) and return to Step S201.

  On the other hand, when the pulse counter value is not zero (step S212: No), the control unit 422 counts up the pulse counter 125 (step S213), and causes the pulse output unit 126 to output a low-state pulse signal (step S213). S208), the process returns to step S201.

  On the other hand, when control unit 422 determines that the digital data input value is ½ or less of the upper limit value (step S202: No), the same operation as in the first embodiment is performed. That is, it is determined whether the ΔΣ output is in a high state. If it is determined that the ΔΣ output is in a high state (step S214: Yes), the integrated value counter 124 is incremented (step S215).

  Next, the control unit 422 reads the set number from the storage unit 123 and also reads the integrated value from the integrated value counter 124 to determine whether the integrated value matches the set number. If they match (step S216: Yes), the control unit 422 sets the integrated value of the integrated value counter 124 to zero (step S217), sets the pulse counter value of the pulse counter 125 to 1 (step S218), and outputs the pulse output unit. A high state pulse signal is output to 126 (step S219), and the process returns to step S201.

  On the other hand, when the integrated value does not match the set number (step S216: No), the control unit 422 reads the pulse counter value from the pulse counter 125 and determines whether the pulse counter value matches the set number. To do. If they match (step S220: Yes), the control unit 422 sets the pulse counter value of the pulse counter 125 to 0 (step S221), causes the pulse output unit 126 to output a low-state pulse signal (step S222), The process returns to step S201.

  On the other hand, when the pulse counter value does not match the set number (step S220: No), the control unit 422 determines whether the pulse counter value is zero. When the pulse counter value is zero (step S223: Yes), the control unit 422 sets the pulse counter value of the pulse counter 125 to 0 (step S221), and causes the pulse output unit 126 to output a low-state pulse signal ( Step S222) and return to step S201.

  On the other hand, when the pulse counter value is not zero (step S223: No), the control unit 422 further counts up the pulse counter 125 (step S224), and causes the pulse output unit 126 to output a high-state pulse signal. (Step S219), the process returns to Step S201.

  As described above, according to the second embodiment, the pulse modulator 4 generates a pulse signal without a high-frequency component regardless of whether the input digital data is small or the upper limit value is close to it. Can output. As a result, the D / A converter 20 can easily design a signal transmission path and take measures against noise, and output an analog signal with reduced high-frequency components. Furthermore, the period of the pulse signal is also dispersed.

(Embodiment 3)
Next, a third embodiment of the present invention will be described. The D / A converter according to the third embodiment has the same configuration as the D / A converter according to the first embodiment, but is configured to add an offset value to the digital data in the ΔΣ modulator. Yes.

  FIG. 11 is a block diagram showing the overall configuration of the D / A converter according to the third embodiment. As shown in FIG. 11, the D / A converter 30 is an n-bit D / A converter, like the D / A converters 10 and 20, and includes the pulse modulator 5 and the amplification / offset circuit 2. And LPF3, which accepts input of n-bit digital data and outputs an analog signal. The pulse modulator 5 includes a ΔΣ modulator 51 and a pulse converter 12.

  FIG. 12 is a block diagram showing a configuration of ΔΣ modulator 51 shown in FIG. As shown in FIG. 12, this ΔΣ modulator 51 includes an n + 1-bit adder 511, an n-bit adder 513, and a flip-flop circuit 512 connected to the adder 511. In this ΔΣ modulator 51, an adder 513 receives input of n-bit digital data and an n-bit offset value, adds the received offset value to the received digital data, and converts it into n + 1-bit digital data. Output. Next, the adder 511 receives the input of the n + 1-bit digital data output from the adder 513, adds the received digital data and the integrated value one clock before output from the flip-flop circuit 512, and adds The carry output of the value is output as a ΔΣ modulation signal.

  As described above, the ΔΣ modulator 51 adds an offset value to the input n-bit digital data to convert it to n + 1 bit digital data, ΔΣ modulates the converted digital data with n + 1 bits, and generates a ΔΣ modulation signal. Output. As a result, in the pulse signal output from the pulse converter 12, it is prevented that the high or low state continues excessively continuously, and the fundamental period of the pulse signal is prevented from becoming excessively large.

  This will be specifically described below. For example, in the case where the input digital data is 4 bits in the pulse modulator 1 according to the first embodiment, for example, when “1” is input as the digital data, as shown in FIG. Since the state may continue for 45 clocks continuously, the basic period of the pulse signal becomes long. If this basic period is too long compared to the time constant of LPF 3, the analog output of LPF 3 is not sufficiently smoothed and ripples remain. On the other hand, for example, when “15” is input as digital data, the pulse modulator 4 of the second embodiment continues to be in a high state for 45 clocks in the output pulse signal as shown in FIG. In some cases, a ripple may remain in the analog output of the LPF 3 as well.

  On the other hand, in the pulse modulator 5 of the third embodiment, assuming that the offset value is “8”, for example, when “1” is input as digital data, the adder 513 changes the input digital data to “9”. The signal is converted and output as a ΔΣ modulation signal by the adder 511 and the flip-flop circuit 512. In this case, the continuous High or Low state in the pulse signal to be output is 3 at the maximum, and therefore the basic period does not become long. Therefore, smoothing is sufficiently performed by the LPF 3, and an analog output with suppressed ripples can be realized.

  That is, in the third embodiment, the offset value is added to the input digital data and converted into digital data having a larger number of bits. Therefore, even if the input digital data is the upper limit or lower limit of the possible values, After being converted into digital data having a larger number of bits, the value becomes far from the upper limit or lower limit of the possible values. As a result, the same state is prevented from continuing in the pulse signal to be output.

(Embodiment 4)
In the third embodiment, the pulse converter 12 may be replaced with the pulse converter 42 in the second embodiment. FIG. 13 is a block diagram showing an overall configuration of a D / A converter according to Embodiment 4 of the present invention. As shown in FIG. 13, the D / A converter 40 includes a pulse modulator 6, an amplification / offset circuit 2, and an LPF 3. The pulse modulator 6 includes a ΔΣ modulator 51, and a pulse converter. Instrument 42. As with the third embodiment, this D / A converter 40 can also realize an analog output with suppressed ripples.

  Here, FIG. 14 shows the relationship between the input value of the digital data and the maximum value of the continuous state of High or Low in the pulse signal output from the pulse modulator in the D / A converters according to the first and second embodiments. FIG. FIG. 14 shows a case where the set number is “3” when the input digital data is 4 bits. As shown in FIG. 14, in any of the first and second embodiments, especially when the digital data is 1 and the upper limit is 15, the continuous state may continue for a maximum of 45 clocks.

  On the other hand, FIG. 15 shows a digital signal input value, an input value obtained by adding an offset value, and a high or low signal in the pulse signal output from the pulse modulator in the D / A converter according to the third and fourth embodiments. It is a figure which shows the relationship with the maximum value of a continuous state. In the case of FIG. 15 as well, when the input digital data is 4 bits, the set number is “3”. As shown in FIG. 15, in any of the third and fourth embodiments, the maximum continuous state is 8 clocks and does not become excessively long with respect to the set number “3”.

  As a modification of the above-described first embodiment, the configuration of the pulse converter is configured such that the reception unit receives the ΔΣ modulation signal, the control unit counts the low state of the ΔΣ modulation signal, and sets the number of counted low states. When the number reaches the number, the pulse output unit may output a pulse signal in which the Low state continues for the set number, and the rest may be configured similarly to the D / A converter 10 according to the first embodiment. According to the D / A converter having the configuration of this modification, the output pulse signal is always set even when the input digital data is at or near the upper limit value, as in the second embodiment. Since the number of Low states is continuous, it is possible to output a pulse signal having no high frequency component. The D / A converter can be particularly preferably used for an apparatus that performs control mainly near the upper limit value of digital data.

  In the above embodiment, the case where the digital data is 4 bits has been described, but the number of bits is not particularly limited. Although the number of settings is set to “3”, it is not particularly limited. For example, it is optimized according to the time constant of the LPF to be used, the required response time, the required characteristics of the analog signal to be output, etc. It can be set appropriately. Further, the offset value set in the third and fourth embodiments can be set as appropriate according to the required characteristics of the analog signal to be output, the circuit characteristics of the amplification / offset circuit, etc., but can take, for example, n-bit digital data. It is preferable to be in the vicinity of the median value.

It is a block diagram which shows the whole structure of the D / A converter which concerns on Embodiment 1 of this invention. FIG. 2 is a block diagram illustrating a configuration of a ΔΣ modulator illustrated in FIG. 1. It is a block diagram which shows the structure of the pulse converter shown in FIG. It is a figure which shows an example of the pulse signal which the pulse converter shown in FIG. 3 outputs. It is a figure which shows another example of the pulse signal which the pulse converter shown in FIG. 3 outputs. It is a flowchart explaining an example of the specific operation | movement of the pulse converter shown in FIG. It is a block diagram which shows the whole structure of the D / A converter which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the pulse converter shown in FIG. It is a figure which shows an example of the pulse signal which the pulse converter shown in FIG. 8 outputs. It is a flowchart explaining an example of the specific operation | movement of the pulse converter shown in FIG. It is a block diagram which shows the whole structure of the D / A converter which concerns on Embodiment 3 of this invention. FIG. 12 is a block diagram illustrating a configuration of a ΔΣ modulator illustrated in FIG. 11. It is a block diagram which shows the whole structure of the D / A converter which concerns on Embodiment 4 of this invention. In the D / A converter which concerns on Embodiment 1, 2, it is a figure which shows the relationship between the input value of digital data, and the maximum value of the continuous state of High or Low in the pulse signal which a pulse modulator outputs. In the D / A converter according to the third and fourth embodiments, the input value of the digital data, the input value obtained by adding the offset value, and the maximum value of the continuous state of High or Low in the pulse signal output from the pulse modulator It is a figure which shows the relationship. It is a figure which shows an example of the pulse signal which the conventional pulse width modulator outputs. It is a figure which shows the pulse signal output when "1" is input as digital data to the conventional pulse width modulator.

Explanation of symbols

1, 4-6 Pulse modulator 2 Amplification / offset circuit 3 LPF
4 Pulse modulator 10 to 40 D / A converter 11, 51 ΔΣ modulator 12, 42 Pulse converter 111, 511, 513 Adder 112, 512 Flip-flop circuit 121, 421 Receiving unit 122, 422 Control unit 123 Storage unit 124 Integrated value counter 125 Pulse counter 126 Pulse output section

Claims (4)

Delta-sigma modulation means for receiving digital data, delta-sigma modulating the digital data and outputting a delta-sigma modulated signal;
When the delta sigma modulation signal is received and counting means for counting either the high state or the low state of the delta sigma modulation signal, and when the number of the counted states reaches a set number that is an integer of 2 or more Pulse conversion means having pulse output means for outputting a pulse signal in which the counted state is continuous by the set number;
A pulse modulator comprising: Delta-sigma modulation means for receiving digital data, delta-sigma modulating the digital data and outputting a delta-sigma modulated signal;
The digital data and the delta sigma modulation signal are received, and when the digital data is larger than half of the upper limit value of the digital data, the low state of the delta sigma modulation signal is counted, and the digital data is equal to the upper limit value. In the case of ½ or less, the counting means for counting the high state of the delta-sigma modulation signal, and the set number when the number of the counted low state or high state reaches a set number that is an integer of 2 or more. Pulse conversion means having pulse output means for outputting a pulse signal in which the counted Low state or High state is continuous;
A pulse modulator comprising:   The delta-sigma modulation means includes conversion means for adding an offset value to the digital data and converting the digital data into digital data having a number of bits larger than the number of bits of the digital data, and the number of bits after conversion of the converted digital data 3. The pulse modulator according to claim 1, wherein the delta-sigma modulation is performed at, and the delta-sigma modulation signal is output. 4. A pulse modulator according to any one of claims 1 to 3,
Smoothing means for receiving a pulse signal output from the pulse modulator, smoothing the pulse signal and outputting an analog signal;
A D / A converter characterized by comprising:

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