JP4711015B2 - Image processing apparatus and image processing system - Google Patents

Description

  The present invention relates to an image processing apparatus and an image processing system used for appearance inspection measurement of an inspection object such as a product in a production line, for example.

  The appearance inspection measurement includes appearance inspection, measurement of dimensions, shape, position, etc., scratch crack inspection, character inspection, etc .. In many cases, it is necessary to output a non-defective product image or a defective product image to be inspected from the image processing apparatus. When the image data needs to be output, for example, when the difference between the reference product for determination and the actual inspection object is a slight difference due to manufacturing error, etc. If it is necessary to investigate what kind of image processing resulted in the judgment result of a defective product if it should be judged as a defective product, what kind of image processing should be used for the previous settings, for example, For example, it may be necessary to investigate whether the product is non-defective.

  However, in manufacturing, it is necessary to ensure productivity that exceeds a certain fixed level. However, the quality of the appearance inspection measurement by image processing is good or bad. If the image processing is stopped or delayed in order to obtain the product, the series of operations for producing the product to be inspected will be delayed, and the overall production efficiency will be reduced. As a result, the productivity above the certain level will be ensured. I can't.

  For this reason, a mechanism for outputting image data used for image processing without stopping or delaying image processing during manufacturing is desired. For outputting image data, for example, a configuration in which data is written and output to a storage medium such as an SD card in a form that can be read by a personal computer (personal computer) or a configuration in which it is transmitted to a personal computer via a communication interface may be used. Further, it is desirable to be able to simultaneously output various corresponding parameters and results of appearance inspection measurement when outputting image data. In this way, without stopping or delaying image processing during manufacturing, the image data used for image processing can be taken out and analyzed in parallel with the manufacturing while analyzing the contents of the image processing on another computer. Or confirm.

  Patent Document 1 discloses an electronic component that can perform an appearance inspection of an electronic component with a high tact time by alternately capturing and storing image data obtained by imaging in a predetermined storage area every time the component changes. An appearance inspection apparatus is disclosed.

JP-A-10-78308

  However, since the amount of information of the image data is large and it takes a long time to output the image data, the analysis or confirmation of the contents of the image processing is hindered. Therefore, it is not easy to provide the above mechanism.

  Since the mechanical tact cycle of the production line using the image processing apparatus is increasing year by year, it is necessary to execute image processing at high speed in accordance with this. When the type of the imaging device connected to the image processing device is, for example, a standard camera, a double-speed camera, or a megapixel camera, the imaging cycles are 33.3 ms (30 frames / second) and 16.7 ms (60 frames), respectively. / Second) or 66.7 ms (15 frames / second). Therefore, in order to perform appearance inspection measurement without dropping frames, image processing must be executed at a speed higher than the above imaging cycle. Therefore, it is necessary to output image data so as not to prevent such high-speed image processing. There is.

  In the case of a standard camera, a double-speed camera, or a megapixel camera, the information amount of image data to be output is about 256 Kbytes (when the number of pixels of one image is 512 × 480 pixels) and about 256 Kbytes (image When the number of pixels of one image is 512 × 480 pixels) or about 1 Mbyte (when the number of pixels of one image is 1024 × 960 pixels). In recent years, due to the miniaturization and refinement of inspection targets, high-precision image processing is required and the number of pixels of the imaging device tends to increase, and along with this, the image data handled by the image processing device also tends to increase. is there.

  In the conventional image processing apparatus, when storing image data, a high-speed memory such as SRAM (Static RAM) is used from the viewpoint of storage time. In the SRAM, image data is usually stored by a CPU (Central Processing Unit) that performs image processing. However, since the SRAM has a relatively small capacity of about several tens of MB, the large image as described above is used. In the case of data, only a few to tens of sheets can be stored. Since the RAM is volatile, the stored image data is erased when the power is turned off unless a backup power source such as a battery is used.

  In addition, some conventional image processing apparatuses are equipped with a non-volatile memory other than a RAM in order to store more image data. Recently, small and low-priced large-capacity flash ROMs such as SD cards, compact flash (registered trademark), and memory sticks have become widespread, and many of them can be backed up by using them as image data storage media. It can be held without power.

  However, this type of storage medium has a problem of storage time due to the nature of the element. For example, in the case of an SD card, it takes 2.9 seconds or 12.4 seconds to store image data of 512 × 480 images (about 256 Kbytes) or 1024 × 960 images (about 1 Mbytes), respectively. Thus, when the storage time is in seconds, if the CPU that performs image processing stores image data, the storage time greatly exceeds the imaging cycle, so that image processing stops each time image data is stored. become. In addition, image data that occurs in the process that is important for knowing the processing contents of the image processing process (for example, the differential image obtained in the process of detecting the edge position, etc., specified before the determination for the original image) It is even more difficult to store an image in the middle of the image processing, data derived in the middle of the processing, and the like.

  Even in a multiprocessor configuration in which multiple processes are performed using a common storage device (shared memory), each CPU cannot access the shared memory at the same time, and it is necessary to use the shared memory in a time-sharing manner. As a result, the image processing is delayed.

  The present invention has been made in view of the above circumstances, and provides an image processing apparatus and an image processing system capable of outputting image data used for image processing without stopping or delaying image processing. The purpose is to do.

An image processing apparatus according to a first aspect of the present invention for solving the above-described problem is an image input interface for obtaining image data from at least one image pickup apparatus that picks up an image of an inspection object, and an image obtained by the image input interface A first image memory that captures and stores data, the first central processing unit connected to the first image memory, and the image input interface so that the image data stored in the first image memory can be read out. A second image memory for taking in and storing the received image data, a second central processing unit connected to the second image memory so that the image data stored in the second image memory can be read out, and the first image memory An inter-central processing unit communication unit that is interposed between the central processing unit and the second central processing unit and transfers information exchanged between them; The first image memory and the second image memory are disposed between the image input interface and the first central processing unit and the second central processing unit, respectively, and the first central processing unit image processing line visual inspection measurement of said object by executing Utotomoni, the course of or after the result of the image processing performing predetermined determination using the image data stored in the first image memory, said When instructing the second central processing unit to output the image data stored in the second image memory corresponding to the image data stored in the first image memory according to the determination result , the central processing While the output instruction data is transmitted to the second central processing unit by message communication via the inter-device communication unit, the second central processing unit transmits the central processing unit. If via the inter-device communication unit receives the output instruction data from said first central processing unit, and executes the output processing of the image data stored in the second image memory.

The invention according to claim 2 is the image processing apparatus according to claim 1, further comprising first and second gate arrays connected to an output of the image input interface, wherein the first image memory is the image input interface. which is connected via a first gate array, under the control of the first gate array, stores captures image data obtained by the image input interface, the first central processing equipment, said first Under the control of the gate array, the image data stored in the first image memory is readable and connected to the first image memory via the first gate array, and the second image memory is connected to the image input. An image obtained by the image input interface is connected to the interface through the second gate array and is controlled by the second gate array. Storing captures data, the second central processing equipment is under control of the second gate array, freely reads the image data stored in said second image memory, via said second gate array It is connected to the second image memory.

  According to a third aspect of the present invention, in the image processing apparatus according to the second aspect, each of the first and second image memories has a storage area for image data for a plurality of frames, and the first and second gate arrays. Each of the storage areas in the first and second image memories has a storage area for image data of one frame as a storage area for image data of the current frame, and the storage area is obtained by the image input interface. In addition to performing control for storing image data, when temporarily storing the storage state of the image data stored in the storage area, image data for another frame in the storage area in the first and second image memories. Storage area of the current frame image data, and the storage area stores image data obtained by the image input interface. And performing control to store.

  According to a fourth aspect of the present invention, in the image processing apparatus according to any one of the first to third aspects, a communication interface for communicating with an external computer is further provided on the second central processing unit side. The first central processing unit transmits image processing status data including at least one of various parameters necessary for the image processing and the image processing result to the second central processing unit side via the communication unit between the central processing units. The second central processing unit transmits the image processing status data from the first central processing unit together with the corresponding image data to the external computer via the communication interface as the output processing. And

  According to a fifth aspect of the present invention, there is provided the image processing apparatus according to any one of the first to third aspects, wherein the image data stored in the second image memory is written and output to a removable storage medium. An apparatus further connected to the second central processing unit side, and the first central processing unit transmits various parameters necessary for the image processing and the results of the image processing via the communication unit between the central processing units. Image processing status data including at least one is transmitted to the second central processing unit, and the second central processing unit outputs the image processing status from the first central processing unit via the storage device as the output process. The data is written and output to the storage medium together with the corresponding image data.

The invention according to claim 6, wherein, in the image processing apparatus according to claim 5, wherein said second image memory is further connected to the read and write freely the second central processing equipment of the image data, the second central processing The apparatus reads the image data written in the storage medium to the second image memory via the storage device, and the first central processing unit is read from the storage medium to the second image memory. The image processing is performed again using the image data.

Invention of claim 7, wherein, in the image processing apparatus according to any one of claims 4-6, wherein the first central processing unit, according to the result of the determination, through the inter-CPU communication unit The image processing status data is transmitted to the second central processing unit, and image data corresponding to the image processing status data is designated.

The invention according to claim 8 is the image processing apparatus according to claim 1 or 7, wherein the predetermined determination is a determination as to whether or not a predetermined number of defect determination results have continued in the image processing, and a defect determination rate is It is a quality determination including at least one determination of whether or not a predetermined rate has been exceeded and whether or not a predetermined abnormality has occurred.

According to a ninth aspect of the present invention, in the image processing apparatus according to the first or seventh aspect, the predetermined determination is a determination as to whether or not a determination result of a non-defective product for at least one determination item has occurred at a predetermined rate. It is characterized by that.

  According to a tenth aspect of the present invention, in the image processing apparatus according to the eighth or ninth aspect, the reference for the determination is input from the external computer or an external device.

  An image processing system according to an eleventh aspect of the present invention is the image processing apparatus according to any one of the fourth to tenth aspects, and an external computer having a communication interface corresponding to the communication interface provided in the image processing apparatus. The external computer includes image processing status data and image data obtained from the image processing device via a communication interface of the external computer, and image processing similar to image processing by the first central processing unit. By performing the above, a simulation of the appearance inspection measurement of the inspection object is performed.

  According to a twelfth aspect of the present invention, in the image processing system according to the eleventh aspect, when the external computer needs to change at least one of various parameters included in the image processing status data, the parameter is set. The simulation is performed again and the simulation is performed again. When an optimal image processing result is obtained by the simulation, data including the parameter that is the optimal image processing result is transmitted to the image processing apparatus.

As is apparent from the above, the image processing apparatus according to the first aspect of the present invention is obtained by an image input interface that obtains image data from at least one image pickup apparatus that picks up an image of an inspection object, and the image input interface. A first image memory that captures and stores the received image data, a first central processing unit connected to the first image memory so that the image data stored in the first image memory can be read, and the image input interface. A second image memory that captures and stores the image data obtained in step 2; a second central processing unit connected to the second image memory so that the image data stored in the second image memory can be read; An inter-central processing unit communication unit that is interposed between the first central processing unit and the second central processing unit and transfers information exchanged between them; The first image memory and the second image memory are disposed between the image input interface and the first central processing unit and the second central processing unit, respectively, image processing line visual inspection measurement of said object by executing Utotomoni, the course of or after the result of the image processing performing predetermined determination using the image data stored in the first image memory And instructing the second central processing unit to output the image data stored in the second image memory corresponding to the image data stored in the first image memory according to the determination result , While transmitting the output instruction data to the second central processing unit by message communication via the central processing unit communication unit, the second central processing unit, When the output instruction data is received from the first central processing unit via the central processing unit communication unit, the output processing of the image data stored in the second image memory is executed. For example, an input device is used. When the second central processing unit performs the output process of the image data stored in the second image memory in accordance with the output instruction of the image data input from the second image memory, the image data output process from the second image memory Since the first central processing unit is completely released, for example, the first central processing unit stores the information in the first image memory with respect to the second central processing unit by transferring information via the communication unit between the central processing units. Even when an instruction to output image data stored in the second image memory corresponding to the received image data is given, the load applied to the first central processing unit includes communication instruction data including output instruction data of about several bytes. Since only the message transmission process is required, the image data used for the image process can be output without stopping or delaying the image process. In addition, with the increase in the capacity of image data, it is possible to solve the problem of a decrease in overall image processing capability due to the storage speed or time of a storage medium used as a measure for lack of capacity such as SRAM. Furthermore, since it is possible to cope with the delay in outputting image data and to output more information than before, it is possible to output an image in the middle of image processing.

The invention according to claim 2 is the image processing apparatus according to claim 1, further comprising first and second gate arrays connected to an output of the image input interface, wherein the first image memory is the image input interface. which is connected via a first gate array, under the control of the first gate array, stores captures image data obtained by the image input interface, the first central processing equipment, said first Under the control of the gate array, the image data stored in the first image memory is readable and connected to the first image memory via the first gate array, and the second image memory is connected to the image input. An image obtained by the image input interface is connected to the interface through the second gate array and is controlled by the second gate array. Storing captures data, the second central processing equipment is under control of the second gate array, freely reads the image data stored in said second image memory, via said second gate array Since the image data reading process from the image input interface to the first and second image memories is executed by the first and second gate arrays because of being connected to the second image memory, the first and second center The load applied to the processing device can be reduced.

  According to a third aspect of the present invention, in the image processing apparatus according to the second aspect, each of the first and second image memories has a storage area for image data for a plurality of frames, and the first and second gate arrays. Each of the storage areas in the first and second image memories has a storage area for image data of one frame as a storage area for image data of the current frame, and the storage area is obtained by the image input interface. In addition to performing control for storing image data, when temporarily storing the storage state of the image data stored in the storage area, image data for another frame in the storage area in the first and second image memories. Storage area of the current frame image data, and the storage area stores image data obtained by the image input interface. In addition to enabling image processing using multiple frames of image data, the output processing cycle of the image data is longer than the image processing cycle, and it is necessary to output image data, for example. Even when the result continues, the image data to be output is not overwritten by the subsequent image data to be output, the output time of the image data to be output can be gained, and the second central processing unit is slow. Can be used.

  According to a fourth aspect of the present invention, in the image processing apparatus according to any one of the first to third aspects, a communication interface for communicating with an external computer is further provided on the second central processing unit side. The first central processing unit transmits image processing status data including at least one of various parameters necessary for the image processing and the image processing result to the second central processing unit side via the communication unit between the central processing units. The second central processing unit transmits the image processing status data from the first central processing unit together with the corresponding image data to the external computer via the communication interface as the output processing. A suitable analysis becomes possible.

  According to a fifth aspect of the present invention, there is provided the image processing apparatus according to any one of the first to third aspects, wherein the image data stored in the second image memory is written and output to a removable storage medium. An apparatus further connected to the second central processing unit side, and the first central processing unit transmits various parameters necessary for the image processing and the results of the image processing via the communication unit between the central processing units. Image processing status data including at least one is transmitted to the second central processing unit, and the second central processing unit outputs the image processing status from the first central processing unit via the storage device as the output process. Since the data is written and output to the storage medium together with the corresponding image data, more suitable analysis can be performed. Further, the image data and the image processing status can be confirmed on another offline computer, and it is not necessary to connect an external computer online.

The invention according to claim 6, wherein, in the image processing apparatus according to claim 5, wherein said second image memory is further connected to the read and write freely the second central processing equipment of the image data, the second central processing The apparatus reads the image data written in the storage medium to the second image memory via the storage device, and the first central processing unit is read from the storage medium to the second image memory. Since the image processing is executed again using the image data, it is possible to suppress a delay in the image processing that may occur at the time of reading the image data written in the storage medium.

Invention of claim 7, wherein, in the image processing apparatus according to any one of claims 4-6, wherein the first central processing unit, according to the result of the determination, through the inter-CPU communication unit Since the image processing status data is transmitted to the second central processing unit and the image data corresponding to the image processing status data is designated, it is necessary for analysis during or after the image processing. Image data is output, output of useless image data is prevented, and the utility value of the output image data is increased.

The invention according to claim 8 is the image processing apparatus according to claim 1 or 7, wherein the predetermined determination is a determination as to whether or not a predetermined number of defect determination results have continued in the image processing, and a defect determination rate is Since it is a pass / fail determination including at least one determination of whether or not a predetermined rate has been exceeded and whether or not a predetermined abnormality has occurred, output is limited to the required image data according to the pass / fail determination status. This makes it possible to efficiently use the storage capacities of the first and second image memories.

According to a ninth aspect of the present invention, in the image processing apparatus according to the first or seventh aspect, the predetermined determination is a determination as to whether or not a determination result of a non-defective product for at least one determination item has occurred at a predetermined rate. Therefore, it is possible to output only the necessary image data according to the pass / fail judgment situation.

  The invention according to claim 10 is the image processing apparatus according to claim 8 or 9, wherein the reference for the determination is input from the external computer or an external device. It is possible to set or change criteria for determination.

  An image processing system according to an eleventh aspect of the present invention is the image processing apparatus according to any one of the fourth to tenth aspects, and an external computer having a communication interface corresponding to the communication interface provided in the image processing apparatus. The external computer includes image processing status data and image data obtained from the image processing device via a communication interface of the external computer, and image processing similar to image processing by the first central processing unit. By performing the above, a visual inspection measurement simulation of the inspection object is performed, so that various confirmations can be made by simulation reproducing image processing similar to that of the image processing apparatus on an external computer without interrupting image processing of the image processing apparatus. It becomes possible.

  According to a twelfth aspect of the present invention, in the image processing system according to the eleventh aspect, when the external computer needs to change at least one of various parameters included in the image processing status data, the parameter is set. When the simulation is performed again and the optimal image processing result is obtained by the simulation, the data including the parameter that is the optimal image processing result is transmitted to the image processing apparatus. Parameters can be updated. Thereby, the division of work between the image processing itself and the image processing setting can be achieved.

1 is a configuration diagram of an image processing system according to a first embodiment of the present invention. It is a block diagram of the image processing apparatus of 2nd Embodiment which concerns on this invention. It is a partial block diagram of an image processing system when output processing is transmission output. It is a figure which shows the example of the image data which arises by performing image processing. It is a block diagram of the image processing apparatus of 3rd Embodiment which concerns on this invention. FIG. 6 is an operation explanatory diagram of the image processing apparatus of FIG. 5. It is a block diagram of the image processing apparatus of 4th Embodiment which concerns on this invention. It is operation | movement explanatory drawing of the image processing apparatus of FIG. It is operation | movement explanatory drawing of the image processing apparatus of FIG. It is operation | movement explanatory drawing of the image processing apparatus of FIG. It is operation | movement explanatory drawing of the image processing apparatus of FIG. It is a block diagram of the image processing apparatus of 5th Embodiment which concerns on this invention. It is a figure which shows the example of an original image. It is a figure which shows the example of a setting menu of determination conditions. It is a block diagram of the image processing apparatus of 6th Embodiment which concerns on this invention. FIG. 16 is an operation explanatory diagram of the image processing apparatus of FIG. 15. It is a figure which shows the example of a usable flag. It is operation | movement explanatory drawing of the image processing system of 7th Embodiment concerning this invention. It is operation | movement explanatory drawing of the image processing system of 7th Embodiment concerning this invention. It is operation | movement explanatory drawing of the image processing system of 7th Embodiment concerning this invention. It is operation | movement explanatory drawing of the image processing system of 7th Embodiment concerning this invention. It is a figure which shows the Example relevant to 1st Embodiment etc. FIG. It is a more detailed block diagram of the communication part of FIG. It is a more detailed block diagram of the image processing part of FIG.

(First embodiment)
FIG. 1 is a block diagram of an image processing system, and a first embodiment of the present invention will be described with reference to this figure.

  The image processing system shown in FIG. 1 is used for, for example, an appearance inspection measurement of an inspection target such as a product in a production line, and includes an image processing apparatus 1 including a communication unit 100 and an image processing unit 150. In addition to a personal computer 2 including an image data storage device 21 and an image processing adjustment unit 22 communicatively connected to the image processing device 1, the peripheral device of the image processing device 1 performs at least imaging of an inspection target. One camera 3, an input device 4 for various operation inputs such as a keypad, and a display device 5 such as a CRT or LCD are provided.

  The communication unit 100 includes a central processing unit (CPU) 130 and a main memory (main storage device) 131 that execute processing for outputting image data used for image processing without stopping or delaying image processing. In addition, an image input interface 101, a VRAM 105, a monitor output interface 116, a communication interface 109, a main controller 137, an image data storage device 120, and a dual port memory 135 are provided.

  The image input interface 101 includes an A / D converter 103, and the A / D converter 103 converts an analog image signal from the camera 3 into digital to obtain image data. The VRAM 105 captures and stores image data obtained by the image input interface 101. The monitor output interface 116 includes a D / A converter 119. The D / A converter 119 converts image data stored in the VRAM 105 into analog and outputs an analog image signal to the display device 5. . The communication interface 109 is a communication means with the outside corresponding to Ethernet (registered trademark) or RS-232C. The main controller 137 performs input / output control of various interfaces such as an operation input interface (not shown) of the input device 4 and the communication interface 109. The image data storage device 120 stores image data stored in, for example, the VRAM 105 in a removable storage medium such as an SD card. The dual port memory 135 is interposed between the CPU 130 and a CPU 160 described later, and transfers information exchanged between them (for example, commands or data).

  The image processing unit 150 includes a VRAM 153 that captures and stores image data obtained by the image input interface 101, and is set through at least one of the input device 4 and an external device connected to the communication interface 109. The CPU 160 and the main memory 161 serving as cores for performing various appearance inspection measurements on the inspection target through image processing using the image data stored in the VRAM 153 under the inspection conditions acquired by message communication via the port memory 135 or the like. It has.

  The operation that characterizes the image processing system configured as described above will be described. Image data obtained by the image input interface 101 is stored in the VRAM 153 and the VRAM 105.

  The image data stored in one VRAM 153 is read by the CPU 160 that operates in an integral manner with the main memory 161, and is used for image processing in the same manner as in the prior art. Measurement is performed.

  The image data stored in the other VRAM 105 is read by the CPU 130 that is inseparably integrated with the main memory 131, is held in the main memory 131, for example, and then transferred to the image data storage device 120. In addition, the data is transmitted and output from the communication interface 109 to the external personal computer 2 via the main controller 137. Note that the image data transferred to the image data storage device 120 is written and output to the storage medium.

  As described above, according to the first embodiment, the image input interface 101 that obtains image data from the camera 3, the VRAM 153 that captures and stores the image data obtained by the image input interface 101, and the image data stored in the VRAM 153. The CPU 160 and the main memory 161 connected to the VRAM 153, the VRAM 105 that captures and stores the image data obtained by the image input interface 101, and the image data stored in the VRAM 105 can be read in the VRAM 105. The CPU 160 and the main memory 131 are connected to each other, and the dual port memory 135 is provided between the CPU 160 and the CPU 130 and transfers information exchanged between them. For example, the CPU 130 performs an output process of the image data stored in the VRAM 105 while performing image processing using the stored image data to perform an appearance inspection measurement of the inspection target. For example, the input device 4 is used. When the CPU 130 performs the output processing of the image data stored in the VRAM 105 in accordance with the image data output instruction of the VRAM 105 input in this way, the CPU 160 is completely released from the image data output processing of the VRAM 105. Even when the CPU 130 is instructed to output the image data stored in the VRAM 105 corresponding to the image data stored in the VRAM 153 to the CPU 130 by message communication via the dual port memory 135, the load applied to the CPU 160 is about several bytes. Output instruction data Transmission processing dealt with in only a communication message including, without stopping or or or delayed image processing, image data used in image processing may be output.

(Second Embodiment)
2 is a block diagram of the image processing apparatus, FIG. 3 is a partial block diagram of the image processing system when the output process is a transmission output, and FIG. 4 is a diagram illustrating an example of image data generated by executing the image process. The second embodiment of the present invention will be described with reference to these drawings.

  The image processing apparatus 1A according to the second embodiment is different from the first embodiment in that a plurality of VRAMs 153 and 105, main memories 161 and 131, and CPUs 160 and 130, as shown in FIG. VRAMs 153a and 105a having storage areas for image data for (1, 2,... N) frames, main memories 161a and 131a in which execution programs different from those in the first embodiment are expanded, and these main memories 161a and 131a. CPUs 160a and 130a that execute processing in accordance with the developed programs are provided.

  The CPU 160a and the main memory 161a are further connected to the VRAM 105a so as to be able to read and write data, and the CPU 160a is different from the CPU 160 of the first embodiment in that it writes image data generated by executing image processing. Further, the CPU 130a executes an output process of image data for at least one frame stored in the VRAM 105a as a difference from the CPU 130 of the first embodiment. In this way, the essential reason for outputting image data during image processing is to analyze how image processing has been performed and a predetermined image processing result has been produced, and adjust the settings of the image processing apparatus. There is to do.

  Various image processing is executed on the CPU 160a and main memory 161a side of the image processing apparatus 1A having such a configuration. As shown in the example of FIG. 4, as the preprocessing of the image processing, the original image of FIG. 4B, when the edge line image shown in FIG. 4D is obtained through the differential image shown in FIG. 4B and the thinned image shown in FIG. 4C, various image data are stored in the main memory 161a (see “ Occurs in the "processed image"). These various image data are written in the VRAM 105a as progress images from the CPU 160a and the main memory 161a side.

  Thereafter, the various image data written in the VRAM 105a is stored in the main memory 131a by, for example, DMA transfer under the instruction and control of the CPU 130a that operates in an integral manner with the main memory 131a, as shown in FIG. In addition to being transferred to the storage device 120 for image data storage and written out (saved) to the storage medium, it is also sent out (transferred) to the external personal computer 2 as shown in FIG.

  Here, in the pre-processing of the image processing, when an inconvenient image processing result is caused due to the interruption of the edge line as shown in FIG. 4D, the progress image shown in FIG. 4 is also output. Analysis such as that caused by the interruption of the edge line as shown in FIG. In this case, if it is inferred that the setting of the differential threshold that is an image parameter of the differential processing is too large, the differential threshold is changed to an optimal value by the image processing adjustment unit 22 shown in FIG. The differential threshold value changed to a value is transmitted to the CPU 130a side.

  As described above, according to the second embodiment, the CPU 160a and the main memory 161a are further connected to the VRAM 105a so as to be able to read and write data, and the CPU 160a writes image data generated by executing image processing to the VRAM 105a. Furthermore, since the CPU 130a executes output processing of various image data stored in the VRAM 105a, the image data generated by executing the image processing can also be confirmed on the personal computer 2.

(Third embodiment)
FIG. 5 is a block diagram of the image processing apparatus, and FIG. 6 is an operation explanatory view of the image processing apparatus of FIG. 5. A third embodiment of the present invention will be described with reference to these drawings.

  The image processing apparatus 1B according to the third embodiment has a storage area for a plurality of frames of image data as shown in FIGS. 5 and 6, respectively, instead of the VRAMs 153 and 105, as a difference from the first embodiment. VRAMs 153a and 105a are provided, and VRAM controllers 152 and 104 for controlling addresses of the VRAMs 153a and 105a are further provided.

  The VRAM controllers 152 and 104 are both field programmable gate arrays (FPGAs), and in accordance with address information from the CPUs 160 and 130, the storage areas for image data for one frame among the storage areas in the VRAMs 153a and 105a, respectively. In addition to performing hardware control to store the image data obtained by the image input interface 101 in this storage area, and temporarily storing the image data stored in the storage area, The storage area for the image data for one frame is set as the storage area for the image data of the current frame, and hardware control for storing the image data obtained by the image input interface 101 is performed in this storage area.

  In the example of FIG. 5, the CPU 160 is configured to give instructions to both the VRAM controllers 152 and 104, but this is because the VRAM controller 104 also serves as the imaging controller of the camera 3. This is because the camera 3 can be controlled via the. The VRAM controller 104 is provided with a register that stores instructions from the CPUs 160 and 130. When an imaging instruction is stored in the register, the VRAM controller 104 executes imaging control according to the imaging instruction.

  In the image processing apparatus 1B having the above configuration, as shown in the example of FIG. 6, among the storage areas in the VRAM 105a, the storage area for the image data with the image number “1” is the storage area for the image data of the current frame (in FIG. If the current frame image storage area is “), the image data obtained by the image input interface 101 is stored in the current frame image storage area.

  At this time, for example, when a result of determination of a defective product is obtained in the appearance inspection measurement, the image data of the defective product is temporarily stored in the VRAM 105a and then output for analysis or the like. That is, the storage area for the image data with the image number “1” is switched to the “temporary storage frame image storage area”, and the storage area for the image data with the image number “2” is set to the “current frame image storage area”. As a result, the defective image data stored in the image data storage area of the image number “1” is not overwritten by new image data and disappears.

  After this, when a result of the defective product determination is obtained by the appearance inspection measurement, the “current frame image storage area” is switched to the “temporary storage frame image storage area” as described above, and the image data of the next image number is stored. The area is set to the “current frame image storage area”. When the storage area of the image number “N” is reached, the next storage area becomes the storage area of the image number “1”, and the “current frame image storage area” is cyclically switched.

  In this “current frame image storage area” switching process, the defective image data stored in the VRAM 105a is written or transmitted in the same manner as in the first embodiment.

  As described above, according to the third embodiment, the VRAM controllers 152 and 104 set the image data storage area for one frame out of the storage areas in the VRAMs 153a and 105a as the storage areas for the current frame image data. In addition to controlling to store the image data obtained by the image input interface 101 in the area, when temporarily storing the image data stored in the storage area, the storage area of the image data for another frame is made the current Since the image data obtained by the image input interface 101 is stored in the storage area of the frame image data, image processing using a plurality of frames of image data can be performed. The output processing cycle of image data is longer than the processing cycle, for example, image data Even when the determination result that needs to be output continues, the image data to be output is not overwritten by the image data to be subsequently output, and the output time of the image data to be output can be gained. It becomes possible to use a low-speed one. Further, a past history can be left and a plurality of images can be displayed on the display device 5. Further, by matching the image data in the VRAMs 153a and 105a, the CPU 160 can designate image data to be output to the CPU 130 only with, for example, an image number.

  In the third embodiment, the “current frame image storage area” is cyclically switched for both the VRAMs 153a and 105a for image data matching, but only for the VRAM 105a. Thus, the “current frame image storage area” may be switched cyclically.

(Fourth embodiment)
FIG. 7 is a configuration diagram of the image processing apparatus, and FIGS. 8 to 11 are operation explanatory views of the image processing apparatus of FIG. 7. The fourth embodiment of the present invention will be described with reference to these drawings.

  The image processing apparatus 1C according to the fourth embodiment is different from the first embodiment in that a plurality of image processing apparatuses 1C are replaced with VRAMs 153 and 105, main memories 161 and 131, and CPUs 160 and 130 as shown in FIG. Processing is performed in accordance with VRAMs 153a and 105a having image data storage areas for frames, main memories 161c and 131c in which execution programs different from those in the first embodiment are expanded, and programs expanded in these main memories 161c and 131c, respectively. CPUs 160c and 130c for executing the above. In FIG. 7, the image input interface 101 and the communication interface 109 are not shown. The VRAM 105a is further connected to the CPU 160c and the main memory 161c so that data can be read and written.

  The CPU 160c is different from the CPU 160 of the first embodiment in that an image including at least one of various parameters such as image processing parameters and determination parameters necessary for image processing and the image processing results via the dual port memory 135. A process of transmitting the processing status data to the CPU 130c side is executed.

  As a difference from the CPU 130 of the first embodiment, the CPU 130c transmits image processing status data from the CPU 160c together with corresponding image data to the personal computer 2 via the communication interface 109 as output processing, and also stores image data. The image processing status data from the CPU 160c is written to the storage medium of the image data storage storage device 120 together with the corresponding image data via the storage device 120.

  Further, the CPU 130c reads the image data written in the storage medium to the VRAM 105a via the image data storage device 120, and the CPU 160c reads the image data from the storage medium of the image data storage device 120 to the VRAM 105a. Image processing is executed again using the image data.

  In the image processing apparatus configured as described above, the image data obtained by the image input interface 101 is stored in parallel in the VRAMs 153a and 105a. N image data can be stored in the VRAMs 153a and 105a, and an image number is assigned to each image data. Similar to the third embodiment, the image data is normally repeatedly stored in the same storage area, but when the CPU 160c determines to output the image data, the storage area for storing the image data is switched.

  On the CPU 160c and main memory 161c side, image processing is executed after copying the current image data stored in the VRAM 153a to the main memory 161c.

  Here, in the example of FIG. 8, when N image data stored in the VRAM 105 a is transmitted and output to the personal computer 2, the CPU 160 c is executing image processing using the Nth image data. In order to transmit and output the N pieces of image data stored in the VRAM 105a, the image processing status data including at least one of various parameters necessary for image processing and the image processing result is used as a communication message via the dual port memory 135. It transmits to CPU130c. The communication message further includes an image number to be output, an instruction via the communication interface 109, and the like.

  When the CPU 130c receives the communication message, the CPU 130c sequentially reads the image data to be output stored in the VRAM 105a into the main memory 131c, and transmits the image data to the personal computer 2 via the communication interface 109 together with the image processing status data.

  The personal computer 2 receives the image data and the image processing status data from the image processing device 1C by the reception function of the image processing adjustment unit 22, and then stores the image data in the image data storage device 21 such as a hard disk device.

  Note that when the personal computer 2 is not connected to the image processing apparatus 1C, or when the personal computer 2 is not in the reception state, the image data and the image processing status data are not received. The CPU 130c transmits information indicating whether it has entered or not, and the CPU 130c transmits and outputs image data and image processing status data after receiving the information.

  In the example of FIG. 9, when N image data stored in the VRAM 105 a is written and output to the image data storage device 120, the CPU 160 c executes image processing using the Nth image data. Sometimes, in order to transmit and output N pieces of image data stored in the VRAM 105a, the dual port memory 135 uses image processing status data including various parameters necessary for image processing and at least one of the image processing results as a communication message. To the CPU 130c. The communication message further includes an image number to be output, an instruction via the image data storage device 120, and the like.

  Upon receiving the communication message, the CPU 130c sequentially reads the image data to be output stored in the VRAM 105a into the main memory 131c, and transfers the image data together with the image processing status data to the image data storage storage device 120. The sequentially transferred image data and image processing status data are written and output to the storage medium of the image data storage device 120.

  In the example of FIG. 10, the CPU 130 c displays a desired image to be output among the plurality of images stored in the VRAM 105 a on the display device 5 so as to be selectable by the input device 4. When an image is selected, the corresponding image data is read from the VRAM 105a to the main memory 131c and transferred to the image data storage device 120. The transferred image data is written and output to the storage medium of the image data storage device 120. In this case, since the CPU 160c is completely released from the image data output process of the VRAM 105a, the image data used for the image process can be output without delaying the image process of the CPU 160c.

  In the example of FIG. 11, an instruction to re-execute image processing using the image data stored in the storage device 120 after attaching the storage medium storing the previous image data to the storage device 120 for image data storage. Is input from the input device 4 to the CPU 130c, the CPU 130c reads the image data of the designated saved image from the image data saving storage device 120 to the main memory 131c, and copies it to the VRAM 105a to copy the saved image. It is displayed on the display device 5. After the arrangement of the stored image in the VRAM 105a is completed, the CPU 130c transmits an image processing execution instruction including the image number of the VRAM 105a in which the stored image is expanded to the CPU 160c via the dual port memory 135.

  When the CPU 160c receives the image processing execution instruction, the CPU 160c executes the image processing again using the image data read from the storage medium of the image data storage device 120 to the VRAM 105a.

  As described above, according to the fourth embodiment, the CPU 160c transmits the image processing status data including at least one of various parameters necessary for image processing and the image processing result to the CPU 130c via the dual port memory 135, and the CPU 130c. Since the image processing status data from the CPU 160c is output together with the corresponding image data, more suitable analysis can be performed.

  Further, the CPU 130c reads the image data written in the storage medium to the VRAM 105a via the image data storage device 120, and the CPU 160c reads the image data from the storage medium of the image data storage device 120 to the VRAM 105a. Since the image processing is executed again using the image data, the CPU 130c reads out the stored image, which takes time (from the image data storage device 120, about 50 ms in the case of an image of 512 × 480 pixels), and the VRAM 105a Since the saved image rearranged at the time is read out to the CPU 160c side, it is possible to suppress delay in image processing that may occur when the saved image is re-read. Further, since the image processing execution instruction is issued after the arrangement of the stored image in the VRAM 105a is completed, there is no contention for access by the CPUs 160c and 130c to the VRAM 105a.

  The instructions exchanged between the CPU 160c and the CPU 130c may be configured to be transmitted in a polling manner, or may be configured to generate an event by writing the instruction in the FPGA register and capture the instruction by interruption.

  Further, the re-execution of the image processing may be executed between image processing using the current image data.

(Fifth embodiment)
FIG. 12 is a configuration diagram of the image processing apparatus, FIG. 13 is a diagram illustrating an example of an original image, and FIG. 14 is a diagram illustrating an example of a determination condition setting menu. The fifth embodiment of the present invention with reference to these diagrams Will be described.

  The image processing apparatus 1D according to the fifth embodiment is different from the first embodiment in that a plurality of image processing apparatuses 1D are replaced with VRAMs 153 and 105, main memories 161 and 131, and CPUs 160 and 130, as shown in FIG. VRAMs 153a and 105a having image data storage areas for frames, main memories 161d and 131d in which execution programs different from those in the first embodiment are expanded, and processing according to the programs expanded in these main memories 161d and 131d, respectively. CPUs 160d and 130d for executing the above. In FIG. 12, the image input interface 101 and the communication interface 109 are not shown.

  As a difference from the CPU 160 of the first embodiment, the CPU 160d makes a predetermined determination on the result during or after the image processing, and in accordance with this determination result, the image is sent to the CPU 130d via the dual port memory 135. The image processing status data including at least one of various parameters necessary for the processing and the image processing result is transmitted, and processing for designating image data corresponding to the image processing status data is further executed. Here, the predetermined determination is a determination as to whether or not a predetermined number of defect determination results have continued in image processing, a determination as to whether the defect determination rate has exceeded a predetermined rate, and whether a predetermined abnormality has occurred. This is a pass / fail determination including at least one of the determinations, and a determination as to whether or not a determination result of a non-defective product for at least one determination item has occurred at a predetermined rate.

  As a difference from the CPU 130 of the first embodiment, the CPU 130d is a determination criterion for the predetermined determination via at least one of an operation input interface (not shown) to which the input device 4 is connected and the communication interface 109. Is received, the process of transmitting the determination criteria to the CPU 160d via the dual port memory 135 is further executed.

  Even in the image processing apparatus 1D having such a configuration, in order to prevent the stagnation of the image processing of the CPU 160d by destroying the data amount of the output command used by the CPU 160d when designating the image data to be output to the CPU 130d, the image number Is attached to each storage area of the VRAMs 153a and 105a.

  When an automatic sampling condition including the determination criterion is input from at least one of the operation input interface and the communication interface 109, the CPU 130d transmits the automatic sampling condition to the CPU 160d via the dual port memory 135. Here, it is assumed that the determination criterion is, for example, “when the determination as a defective product is continued N times”.

  Thereafter, the CPU 160d determines a non-defective product in accordance with preset inspection measurement conditions, and if this determination result (result during or after the above-described image processing) is a defective product, the third embodiment and the third embodiment. Similarly, the “current frame image storage area” is switched. At this time, the image number of the “temporarily stored frame image storage area” is stored in the main memory 161d, for example. Also, the CPU 160d issues a “current frame image storage area” switching instruction to the CPU 130d.

  Thereafter, if the determination result of the defective product is N times consecutively, the CPU 160d corresponds to “when the determination of being a defective product continues N times” according to the predetermined determination. Image processing status data including at least one of the image processing results, an image number specifying image data corresponding to the image processing status data, and the like are included in the communication message and transmitted to the CPU 130d via the dual port memory 135.

  When the CPU 130d receives the above communication message, the CPU 130d reads the corresponding image data from the VRAM 105a into the main memory 131d, writes it together with the image processing status data to the image data storage storage device 120, or the personal computer 2 via the communication interface 109. To send output.

  By the way, in the above-described operation example, the determination criterion is “when the determination as a defective product is repeated N times”, but various other determination criteria are conceivable.

  In the image processing for calculating the area value in the frame F (the number of pixels having a light quantity equal to or greater than the binarization threshold) and the average light quantity in the frame F for the original image shown in FIG. Considering the case where the area value and the average gray value are set as determination criteria, the image data that is out of the range is the output target.

  The check box in FIG. 14 is for setting whether to validate or invalidate as a criterion, and becomes valid when a check is entered. The check can be set through the input device 4 or the personal computer 2.

  As described above, according to the fifth embodiment, the CPU 160d performs a predetermined determination on the result during or after the image processing, and the image processing status data is transmitted to the CPU 131d via the dual port memory 135 according to the determination result. Since the image data corresponding to the image processing status data is specified, the image data necessary for analysis or the like during or after the image processing is output, and the output image Increases the utility value of data.

  Further, the predetermined determination is a determination as to whether or not a predetermined number of failure determination results have continued in image processing, a determination as to whether the failure determination rate has exceeded a predetermined rate, and a determination as to whether a predetermined abnormality has occurred. If it is a pass / fail judgment including at least one determination, it is possible to narrow down the output to the necessary image data according to the pass / fail judgment situation, and the storage capacity of the VRAM can be used efficiently.

  In addition, even if the predetermined determination is a determination as to whether or not a non-defective / non-defective product determination result for at least one determination item has occurred at a predetermined rate, it is possible to output only the necessary image data according to the pass / fail determination situation. It becomes. For example, if a predetermined rate is set in consideration of the importance, the probability that the image data is output for a defective product that often occurs is reduced, and the probability that the image data is output for a defective product that occurs rarely is reduced. Can be high.

  In addition, in the case of a configuration in which a criterion for determination is input from the personal computer 2 connected to the communication interface 109 or an external device, the criterion for determination can be set or changed before and after image processing or during image processing. It becomes.

  In the fifth embodiment, image data that is a defective product determination result is output N times in succession. However, for example, for analysis of changes in background, the upper limit of the set defective rate is exceeded. The configuration may be such that N pieces of image data before and after the time point are output.

  Further, when the CPU 160d uses the VRAM 105a as the storage position for the intermediate progress image data instead of the main memory 161d, it is possible to specify to store the intermediate progress of the image that has been determined to be defective for N consecutive times. It is.

(Sixth embodiment)
FIG. 15 is a block diagram of the image processing apparatus, FIG. 16 is a diagram for explaining the operation of the image processing apparatus in FIG. 15, and FIG. 17 is a diagram showing an example of an available flag. Embodiments will be described.

  The image processing apparatus 1E according to the sixth embodiment is different from the third embodiment in that instead of the dual port memory 135, the main memories 161 and 131, and the CPUs 160 and 130, shown in FIGS. 15 and 16, respectively. As described above, the dual port memory 135e in which the usable flag (see the example of FIG. 17) is set, the main memories 161e and 131e in which the execution program different from the third embodiment is expanded, and the main memories 161e and 131e. And CPUs 160e and 130e for executing processing in accordance with the programs developed in FIG. It is assumed that each flag of the usable flag is set to “1” as an initial value.

  As a difference from the CPU 160b of the third embodiment, the CPU 160e executes a process of setting a flag corresponding to the image number of the image data to be output among the available flags of the dual port memory 135e to “0”.

  As a difference from the CPU 130b of the third embodiment, the CPU 130e reads out and outputs the image data corresponding to the image number of the flag “0” from the VRAM 105a in the usable flag of the dual port memory 135e, and outputs the image data. When the output is completed, a process of replacing the flag with “1” is executed.

  The operation of the image processing apparatus 1E having the above configuration will be described. When the CPU 160e determines that the image data is to be output by the appearance inspection measurement, the CPU 160e sets a flag corresponding to the image number of the image data to “0” and An instruction to output the image data is issued.

  Thereafter, the CPU 130e monitors each flag state of the usable flag in a polling manner, and when detecting the flag set to “0”, reads out the image data corresponding to the image number of the flag from the VRAM 105a and outputs it. Execute. Subsequently, when the output of the image data is completed, a process of replacing the corresponding flag with “1” is executed.

  By the way, the CPU 160e and the CPU 130e monitor each flag state of the usable flag in a polling manner. When a flag set to “0” is detected, the CPU 160e and the CPU 130e correspond to the corresponding storage areas in the VRAMs 153a and 105a. When the storage area of the image number to be written is set to the write-inhibited state and the flag replaced with “1” is detected, the storage area of the corresponding image number is set to the write-permitted state.

  As described above, according to the sixth embodiment, since the image data to be output is instructed using the flag, the VRAM can be used efficiently.

(Seventh embodiment)
FIGS. 18 to 21 are diagrams for explaining the operation of the image processing system. The seventh embodiment of the present invention will be described with reference to these drawings.

  The image processing system according to the seventh embodiment includes the image processing apparatus described in each of the above embodiments, and a personal computer 2e having a communication interface (not shown) corresponding to the communication interface 109 included in the image processing apparatus. ing.

  The personal computer 2e performs image processing similar to the image processing by the CPU of the image processing unit using the image processing status data and the image data obtained from the image processing apparatus via its own communication interface, and thereby the inspection target object. In addition to performing a visual inspection measurement simulation, if it is necessary to change at least one of the various parameters included in the image processing status data, the parameter is changed and the above simulation is performed again. When the processing result is obtained, the data including the parameter that is the optimum image processing result is transmitted and set to the image processing apparatus.

  In the operation example of FIG. 18, when a defective product determination result (NG) occurs in the image processing apparatus (S1), the image processing apparatus transmits image data and image processing status data to the personal computer 2e via the communication interface 109. Thereafter, the image processing is continued using the previously set image processing parameters (S3). This will continue production.

  On the personal computer 2e side that has received the image data and the image processing status data, the same image processing as that of the image processing apparatus is reproduced based on the information, and the contents of the image processing occurring on the image processing apparatus are reproduced. Adjust to optimum parameters (S4 to S7). In other words, the image processing adjustment unit 22e (see FIG. 20) adjusts the image processing inspection parameters and repeatedly executes the image processing using the received image data, thereby performing an inspection simulation, independently of the image processing apparatus. Adjust the parameters.

  After the parameter adjustment is completed, the adjusted parameter is transferred to the image processing apparatus, and the image processing parameter used by the CPU in the image processing unit of the image processing apparatus is changed (S8).

  In the operation example of FIG. 19, the image processing is performed by using a combination of specific image processing routines such as “image processing A” and “image processing B”. It is mounted as a library on the processing device.

  In the image processing apparatus, an image processing program operates on the CPU of the image processing unit. First, an image processing procedure is read, image processing parameters and determination parameters are sequentially input according to the procedure (S11), and image processing is executed by calling an image processing routine in the library using these parameters (S12). The image processing result data (parameter) is output (S13).

  The personal computer 2e is equipped with the same programs and libraries in the image processing apparatus in order to perform image processing adjustment, and receives image data and image processing status data from the image processing apparatus (S14). Image processing similar to that of the apparatus is executed (S15).

  In this case, it is possible to check the background of the image processing and correct the parameters with the personal computer 2e, and it is possible to adjust the image processing of the image processing apparatus by setting only the image processing status data in the image processing apparatus.

  In the operation example of FIG. 20, the image processing parameters adjusted by the image processing adjustment unit 22e on the personal computer 2e are stored in the image data storage device 21 and read by the image processing adjustment unit 22e (S21). The data is transferred to the CPU side of the communication unit of the image processing apparatus (S22).

  The CPU of the communication unit has a routine for analyzing a communication command from the image processing adjustment unit 22e, analyzes the image processing parameter sent from the image processing adjustment unit 22e, and sends a parameter change instruction to the dual port memory. Arrange (S23).

  The CPU of the image processing unit receives the parameter change instruction in a polling manner during the image processing (S24) and sets it as an image processing parameter.

  Here, the amount of parameter data used for image processing is not so large compared to the case where the image to be subjected to image processing is large data (256 KB to 1 MB). This is because the ratio of repetitive calculations in image processing is large. For example, when performing differential processing such as the Sobel operator on the original image, the input operator only needs the operator's size, differential value threshold, etc., and repeats calculations using those settings. Then, operator processing of a predetermined image is performed. The image processing parameter to be corrected and set is about several tens to several hundreds of bytes, compared with the image data to be subjected to image processing having a large capacity of 256 KB to 1 MB.

More specifically, there are only 11 input parameters of the appearance inspection image processing routine for detecting cracks using the Sobel operator in the conventional image processing apparatus as follows. 11 × 4 bytes = only 44 bytes.
Input parameter Parameter name
param [0] Filter size
param [1] Edge extraction threshold
param [2] Edge extension lower limit
param [3] differential value threshold
param [4] Detected differential direction value
param [5] Black and white judgment
param [6] Density judgment threshold correction amount
param [7] Wing size for concentration determination
param [8] Differential sum threshold
param [9] Bad pixel count threshold
param [10] Error code Therefore, even if the input parameter is changed and set by the CPU of the image processing unit, there is no problem of setting time.

  In the operation example of FIG. 21, when the personal computer 2e transfers the parameters adjusted in S4 to S7 to the image processing apparatus, the image processing apparatus temporarily changes the parameters to the adjusted parameters for a specified fixed time, for example. An image processing simulation is executed (S31), and the validity of the adjusted parameter is verified by the image processing simulation depending on whether the target NG rate is reached, for example (S32), and the problem is solved. When a verification result indicating this is obtained, the image processing parameter in the image processing apparatus is switched to the adjusted parameter for the first time (S33).

  In this operation, even if the image processing apparatus and the personal computer 2e have different conditions, the validity of the adjusted parameter by the personal computer 2e is verified by the image processing apparatus. Is possible. As an example of different conditions, the image data is fixed in the personal computer 2e, whereas in the image processing apparatus, the image data changes due to the change in imaging conditions such as lamp illuminance with respect to the inspection target flowing through the line. However, the processing speed is not limited, but the image processing apparatus must execute processing at a processing speed that is higher than the line speed. If the inspection target area is widened, the image processing speed decreases and the determination in S32 is made. In some cases, NG may not be resolved.

  As described above, according to the seventh embodiment, the personal computer 2e has a communication interface corresponding to the communication interface 109 provided in the image processing apparatus, and the image processing status data obtained from the image processing apparatus via this communication interface, and By performing image processing similar to the image processing performed by the CPU of the image processing unit of the image processing apparatus using the image data, the appearance inspection measurement simulation of the inspection target is performed, so the image processing of the image processing apparatus is interrupted. Without any problem, various confirmations can be made by simulation in which the personal computer 2e reproduces the same image processing as the image processing apparatus.

  When the computer 2e needs to change at least one of various parameters included in the image processing status data, the parameter is changed and the simulation is performed again, and the simulation results in an optimal image processing result. When obtained, the data including the parameter that is the optimum image processing result is transmitted to the image processing apparatus, so that the parameter of the image processing apparatus can be updated.

  22 to 24 are diagrams showing examples related to the first embodiment and the like. FIG. 22 is a configuration diagram of the image processing apparatus, FIG. 23 is a more detailed configuration diagram of the communication unit in FIG. FIG. 23 is a more detailed configuration diagram of the image processing unit in FIG. 22.

  The image processing apparatus according to this embodiment performs various appearance inspection measurements on an inspection object through image processing on an image obtained by imaging with the camera 3 under inspection conditions set using the input device 4 described above. In addition, the image data used for the image processing is output without stopping or delaying the image processing. As shown in FIG. 22, the image processing unit includes a communication unit and an image processing unit.

  In the communication unit of FIG. 23, reference numeral 101 denotes an image input interface that obtains image data from a maximum of four cameras 3 that capture an image of an inspection target. A connector 102 connected to the output of each camera 3, and each connector 102 And an A / D converter 103 that converts an analog image signal from the camera 3 to a digital signal to obtain image data.

  Reference numeral 104 denotes a VRAM controller (gate array), which is composed of an FPGA in FIG. 23 and is connected to the output of the image input interface 101.

  Reference numeral 105 denotes a VRAM (SDRAM), which is connected to the image input interface 101 via the VRAM controller 104 and captures and stores image data obtained by the image input interface 101 under the hardware control of the VRAM controller 104.

  Reference numeral 106 denotes an operation input interface for connecting the input device 4, which includes a connector 107 connected to the input device 4 and a circuit unit 108 that obtains an input signal from the input device 4 connected to the connector 107. ing.

  Reference numeral 109 denotes a communication interface for communicating with an external device such as the personal computer 2, an Ethernet (registered trademark) interface including a connector 110, a transformer 111 and an Ethernet (registered trademark) controller 112, and a connector 113. And two sets of serial communication interfaces configured by the circuit unit 114 for RS-232C. Reference numeral 115 denotes a selector.

  Reference numeral 116 denotes a monitor output interface, which converts the image data from the NTSC or VGA connectors 117 and 118 and the VRAM 105 acquired under the control of the VRAM controller 104 to analog, and converts the analog image signal to the connectors 117 and 118. And a D / A converter 119 for outputting to the connected display device 5.

  Reference numeral 120 denotes a storage device for storing image data. In the example of FIG. 23, the storage device 120 includes an SD card 121 and an SD card controller 122 that writes and outputs image data and the like to the SD card 121. In addition, interfaces 123 and 124 including photocouplers and the like are provided for controlling the strobe and the like.

  Reference numeral 130 denotes a CPU that executes processing such as control of the entire communication unit in FIG. 23, 131 is a main memory, and 132 is a FROM (flash memory). These CPU 130, main memory 131 and FROM 132, VRAM controller 104, and image data storage The storage devices 120 are connected to each other via the bus B1. Among these, the CPU 130 and the main memory 131 that operate as an integral inseparable unit are connected to the VRAM 105 via the VRAM controller 104 so that image data stored in the VRAM 105 can be read out under the control of the VRAM controller 104. Reference numeral 133 denotes an SROM in which data is read and written by the CPU 130. Reference numeral 134 denotes a VME bus controller, which is composed of, for example, an FPGA.

  Reference numeral 136 denotes an SRAM. Reference numeral 137 denotes a main controller (FPGA in FIG. 23), which is connected to the bus B1 and the bus B2 to which the SRAM 136 and the VRAM controller 104 are connected, and performs input / output control of the operation input interface 106, the communication interface 109, and the interface 124. In addition, it performs data transfer control as a dual port memory. That is, a part of the main controller 137 and the SRAM 136 constitute a dual port memory 135 that is interposed between the CPU 130 and the CPU 160 shown in FIG. 24 and transfers information exchanged between them. is there. With respect to the dual port memory 135, even when the CPU 130 is accessing the SRAM 136 via the main controller 137, the CPU 160 shown in FIG. 24 can access the SRAM 136 via the bus B2. When the CPU 160 is accessing the SRAM 136 via the bus B <b> 2, the CPU 130 cannot access the SRAM 136 via the main controller 137.

  Reference numeral 138 denotes a connector for connecting the communication unit shown in FIG. 23 and the image processing unit shown in FIG. 24, and is connected to the output of the image input interface 101 and the bus B2.

  In the image processing unit in FIG. 24, reference numeral 151 denotes a connector connected to the connector 138 of the communication unit in FIG. Reference numeral 152 denotes a VRAM controller (gate array), which is composed of an FPGA in FIG. 24 and is connected to the output of the image input interface 101 via connectors 151 and 138.

  Reference numeral 153 denotes a VRAM (SDRAM), which is connected to the image input interface 101 via the VRAM controller 152 and captures and stores the image data obtained by the image input interface 101 under the hardware control of the VRAM controller 152. Reference numeral 154 denotes an overlay memory such as an SDRAM, which constitutes a part of the VRAM (see FIG. 22).

  Reference numeral 160 denotes an image processing CPU, 161 denotes a main memory, and 162 denotes a main controller. The CPU 160, the main memory 161, and the main controller 162 are connected to each other via a bus B3. Among these, the CPU 160 and the main memory 161 that operate as an integral inseparable unit are connected to the VRAM 153 via the VRAM controller 152 so that image data stored in the VRAM 153 can be read out under the control of the VRAM controller 152. On the other hand, the main controller 162 is connected to the overlay memory 154 and the FROM 163, and is also connected to the bus B2 of the communication unit in FIG. The FROM 163 reads and writes data by the CPU 160 via the main controller 162.

  The operation that characterizes the image processing apparatus configured as described above will be described. Image data obtained by the image input interface 101 is stored in the VRAM 153 under the control of the VRAM controller 152, and the VRAM 105 is controlled by the control of the VRAM controller 104. Is remembered.

  The image data stored in one VRAM 153 is read by the CPU 160 that operates in an integral manner with the main memory 161, and is used for image processing in the same manner as in the prior art. Measurement is performed. Various setting information necessary for image processing is transmitted from at least one of the operation input interface 106 and the communication interface 109 via the CPU 103, the main memory 131, the dual port memory 135, and the main controller 162, and the CPU 160 and the main memory 161. Is taken in.

  The image data stored in the other VRAM 105 is read by the CPU 130 that is inseparably integrated with the main memory 131, is held in the main memory 131, for example, and then transferred to the image data storage device 120. In addition, the data is transmitted and output from the communication interface 109 to the external personal computer 2 via the main controller 137. The image data transferred to the image data storage device 120 is written and output to the SD card 121. Further, what image data is written out or transmitted is processed in the same manner as in the above-described embodiment, and the VRAMs 153a and 105a having a storage area for a plurality of frames of image data according to the specified memory capacity. Installed.

  As described above, according to the present embodiment, the image input interface 101 that obtains image data from the camera 3 that images the inspection target, the VRAM controllers 152 and 104 connected to the output of the image input interface 101, and the image input interface 101 Are connected via the VRAM controller 152, and under the control of the VRAM controller 152, the VRAM 153 that captures and stores the image data obtained by the image input interface 101, and is stored in the VRAM 153 under the control of the VRAM controller 152. The CPU 160 and the main memory 161 connected to the VRAM 153 via the VRAM controller 152 and the image input interface 101 are connected via the VRAM controller 104 so that the image data can be read freely. Under the control of the VRAM controller 104, the VRAM 105 that captures and stores the image data obtained by the image input interface 101, and under the control of the VRAM controller 104, the image data stored in the VRAM 105 can be freely read. A CPU 130 and a main memory 131 connected to the VRAM 105 via the CPU, and a dual port memory 135 interposed between the CPU 160 and the CPU 130 via the FPGA 162 and transferring information exchanged between them. The CPU 160 performs an image inspection using the image data stored in the VRAM 153 to perform an appearance inspection measurement of the inspection target, while the CPU 130 executes an output process of the image data stored in the VRAM 105. For example, when the CPU 130 performs the output process of the image data stored in the VRAM 105 in accordance with the image data output instruction of the VRAM 105 input using the input device 4, the CPU 160 is completely released from the image data output process of the VRAM 105. Therefore, for example, even when the CPU 160 instructs the CPU 160 to output the image data stored in the VRAM 105 corresponding to the image data stored in the VRAM 153 to the CPU 130 by message communication via the dual port memory 135, the CPU 160 Since only a transmission process of a communication message including output instruction data with a load of about several bytes is required, the image data used for the image processing can be output without stopping or delaying the image processing.

1, 1A, 1B, 1C, 1D, 1E Image processing device 2 Personal computer 3 Camera 4 Input device 5 Display device 101 Image input interface 103 A / D converter 104 VRAM controller (FPGA)
105,105a VRAM (SDRAM)
106 Operation Input Interface 109 Communication Interface 116 Monitor Output Interface 119 D / A Converter 120 Image Data Storage Device 121 SD Card 122 SD Card Controller 130, 130a, 130c, 130d, 130e CPU
131, 131a, 131c, 131d, 131e Main memory 135, 135e Dual port memory 137 Main controller 152 VRAM controller (FPGA)
153, 153a VRAM (SDRAM)
160, 160a, 160c, 160d, 160e CPU
161, 161a, 161c, 161d, 161e Main memory

Claims (12)

An image input interface for obtaining image data from at least one imaging device for imaging the inspection object;
A first image memory for capturing and storing image data obtained by the image input interface;
A first central processing unit connected to the first image memory so that image data stored in the first image memory can be read out;
A second image memory for capturing and storing image data obtained by the image input interface;
A second central processing unit connected to the second image memory so that image data stored in the second image memory can be read out;
An inter-central processing unit communication unit that is interposed between the first central processing unit and the second central processing unit and transfers information exchanged between them;
The first image memory and the second image memory are respectively disposed between the image input interface and the first central processing unit and the second central processing unit,
Wherein the first central processing unit, said line visual inspection measurement of said object by performing image processing using the image data stored in the first image memory Utotomoni, during the course of the image processing or after Image data stored in the second image memory corresponding to the image data stored in the first image memory for the second central processing unit according to the determination result. When sending the output instruction data to the second central processing unit by message communication via the communication unit between the central processing units,
When the second central processing unit receives the output instruction data from the first central processing unit via the inter-central processing unit communication unit, the second central processing unit executes output processing of image data stored in the second image memory. An image processing apparatus. Further comprising first and second gate arrays connected to the output of the image input interface;
The first image memory is connected to the image input interface via the first gate array, and under the control of the first gate array, captures and stores image data obtained by the image input interface;
The first central processing unit is connected to the first image memory via the first gate array so that image data stored in the first image memory can be read out under the control of the first gate array. ,
The second image memory is connected to the image input interface via the second gate array, and under the control of the second gate array, captures and stores image data obtained by the image input interface;
The second central processing unit is connected to the second image memory via the second gate array so that the image data stored in the second image memory can be read out under the control of the second gate array. The image processing apparatus according to claim 1, wherein: Each of the first and second image memories has a storage area for image data for a plurality of frames,
Each of the first and second gate arrays has a storage area for image data of one frame of storage areas in the first and second image memories as a storage area for image data of a current frame. In addition to performing control to store the image data obtained by the image input interface, when temporarily storing the storage state of the image data stored in the storage area, of the storage areas in the first and second image memories The storage area for the image data of another frame is set as the storage area for the image data of the current frame, and control for storing the image data obtained by the image input interface is performed in this storage area. 2. The image processing apparatus according to 2. A communication interface for communicating with an external computer is further provided on the second central processing unit side,
The first central processing unit sends image processing status data including at least one of various parameters necessary for the image processing and the image processing result via the communication unit between the central processing units to the second central processing unit side. To
The second central processing unit transmits the image processing status data from the first central processing unit together with the corresponding image data to the external computer via the communication interface as the output process. The image processing apparatus according to claim 1. A storage device for writing and outputting image data stored in the second image memory to a removable storage medium is further connected to the second central processing unit side,
The first central processing unit sends image processing status data including at least one of various parameters necessary for the image processing and the image processing result to the second central processing unit via the communication unit between the central processing units. Send
The second central processing unit writes and outputs the image processing status data from the first central processing unit together with the corresponding image data to the storage medium via the storage device as the output processing. The image processing apparatus according to claim 1. The second image memory is further connected to the second central processing unit so that image data can be read and written,
The second central processing unit reads image data written in the storage medium to the second image memory via the storage device,
The image processing apparatus according to claim 5, wherein the first central processing unit re-executes image processing using image data read from the storage medium to the second image memory. It said first central processing unit, according to the result of the determination, through the inter-CPU communication unit, and transmits the image processing status data to the second central processing device side, corresponding to the image processing status data The image processing apparatus according to claim 4, wherein image data to be specified is designated. The predetermined determination is a determination as to whether or not a predetermined number of defect determination results have continued in the image processing, a determination as to whether or not a defect determination rate has exceeded a predetermined rate, and whether or not a predetermined abnormality has occurred. The image processing apparatus according to claim 1 , wherein the image processing apparatus is a pass / fail determination including at least one determination. The predetermined determination and at least one non-defective defective for judgment item determination result by the image processing apparatus according to claim 1 or 7, wherein the is that the determination of whether the generated predetermined rate.   The image processing apparatus according to claim 8, wherein the criterion for the determination is input from the external computer or an external device. The image processing apparatus according to any one of claims 4 to 10,
An external computer having a communication interface corresponding to the communication interface provided in the image processing apparatus,
The external computer executes image processing similar to the image processing by the first central processing unit, using image processing status data and image data obtained from the image processing device via a communication interface of the external computer. An image processing system characterized in that a simulation of an appearance inspection measurement of the inspection object is performed.   When the external computer needs to change at least one of various parameters included in the image processing status data, the parameter is changed and the simulation is performed again, and the simulation results in an optimal image processing result. 12. The image processing system according to claim 11, wherein when obtained, data including a parameter that is an optimum image processing result is set to be transmitted to the image processing apparatus.

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