JP4709816B2 - Method for manufacturing thin film transistor substrate - Google Patents

Description

  The present invention relates to a thin film transistor substrate preferably applied to a liquid crystal display device and the like, and a liquid crystal display device including the same, and relates to a structure using a terminal or a pixel electrode made of indium tin zinc oxide or indium zinc oxide.

  FIG. 29 is a plan view showing a structural example of a thin film transistor (array) substrate including a top gate thin film transistor, a gate wiring, a source wiring, a pixel electrode, and the like in a conventional general thin film transistor liquid crystal display device. FIG. 31 is a partial sectional view of the thin film transistor array substrate.

  In the thin film transistor array substrate of this example, gate lines G and source lines S are arranged in a matrix on a transparent substrate 100 made of glass or the like. An area surrounded by the gate wiring G and the source wiring S is one pixel, and a pixel electrode 101 is provided for each pixel area.

In the thin film transistor array substrate of this example, an island-shaped semiconductor film 102 made of a semiconductor film such as n ⁺ polysilicon or amorphous silicon is formed at a corner portion of each pixel region on a transparent substrate, and covers the semiconductor film 102 and the substrate 100. Thus, the gate insulating film 103 is formed, the previous gate wiring G is formed on the gate insulating film 103, and the gate electrode 105 is formed by being drawn out from the gate wiring G onto the central portion of the semiconductor film 102. Note that a portion facing the gate electrode 105 with the gate insulating film 103 interposed therebetween is a channel portion 102 a of the semiconductor film 102.

  An upper insulating film 106 is formed to cover the gate insulating film 103, the gate wiring G thereon and the gate electrode 105, and the source wiring S is formed on the upper insulating film 106. An extended source electrode 107 is connected to one end of the semiconductor film 102 through a contact hole 108 formed in the insulating films 103 and 106 on one end of the semiconductor film 102. Next, a contact hole 109 is also formed in the insulating films 103 and 106 on the other end of the semiconductor film 102, and the drain electrode 110 connected to the other end of the semiconductor film 102 through the contact hole 109. Is formed on the insulating film 106.

  Then, a passivation film 111 made of an insulating film is formed so as to cover the source electrode 107, the drain electrode 110, and the upper insulating film 106, the pixel electrode 101 is formed on the passivation film 111, and the pixel electrode 101 is formed on the passivation film 111. The source wiring S is connected to the drain electrode 110 through the formed contact hole 112 and is formed on the insulating film 111 at one end of the source wiring S through the contact hole 113 formed in the passivation film 111. Pad-like terminals 115 connected to a part 114 are formed, and a thin film transistor T6 having a cross-sectional structure is formed in FIG.

Next, a process for manufacturing this type of top gate thin film transistor array substrate structure will be described with reference to FIGS. A semiconductor film made of polysilicon and a base insulating film made of SiO ₂ are laminated on a transparent substrate 100 such as glass, and these are patterned by a photolithography process to form an island-like semiconductor film 120 and a gate lower insulating film 121 shown in FIG. Form. Next, a gate insulating film and an electrode film for forming a gate electrode are stacked and patterned by a photolithography process to form a gate insulating film 122 and a gate electrode 123 as shown in FIG.

  Next, ion doping is performed, ion doping is performed on both sides of the semiconductor film 120, and these are covered with an intermediate insulating film 125, and contact holes 126 and 127 that are connected to both ends of the semiconductor film 120 are formed in the intermediate film 125. A source electrode 128 connected to one side of the semiconductor film 120 through the contact holes 126 and 127 is formed on the intermediate insulating film 125 as shown in FIG. 35, and further connected to the other side of the semiconductor film 120. A drain electrode 129 is formed.

  Subsequently, an insulating film is formed thereon as shown in FIG. 36 to form a passivation film 130. A contact hole 131 leading to the source electrode 128 and a contact hole 132 leading to the drain electrode 129 are formed in the passivation film 130 in FIG. Form as shown. Further, a pixel electrode 133 made of ITO (indium tin oxide) communicating with the drain electrode 129 through the contact hole 132 is formed on the passivation film 130, and the source electrode 128 is formed on the passivation film 130 through the contact hole 131. By forming the ITO terminal electrode 135 leading to, a thin film transistor T7 having a top gate structure as shown in FIG. 37 can be obtained, and this thin film transistor T7 has a structure equivalent to the thin film transistor T6 described above.

  In the top gate type thin film transistor T7 having the structure shown in FIG. 37, a contact is made with the passivation film 130 in order to connect the pixel electrode 133 and the drain electrode 129 and in order to connect the terminal electrode 135 and the source wiring S. Since it is necessary to form the holes 131 and 132, there is a problem that a photolithographic process for forming a contact hole, that is, an exposure process, a dry etching process, a stripping process, and a cleaning process for forming the contact hole are required, thereby reducing the number of processes. There was a difficult situation. Also, the thin film transistor T6 having the structure shown in FIGS. 29 to 31 has the same problem as the thin film transistor T7 because it has the same structure as the thin film transistor T7 shown in FIG.

Next, the reason why the pixel electrode 133 is provided after providing the passivation film 130 as described above will be described. When the ITO pixel electrode 133 is directly connected to the drain electrode 129 without providing the passivation film 130, the source electrode is used as an etching solution for etching the ITO when the ITO pixel electrode 133 is patterned by a photolithography process. 128 and the drain electrode 129 are also immersed, but the source electrode 128 and the drain electrode 129 are also etched by an etching solution (HCl: HNO ₃ : H ₂ O = 1: 0.08: 1) for etching ITO. There is a risk of damage.

  For this reason, conventionally, the source electrode 128 and the drain electrode 129 are once covered with a passivation film 130, and then a ITO transparent conductive film is formed and patterned to form the pixel electrode 133 and the terminal electrode 135. However, in such a structure, since the passivation film 130 is necessarily required, a series of processes necessary for forming the passivation film 130 is required, and there is a problem that the number of processes increases.

  The present invention has been made in view of the above circumstances, and can eliminate the passivation film conventionally required for the thin film transistor substrate structure, reduce the number of processes, and form a contact hole necessary for the passivation film. It is an object to provide a thin film transistor substrate in which the number of processes is reduced. Another object of the present invention is to provide a liquid crystal display device including a thin film transistor substrate having such characteristics.

  The present invention is characterized in that a source terminal made of indium tin zinc oxide or indium zinc oxide is directly connected to the source wiring. By directly connecting a source terminal made of indium tin zinc oxide or indium zinc oxide to the source wiring, an insulating film such as a passivation film which has been conventionally required on the source wiring can be made unnecessary. Contact holes that were necessary in the past are also unnecessary. Therefore, the process for forming the insulating film can be omitted, and the process necessary for forming the contact hole is not necessary, and the process can be simplified. In the present invention, it is preferable that the source wiring is any one of aluminum, copper, molybdenum, chromium, titanium, tantalum and tungsten, or an alloy thereof. If the source wiring is made of these materials, by selecting an etching solution for indium tin zinc oxide or indium zinc oxide, indium tin zinc oxide or indium zinc oxide can be used without damage to the etching solution. Source terminals can be formed.

  The present invention is characterized in that a gate terminal made of indium tin zinc oxide or indium zinc oxide is directly connected to the gate wiring. By directly connecting a gate terminal made of indium tin zinc oxide or indium zinc oxide to the gate wiring, an insulating film such as a passivation film which has been conventionally required on the gate wiring can be made unnecessary. Contact holes that were necessary in the past are also unnecessary. Therefore, the process for forming the insulating film can be omitted, and the process necessary for forming the contact hole is not necessary, and the process can be simplified.

  In the present invention, it is preferable that the gate wiring is one of aluminum, copper, molybdenum, chromium, titanium, tantalum, and tungsten, or an alloy thereof. If the gate wiring is made of these materials, indium tin zinc oxide or indium zinc oxide can be used without damage to the etching liquid by selecting an etching liquid for indium tin zinc oxide or indium zinc oxide. A gate terminal can be formed.

  The present invention is characterized in that a pixel electrode made of indium tin zinc oxide or indium zinc oxide is directly connected to a drain electrode forming a thin film transistor for switching a plurality of pixel electrodes. By directly connecting the pixel electrode made of indium tin zinc oxide or indium zinc oxide to the drain electrode, an insulating film such as a passivation film that has been conventionally required on the drain electrode can be made unnecessary. Contact holes that were necessary in the past are also unnecessary. Therefore, the process for forming the insulating film can be omitted, and the process necessary for forming the contact hole is not necessary, and the process can be simplified. In the present invention, it is preferable that the drain electrode is any one of aluminum, copper, molybdenum, chromium, titanium, tantalum, and tungsten, or an alloy thereof. If the drain electrode is made of these materials, it is possible to select indium tin zinc oxide or indium zinc oxide etching solution without damaging the etching solution. A pixel electrode can be formed.

  Furthermore, in the present invention, a plurality of gate wirings and a plurality of source wirings are formed in a matrix on a substrate having an insulating surface at least, and a pixel electrode is provided in each region surrounded by these wirings. A thin film transistor serving as a switching element of the pixel electrode is provided in connection with the electrode, the gate wiring, and the source wiring, and a gate terminal made of indium zinc oxide is directly connected to each of the gate wirings. A source terminal made of indium tin zinc oxide or indium zinc oxide is directly connected to each, and a pixel electrode made of indium tin zinc oxide or indium zinc oxide is directly connected to the drain electrode of the thin film transistor. The following structure can be adopted.

  Indium tin zinc oxide or indium zinc oxide gate terminal is directly connected to the gate wiring, indium tin zinc oxide or indium zinc oxide source terminal is directly connected to the source wiring, and indium tin zinc oxide is connected to the drain electrode. Insulating zinc oxide pixel electrodes can be directly connected to eliminate the need for conventional insulation films such as passivation films on the gate, source and drain electrodes. The contact hole which was was also unnecessary. Therefore, the process for forming the insulating film can be omitted, and the process necessary for forming the contact hole is not necessary, and the process can be simplified.

  In the present invention, the indium tin zinc oxide is composed of a composite oxide containing indium oxide, tin oxide, and zinc oxide, and the atomic ratio of zinc to the total amount of zinc, indium, and tin is 1 at% to 9 atomic%, the atomic ratio of tin to zinc is 1 or more, and the atomic ratio of tin to the total amount of zinc, indium and tin is 20 atomic% or less, and at least a part of the crystalline It is preferable to have it. In such a composition range, an indium tin zinc oxide that is amorphous at the time of film formation, can be etched with a weak acid, can be crystallized by heat treatment, and can have low resistance can be obtained. In the present invention, the atomic ratio of zinc to the total amount of zinc, indium and tin is 2 at% to 7 at%, and the atomic ratio of tin to the total amount of zinc, indium and tin is 5 at% to 10 at%. Preferably there is.

  The present invention can employ a configuration in which the thin film transistor substrate according to any one of the above is used as one of the pair of substrates sandwiching the liquid crystal. Thereby, in the manufacturing process of the thin film transistor substrate of the liquid crystal display device, the creation of the passivation film as the insulating film can be omitted, and the contact hole of the passivation film can be omitted, so that the manufacturing process can be simplified. .

    The present invention eliminates the need for an insulating film such as a passivation film conventionally required on a source wiring by directly connecting the source terminal made of indium tin zinc oxide or indium zinc oxide to the source wiring in the thin film transistor substrate. In addition, a contact hole that is conventionally required for the insulating film can be eliminated. Therefore, the process for forming the insulating film can be omitted, and the process necessary for forming the contact hole is not necessary, and the process can be simplified. Further, in the thin film transistor substrate, a gate terminal made of indium tin zinc oxide or indium zinc oxide is directly connected to the gate wiring, or a pixel electrode made of indium tin zinc oxide or indium zinc oxide is connected to the drain electrode. By directly connecting, an insulating film such as a passivation film which has been conventionally required can be eliminated, and a contact hole which has been conventionally required for the insulating film can be eliminated. Therefore, the process for forming the insulating film can be omitted, and the process necessary for forming the contact hole is not necessary, and the process can be simplified.

Each embodiment of the present invention will be described in detail below, but the present invention is not limited to these embodiments.
“First Embodiment”
FIG. 1 is a plan view of an essential part of a thin film transistor (array) substrate H1 provided with a thin film transistor T1 according to a first embodiment of the present invention. FIG. 2 is a sectional view of an essential part of a liquid crystal display device E provided with the thin film transistor array substrate H1. 3 is a partial sectional view of the apparatus. In the thin film transistor (array) substrate H1 of this embodiment, a plurality of gate lines G ... and a plurality of source lines S ... are arranged in a matrix in plan view on a transparent substrate 1 made of glass or the like. Has been. A region surrounded by the gate wiring G... And the source wiring S... Is a pixel, and transparent conductive material ITZO (indium tin zinc oxide) or IZO (indium) is used for each pixel region. A pixel electrode 2 made of zinc oxide) is provided in a state of being positioned above the substrate 1, and a thin film transistor T1 as a switching element is provided at a corner of each pixel region. The substrate 1 may be a substrate having at least a surface having insulation and a necessary portion being transparent. For example, when the substrate 1 is applied to the liquid crystal display device E, a substrate in which a portion corresponding to a pixel region contributing to display is at least a transparent region and a light shielding film such as a black matrix is incorporated in the other portion may be used. Of course.

  In the thin film transistor array substrate H1 of this example, an island-shaped semiconductor active film 3 made of polysilicon, amorphous silicon (a-Si), or the like is formed in the thin film transistor forming portion at the corner of each pixel region on the substrate 1, and the substrate A lower gate insulating film 5 is laminated on the semiconductor active film 3 and the upper surface of the substrate, and a plurality of gate lines G are formed on the lower gate insulating film 5 in parallel with each other as shown in FIG. In addition, a strip-shaped gate electrode 6 is formed so as to extend on the central portion of the semiconductor active film 3 in each pixel region in each gate wiring G. The semiconductor active film 3 has a channel portion 3a formed at the center thereof, and both ends thereof are doped with ions.

  Further, an upper gate insulating film 7 is laminated on the lower gate insulating film 5 so as to cover the lower gate insulating film 5, the gate wirings G, and the gate electrodes 6. The upper gate insulating film 7 and the lower gate insulating film 5 have a contact hole 8 connected to one end of the semiconductor active film 3 and a contact hole 9 connected to the other end of the semiconductor active film 3. Each is formed and extends on the upper gate insulating film 7 at a portion on one side end of the semiconductor active film 3 and passes through the contact hole 8 to be connected to one side end of the semiconductor active film 3. A drain electrode 10 is formed and extends on the upper gate insulating film 7 in a portion on the other end of the semiconductor active film 3 and passes through the contact hole 9 to the other end of the semiconductor active film 3. A source electrode 11 connected to is formed. Therefore, the semiconductor active film 3, the lower gate insulating film 5, the upper gate insulating film 7, the gate electrode 6, the drain electrode 10, and the source electrode 11 constitute a thin film transistor T1.

  Next, the region surrounded by the source wiring S and the gate wiring G, and occupies most of the region surrounded by the source wiring S and the gate wiring G on the upper gate insulating film 7. The portion excluding the region where the source electrode 11 is formed, the portion where the semiconductor active film 3 is formed, and the portion where the gate electrode 6 is formed is in close contact with the upper gate insulating film 7 and directly in close contact with the end of the drain electrode 10. Thus, the pixel electrode 2 is formed.

  Further, a part of the source line S formed on the end side (only the upper end part is shown in FIG. 1) is directly stacked on the end part SE1 of the source line S, and the other part is used as the upper gate. A gate terminal 12 made of ITZO (indium tin zinc oxide) or IZO (indium zinc oxide) laminated on the insulating film 7 is formed. Further, a part of the gate wiring G is formed on the end GE1 of the gate wiring G directly on each end side (only the left end is shown in FIG. 1), and the other part is used as the upper gate. A gate terminal 13 made of ITZO (indium tin zinc oxide) or IZO (indium zinc oxide) laminated on the insulating film 7 is formed.

  In the structure of this embodiment, the pixel electrode 2 made of ITZO or IZO is formed in direct contact with the upper gate insulating film 7 and is further formed in direct contact with the drain electrode 10. Unlike the conventional structure shown in FIGS. 29 to 31, the passivation film 111 is omitted. By adopting such a structure, the process for forming the passivation film 111 can be simplified, and the process for forming the contact holes 112, 108, 113 formed in the passivation film 111 can be omitted. Simplification can be promoted.

  When the structure shown in FIGS. 1 to 3 is adopted, when the pixel electrode 2 is patterned by etching in the patterning process of the pixel electrode 2, the drain electrode 10 and the source electrode 11 are also immersed in the etching solution of the pixel electrode 2. However, an etching solution for etching the pixel electrode 2 made of ITZO or IZO can be selected such as oxalic acid or hydrochloric acid that does not damage the constituent metal materials of the drain electrode 10 and the source electrode 11 as will be described later. Therefore, the drain electrode 10 and the source electrode 11 are not damaged when the pixel electrode 2 is etched.

  Next, in the structure shown in FIGS. 1 to 3, a liquid crystal display device is configured by sealing liquid crystal 16 between a thin film transistor array substrate and a transparent substrate 15 facing the thin film transistor array substrate, and is provided on the counter substrate 15 side. The common electrode 17 and the pixel electrode 2 are configured such that the alignment of the liquid crystal can be controlled depending on whether or not an electric field is applied to the liquid crystal. Here, the source terminal 12... And the gate terminal 13... Are provided on the outside of a sealing material (not shown) that seals the liquid crystal 16. Are connected. That is, since a terminal of a driving LSI called a tape carrier package is connected, an ITZO or IZO source terminal 12... And a gate terminal 13. It is preferable to ensure connectivity.

A method for manufacturing a thin film transistor (array) substrate having a structure equivalent to the structure shown in FIGS. 1 to 3 will be described below with reference to FIGS. A semiconductor film made of polysilicon or amorphous silicon and a base insulating film made of SiO ₂ are laminated on a transparent substrate 1 such as glass, and these are patterned by a photolithography process to form an island-like semiconductor film 20 and a gate lower portion shown in FIG. An insulating film 21 is formed. Next, a gate insulating film and an electrode film for forming a gate electrode are stacked and patterned by a photolithography process to form a gate insulating film 22 and a gate electrode 23 as shown in FIG.

  Next, ion doping is performed, ion doping is performed on both sides of the semiconductor film 20, and these are further covered with the intermediate insulating film 25. Contact holes 26 and 27 that lead to both ends of the semiconductor film 20 are formed in the intermediate insulating film 25. A source electrode 28 is formed on the intermediate insulating film 25 and connected to one side of the semiconductor film 20 through the contact holes 26 and 27 described above, and further connected to the other side of the semiconductor film 20. A drain electrode 29 is formed.

Next, an IZO (Indium Zinc Oxide) layer or ITZO (Indium Tin Zinc Oxide) layer is laminated on the whole and then patterned by a photolithography process to form the pixel electrode 30 as shown in FIG. The source terminal 31 is formed on the end side of the source line S, and the gate terminal is formed on the end side of the gate line G. Here, as the IZO layer used, indium oxide (InO _x) 90% zinc oxide (ZnO _x) can be illustrated a layer of 10% of the mixture. As an etchant for etching the IZO layer, an acid such as oxalic acid: (COOH) ₂ or hydrochloric acid: HCl can be used. As the oxalic acid, for example, one having a concentration of 0.6 mol / l can be used, and as the hydrochloric acid, one having a concentration of 3.5% can be used. Of course, it may be oxalic acid or hydrochloric acid.

As the ITZO layer to be used, a composite oxide containing indium (In) oxide (In ₂ O ₃ ), tin (Sn) oxide (SnO ₂ ), and zinc (Zn) oxide (ZnO) as main components is used. The layer which consists of can be illustrated. It should be noted that impurities of about several at% may be included in addition to these main component oxides.

  In this ITZO layer, since it is used in connection with other wirings or conductors, it is necessary to mix at least more tin than zinc in the connection part with these and to show crystallinity. For example, when connecting with wiring or other conductors in the surface portion of the ITZO layer, it is necessary that the composition of the surface portion contains at least tin more than zinc and exhibits crystallinity.

  Next, in the ITZO layer, the atomic ratio of zinc to the total amount of zinc, indium and tin is 1 at% to 9 at%, the atomic ratio of tin to zinc is 1 or more, and zinc, indium and tin The atomic ratio of tin to the total amount is 20 at% or less, more preferably 1 at% or more and 20 at% or less. Further, the atomic ratio of zinc to the total amount of zinc, indium and tin is 2 at% to 7 at%, and the atomic ratio of tin to the total amount of zinc, indium and tin is 5 at% to 10 at%. It is more preferable. Furthermore, in the composition range of indium, the atomic ratio of indium with respect to the total amount of zinc, indium and tin is 98 at% or less and 75 at% or more.

  The indium oxide in the ITZO layer is a main component, and excess indium that is not bonded to oxygen in the composite oxide generates electron carriers and constitutes an oxygen deficient conductive mechanism. The tin oxide as an additive component is important for activating tetravalent tin in the composite oxide to generate electron carriers. Further, when the composite oxide is in an amorphous state, the divalent zinc of the zinc oxide is not activated, so that it does not become an acceptor that consumes electron carriers. The composition range is selected in consideration of the balance of these additives.

  When the ITZO layer having the above-described composition is used for actual wiring, it is preferable that a connection portion with another wiring or terminal is at least crystalline. The ITZO layer having the above composition range is an amorphous film as it is normally formed, but it can be easily crystallized by performing an annealing process (heating process at a temperature of 180 ° C. to 300 ° C.) for heating it above the crystallization temperature. Turn into. The heat treatment temperature can be properly selected according to the heat resistance temperature of the surrounding circuit and the substrate. However, when used for a liquid crystal panel described later, the heat treatment temperature of the peripheral circuit and the substrate is preferably 250 ° C. or less, 200 ° C. It is considered that about ° C is more preferable.

The ITZO layer having the above composition has a high contact resistance (about 41Ω) with a conductor (end of source wiring, gate wiring, or TCP: tape carrier package) in the amorphous state as it is formed, and is used for connecting fine wiring. Although it cannot be said that the resistance is good, it is heat-treated at the previous temperature to crystallize at least the surface portion (depth about 50 mm from the surface), thereby reducing the resistance of at least the connection portion (about 2.3Ω) )can do. The heat treatment atmosphere for the crystallization may be any of air, N ₂ atmosphere, H ₂ 20%, N ₂ 80% atmosphere, O ₂ 20%, N ₂ 80% atmosphere, and vacuum atmosphere. Note that since the crystallized oxide transparent conductive film can prevent bonding with moisture (or oxygen) in the atmosphere, the connection resistance does not increase over time. In addition, the amorphous ITZO layer having the above composition can be easily etched with a weak acid such as dilute hydrochloric acid or an organic acid. Therefore, the amorphous oxide transparent conductive film remains in the amorphous state and is patterned and patterned. After the patterning, a necessary part such as a wiring connection part is heat-treated to reduce the resistance of the wiring connection part, so that a low resistance connection can be achieved even in a fine circuit connection part.

  Next, the ITZO layer having the above-described composition can be obtained by forming a film on the upper surface of an insulating substrate or the like by a film formation method such as sputtering film formation, and performing heat treatment. A target having the following composition is preferred as the target. The composition of the target that can be suitably used is a composite oxide containing indium oxide, tin oxide, and zinc oxide, and the atomic ratio of zinc to the total amount of zinc, indium, and tin is 1 at% to 12 at%. The atomic ratio of tin to zinc is 1 or more, and the atomic ratio of tin to the total amount of zinc, indium and tin is 22 at% or less. Further, as the aforementioned target, the atomic ratio of zinc to the total amount of zinc, indium and tin is 2 at% to 10 at%, and the atomic ratio of tin to the total amount of zinc, indium and tin is 5 at% to More preferably, it is 12 at%.

  In the target used to obtain the oxide transparent conductive film having the above composition, zinc and tin are likely to be scattered when sputtered and are not easily taken into the film. A composition containing a large amount is acceptable.

  Incidentally, when the IZO layer or the ITZO layer is etched with the etching solution, the source wiring S, the source electrode 28, and the gate electrode 29 are immersed in the etching solution, but oxalic acid is used as the etching solution. In this case, the source wiring S, the source electrode 28, and the gate electrode 29 can be formed from a metal such as Al, Cu, Mo, Cr, Ti, Ta, W, or an alloy thereof, and diluted hydrochloric acid is used as an etching solution. When used, the source wiring S, the source electrode 28, and the gate electrode 29 can be formed from a metal such as Cu, Mo, Cr, Ti, Ta, or W. However, when dilute hydrochloric acid is used as an etching solution, it is not preferable to use Al for wiring or electrodes because Al is damaged by hydrochloric acid. In addition, etching can be performed using a weak acid such as an organic acid.

  Note that in the case of using the ITZO layer, it is necessary to form an amorphous ITZO layer and then perform etching to form a connection portion with a conductor portion of another layer. If the ITZO layer has the above composition, it can be etched with a weak acid such as dilute hydrochloric acid or an organic acid instead of a strong acid as an etching solution, so that the amount of side etching can be reduced, and a fine structure can be obtained by etching. be able to. Then, after fine etching is performed on the ITZO layer to form pixel electrodes of a prescribed size, if these layers are heated to a temperature higher than the crystallization temperature to crystallize the amorphous ITZO layer, the crystallized portion Therefore, the connection with the drain electrode and the connection with the terminal portion can be performed with a low resistance. As described above, if the ITZO layer is etched in an amorphous state and then crystallized by heat treatment for low resistance connection, a structure having a connection portion with a low connection resistance is obtained even for a fine wiring portion. be able to.

  Through the above steps, a thin film transistor T2 having a cross-sectional structure shown in FIG. 8 can be obtained. The thin film transistor T2 obtained in this way has a structure substantially equivalent to the thin film transistor T1 described above with reference to FIGS. 1 to 3, the pixel electrode 30 is directly connected to the drain electrode 29, and the source terminal 31 is the source. Since the gate terminals of the wiring are directly connected to the gate terminals, a passivation film as an insulating film, which has been conventionally required, can be omitted on the source electrode 28 and the drain electrode 29. Conventionally, the passivation film is formed on the passivation film. This eliminates the need for the contact hole that has been formed, so that the passivation film can be omitted as described above, and the contact hole formed in the passivation film can also be omitted, which contributes to simplification of the process. More specifically, the step of forming the passivation film itself, the exposure step for forming the contact hole, the dry etching step, the stripe step, and the cleaning step can be omitted.

“Second Embodiment”
FIG. 9 is a plan view of an essential part of a thin film transistor (array) substrate H3 including the thin film transistor T3 according to the second embodiment of the present invention, and FIG. 12B is a sectional view of the essential part of the thin film transistor portion. In FIG. 12B, the description of the configuration on the counter substrate side and the liquid crystal for configuring the liquid crystal display device is omitted. However, when the liquid crystal display device is configured using the thin film transistor array substrate H3 illustrated in FIG. Similarly to the case shown in the drawing, the counter substrate and the liquid crystal can be combined with the thin film transistor array substrate H3 shown in FIG. 12B.

  In the thin film transistor (array) substrate H3 of this embodiment, a plurality of gate lines G ... and a plurality of source lines S ... are arranged in a matrix in plan view on a transparent substrate 1 made of glass or the like. Has been. A region surrounded by the gate wiring G... And the source wiring S... Is a pixel, and transparent conductive material ITZO (indium tin zinc oxide) or IZO (indium) is used for each pixel region. A pixel electrode 32 made of zinc oxide is provided in a state of being positioned above the substrate 1, and a thin film transistor T3 as a switching element is provided at a corner of each pixel region.

In the thin film transistor array substrate H3 of this example, a strip-shaped gate electrode 33 drawn from the gate wiring G is formed in the thin film transistor forming portion at the corner of each pixel region on the transparent substrate. A gate insulating film 34 is formed so as to cover the gate electrode 33, and an island-like semiconductor active film 35 made of polysilicon, amorphous silicon (a-Si) or the like is formed on the gate insulating film 34 on the gate electrode 33. It is provided so as to cross over A source electrode 37 is stacked on one end of the semiconductor active film 35 via an ohmic contact layer 36 made of amorphous silicon (a-Si: n ⁺ ) containing n-type impurities such as phosphorus, and the semiconductor active film A drain electrode 38 is stacked on the other end portion of 35 via a similar ohmic contact layer 36, and the source electrode 37 and the drain electrode 38 are opposed to each other above the gate electrode 33, while the source electrode 37 is the source wiring S In addition, the drain electrode 38 is directly laminated on the pixel electrode 32 described later to form a thin film transistor T3.

  Next, a region surrounded by the source wiring S and the gate wiring G, and occupies most of the region surrounded by the source wiring S and the gate wiring G on the gate insulating film 34, and the source The electrode 37 is formed in close contact with the gate insulating film 34 except for the region where the electrode 37 is formed, the portion where the semiconductor active film 35 is formed, and the portion where the gate electrode 38 is formed, and is directly stacked on the end side of the drain electrode 38. A pixel electrode 32 is formed on the substrate.

  A source terminal 42 made of IZO or ITZO partially laminated directly on the end portion SE2 of the source wiring S is provided on each end portion side of the plurality of source wirings S (only the upper end portion is described). Is formed. Furthermore, a part of the gate wiring G formed on each end side (only the left end portion is shown in FIG. 1) is directly laminated on the end GE2 of the gate wiring G, and the other part is placed on the substrate 1. A gate terminal 43 made of IZO or ITZO is formed.

  Although the liquid crystal and the counter substrate are omitted in the structure shown in FIG. 12B, the liquid crystal display device is configured by sealing the liquid crystal between the thin film transistor array substrate H3 and the counter substrate shown in FIG. 12A. This is equivalent to the case of the first embodiment.

  In the structure of this embodiment, the pixel electrode 32 made of IZO or ITZO is formed in direct contact with the gate insulating film 34, and further directly stacked on the drain electrode 38. Unlike the conventional structure shown in FIG. 31, the passivation film 111 is omitted. By adopting such a structure, the process for forming the passivation film 111 can be simplified, and the process for forming the contact holes 112, 108, 113 formed in the passivation film 111 can be omitted. Simplification can be promoted.

  9 and 12B, when the pixel electrode 32 is patterned by etching in the patterning process of the pixel electrode 32, the drain electrode 38 and the source electrode 37 are also immersed in the etching solution of the pixel electrode 32. As described above, as an etching solution for etching the pixel electrode 32 made of IZO or ITZO, an oxalic acid or hydrochloric acid that does not damage the constituent metal materials of the drain electrode 38 and the source electrode 37 is used. Therefore, the drain electrode 38 and the source electrode 37 are not damaged. Similarly, when the pixel electrode 32 is patterned by etching in the patterning process of the pixel electrode 32, the end portion SE2 of the source wiring S and the end portion GE2 of the gate wiring G are also immersed in the etching solution of the pixel electrode 32. However, as an etchant for etching the pixel electrode 32 made of IZO or ITZO, the constituent metals of the end portion SE2 of the source wiring S and the end portion GE2 of the gate wiring G such as oxalic acid and hydrochloric acid as described above are used. Since a weak acid that does not damage the material can be selected, the source terminal 42 and the gate terminal 43 can be formed without damaging the end SE2 of the source wiring S and the end GE2 of the gate wiring G.

  Hereinafter, a method of manufacturing a thin film transistor (array) substrate having the structure shown in FIGS. 9 and 12B using four masks will be described with reference to FIGS. 10 to 12A. A metal film made of the above-described metal material is formed on a transparent substrate 1 such as glass, and this metal film is patterned by a photolithography process using a first mask to form a gate wiring G and a gate electrode 33 as shown in FIG. And an end portion GE2 of the gate wiring is formed. Next, a gate insulating film 34, a semiconductor film 35 made of polysilicon or amorphous silicon, an ohmic contact film 36, and a metal film 45 are laminated on them as shown in FIG. 11, and these are used using a second mask. All the films covering the gate wiring end portion and the source wiring end portion are removed by patterning in a photolithography process, and these end portions are exposed.

  Next, in a photolithography process using a third mask, the metal film 45 and the ohmic contact film 36 are patterned to form a source electrode 37 and a drain electrode 38 so as to face each other on the gate electrode 33 as shown in FIG. 12A.

Next, an IZO layer or ITZO layer is laminated on the entire surface, and then patterned by a photolithography process using a fourth mask to form a pixel electrode 32 as shown in FIG. A source terminal 42 is formed on the portion side, and a gate terminal 43 is formed on the end portion side of the gate wiring G. Here, it can be illustrated as IZO layer, an indium oxide (InO _x) 90%, zinc oxide layer (ZnO _x) a mixture containing 10% to be used. As an etchant for etching the IZO layer, an acid such as oxalic acid: (COOH) ₂ or hydrochloric acid: HCl can be used. For example, oxalic acid having a concentration of 0.6 mol / l can be used, and hydrochloric acid having a concentration of 3.5% can be used. Further, it is possible to as ITZO layer, indium tin oxide (InO _x) 85%, tin oxide (SnO _x) 10%, illustrating the layers of a mixture containing zinc oxide (ZnO _x) 5% . Further, an etching solution for etching the ITZO layer can be the same as that used for the IZO layer.

  When the aforementioned IZO layer or ITZO layer is etched with the etching solution, the source wiring S, the source electrode 37, and the gate electrode 38 are immersed in the etching solution. When oxalic acid is used as the etching solution, When the source wiring S, the source electrode 37 and the gate electrode 38 can be formed from a metal such as Al, Cu, Mo, Cr, Ti, Ta, W or an alloy thereof, and hydrochloric acid is used as an etching solution, The source wiring S, the source electrode 37, and the gate electrode 38 can be formed from a metal such as Cu, Mo, Cr, Ti, Ta, or W or an alloy thereof. However, when hydrochloric acid is used as an etching solution, using Al for wiring or electrodes is not preferable because Al is damaged. Note that when the ITZO layer is used, it is amorphous and has high resistance at the stage where the ITZO layer is formed by a film formation method. Therefore, after the etching process is completed, heat treatment is performed by heating to 180 ° C. or higher in an appropriate process. It is necessary to reduce the resistance of the connecting portion (surface portion).

  Through the above steps, the thin film transistor array substrate H3 including the thin film transistor T3 having a cross-sectional structure shown in FIG. 12B can be obtained. In the thin film transistor T3 thus obtained, the pixel electrode 32 is directly connected to the drain electrode 38, the source terminal 42 is directly connected to the source wiring S, and the gate terminal 43 is directly connected to the gate wiring G. A passivation film as an insulating film which has been conventionally required can be omitted on the 37 and the drain electrode 38, and a contact hole which has been conventionally formed in the passivation film is not necessary. Contributes to simplification. More specifically, the step of forming the passivation film itself, the exposure step for forming the contact hole, the dry etching step, the stripe step, and the cleaning step can be omitted.

“Third Embodiment”
FIG. 13 is a plan view of an essential part of a thin film transistor (array) substrate H5 having a thin film transistor T5 according to a third embodiment of the present invention, and FIG. 19 is a sectional view of the essential part of the thin film transistor portion. In the thin film transistor (array) substrate H5 of this embodiment, a plurality of gate lines G ... and a plurality of source lines S ... are arranged in a matrix in plan view on a transparent substrate 1 made of glass or the like. Has been. A region surrounded by the gate wiring G... And the source wiring S... Is a single pixel, and a pixel electrode 52 made of transparent conductive material IZO or ITZO is formed on the substrate 1 for each pixel region. A thin film transistor T5 serving as a switching element is provided at a corner of each pixel region.

In the thin film transistor array substrate H5 of this example, a strip-shaped gate electrode 53 drawn from the gate wiring G is formed in the thin film transistor forming portion at the corner of each pixel region on the transparent substrate. A gate insulating film 54 is formed so as to cover the gate electrode 53, and an island-like semiconductor active film 55 made of polysilicon, amorphous silicon (a-Si) or the like is formed on the gate insulating film 54 on the gate electrode 53. It is provided so that it may be located above. A source electrode 57 is formed on one end of the semiconductor active film 55 via an ohmic contact film 56 made of amorphous silicon (a-Si: n ⁺ ) containing n-type impurities such as phosphorus, and the semiconductor active film A drain electrode 58 is formed on the other end of 55 via a similar ohmic contact film 56, and the source electrode 57 and the drain electrode 58 are opposed to each other above the gate electrode 53, while the source electrode 57 is connected to the source wiring S In addition, the drain electrode 58 is directly connected to a pixel electrode 52, which will be described later, to form a thin film transistor T5.

  Next, the region surrounded by the source wiring S and the gate wiring G, and occupies most of the region surrounded by the source wiring S and the gate wiring G on the gate insulating film 54, and the source It is in close contact with the gate insulating film 54 in the portion excluding the region where the electrode 57 is formed, the portion where the semiconductor active film 55 is formed, and the portion where the gate electrode 58 is formed, and is in direct contact with the end of the drain electrode 58. A pixel electrode 52 is formed. Further, a source made of IZO or ITZO partially laminated directly on the end portion SE3 of the source wiring S is provided on each end portion side (only the upper end portion is shown in FIG. 13) of the formed source wiring S. A terminal 62 is formed. Furthermore, a part of the gate wiring G is formed on the end GE3 of the gate wiring G directly on each end side (only the left end is shown in FIG. 1), and the other part is placed on the substrate 1. A gate terminal 63 made of IZO or ITZO is formed.

  Although the liquid crystal and the counter substrate are omitted in the structure shown in FIG. 19, the liquid crystal display device is configured by sealing the liquid crystal between the thin film transistor array substrate H5 and the counter substrate shown in FIG. This is equivalent to the case of the first embodiment.

  In the structure of this embodiment, the pixel electrode 52 made of IZO or ITZO is formed in direct contact with the gate insulating film 54, and further directly stacked on the drain electrode 58. Unlike the conventional structure shown, the passivation film 111 is omitted. By adopting such a structure, the process for forming the passivation film 111 can be simplified, and the process for forming the contact holes 112, 108, 113 formed in the passivation film 111 can be omitted. Simplification can be promoted.

  Here, when the structure shown in FIG. 13 is adopted, when the pixel electrode 52 is patterned by etching in the patterning process of the pixel electrode 52, the drain electrode 58 and the source electrode 57 are also immersed in the etching solution of the pixel electrode 52. However, as the etching solution for etching the pixel electrode 52 made of IZO or ITZO, one that does not damage the constituent metal materials of the drain electrode 58 and the source electrode 57 such as oxalic acid or hydrochloric acid can be selected as described above. Therefore, the drain electrode 58 and the source electrode 57 are not damaged.

  Similarly, when the pixel electrode 52 is patterned by etching in the patterning process of the pixel electrode 52, the end portion SE3 of the source wiring S and the end portion GE3 of the gate wiring G are also immersed in the etching solution of the pixel electrode 52. However, as an etchant for etching the pixel electrode 52 made of IZO or ITZO, the constituent metals of the end portion SE3 of the source wiring S and the end portion GE3 of the gate wiring G such as oxalic acid and hydrochloric acid as described above are used. Since a material that does not damage the material can be selected, the source terminal and the gate terminal can be formed without damaging the end portion SE3 of the source wiring S and the end portion GE3 of the gate wiring G.

  A method of manufacturing the thin film transistor (array) substrate having the structure shown in FIGS. 13 and 19 using five masks will be described below with reference to FIGS. A metal film made of the above-described metal material is formed on a transparent substrate 1 such as glass, and this metal film is patterned by a photolithography process using a first mask to form a gate wiring G and a gate electrode 53 as shown in FIG. And an end portion GE3 of the gate wiring is formed.

  Next, a gate insulating film 54, a semiconductor active film 551 made of polysilicon or amorphous silicon, and an ohmic contact film 561 are laminated on them as shown in FIG. 15, and these are formed by a photolithography process using a second mask. By patterning, only the semiconductor active film 551 and the ohmic contact film 561 on the gate insulating film 54 on the gate electrode 53 are left as shown in FIG. Next, a metal film 59 is laminated on them as shown in FIG. 17, and the metal film 59 is patterned in a photolithography process using a third mask to form one side of the semiconductor active film 55 as shown in FIG. A source electrode 57 is formed on one end of the semiconductor active film 55 at one end via an ohmic contact film 561, and at the same time a semiconductor electrode is formed on the other end of the semiconductor active film 55 via an ohmic contact film 56. A drain electrode 58 is formed on the other side end of the active film 55 so as to overlap the tip.

Next, the gate insulating film 54 around the end portion GE3 of the gate wiring G and the end portion SE3 of the source wiring S is removed by a photolithography process using a fourth mask as shown in FIG. Next, an IZO layer or ITZO layer is laminated on the entire surface, and then patterned by a photolithography process using a fifth mask to form a pixel electrode 52 as shown in FIG. 19, and at the same time as shown in FIG. A source terminal 62 is formed on the end SE3 side of the source wiring S, and a gate terminal 63 is formed on the end GE3 side of the gate wiring G as shown in FIG. Here, as the IZO layer used, indium oxide (InO _x) 90% zinc oxide (ZnO _x) can be illustrated a layer of 10% of the mixture. As an etchant for etching the IZO layer, an acid such as oxalic acid: (COOH) ₂ or hydrochloric acid: HCl can be used. For example, oxalic acid having a concentration of 0.6 mol / l can be used, and hydrochloric acid having a concentration of 3.5% can be used. Further, it is possible to as ITZO layer, indium tin oxide (InO _x) 85%, tin oxide (SnO _x) 10%, illustrating the layers of a mixture containing zinc oxide (ZnO _x) 5% . Further, an etching solution for etching the ITZO layer can be the same as that used for the IZO layer.

  When the aforementioned IZO layer or ITZO layer is etched with the etching solution, the source wiring S, the source electrode 57, and the gate electrode 58 are immersed in the etching solution. When oxalic acid is used as the etching solution, When the source wiring S, the source electrode 57 and the gate electrode 58 can be formed from a metal such as Al, Cu, Mo, Cr, Ti, Ta, W or an alloy thereof, and hydrochloric acid is used as an etching solution, The source wiring S, the source electrode 57, and the gate electrode 58 can be formed from a metal such as Cu, Mo, Cr, Ti, Ta, or W or an alloy thereof. However, when hydrochloric acid is used as an etching solution, using Al for wiring or electrodes is not preferable because Al is damaged. Note that when the ITZO layer is used, it is amorphous and has high resistance at the stage where the ITZO layer is formed by a deposition method. Therefore, after the etching process is completed, heat treatment is performed by heating to 200 ° C. or higher in an appropriate process. It is necessary to reduce the resistance of the connecting portion (surface portion).

  Through the above steps, a thin film transistor T5 having a cross-sectional structure shown in FIG. 19 can be obtained. In the thin film transistor T5 thus obtained, the pixel electrode 52 is directly connected to the drain electrode 58, and the source terminal 62 is directly connected to the source line S and the gate terminal 63 is directly connected to the gate line G. A passivation film as an insulating film which has been conventionally required can be omitted on the 57 and the drain electrode 58, and a contact hole which has been conventionally formed in the passivation film is also unnecessary. Contributes to simplification. More specifically, the step of forming the passivation film itself, the exposure step for forming the contact hole, the dry etching step, the stripe step, and the cleaning step can be omitted.

Indium tin oxide film (ITO film, In: Sn = 92 at%) on a plurality of glass substrates under the conditions of room temperature film formation and O ₂ partial pressure of 6.3 × 10 ⁻³ Pa (5 × 10 ⁻⁵ Torr) : 8 at%, thickness 1200 mm) and indium tin zinc oxide film “ITZO film: In ₂ O ₃ —SnO ₂ —ZnO film” (In: Sn: Zn = 88 at%: 9 at%: 3 at%, thickness 1200 mm) And an indium zinc oxide film (IZO film: In: Zn = 82 at%: 18 at%, thickness 1200 mm) were individually formed by a sputtering apparatus, and the X-ray diffraction peak of each film was obtained. The target used here is an In: Sn = 90 at%: 10 at% target in the case of an ITO film, and an In: Sn: Zn = 85 at%: 10 at%: 5 at% target in the case of an ITZO film. In the case of an IZO film, a target having a composition of In: Zn = 83 at%: 17 at% was used. Further, for the indium zinc film and the indium tin zinc film, the X-ray diffraction peak after heat treatment was performed by heating to 250 ° C. for 2 hours in an annealing furnace in an atmosphere of 20% H ₂ / N ₂ was also obtained. FIG. 21 shows the result of the ITO film, FIG. 22 shows the result of the ITZO film, and FIG. 23 shows the result of the IZO film.

From the results shown in FIG. 21, FIG. 22 and FIG. 23, it was found that when the film was formed at room temperature, the ITO film showed crystallinity, and the ITZO film and the IZO film were both amorphous films showing broad curves. It was also found that the ITZO film crystallizes when heat-treated, but the IZO film does not crystallize even when heat-treated. From the above, it has been clarified that the ITZO film having the composition according to the present invention is in an amorphous state in a film formation state but can be crystallized by heat treatment. In addition, the ITZO film exhibited a resistance of 600 × 10 ⁻⁶ Ω · cm in the amorphous state as it was formed, but after the heat treatment, the resistance became 250 × 10 ⁻⁶ Ω · cm and should be crystallized from the amorphous state. It was confirmed that the resistance value decreased.

  FIG. 24 is a graph showing whether the indium tin zinc oxide film according to the present invention is in an amorphous phase state or a polycrystalline state after heat treatment. In the vertical axis of FIG. 24, Zn / (In + Sn + Zn) [at%] indicates the atomic ratio of zinc to the total amount of zinc, indium and tin, and the horizontal axis is Sn / (In + Sn + Zn) [at%]. Indicates the atomic ratio of tin to the total amount of zinc, indium and tin.

  The a line drawn in FIG. 24 shows the composition of Zn: 1 at% with respect to the total amount of zinc, indium and tin, the b line shows the composition of Zn: 9 at% with respect to the total amount of zinc, indium and tin, and the c line is The composition when the atomic ratio of tin to zinc is 1 is shown. In FIG. 24, the composition range below the a line is a composition range in which the oxide transparent conductive film becomes a polycrystalline phase during film formation and cannot be easily etched with a weak acid. In FIG. 24, the composition range above the b line is a composition range in which the amorphous state film as it is formed is kept amorphous even after heat treatment (annealing), and the connection resistance cannot be lowered. It is a range. Further, in FIG. 24, the c line indicates that the composition ratio of zinc and tin is the same, so that the ratio of consumption of electron carriers by zinc increases, and in the composition range above the c line, zinc that consumes electron carriers. This is a composition range in which a low resistance connection cannot be made due to an excessively large amount. In addition, even if the composition range is a region below the c line, it means that the resistance tends to increase as it approaches the c line.

  Further, a film in which the vertical axis zinc amount in FIG. 24 is 10 at%, the horizontal axis tin quantity is 5 at%, and the vertical axis zinc quantity is 10 at%, and the horizontal axis tin quantity is 9 at%. These are samples that did not crystallize even when subjected to heat treatment at 300 ° C. On the other hand, a film in which the vertical axis zinc amount is 5 at%, the horizontal axis tin amount is 8 at%, and the vertical axis zinc amount is 5 at%, and the horizontal axis tin amount is 9 at%. All of them could be crystallized by heat treatment at 230 ° C. Furthermore, the film in which the vertical axis zinc amount is 3 at%, the horizontal axis tin amount is 6 at%, and the vertical axis zinc amount is 3 at%, and the horizontal axis tin amount is 9 at%. Crystallization was possible by heat treatment at 200 ° C.

  From the above, it has been found that the crystallization temperature can be lowered by reducing the amount of zinc. Moreover, when the oxide transparent conductive film according to the present invention is applied to an electronic device, the heat treatment temperature is preferably as low as possible from the limitation of the heat resistance temperature of the substrate or various films laminated thereon. Therefore, in order to lower the heat treatment temperature and at the same time reduce the connection resistance, it can be considered that it is preferable that both the amount of zinc and the amount of tin added to indium are small.

  Furthermore, in order to satisfactorily satisfy these various conditions, after satisfying the condition that the atomic ratio of tin to zinc exceeds 1, the zinc content is within the range of 1 at% or more and 9 at% or less. The range of 2 at% or more and 7 at% or less is more preferable, and regarding the tin content, the range of 5 at% or more and 10 at% or less is more preferable even in the range of 20 at% or less.

  Next, FIG. 25 shows the ITZO film as-deposited (as.depo state) in 60 seconds corresponding to the tin content when the zinc addition amount (Zn addition amount) is fixed at 5 at%. The result of having measured the change of the etching amount of is shown. The etchant used was a 3.5% strength hydrochloric acid solution (weak acid solution). From the results shown in FIG. 25, it is clear that the etching amount decreases as the amount of Sn added increases. Therefore, it was found that the fine wiring using the oxide transparent conductive film according to the present invention can be handled by appropriately selecting the etching rate (E / R) by adjusting the amount of tin added. However, since the etching amount obtained when the Sn addition amount is 20 at% is small, the etching time becomes longer and the processing time increases even if the Sn addition amount is further increased. Therefore, the upper limit of the addition amount is preferably 20 at%. .

  FIG. 26 shows the transmission of the transparent oxide conductive film obtained when the zinc addition amount (Zn addition amount) is set to 3 at% and the tin addition amount (Sn) is set to 9 at% in the ITZO film as it is formed. The wavelength dependence of the rate is shown. From the results shown in FIG. 26, it is clear that the oxide transparent conductive film according to the present invention exhibits excellent transmittance exceeding 90% in the visible light region (approximately 450 nm to 750 nm). This value is equivalent to that of a transparent conductive film of an indium tin oxide film that has been used conventionally, or more excellent depending on the wavelength. Therefore, it is clear that a bright display can be obtained even when the transparent oxide conductive film according to the present invention is used as a pixel electrode or a transparent wiring for a liquid crystal panel.

FIG. 27 shows the result of measuring the dependence of the resistance value of the as-deposited film and the resistance value of the annealed film on the oxygen partial pressure (O ₂ partial pressure) in the deposition atmosphere in the ITZO film having the above composition. 2 shows the oxygen partial pressure dependence on the etching rate (E / R) of an amorphous ITO film. An amorphous a-ITO film with a low etching rate (E / R) can be obtained by finely adjusting the oxygen partial pressure in the ITO film, but if the oxygen partial pressure is not adjusted precisely, etching is partially performed. There is a tendency that a-ITO films having different rates (E / R) are generated. This is because when an a-ITO film is etched to form a wiring, an a-ITO film is likely to cause uneven etching due to variations in oxygen partial pressure during film formation. It means that it is difficult to obtain precisely.

FIG. 28 shows the result of a reliability test after TCP connection. Each measured value is shown in Table 1 below. The TCP resistance in Table 1 is a connection by TCP (connection with a metal terminal electrode having a width of 40 × 10 ⁻⁶ cm), and a resistance value between any two is measured. The average value of 50 connection parts is shown. The reliability test is a measurement of a resistance value after high temperature and high humidity (80 ° C., 90% RH, 240 hours).

"Table 1"
H ₂ anneal film structure initial TCP ITO film without resistance after reliability test polycrystalline 〇 1.1Ω Rei_1.9Omu
a-ITO film Available Polycrystalline ○ 1.4Ω ○ 2.0Ω
ITZO film Yes Polycrystalline ○ 3.7Ω ○ 2.3Ω
No IZO film Amorphous × 7.4Ω × 41.3Ω
ITZO film None Amorphous (× 7.4Ω) (× 41.3Ω)

  From these results, it was found that the contact resistance of the IZO film and the a-ITO film increases in the air over time. It was also found that a-ITO was crystallized by the annealing treatment and stabilized with a low contact resistance. Although not shown in Table 1, the annealed IZO film was found to be amorphous by X-ray diffraction, and although the contact resistance was improved, it was not improved to the same extent as the ITO film. As a reliability test, an equivalent test was performed in an environment of high temperature dry 80 ° C., 10% RH, 240H, but the same result as that shown in FIG. 28 could be obtained. From these test results, it was found that the resistance can be lowered by annealing the ITZO film in an amorphous state, and that the low resistance can be maintained even after the environmental test.

  As described above, according to the present invention, in the thin film transistor substrate, the source terminal made of indium tin zinc oxide or indium zinc oxide is directly connected to the source wiring, thereby insulating the passivation film or the like conventionally required on the source wiring. A film can be dispensed with, and a contact hole conventionally required for the insulating film can be dispensed with. Therefore, the process for forming the insulating film can be omitted, and the process necessary for forming the contact hole is not necessary, and the process can be simplified. Further, in the thin film transistor substrate, a gate terminal made of indium tin zinc oxide or indium zinc oxide is directly connected to the gate wiring, or a pixel electrode made of indium tin zinc oxide or indium zinc oxide is connected to the drain electrode. By directly connecting, an insulating film such as a passivation film which has been conventionally required can be eliminated, and a contact hole which has been conventionally required for the insulating film can be eliminated. Therefore, the process for forming the insulating film can be omitted, and the process necessary for forming the contact hole is not necessary, and the process can be simplified.

  In each of the structures described above, the source wiring, the gate wiring, or the drain electrode is preferably made of any one of aluminum, copper, molybdenum, chromium, titanium, tantalum, and tungsten, or an alloy thereof. By selecting these materials, it is possible to prevent the source wiring, the gate wiring, or the drain electrode from being damaged by the etching solution for etching indium zinc oxide.

  In addition, if the thin film transistor array substrate has the source wiring, the gate wiring, and the drain electrode having the structure described above, and the source terminal, the gate terminal, and the pixel electrode described above, a conventionally required passivation film or the like can be used. An insulating film can be dispensed with, and a contact hole that is conventionally necessary for the insulating film can be dispensed with. Therefore, the process for forming the insulating film can be omitted, and the process necessary for forming the contact hole is not necessary, and the process can be simplified. More specifically, the step of forming the passivation film itself, the exposure step for forming the contact hole, the dry etching step, the stripe step, and the cleaning step can be omitted.

  In the liquid crystal display device having the thin film transistor array substrate having this structure, an insulating film such as a passivation film which has been conventionally required can be made unnecessary, and a contact hole which has been conventionally required for the insulating film is also unnecessary. Can be. Therefore, the process for forming the insulating film can be omitted, and the process necessary for forming the contact hole is not necessary, and the process can be simplified.

1 is a schematic plan view showing a main part of a first embodiment of a thin film transistor substrate according to the present invention. FIG. 2 is a cross-sectional view of a main part of the first embodiment of the thin film transistor substrate shown in FIG. FIG. 2 is a partial cross-sectional view of the first embodiment of the thin film transistor substrate shown in FIG. 1. Sectional drawing which is for demonstrating the method to manufacture the structure of 1st Embodiment shown in FIGS. 1-3, and has laminated | stacked the semiconductor film and the insulating film on the board | substrate. Sectional drawing which shows the state which formed the gate insulating film and the gate electrode on the board | substrate for demonstrating the method. Sectional drawing which shows the state which formed the insulating film on the board | substrate for demonstrating the method. Sectional drawing which shows the state which formed the contact hole in the insulating film on a board | substrate for the same method, and connected the source electrode and the drain electrode to the semiconductor active film. Sectional drawing which shows the state which connected the source terminal to the source wiring edge part, and the pixel electrode to the drain electrode edge part each for the same method. FIG. 5 is a schematic plan view showing a main part of a second embodiment of a thin film transistor substrate according to the present invention. Sectional drawing which is for demonstrating the method to manufacture the structure of 2nd Embodiment shown in FIG. 9, and has formed the gate electrode and gate wiring on the board | substrate. Sectional drawing which shows the state which formed the gate insulating film, the semiconductor active film, the ohmic contact film | membrane, and the metal film on the board | substrate for demonstrating the method. FIG. 12A is a sectional view showing a state in which necessary portions of the metal film, ohmic contact film, and gate insulating film on the substrate are patterned, and FIG. 12B is obtained by forming pixel electrodes and terminals. Sectional drawing which shows 2nd Embodiment of the obtained thin-film transistor. FIG. 6 is a schematic plan view showing a main part of a third embodiment of a thin film transistor substrate according to the present invention. FIG. 14 is a cross-sectional view illustrating a state in which a gate electrode and a gate wiring are formed on a substrate for explaining a method of manufacturing the structure of the third embodiment shown in FIG. 13. Sectional drawing which shows the state which laminated | stacked the gate insulating film, the semiconductor active film, and the metal film on the board | substrate for demonstrating the method. Sectional drawing which shows the state which formed the island-like ohmic contact film | membrane and the semiconductor active film on the gate insulating film above the gate electrode on a board | substrate for demonstrating the method. For explaining the method, an electrode film is formed on the ohmic contact film and the semiconductor active film on the substrate. Sectional drawing which shows the state which formed the thin-film transistor above the gate electrode for demonstrating the method. FIG. 14 is a cross-sectional view illustrating a state in which a pixel electrode and a terminal are formed to obtain the thin film transistor substrate having a planar structure illustrated in FIG. FIG. 20 is a cross-sectional view showing a source wiring terminal portion in the thin film transistor having the structure shown in FIG. 19. FIG. 21 is a diagram showing an X-ray diffraction test result of the ITO film. FIG. 22 is a view showing an X-ray diffraction test result of the ITZO film. FIG. 23 is a view showing an X-ray diffraction test result of the IZO film. FIG. 24 is a diagram showing the zinc content dependency and the tin content dependency when the transparent oxide conductive film according to the present invention is in a crystallized state or an amorphous state. FIG. 25 is a diagram showing the etching amount dependency on the tin addition amount in the oxide transparent conductive film according to the present invention. FIG. 26 is a diagram showing the wavelength dependence of light transmittance in an oxide transparent conductive film according to the present invention. FIG. 27 is a diagram showing the oxygen partial pressure dependency during film formation with respect to the specific resistance value of the oxide transparent conductive film according to the present invention and the oxygen partial pressure dependency during film formation with respect to the etching rate of the ITO film. FIG. 28 is a view showing a reliability test result of TCP connection resistance of the oxide transparent conductive film according to the present invention. 1 is a schematic plan view showing an example of a conventional thin film transistor substrate. FIG. 30 is a fragmentary cross-sectional view of the conventional thin film transistor substrate shown in FIG. 29. FIG. 30 is a partial cross-sectional view of the conventional thin film transistor substrate shown in FIG. 29. Sectional drawing which is for demonstrating the method of manufacturing the conventional thin-film transistor substrate, and shows the state which formed the island-shaped semiconductor film and the lower insulating film on the board | substrate. Sectional drawing which shows the state which formed the gate insulating film and the gate electrode on the lower insulating film for demonstrating the method. Sectional drawing which shows the state which formed the source electrode and the drain electrode for demonstrating the method. Sectional drawing which shows the state which formed the passivation film for demonstrating the method. Sectional drawing which shows the state which formed the contact hole in the passivation film for demonstrating the method. Sectional drawing which shows the state which formed the pixel electrode and terminal electrode of ITO for demonstrating the method.

Explanation of symbols

  E ... Liquid crystal display device, H1, H3, H5 ... Thin film transistor array substrate, S ... Source wiring, G ... Gate wiring, 1 ... Substrate, 2 ... Pixel electrode, 12, 42, 62 ... Source terminal, 13, 43, 63 ... Gate terminal, 15 ... Counter substrate, T1, T2, T3, T5 ... Thin film transistor, 10, 29, 38, 58 ... Drain electrode, 11 , 28, 37, 57 ... source electrodes.

Claims (2)

Forming a thin film transistor near the intersection of the gate wiring and the source wiring on the substrate; forming a gate terminal directly connected to the gate wiring; a source terminal directly connected to the source wiring; and a pixel electrode directly connected to the thin film transistor In the method of manufacturing a thin film transistor substrate including the step of:
Forming the gate terminal, the source terminal, and the pixel electrode;
And stacking the Lee indium tin zinc oxide (ITZO) layer on the substrate on which the thin film transistor is formed,
Patterning the ITZO layer;
A step of crystallizing at least a surface portion of the ITZO layer was heat-treated at the I TZO layer 180 ° C. to 300 ° C. temperature,
A method for manufacturing a thin film transistor substrate, comprising: The heat treatment in the crystallization stage is performed in any one of air, N ₂ atmosphere, H ₂ / N ₂ atmosphere, O ₂ / N ₂ atmosphere, and vacuum atmosphere. 2. The method of manufacturing a thin film transistor substrate according to claim 1, wherein

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