JP4703189B2 - インタリーブされたメモリコントローラとともに用いるために再構成可能な処理要素を１つ以上のマイクロプロセッサに結合するスイッチ／ネットワークアダプタポート - Google Patents

インタリーブされたメモリコントローラとともに用いるために再構成可能な処理要素を１つ以上のマイクロプロセッサに結合するスイッチ／ネットワークアダプタポート Download PDF

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JP4703189B2
JP4703189B2 JP2004566539A JP2004566539A JP4703189B2 JP 4703189 B2 JP4703189 B2 JP 4703189B2 JP 2004566539 A JP2004566539 A JP 2004566539A JP 2004566539 A JP2004566539 A JP 2004566539A JP 4703189 B2 JP4703189 B2 JP 4703189B2
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computer system
memory
coupled
adapter port
control block
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フッペンサル，ジョン・エム
シーマン，トーマス・アール
バートン，リー・エイ
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エス・アール・シィ・コンピューターズ・インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP2004566539A 2003-01-10 2003-12-12 インタリーブされたメモリコントローラとともに用いるために再構成可能な処理要素を１つ以上のマイクロプロセッサに結合するスイッチ／ネットワークアダプタポート Expired - Fee Related JP4703189B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/340,390 2003-01-10
US10/340,390 US7197575B2 (en) 1997-12-17 2003-01-10 Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
PCT/US2003/039609 WO2004064413A2 (en) 2003-01-10 2003-12-12 Switch/network adapter port coupling a reconfigurable processing element for microprocessors with interleaved memory controllers

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Publication Number Publication Date
JP2006513492A JP2006513492A (ja) 2006-04-20
JP2006513492A5 JP2006513492A5 (enExample) 2007-02-01
JP4703189B2 true JP4703189B2 (ja) 2011-06-15

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JP2004566539A Expired - Fee Related JP4703189B2 (ja) 2003-01-10 2003-12-12 インタリーブされたメモリコントローラとともに用いるために再構成可能な処理要素を１つ以上のマイクロプロセッサに結合するスイッチ／ネットワークアダプタポート

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US (1) US7197575B2 (enExample)
EP (1) EP1588272A4 (enExample)
JP (1) JP4703189B2 (enExample)
AU (1) AU2003296986A1 (enExample)
CA (1) CA2508344A1 (enExample)
WO (1) WO2004064413A2 (enExample)

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US9530483B2 (en) 2014-05-27 2016-12-27 Src Labs, Llc System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem
US9153311B1 (en) 2014-05-27 2015-10-06 SRC Computers, LLC System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers
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Also Published As

Publication number Publication date
US20050076152A1 (en) 2005-04-07
WO2004064413A3 (en) 2005-01-27
EP1588272A2 (en) 2005-10-26
CA2508344A1 (en) 2004-07-29
WO2004064413A2 (en) 2004-07-29
EP1588272A4 (en) 2008-10-22
US7197575B2 (en) 2007-03-27
AU2003296986A1 (en) 2004-08-10
JP2006513492A (ja) 2006-04-20

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