CA2508344A1 - Switch/network adapter port coupling a reconfigurable processing element for microprocessors with interleaved memory controllers - Google Patents

Switch/network adapter port coupling a reconfigurable processing element for microprocessors with interleaved memory controllers Download PDF

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Publication number
CA2508344A1
CA2508344A1 CA002508344A CA2508344A CA2508344A1 CA 2508344 A1 CA2508344 A1 CA 2508344A1 CA 002508344 A CA002508344 A CA 002508344A CA 2508344 A CA2508344 A CA 2508344A CA 2508344 A1 CA2508344 A1 CA 2508344A1
Authority
CA
Canada
Prior art keywords
computer system
memory
coupled
adapter port
control block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002508344A
Other languages
English (en)
French (fr)
Inventor
Jon M. Huppenthal
Thomas R. Seeman
Lee A. Burton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SRC Computers LLC
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2508344A1 publication Critical patent/CA2508344A1/en
Abandoned legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
CA002508344A 2003-01-10 2003-12-12 Switch/network adapter port coupling a reconfigurable processing element for microprocessors with interleaved memory controllers Abandoned CA2508344A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/340,390 2003-01-10
US10/340,390 US7197575B2 (en) 1997-12-17 2003-01-10 Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
PCT/US2003/039609 WO2004064413A2 (en) 2003-01-10 2003-12-12 Switch/network adapter port coupling a reconfigurable processing element for microprocessors with interleaved memory controllers

Publications (1)

Publication Number Publication Date
CA2508344A1 true CA2508344A1 (en) 2004-07-29

Family

ID=32711321

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002508344A Abandoned CA2508344A1 (en) 2003-01-10 2003-12-12 Switch/network adapter port coupling a reconfigurable processing element for microprocessors with interleaved memory controllers

Country Status (6)

Country Link
US (1) US7197575B2 (enExample)
EP (1) EP1588272A4 (enExample)
JP (1) JP4703189B2 (enExample)
AU (1) AU2003296986A1 (enExample)
CA (1) CA2508344A1 (enExample)
WO (1) WO2004064413A2 (enExample)

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US7886103B2 (en) * 2008-09-08 2011-02-08 Cisco Technology, Inc. Input-output module, processing platform and method for extending a memory interface for input-output operations
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US20130157639A1 (en) 2011-12-16 2013-06-20 SRC Computers, LLC Mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption
CN103399827B (zh) * 2013-07-25 2015-11-25 华为技术有限公司 存储装置、执行访问操作的系统和方法
US9530483B2 (en) 2014-05-27 2016-12-27 Src Labs, Llc System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem
US9153311B1 (en) 2014-05-27 2015-10-06 SRC Computers, LLC System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers
US10572430B2 (en) 2018-10-11 2020-02-25 Intel Corporation Methods and apparatus for programming an integrated circuit using a configuration memory module

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Also Published As

Publication number Publication date
US20050076152A1 (en) 2005-04-07
WO2004064413A3 (en) 2005-01-27
JP4703189B2 (ja) 2011-06-15
EP1588272A2 (en) 2005-10-26
WO2004064413A2 (en) 2004-07-29
EP1588272A4 (en) 2008-10-22
US7197575B2 (en) 2007-03-27
AU2003296986A1 (en) 2004-08-10
JP2006513492A (ja) 2006-04-20

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Legal Events

Date Code Title Description
FZDE Discontinued