JP4702295B2 - Semiconductor manufacturing apparatus and semiconductor inspection apparatus - Google Patents

Description

  The present invention relates to a sample holder for holding a sample such as a semiconductor wafer, a semiconductor manufacturing apparatus having the sample holder, a semiconductor inspection apparatus, and a sample holding method.

  With the miniaturization of circuit patterns on semiconductor wafers, circuit pattern inspection apparatuses using electron beams have been put into practical use.

For example, Japanese Patent Publication No. 59-192943 (Patent Document 1), Japanese Patent Publication No. 5-258703 (Patent Document 2), Sandland, et al., “An electron-beam inspection system”.
for x-ray maskproduction ”, J. Vac. Sci. Tech. B, Vol.9, No.6, pp.3005-3009
(1991) (Non-patent document 1), Meisburger, et al., “Requirements and performance of an electron-beam column designed for x-ray mask inspection”, J. Vac. Sci. Tech. B, Vol. 9, No. .6, pp.3010-3014 (1991) (non-patent document 2), Meisburger, et al., “Low-voltage electron-optical system for the high-speed inspection of integrated”
circuits ”, J. Vac. Sci. Tech. B, Vol. 10, No. 6, pp. 2804-2808 (1992) (non-patent literature 3), literature Hendricks, et al.,“ Characterization of a New Automated Electron ” -Beam
A technique described in “Wafer Inspection System”, SPIE Vol. 2439, pp.174-183 (20-22 February, 1995) (Non-Patent Document 4) is known.

  In order to perform high-throughput and high-accuracy inspection following the increase in wafer diameter and circuit pattern miniaturization, it is necessary to acquire a high SN image at a very high speed. Therefore, the number of electrons irradiated using a large current beam 100 times or more (10 nA or more) of a normal scanning electron microscope (SEM) is secured, and a high SN ratio is maintained. Furthermore, high-speed and highly efficient detection of secondary electrons and reflected electrons generated from the substrate is essential.

Further, the semiconductor substrate with an insulating film such as a resist is irradiated with a low acceleration electron beam of 2 KeV or less so as not to be affected by charging. About this technology, the Japan Society for the Promotion of Science 132nd edition edited by "Electron / Ion Beam Handbook (2nd edition)" (Nikkan Kogyo Shimbun, 1986)
(Non-Patent Document 5) pp. 622 to 623. However, an electron beam with a large current and a low acceleration causes aberration due to the space charge effect, and high-resolution observation is difficult.

  As a method for solving this problem, there is known a method in which a high acceleration electron beam is decelerated immediately before a sample and irradiated on the sample as a substantially low acceleration electron beam. For example, there are techniques described in Japanese Patent Publication No. Hei 2-1442045 (Patent Document 3) and Japanese Patent Publication Hei 6-139985 (Patent Document 4).

  Hereinafter, an outline of an example of an electron optical system of a circuit pattern inspection apparatus according to the prior art will be described with reference to FIG. FIG. 9 is a schematic diagram of an electron optical system of a circuit pattern inspection apparatus in the prior art.

  The primary electron beam 201 emitted from the electron gun 1 by the voltage of the extraction electrode 2 passes through the condenser lens 3, the scanning deflector 5, the diaphragm 6, the shield pipe 7, the objective lens 9, etc., and is converged and deflected to be XY. Irradiated to a substrate 10 to be inspected such as a semiconductor device on the stage 11 and the rotary stage 12. A deceleration voltage (hereinafter referred to as a retarding voltage) is applied to the substrate 10 to be inspected from the high-voltage power source 23 for primary electron beam deceleration. From the substrate 10 to be inspected, the first secondary electrons 202 are generated by the irradiation of the primary electron beam 201. The first secondary electrons 202 are accelerated to energy of several keV by the retarding voltage. An E-cross B deflector 8 is provided adjacent to the objective lens 9 on the electron gun side.

  The E-cross B deflector 8 deflects the deflection amount due to the electric field and the magnetic field with respect to the primary electron beam 201 and deflects electrons with respect to the first secondary electron 202 by superimposing the two. It is a vessel. The accelerated first secondary electrons 202 are deflected by the E-cross B deflector 8, and further, the suction voltage between the suction electrode 14 externally attached to the secondary electron detector 13 and the secondary electron detector 13. Is attracted to the electric field formed by the light and enters the secondary electron detector 13.

  The secondary electron detector 13 is a semiconductor detector. The first secondary electrons 202 enter the semiconductor detector and form electron-hole pairs, which are taken out as current and converted into electrical signals. This output signal is further amplified by the preamplifier 21 and becomes a luminance modulation input for the image signal. After obtaining an image of one area on the substrate by the above-described operation of the electron optical system, the image output signal is delayed by one screen, and an image of the second area is obtained in the same manner. The two images are compared by an image comparison / evaluation circuit, and a defective portion of the circuit pattern is detected. Here, the irradiation position of the primary electron beam 201 is determined as a position where the beam is irradiated onto the substrate by the scanning deflection signal input to the scanning deflector 5.

  However, when the surface height of the substrate varies due to wafer warpage or the like, even if scanning is performed with the same deflection signal, the region of the actual substrate irradiation position of the electron beam varies, and beam deflection to the same region is obtained. I can't.

Therefore, conventionally, the following deflection correction technique has been adopted in electron beam application apparatuses such as an electron beam drawing apparatus.
(1) At least two samples with standard marks having different thicknesses are placed on the outermost peripheral portion of the sample table, and the positional deviation of the image signal of the standard mark at each height is calculated.
(2) Along with the calculation of the positional deviation, an optical sensor that sequentially measures the height of the sample surface is installed and operated to convert the standard mark height into a signal.
(3) A deflection correction table corresponding to the height is calculated and stored from the positional deviation between the standard mark height signal and the image signal, and a deflection correction signal corresponding to the height of the substrate surface is calculated when the substrate is observed. To correct the deflection.

  This technology makes it possible to irradiate the same deflection region with an electron beam regardless of the height of the wafer surface by correcting the deflection signal even when the wafer surface height fluctuates due to warpage of the semiconductor wafer or the like. . This technique is described in, for example, Japanese Patent Publication No. 56-103420 (Patent Document 5). According to the present technology, it is possible to easily update the deflection correction table by observing the reference mark on the outer periphery any number of times while holding the wafer. Therefore, even with respect to drift due to time variation of the electron beam optical system of the primary beam deflection, the standard mark is observed again about a dozen times at regular time intervals during the processing of one wafer, and the deflection correction table is set each time. By updating, the deflection correction can follow the time change.

  However, a circuit pattern inspection apparatus that embodies the deflection correction method as described above has not been realized so far.

  The gist of the present invention is to employ the above-described deflection correction method as the deflection correction method corresponding to the warp of the wafer also in the circuit pattern inspection apparatus. However, when this deflection correction method is employed as it is in a circuit pattern inspection apparatus, there are the following problems.

  By applying a retarding voltage to the substrate, the primary electron beam is affected by a retarding electric field immediately before irradiating the substrate.

  In general, the change in electric field is distributed symmetrically with respect to the central axis of the primary electron beam. Therefore, the primary electron beam is deflected to a desired region by adjusting the deflection sensitivity uniformly regardless of the wafer position. be able to. However, at the outer periphery of the wafer, there is a problem in that an asymmetrical retarding electric field is generated in the axis due to the cross-sectional shape of the wafer itself and the cross-sectional structure of the end of the sample stage on which the wafer is placed.

  In the circuit pattern inspection device, a signal is obtained by scanning once with a large current, so that the retarding voltage is several times higher than that of other electron beam application devices in order to irradiate the beam with a desired beam diameter and low acceleration. It is. Therefore, there is a problem that the amount of change in the retarding electric field is larger than that of other electron beam application apparatuses.

  Therefore, there is a problem that a non-negligible difference, so-called beam distortion, occurs in the substrate irradiation region of the primary beam by the same deflection signal depending on whether or not the observation position of the substrate is near the outer peripheral portion on the wafer.

  In this situation, as in other electron beam application apparatuses, when a deflection correction table is created by providing two standard marks with different thicknesses on the outermost periphery of the sample stage, the outer circumference of the sample stage is added to the deflection correction table. The influence of beam distortion peculiar to the part is added. As a result, even if the deflection correction table is referred to from the measurement result of the sample surface height at the center of the sample stage, an appropriate deflection correction signal for the position cannot be obtained, and the beam has a problem that the irradiation position shifts. is there.

  This beam irradiation position shift causes a pixel shift of the image signal obtained thereby, which causes a decrease in accuracy in the image comparison inspection. If this pixel deviation exceeds a certain allowable range, there is a problem that a critical inspection accuracy is lowered in a circuit pattern inspection apparatus for the purpose of comparative inspection of images.

  On the other hand, among semiconductor manufacturing apparatuses and semiconductor inspection apparatuses, in an electron beam application apparatus that performs processing or inspection by irradiating a sample with an electron beam, the electron beam must be irradiated in a vacuum. Further, in order to improve the processing accuracy of the sample or improve the resolution of the image obtained at the time of inspection, it is necessary to control the irradiation energy intensity of the generated electron beam.

  In recent years, an electron beam drawing apparatus that processes a semiconductor pattern by irradiating an electron beam, a length measuring SEM (scanning electron microscope length measuring apparatus) that measures the width of the pattern on the semiconductor surface, and the semiconductor material is irradiated with an electron beam. In an electron beam application apparatus such as an analysis SEM for analyzing by this, a method called retarding is applied in which a voltage is applied to a sample in order to control the irradiation energy intensity of the electron beam. This technique is described in, for example, Japanese Patent Publication No. 5-258703 (Patent Document 2) and Japanese Patent Publication No. 6-188294 (Patent Document 6).

  However, in the sample holders of electron beam application apparatuses such as these length measurement SEMs and analysis SEMs, no consideration has been given to the fluctuation of the electric field generated at the end of the sample due to the application of the retarding voltage. As a result, the accuracy of the relationship between the irradiation position of the electron beam and the sample position is significantly reduced due to the fluctuation of the electric field even if the electron beam is radiated to the edge of the sample. This part could not be processed, analyzed or inspected.

JP 59-192943 A JP-A-5-258703 JP-A-2-142045 JP-A-6-139985 JP-A-56-103420 JP-A-6-188294 Sandland, et al., “An electron-beam inspection system for x-ray maskproduction”, J. Vac. Sci. Tech. B, Vol.9, No.6, pp.3005-3009 (1991) Meisburger, et al., “Requirements and performance of an electron-beam column designed for x-ray mask inspection”, J. Vac. Sci. Tech. B, Vol. 9, No. 6, pp. 3010-3014 (1991 ) Meisburger, et al., “Low-voltage electron-optical system for the high-speed inspection of integrated circuits”, J. Vac. Sci. Tech. B, Vol. 10, No. 6, pp. 2804-2808 (1992) Hendricks, et al., “Characterization of a New Automated Electron-Beam Wafer Inspection System”, SPIE Vol. 2439, pp.174-183 (20-22 February, 1995) The 132nd Committee of the Japan Society for the Promotion of Science "Electron / Ion Beam Handbook (2nd edition)" (Nikkan Kogyo Shimbun, 1986)

  A first object of the present invention is to prevent a decrease in the accuracy of the relationship between the electron beam irradiation position at the end of the sample and the sample position, thereby enabling processing, analysis, and inspection.

  A second object of the present invention is to irradiate a sample with an electron beam without reducing the accuracy of the irradiation position in an electron beam application apparatus having a function of controlling electron beam irradiation energy with a retarding voltage.

  As a means for achieving the first object of the present invention, a typical example of a circuit pattern inspection apparatus according to the present invention will be described.

  The circuit pattern inspection apparatus according to the present invention includes an irradiation optical system that converges the primary charged particle beam and scans and deflects the first and second regions of the circuit pattern of the sample, deceleration of the primary charged particle beam, and irradiation thereof. Acceleration / deceleration means for accelerating secondary charged particles and reflected electrons generated from the sample, a sample stage for holding the sample, a sensor for measuring the surface height of the irradiation position of the primary charged particle beam on the sample, and In a circuit pattern inspection apparatus having a detector for detecting charged particles generated from a sample and an image forming means for forming an image of an irradiation area of the sample from the detection signal, the sample stage is placed on the outer periphery of a substrate installation portion. An image of a standard mark sample at the center of at least two substrate mounting portions, which is substantially the same as the standard mark sample, so that at least two standard mark samples having different thicknesses in the beam axis direction can be set. Storage means for storing the signal, computing means for calculating the distortion amount of the primary charged particle beam peculiar to the outer peripheral portion from the both standard mark image signals, and removing the distortion amount peculiar to the outer peripheral portion from the outer peripheral portion standard mark image signal. Removing means, creating means for storing a deflection correction table corresponding to the sample height from the outer peripheral standard mark image signal after removing the distortion amount, and the deflection according to the surface height signal obtained by the sensor. A deflection correction signal generating means for extracting a deflection correction signal from the correction table, and a control means for irradiating the outer periphery standard mark sample at a desired timing and updating the deflection correction table are provided.

  Note that a shield electrode is provided in the vicinity of the substrate in order to reduce disturbance of the retarding electric field.

  The circuit pattern inspection apparatus and method having the above configuration will be described functionally. The circuit pattern inspection apparatus can obtain the distortion amount peculiar to the outer periphery of the sample by comparing the height dependency of the sample surface of the deflection correction amount at the center of the sample stage with the outer periphery of the sample. If the height dependency of the deflection correction amount is calculated by removing the distortion amount peculiar to the outer periphery from the standard mark signal at the outer periphery, the correction amount equivalent to the deflection correction amount obtained at the center can be known. .

  In addition, since an appropriate deflection correction table can be created from only the standard marks on the outer peripheral portion, the table can be updated by calculating the deflection correction table at the outer peripheral portion as many times as desired while the wafer is installed. . As a result, it is possible to accurately obtain a deflection correction table including surface height dependency that can follow beam drift and the like without reducing throughput.

  On the other hand, at the outermost peripheral portion of the wafer, there is a region that causes a positional shift that cannot be corrected by the same correction table. If the image comparison result in this region is output as it is, a large amount of erroneous detection occurs. there is a possibility. For this reason, in the present invention, a configuration in which an inspection is not performed in an area that cannot be corrected by the same correction table on the wafer is implemented. As a result, high-accuracy inspection that does not cause erroneous detection has become possible.

  Furthermore, by providing a shield electrode having the same potential as the retarding voltage of the sample in the vicinity of the sample, electric field disturbance in the vicinity of the sample is reduced, and a region on the wafer that can be corrected with the same correction table is further increased. Realized to enlarge.

  Due to these actions, the circuit pattern inspection apparatus according to the present invention does not cause a beam irradiation position shift under an application condition of a high retarding voltage without degrading accuracy, and an insulator or an insulator and a conductive substance. The circuit pattern in the manufacturing process of the semiconductor element mixed with can be acquired as an image having high irradiation position accuracy at high speed and stably with an electron beam, and the image can be automatically compared and detected to detect a defect without error.

  In order to achieve the second object of the present invention, the present invention employs the following means.

  Electron beam application equipment consists of a vacuum chamber that irradiates a sample such as a semiconductor device with an electron beam, a loader that transports the sample into the vacuum chamber, a stage that can be moved to place the sample and adjust the irradiation position of the electron beam, A sample holder for holding the sample between the samples, a power source for applying a retarding voltage to the sample, a position measuring device for measuring the moving amount or position of the stage, and an electron beam on the sample for processing and observing the sample And an information processing device that observes, analyzes, and inspects the sample using information obtained by detecting reflected electrons and secondary electrons generated from the sample. And the boundary part with the sample of the electron beam irradiation surface side of a sample holder shall be substantially the same as the height of the sample surface. In this way, the electric field distribution on the sample surface becomes almost uniform over the end of the sample, and the fluctuation of the electric field caused by the retarding voltage can be prevented. As a result, it is possible to irradiate the electron beam over the entire surface of the sample without lowering the position accuracy.

  According to the present invention, there is an effect that processing, analysis, and inspection can be performed by preventing a decrease in accuracy of the relationship between the irradiation position of the electron beam at the end of the sample and the sample position.

  In addition, in the electron beam application apparatus having a function of controlling the electron beam irradiation energy by the retarding voltage, there is an effect that the sample can be irradiated with the electron beam without lowering the accuracy of the irradiation position.

  Embodiments of the present invention will be described below with reference to the drawings.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a circuit pattern inspection apparatus and method and a calibration substrate according to the present invention will be described below with reference to FIGS.

  A circuit pattern inspection apparatus according to an embodiment of the present invention will be described with reference to FIGS.

  The basic concept of the circuit pattern inspection apparatus according to the present embodiment is that the retarder conforms to the cross-sectional shape of the outer peripheral portion of the substrate and the sample stage that is manifested because the retarding voltage applied to the substrate is a high negative potential. This is to perform high-precision inspection by taking into account disturbance of the electric field based on the ding voltage in advance and optimizing the deflection correction table as much as possible.

  In addition, an electrode for flattening the disturbance of the retarding electric field is provided, and the region where the correction cannot be performed is reduced to a range where there is no practical problem.

  FIG. 1 is a longitudinal sectional view showing a configuration of a circuit pattern inspection apparatus according to the present invention. The circuit pattern inspection apparatus according to the present embodiment will be described in detail with reference to FIG. The circuit pattern inspection apparatus is roughly composed of an electron optical system 101, a sample chamber 102, a control unit 103, and an image processing unit 104.

  The electron optical system 101 includes an electron gun 1, an electron beam extraction electrode 2, a condenser lens 3, a scanning deflector 5, an aperture 6, a shield pipe 7, an E cross B deflector 8, an objective lens 9, a ground electrode 15, and a shield electrode. 16.

  The sample chamber 102 includes an XY stage 11, a rotary stage 12, an optical sample height measuring device 26, and a position monitor length measuring device 27, and the secondary electron detector 13 is an object lens 9. The output signal of the secondary electron detector 13 located below is amplified by the preamplifier 21 and converted into digital data by the AD converter 22.

  The image processing unit 104 includes image storage units 30a and 30b, a calculation unit 33, and a defect determination unit 34. The captured electron beam image and optical image are displayed on the monitor 32.

  Operation commands and operation conditions of each unit of the circuit pattern inspection apparatus are input / output from the control unit 103. The controller 103 is previously input with conditions such as an acceleration voltage, an electron beam deflection width, a deflection speed, a sample stage moving speed, a signal acquisition timing of a detector, and the like when an electron beam is generated.

  In addition, a correction signal is generated from the signals of the optical sample height measuring device 26 and the position monitoring length measuring device 27, and the power supply 25 of the objective lens 9 and the scanning signal are used so that the primary electron beam 210 is always irradiated to the correct position. A correction signal is sent from the correction control circuit 28 to the generator 24.

  The electron gun 1 uses a diffusion supply type thermal field emission electron source. As a result, a comparative inspection image with little brightness fluctuation can be obtained and the electron beam current can be increased, so that high-speed inspection can be performed.

The primary electron beam 201 is extracted from the electron gun 1 when a voltage is applied to the extraction electrode 2. The primary electron beam 201 is accelerated by applying a high voltage negative potential to the electron gun 1. Thereby, the primary electron beam 201 has energy corresponding to its potential, for example, 12 in this embodiment.
KeV proceeds in the direction of the XY stage 11, converged by the condenser lens 3, further narrowed by the objective lens 9, and mounted on the XY stage 11 (specifically, a wafer to be inspected) Or a chip or the like).

  A negative voltage, that is, a retarding voltage can be applied to the substrate 10 to be inspected by a high voltage power source 23. A ground electrode 15 is provided between the substrate to be inspected 10 and the E-cross B deflector 8, and a retarding electric field is formed between the ground electrode 15 and the substrate to be inspected 10. By adjusting the high voltage power supply 23 connected to the substrate 10 to be inspected, the electron beam irradiation energy to the substrate 10 to be inspected can be easily adjusted to the optimum value.

  In this embodiment, a negative potential of −11.5 kV is applied to the substrate 10 as a retarding voltage. For image formation, the XY stage 11 is stationary and the primary electron beam 201 is scanned two-dimensionally, and the primary electron beam 201 is scanned only one-dimensionally, and the XY stage is in a direction substantially orthogonal to the scanning direction. Any of the methods of continuously moving 11 can be selected.

  When inspecting only a specific place, the XY stage 11 is stationary and inspected. When inspecting a wide range of the substrate 10 to be inspected, the XY stage 11 is continuously moved and inspected. Good inspection can be performed.

  In order to acquire an image of the substrate 10 to be inspected, a primary electron beam 201 that is narrowed down is irradiated onto the substrate 10 to be inspected to generate first secondary electrons 202, which are scanned by the primary electron beam 201 and X -By detecting in synchronization with the movement of the Y stage 11, a surface image of the inspected substrate 10 is obtained. In this embodiment, the generated first secondary electrons 202 are applied by the reflecting member 300, and the generated second secondary electrons 203 are detected by the secondary electron detector 13.

  In the automatic inspection of this embodiment, it is essential that the inspection speed is high, and therefore, scanning is performed at a low speed with a beam current of the order of pA as in a normal SEM, or multiple scanning is not performed. In view of this, an image is formed by scanning a large current electron beam of, for example, 100 nA, which is about 100 times or more compared with a normal SEM, only once.

  One image is acquired at 1000 m × 1000 pixels in 10 msec, the image signal is delayed by one image, and image comparison evaluation is performed in synchronization with the capture of the next image. The above defect search was performed.

  2 is a plan view showing a mounting state of the substrate to be inspected on the circuit pattern inspection apparatus, and FIG. 3 is an electric field distribution diagram showing the result of the simulation of the internal electric field of the circuit pattern inspection apparatus. The substrate to be inspected 10 is mounted on the XY stage 11. With the above configuration, when a retarding voltage is applied to the inspected substrate 10, a retarding electric field along the shape of the inspected substrate 10 is generated.

As shown in FIG. 2, X-Y stage 11 with four projections C _1, C _2, C _3, C ₄ on the periphery of the substrate to be inspected 10 is provided, the inner one C ₁ thereof is interposed a spring movable It is the configuration that was installed. The surface of the substrate 10 to be inspected is macroscopically flat, and when observing the central portion of the substrate, FIG.
It is considered that the electric field distribution is free from disturbance (a).

On the other hand, at the outer peripheral portion of the substrate 10 to be inspected, as shown in FIG. 2, the substrate 10 itself has a non-uniform cross-sectional shape and projections C ₁ , C ₂ , C ₃ , C ₄ for suppressing the substrate. As shown in FIG. 3B, the electric field is disturbed around the protrusion. Here, the disturbance of the retarding electric field is reduced by the shield electrode 16 provided between the substrate to be inspected 10 and the ground electrode 15. From the electric field distribution, the primary electron beam 201 is affected as follows.

FIG. 4 is a schematic diagram for explaining the electron trajectory, and FIG. 5 is a relational diagram showing the relationship between the spread of the electron irradiation position and the deflection position. As shown in FIG. 4, the primary electron beam 201 does not irradiate the substrate 10 to be inspected in a linear trajectory from the intersection of the beam axis and the deflection beam line, that is, a so-called deflection fulcrum (not shown). As it approaches the vicinity of the substrate 10 to be inspected, it is decelerated and is subjected to an axisymmetric deflection action by the retarding electric field, so that it expands by a small amount compared to the linear trajectory. When the primary electron beam 201 irradiates the central portion of the substrate 10 to be inspected, the surface of the substrate 10 to be inspected is considered to be macroscopically substantially flat, and this axially symmetric spread may be considered.

  At the time of irradiation of the center portion of the substrate 10 to be inspected shown in FIG. 4, the primary electron beam 201 reaches the irradiation position x1 that changes linearly with respect to the irradiation planned position x0 by the deflection signal. The irradiation position x1 has a value corresponding to the surface height of the substrate 10 to be inspected as shown in FIG.

  On the other hand, when irradiating the outer peripheral portion of the substrate 10 to be inspected, the primary electron beam 201 is further deflected by the disturbance of the near electric field generated according to the cross-sectional shape of the substrate 10 to be inspected. As shown in FIG. 5, the irradiation position x <b> 2 of the primary electron beam 201 moves in almost one direction on the substrate 10 to be inspected when the outer periphery is observed. The amount of movement (x2-x1) is the amount of beam distortion, and depends on the cross-sectional shape near the irradiation position.

  As a result of examination, it has been found that the amount of movement (x2-x1) can reach several tens of percent of the deflection width. At the same time, it has also been found that the amount of beam distortion (x2-x1) does not change strictly linearly with respect to the planned irradiation position. Since the beam distortion at the outer periphery of the substrate is non-linear and cannot be ignored, the following two problems occur.

  The correction during observation of the outer peripheral portion and the correction during observation of the central portion cannot be corrected by the same correction table, and the standard mark sample for generating the deflection correction table is the outer peripheral portion of the XY stage 11. If this is the case, the correction table becomes an amount including the distortion of the primary electron beam 201, and it is impossible to achieve an appropriate deflection correction.

  In addition, since this circuit pattern inspection apparatus is intended for high-speed automatic image comparison inspection, it is necessary to generate a deflection correction table that follows the beam drift due to the time change of the electron optical system 101 and has a short required time. is there.

  Therefore, in the configuration of the circuit pattern inspection apparatus according to the present invention, image comparison inspection is performed while deflection correction is performed according to the procedure shown in FIG. FIG. 6 is a flowchart for explaining the operation procedure and a plan view of the substrate to be inspected. First, a basic calibration flow is performed during periodic maintenance of the circuit pattern device.

  Specifically, a calibration wafer in which samples with standard marks (+200 μm, −200 μm) having two different thicknesses are embedded in the center of the sample stage 10 is loaded, and the center of the standard mark surface heights zH and zL is loaded. Get the image. The center standard mark signal storage unit 35 stores the image signals of the two surfaces. As the surface heights zH and zL of the standard marks, a width approximately equal to the surface height fluctuation width due to the warp of the substrate 10 to be inspected was set. Next, two standard mark-attached samples 17 having different thicknesses are similarly installed in the outermost peripheral part, and an image is acquired and stored in the outer peripheral part standard mark signal storage unit 36.

  Thus, the image signal of the standard mark obtained by the present invention is illustrated in FIG. FIG. 7 is a schematic diagram showing an example of image display.

As illustrated in FIG. 7, the true configuration of the standard mark [xk], the central standard mark signal [x3], and the outer peripheral standard mark signal [x2] form different mark images. The comparison unit 37 converts the signals read from the storage unit 35 for the central standard mark signal [x3] and the peripheral standard mark signal [x2] into the deflection distortion coefficient [B]. . In other words, the outer peripheral distortion coefficient B is calculated from the positional deviation of the signals of the standard marks at the central part and the outer peripheral part, and stored in the outer peripheral distortion amount storage unit 38.

  The outer periphery distortion coefficient B is defined by the following equations (1) and (2).

[X2 (zH)] = [B (zH)] [x3 (zH)] (1)
[X2 (zL)] = [B (zL)] [x3 (zL)] (2)
The calibration flow using the next outer peripheral standard mark is performed for each wafer while the outer peripheral distortion amount B at the time of the regular maintenance is stored. As in the case of the basic calibration, an image of a sample with a standard mark on two surfaces having a height of zH and zL installed on the outermost periphery of the sample table is formed. | ZH−zL | is 400 μm.

Then, [x2 (zH)] and [x2 (zL)] of the position signal of the standard mark on the outer peripheral portion are stored in the storage unit 36. The outer peripheral distortion amount removal calculation circuit 39 compares the true configuration position xk of the standard mark with the signal [x2] of the outer peripheral standard mark to calculate the outer peripheral deflection distortion coefficient C.

  The outer peripheral deflection distortion coefficient C is defined by the following equations (3) and (4).

[X2 (zH)] = [C (zH)] [xk]
= ([A (zH)] + [B (zH)]) [xk] (3)
[X2 (zL)] = [C (zL)] [xk]
= ([A (zL)] + [B (zL)]) [xk] (4)
Next, the distortion amount includes a distortion amount peculiar to the outer peripheral portion since the standard mark is the outermost peripheral portion of the sample stage.

  The distortion [B] generated only in the outer peripheral portion from the difference between the outer peripheral standard mark signal and the central standard mark signal represented by the equations (1) and (2) is substituted into the above equations (3) and (4). By subtracting the distortion coefficient [B] at the outer periphery, a deflection distortion coefficient [A] equivalent to the distortion amount at the center is calculated.

  The deflection distortion coefficient [A] is defined by the following equations (5) and (6).

[A (zH)] = [C (zH)]-[B (zH)] (5)
[A (zL)] = [C (zL)]-[B (zL)] (6)
The deflection distortion coefficient [A] is obtained for each of the two surfaces of the standard mark sample, a deflection correction table is calculated from the deflection distortion coefficient [A], and the storage unit 40 has an arbitrary height. A deflection correction table can be calculated.

  The deflection correction table can be completed by obtaining each value using a so-called interpolation method, assuming that the height dependency is linear.

[A (z)] = ([A (zH)]-[A (zL)]) * (z-zL)
/ (ZH-zL) + [A (zL)] (7)
By the calibration operation of the two-stage deflection correction table, the substrate 10 to be inspected needs to be replaced, and the high-precision deflection correction table that is not affected by the beam distortion without frequently performing the basic calibration flow with a long time required. Updates are now possible.

  After the deflection correction table is completed and stored by the calibration flow described above, the normal inspection is started.

First, the inspection area on the inspection substrate 10 is sequentially measured by the sample height measuring device 26, the height signal is sent to the deflection correction signal generation circuit 29, and the deflection correction signal is obtained by referring to the deflection correction table. While the primary electron beam 201 is deflected, an image signal is taken out. The extracted image signal is delayed by one image by the delay circuit 31 and compared by the calculation unit 33, and the defect determination unit 34 determines the presence or absence of a defect. In the present embodiment, in order to make the deflection correction table follow the drift of the primary electron beam 201 accompanying the time change of the electron optical system 101 with high accuracy, the correction table update control means 41 performs the above outer peripheral portion standard mark. 17 image observations and deflection correction table updates were performed once for each wafer.

  A new outer periphery mark signal and an existing outer peripheral distortion amount are processed, and a deflection correction table from which the distortion amount is removed is generated and updated. The table update can be preset in the correction table update control means 41 so as to be performed at a desired timing.

  Further, in this embodiment, as shown in FIG. 6, it is determined that the inspection invalid area control means 42 cannot inspect the area from the outer periphery of the inspected substrate 10 to 10 mm as the area where the same deflection correction table cannot be corrected, The defect determination unit 34 invalidates the determination and does not perform irradiation of the primary electron beam 201 itself.

  This is because, since the XY stage 11 has an anisotropic configuration, the beam distortion is not uniform, and the correction considering the substrate position dependency of the correction table is very complicated and takes a long time. It is.

  Further, the sample with the outer periphery standard mark is configured with a width of 10 mm so that the beam can be corrected by the same deflection correction table, and the image is acquired at the center of the sample surface at each height. . The sample with the center standard mark was configured to have a larger area than that of the sample with the outer periphery standard mark, and was operated to perform image formation of the standard mark at a position 10 mm or more away from the boundary line between the two surfaces.

  As a result of carrying out the present invention, it was possible to reduce the false detection rate by about 20% as compared with the result of inspection using the same electron optical system with deflection correction not considering beam distortion.

  In the above embodiment, the case where an electron source and an electron beam are used has been described. However, when a charged particle source and a charged particle beam are used, an irradiation optical system having the same configuration as the electron optical system is used.

  Next, an example of a circuit pattern inspection apparatus according to another embodiment of the present invention will be described with reference to FIG.

  FIG. 8 is a plan view showing the mounting state of the substrate to be inspected, similar to FIG. The present embodiment is the same as the first embodiment except that the XY stage 11 has an isotropic configuration, and the re-explanation is troublesome. Therefore, only a partial configuration diagram is shown. The XY stage 11 is configured so that the periphery of the substrate to be inspected 10 as a sample has a height within +100 μm from the substrate surface and a width of 10 mm from the outer periphery in the radial direction, and adopts an electrostatic chuck method. .

  A portion having a central angle of 180 degrees or more around the substrate 10 to be inspected is movable in the radial direction, and after the substrate is installed, the movable portion is brought closest to the substrate and fixed at a position in contact with the outer periphery of the substrate. Although this configuration is complicated and difficult to perform in actual operation, the beam distortion generated at the end of the substrate 10 to be inspected is reduced, and the entire surface can be inspected from the outer periphery to 3 mm. In this case, the inspection invalid area control means 42 does not need to issue an invalid signal.

  Next, still another embodiment according to the present invention will be described. In this example, although not shown, the inner diameter of the shield electrode 16 in Example 1 was reduced by half from 30 mmφ to 15 mmφ. As a result, the disturbance of retarding voltage was reduced, and inspection from the outer circumference to 7 mm became possible.

  As described above, according to the present invention, the disturbance of the electric field generated in the vicinity of the outer peripheral portion of the substrate 10 to be inspected, which is a sample to which a high-voltage negative retarding potential is applied, is considered in advance and is affected by the outer peripheral distortion. Therefore, it is possible to obtain a circuit pattern inspection apparatus or inspection method that performs highly accurate deflection correction of the primary electron beam 201 in accordance with the height of the irradiation position of the substrate. For this purpose, the deflection correction table is taken from the outer peripheral inspection mark position, but the diameter of the XY stage 11 is sufficiently larger than the wafer so that the installation position of the standard mark 17 is sufficiently inside so as not to cause beam distortion. It can be installed.

  In addition, since the influence of the electric field disturbance is changed by changing the retarding voltage, and the effective inspection area changes accordingly, if the control means 42 is configured in consideration of this, inspection with less waste is possible. Become. It should be noted that the numerical values described in the examples are all examples, and it goes without saying that implementation with different specifications is of course possible. In consideration of conditions such as the substrate size, thickness, variation in surface height due to warpage, retarding voltage, etc., the width and height of the sample holder substrate protrusions and substrate drop holes, and the standard mark sample If the thickness, size, etc. are optimized, the circuit pattern can be inspected more efficiently and with high accuracy.

  As described above, according to the present invention, the sample height can be increased at high speed and high accuracy without being affected by beam distortion at the outer periphery of the substrate under the condition of applying a high retarding voltage without reducing accuracy. As a result, the circuit pattern in the manufacturing process of the semiconductor device in which the insulator or the insulator and the conductive material are mixed is not generated without causing the beam irradiation position shift in the comparative inspection image. A high-accuracy image of the irradiation position can be acquired at high speed and stably by the line, and the image can be automatically compared and detected without errors. Furthermore, the result is reflected in the manufacturing conditions of the semiconductor device, so that the reliability of the semiconductor device can be improved and the defect rate can be reduced.

  Next, still another embodiment according to the present invention will be described.

  As an example of an electron beam application apparatus, an example of a semiconductor inspection apparatus using an electron beam will be described below. FIG. 10 shows a longitudinal sectional view of a main part of a semiconductor inspection apparatus using an electron beam. In a semiconductor inspection apparatus, it is inspected whether a circuit pattern formed on a semiconductor wafer or a circuit pattern mask for transferring a circuit pattern onto the wafer is as desired, and the wafer or mask becomes a sample.

  10, the electron optical system of the semiconductor inspection apparatus converges an electron gun 502 that emits electrons when power is supplied from a power source 501, an electron beam 503 drawn out from the electron gun 502, and an electron beam 503 onto a wafer 510 as a sample. Irradiating a converging lens 506a, objective lens 506b, and electron beam 503 for irradiating a desired position of the wafer 510 with a deflector 511 and an electron beam 503 for detecting secondary electrons generated from the wafer 510 by irradiation. A secondary electron detector 515 and a mirror body 505 including a Wien filter 514 that changes the secondary electrons toward the secondary electron detector 515 are configured. The magnitude of the current applied to the deflector 511 and the objective lens 506b is controlled by the control device 513.

The wafer 510 is transferred from the load lock chamber 519 to the sample chamber 507 by the transfer device 520 and placed on the sample holder 521. The position of the sample holder 521 is fixed by a pallet guide 526 of a movable stage 508. The mirror body 505 and the sample chamber 507 are maintained in vacuum by the exhaust devices 504a, 504b, 504c, and 504d. A gate valve 518 is provided between the load lock chamber 519 and the sample chamber 507 and is opened only when the wafer 510 is transferred.

  Since the scanning range of the electron beam 503 by the deflector 511 is narrower than the size of the wafer 510, the stage 508 is moved continuously or intermittently to irradiate the circuit pattern of the wafer 510 to be inspected. The alignment of the wafer 510 at this time is performed by measuring the position of the stage 508 with the laser interferometer 512 and superimposing a correction amount representing the position of the stage 508 on the amount of deflection of the electron beam 503 by the control device 513. Do.

Secondary electrons generated from the wafer 510 by irradiation with the electron beam 503 are deflected and detected by the Wien filter 514 toward the secondary electron detector 515. The detected amount of secondary electrons is amplified by the amplifier 516 and then output from the information processing device 517 as an image signal.

  In order to improve the resolution of the secondary electron image, the voltage of the electron beam 503 may be increased, but the sample may be destroyed depending on the type of the irradiated sample. In order to prevent this, a method is known in which a negative retarding voltage is applied to the sample from the retarding power source 509 to decelerate the electron beam 503 in front of the sample. This method is particularly effective for a sample such as a semiconductor wafer.

  FIG. 11 is a perspective view showing configurations of the stage 508 and the sample holder 521, and a part thereof is shown in cross section.

On the stage 508, the sample holder 521 is guided by a pallet guide 526 and the position is fixed. The wafer 510 is mounted on the sample holder 521 via the electrostatic chuck 521a. A holding plate 521b surrounds the periphery of the wafer 510. The sample holder 521 is provided with a transfer port 531 for taking in and out the wafer. The stage 508 is moved by the drive rods 525a and 525b in the direction guided by the linear guides 527a and 527b.

  12 is a plan view and a longitudinal sectional view of the sample holder 521 shown in FIG. 11. FIG. 12 (a) shows the state before the holding plate 521b around the wafer 510 is moved, and FIG. After the holding plate 521b is moved.

In FIG. 12A, when the wafer 510 is transferred from the transfer port 531 into the sample holder 521, it is placed on the electrostatic chuck 521a. Next, the lift mechanism 528 causes FIG.
As shown in FIG. 5B, the wafer is lifted in the lift direction 536 to substantially the same height as the holding plate 521b, and the height of the surface of the wafer 510 and the height of the surface of the holding plate 521b of the sample holder 521 become substantially the same. Next, the holding plate 521b divided into two or more pieces is slid by the holding machine slide mechanism 532 in the sliding direction 535 toward the center of the wafer 510, and comes into contact with the end of the wafer 510. In the embodiment shown in the figure, the holding plate 521b is divided into four parts.

  Here, the height of the surface of the wafer 510 and the height of the surface of the holding plate 521b of the sample holder 521 are preferably completely the same, but it is difficult to make them completely the same because of processing accuracy, assembly accuracy, and the like. . Therefore, it is necessary to consider a dimensional tolerance for the height identity of the two, and the inventors have found this through experiments. Details will be described later.

In this embodiment, there is a slight gap 537 between the wafer 510 and the holding plate 521b, and it is desirable that there is no gap. However, a gap 537 is formed depending on the processing accuracy of the outer peripheral dimension of the wafer 510 and the dimension of the holding plate 521b. The dimension allowable value of this gap will be described later.

  FIG. 13 shows another embodiment of the present invention, and shows a plan view and a longitudinal sectional view of a sample holder 521. The wafer 510 is placed on the electrostatic chuck 521a, and one of the plurality of holding pins 539 moves in the pin moving direction 540, and the position of the wafer 510 is fixed. Next, the holding plate 521c moves in the lift direction 536, and the height of the surface of the wafer 510 and the height of the surface of the holding plate 521c become substantially the same.

  14 to 15 show the configuration of a conventional sample holder. FIG. 14 is a plan view and a side view of a conventional sample holder.

  In FIG. 14, a wafer 510 is placed on a support base 530 fixed on a sample holder 521 and the position is fixed by a plurality of bearings 529. Therefore, the height of the sample holder 521 around the edge of the wafer 510 is lower by the thickness of the wafer 510.

FIG. 15 is a plan view and a side view of a conventional sample holder. In FIG. 15, a wafer 510 is placed on an electrostatic chuck 521a fixed on a sample holder 521, and the position is fixed by a plurality of claws 523a, 523b, and 523c. The cross-sectional shape of the claw 523a is a claw 523b as shown in FIG. 15B and a claw 523c as shown in FIG. Around these nails 523a,
523b and 523c protrude. Assuming the case of using such a conventional sample holder, the following simulation was performed.

  16 to 18 are electric field distribution diagrams simulating the electric field distribution on the surface of the wafer 510 when the wafer 510 is fixed to the sample holder 521 and the electron beam 503 is irradiated with a retarding voltage. The plurality of lines are equipotential lines 524 connecting equal voltages.

  FIG. 16 shows the case where the central portion of the wafer 510 is irradiated with the electron beam 503. The center of the figure is the locus of the electron beam 503. The equipotential lines 524 on the surface of the wafer 510 are parallel to the surface of the wafer 510 up to the vicinity of the shield electrode 541, and no change such as turbulence is observed. In such a portion, there is no dimensional influence due to the retarding potential on the electron beam 503. In the vicinity of the shield electrode 541, the equipotential line 524 is separated from the surface of the wafer 510.

FIG. 17 shows an electric field distribution diagram as a result of electric field simulation when the protrusion of the sample holder 521 is 1 mm higher than the wafer 510 at the edge of the wafer 510. FIG. 17A shows the case where the irradiation position of the electron beam 503 is 5 mm away from the protrusion, and FIG. 17B shows the case where the irradiation position of the electron beam 503 is 10 mm away from the protrusion.

  When FIG. 17A and FIG. 17B are compared, the variation in the electric field is observed in the direction of (a), that is, the direction in which the protrusion is closer to the electron beam 503 than in FIG. It is expected that there is a high possibility that the irradiation position of the electron beam 503 is disturbed in the range of 5 mm from the protrusion, in which the electric field fluctuates.

  FIG. 18 shows an electric field distribution diagram as a result of electric field simulation when the periphery of the edge of the wafer 510 is a space. 18A shows the case where the irradiation position of the electron beam 503 is 5 mm from the wafer end, and FIG. 18B shows the case where the irradiation position of the electron beam 503 is 10 mm from the wafer end.

  18A and 18B are compared, the variation in the equipotential line 524 is larger as the irradiation position of the electron beam 503 is closer to the end of the wafer 510 in FIG. It is expected that the irradiation position of the electron beam 503 is likely to be disturbed. Therefore, it can be seen that providing a large space at the end of the wafer 510 should be avoided.

Therefore, it was found that when a projection having a height or a low space is provided on the outer side from the end of the wafer 510, the range in which the irradiation position of the electron beam 503 is not disturbed is at least 10 mm inside from the end of the wafer 510. .

Looking at the electric field distribution map based on the result of the electric field simulation described above, in order to prevent fluctuation of the electric field at the edge of the wafer 510 and to prevent the influence on the irradiation position of the electron beam 503, the wafer 510 of the sample holder 521 It has been found that it is effective to make the periphery of the end portion the same height as the surface of the wafer 510.

  Further, it is difficult to make the height dimension of the wafer 510 and the height dimension of the sample holder 521 completely the same due to errors in machining and assembly, but according to the experiments by the inventors, It was found that the influence on the irradiation position of the electron beam 503 is almost negligible when the difference in height between the surface of the edge of the wafer 510 and the sample holder 521 is ± 200 μm.

  Further, a gap 537 is formed between the wafer 510 and the holding plates 521b and 521c shown in FIGS. According to experiments by the inventors, it has been found that if the gap 537 is 0.5 mm or less, the influence on the irradiation position of the electron beam 503 can be almost ignored.

  As described above, in the electron beam application apparatus having the function of controlling the electron beam irradiation energy by the retarding voltage, the height of the sample and the sample holder for holding the sample are made substantially the same, or the allowable dimension is set to this height. Or an area with almost the same height to prevent fluctuations in the electric field, so that the electron beam can be irradiated even at the end of the sample without lowering the accuracy of the irradiation position. it can.

1 is a longitudinal sectional view showing a configuration of a circuit pattern inspection apparatus according to the present invention. The top view which shows the mounting state of a to-be-inspected board | substrate. The electric field distribution map which shows the result of the simulation of an internal electric field. The schematic diagram explaining an electron orbit. The relationship figure which shows the relationship between the breadth of the irradiation position of an electron, and a deflection position. The flowchart explaining the operation | movement procedure of the circuit pattern inspection apparatus which concerns on this invention, and the top view of the to-be-inspected board | substrate mounted. The schematic diagram which shows an example of an image display. The top view which shows the mounting state of a to-be-inspected board | substrate. The longitudinal cross-sectional view which shows the structure of the circuit pattern inspection apparatus in a prior art. The longitudinal cross-sectional view of the principal part of the semiconductor inspection apparatus using an electron beam. The perspective view which showed the structure of the stage of a semiconductor inspection apparatus using an electron beam, and the sample holder, and gave a partial cross section. The top view and longitudinal cross-sectional view of the sample holder of FIG. The top view and longitudinal cross-sectional view of a sample holder. The top view and side view of the conventional sample holder. The top view and sectional drawing which show the sample holding structure of the conventional sample holder. The electric field distribution figure which shows the result of the electric field distribution simulation of the longitudinal cross section on the sample surface. The electric field distribution figure which shows the result of the electric field distribution simulation of the longitudinal cross section on the sample surface. The electric field distribution figure which shows the result of the electric field distribution simulation of the longitudinal cross section on the sample surface.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electron gun, 5 ... Scanning deflector, 8 ... E cross B deflector, 9 ... Objective lens, 10 ... Substrate to be inspected, 11 ... XY stage, 13 ... Secondary electron detector, 26 ... Optical sample Height measuring instrument,
34... Defect determination unit 35. Center standard mark signal storage unit 36. , 40: Deflection correction table calculation / storage unit, 41 ... Correction table update control means, 201 ... Primary electron beam, 202 ... First secondary electron, 203 ... Second secondary electron, 503 ... Electron beam, 510 ... Wafer, 521, sample holder.

Claims (2)

In a length measuring device that measures the sample using an image signal obtained by irradiating the surface of the sample with an electron beam and detecting secondary electrons or reflected electrons,
An electrostatic chuck for holding the sample;
A sample chamber for storing the electrostatic adsorption device;
A mirror provided with an objective lens for focusing the electron beam on the sample;
A retarding power source for supplying a retarding voltage applied to the sample;
Between the electrostatic adsorption device and the objective lens, an electrode for reducing disturbance of an electric field based on the retarding voltage ,
Furthermore, the same voltage as the said retarding voltage is applied to the said electrode, The length measuring apparatus characterized by the above-mentioned . In an inspection apparatus for inspecting or observing the sample using an image signal obtained by irradiating the surface of the sample with an electron beam and detecting secondary electrons or reflected electrons,
An electrostatic chuck for holding the sample;
A sample chamber for storing the electrostatic adsorption device;
A mirror provided with an objective lens for focusing the electron beam on the sample;
A retarding power source for supplying a retarding voltage applied to the sample;
Between the electrostatic adsorption device and the objective lens, an electrode for reducing disturbance of an electric field based on the retarding voltage,
Furthermore, the same voltage as the said retarding voltage is applied to the said electrode, The inspection apparatus characterized by the above-mentioned .

Images