JP4695888B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

  The present invention relates to a solid-state imaging device such as a digital still camera and a digital video camera.

  Conventionally, a solid-state imaging device that converts received light into an electrical signal and outputs it as a video signal is known, and a camera such as a digital still camera that displays a video signal obtained from the solid-state imaging device as a still image is known. ing. In recent years, a camera using such a solid-state imaging device is required to further improve image quality and function, and the number of pixels is rapidly increasing.

  For example, in the case of a solid-state imaging device having about 5 million pixels, the number of pixels in the vertical direction is about 1920 pixels, the number of pixels in the horizontal direction is about 2560 pixels, and the number of pixels that a normal NTSC solid-state imaging device has When the conventional pixel clock of about 12 MHz is used, the frame rate at the time of output of all pixels is about ½ second. For this reason, video signals output from a solid-state image sensor cannot be output to a camera display device (liquid crystal monitor or the like) at the same frame rate.

  Therefore, in such a solid-state imaging device, a driving method for reading a video signal of a moving image at high speed by thinning out pixels to be read out in the vertical direction in addition to increasing the pixel clock speed has been conventionally used. . For example, a method using only the signals of the pixels of 2 lines out of 8 lines is used.

In addition, a technique for reducing the number of output pixels of a solid-state imaging device by a pixel mixing method is also known (see Patent Document 1).
JP 2001-36920 A

  However, in the pixel thinning configuration as described above, resampling is extremely performed in the vertical direction (1/4 in the above example), and there is a space LPF in the vertical direction at the time of resampling. Therefore, when an image that includes a high-frequency signal in the vertical direction of the video signal is captured, a large amount of the folding component of the high-frequency component in the vertical direction to a low frequency is generated, and a large number of false signals are generated for both the luminance signal and the chromaticity signal. In addition, there is a problem in that the vertical resolution is significantly lowered with respect to the horizontal resolution due to the imbalance between pixel sampling densities in the horizontal and vertical directions. In addition, since the signal of the pixel in the row that is not read out is discarded, there arises a problem that the substantial sensitivity is lowered. The pixel utilization rate in the above example is 25%.

  Furthermore, all of the above problems are related to the necessity of lowering the ratio of the vertical readout row to the entire row of the solid-state image sensor to increase the frame rate as the number of pixels of the solid-state image sensor increases with the use of the conventional method. Therefore, in principle, the problem has the property of becoming more prominent.

  The present invention solves the above-described problems, and reduces the number of output pixel signals of a solid-state image pickup device having many pixels such as a super megapixel by a pixel addition method, and is an ultra-high pixel solid-state image pickup device suitable for an interless scan system. And a solid-state imaging device capable of capturing a moving image and a driving method thereof.

  In order to achieve the above object, the present invention provides a solid-state imaging device, a solid-state imaging device, and a pixel addition process for a first field and a second field for adding charges of a plurality of pixels each included in a plurality of pixel mixture area units. Thus, the pixel charge signal obtained by the pixel addition processing in the first field and the second field is alternately output as an interlace scan signal.

  Specifically, in the solid-state imaging device of the present invention, the solid-state imaging device includes a solid-state imaging device having a plurality of photoelectric conversion elements arranged in a matrix, and q (q is q) arranged in the first direction of the solid-state imaging device. A plurality of pixel mixture areas, each of which is a pixel mixture area unit of two or more pixels) and p (p is a natural number of two or more) pixels arranged in the second direction intersecting the first direction. The pixel addition process of the first field for adding the charges of the plurality of pixels included in the unit and the pixel mixture area unit by a combination different from the combination of the pixel mixture area unit added by the pixel addition process of the first field Pixel addition processing means for performing pixel addition processing in a second field for adding charges of a plurality of included pixels, and interpolating signals of pixel charges obtained by pixel addition processing in the first field and second field. Characterized in that an output means for outputting alternately as a signal for the scan.

  According to the solid-state imaging device of the present invention, the pixel mixture area added by the pixel addition process of the first field for adding the charges of the plurality of pixels included in the unit of the plurality of pixel mixture areas and the pixel addition process of the first field. Since there is a means for performing pixel addition processing in the second field for adding charges of a plurality of pixels included in a plurality of pixel mixture area units by a combination different from the unit combination, pixels to be read out are thinned out The video signal can be read at high speed. Therefore, it becomes possible to output the signals of all the pixels without discarding them, and the sensitivity is greatly improved. Further, since the aliasing component of the high frequency component to the low frequency is significantly reduced, the false signal is greatly suppressed for both the luminance signal and the chromaticity signal, and as a result, the image quality is improved.

  In the solid-state imaging device according to the present invention, the plurality of pixel mixture area units added in the first field pixel addition process and the second field pixel addition process overlap each other in the first direction and the second direction. It is preferable that it is arrange | positioned so that it may have.

  In the solid-state imaging device of the present invention, the number q of pixels in the first direction in the pixel mixture area unit is represented by q = 4m + 1 (m is a natural number), and the number p in the second direction is p = 4n + 1 (n is a natural number). It is preferable that the pixel mixture area unit is overlapped with a shift of (p + 1) / 2 pixels in the second direction and (q + 1) / 2 pixels in the first direction.

  The number q of pixels in the first direction in the pixel mixture area unit is represented by q = 4m−1, and the number p in the second direction is represented by p = 4n−1 (n is a natural number). Alternately repeats the shift amount between (p-1) / 2 pixels and (p + 3) / 2 pixels in the second direction, and (q-1) / 2 pixels and (q + 3) / 2 pixels in the first direction. The amount of deviation may be repeated alternately to overlap.

  In the first direction, charges of a plurality of pixels included in one pixel mixture area unit are added, and in the second direction, addition is performed for each of the plurality of pixel mixture areas that are added and transferred in the first direction. You may add the electric charge of the selected pixel. With this configuration, it is possible to clearly separate the process of adding the pixel charges in the first direction and the process of adding the pixel charges in the second direction, and to perform a quick time-series process. .

  Further, the pixel addition processing means includes a plurality of pixels included in each of the two pixel mixture area units with respect to two pixel mixture area units arranged adjacent to each other in the first direction among the plurality of pixel mixture area units. A plurality of line processes for adding the charges of each other may be performed, and at least one of the plurality of line processes may process two pixel mixed area units arranged with a shift of one pixel or more in the second direction. With such a configuration, it becomes easy to add charges of pixels having different colors along the second direction.

  Furthermore, the center-of-gravity position of the first region obtained by combining two pixel mixture area units processed in one line process among the plurality of line processes is processed in the other line process among the plurality of line processes. The center of gravity of the second region combining the two pixel mixture area units, and two pixel mixture area units processed simultaneously with the second region and arranged adjacent to the second region in the second direction You may be located on the line | wire of the line along the 1st direction which passes along the center with the gravity center position of the 3rd area | region which match | combined each other. With such a configuration, the correction of the center of gravity of the pixel signal output from the solid-state imaging device is simplified, and the afterimage in the moving image can be reduced.

  In the solid-state imaging device of the present invention, each solid-state imaging device preferably includes a color filter attached to the front surface of each photoelectric conversion element. In this case, the arrangement of the color filters of the solid-state imaging device is two rows. A combination of two rows of Bayer arrays, wherein the pixel addition processing means adds a first direction transfer stage for adding charges of a plurality of pixels along a first direction for each pixel mixed area unit, and a first direction transfer And a second direction transfer stage that adds the charges obtained by adding in the stage along the second direction, and each charge obtained by adding in the second direction transfer stage is stored in the complementary color filter array. Each pixel signal for display may be a combination of four colors of cyan, yellow, green and magenta in 2 rows and 2 columns.

  In the solid-state imaging device of the present invention, the means for performing pixel addition processing is transferred from the first direction transfer stage composed of a plurality of CCDs that transfer the charge of each pixel along the first direction, and from the first direction transfer stage. It is preferable to have a second direction transfer stage composed of a CCD that transfers charges along the second direction. By adopting such a configuration, it is possible to perform processing for adding the charges of the pixels using the CCD.

  In this case, the second direction transfer stage includes a storage region that has a first gate and holds charges, and a barrier region that has a second gate and serves as a barrier against charge transfer. Are preferably arranged alternately, and the first gate and the second gate are preferably electrically separated and individually biased. With such a configuration, it becomes possible to transfer the charge of the pixel in the second direction transfer stage not only in the forward direction but also in the reverse direction, and the pixel addition process can be performed quickly.

  The solid-state imaging device driving method of the present invention includes a solid-state imaging device having a plurality of photoelectric conversion elements arranged in a matrix, and q arranged in the first direction of the solid-state imaging device (q is a natural number of 2 or more). And a solid-state imaging device driving method in which a pixel mixture area unit is p (p is a natural number of 2 or more) pixels arranged in a second direction intersecting the first direction, and the first direction A step (a) of adding and transferring the charges of each pixel in each pixel mixed area unit along the direction, and transferring the charge of the pixel transferred after being added in the first direction along the second direction. On the other hand, signals for pixel charges in the first field and the second field added in step (b) and step (b) of adding pixel charges from a plurality of pixel mixed area units are used for interlace scanning. Alternately output as Characterized in that it comprises a step (c) to.

  According to the driving method of the solid-state imaging device of the present invention, the step of adding and transferring the charges of each pixel in each pixel mixed area unit along the first direction and the transfer after the addition in the first direction are performed. Transfer of the pixel charges along the second direction while adding the pixel charges from a plurality of pixel mixed area units, so that the video signal can be transferred at high speed without thinning out the pixels to be read out. Can be read out. Therefore, it becomes possible to output the signals of all the pixels without discarding them, and the sensitivity is greatly improved. Further, since the aliasing component of the high frequency component to the low frequency is significantly reduced, the false signal is greatly suppressed for both the luminance signal and the chromaticity signal, and as a result, the image quality is improved.

  The solid-state imaging device driving method according to the present invention includes the plurality of pixel mixture area units added in the pixel addition processing step in the first field and the pixel addition processing step in the second field, respectively, in the first direction and It is preferable to arrange so as to have overlapping portions in the second direction.

  In the driving method of the solid-state imaging device of the present invention, in step (a), the charges of the pixels in one pixel mixed area unit are added in the first direction, and in step (b), the pixels added in the first direction are added. Are preferably added along the second direction. Further, in step (b), it is preferable that line processing for adding the charges of the pixels in two pixel mixed area units adjacent to each other in the first direction in the second direction is performed in a plurality of stages.

  In the solid-state imaging device driving method of the present invention, the solid-state imaging device preferably has a color filter attached to the front surface of the photoelectric conversion device. In this case, the arrangement of the color filters of the solid-state imaging device is a combination of 2 rows and 2 columns of Bayer arrangement, and in step (b), the charges of the pixels of different colors from each pixel mixture area unit are added to obtain complementary colors. Even if the pixel signal for the filter arrangement is generated, the arrangement of the color filters of the solid-state imaging device may be a combination of four colors of cyan, yellow, green and magenta in 2 rows and 2 columns.

  In the driving method of the solid-state imaging device according to the present invention, in step (a), a first direction transfer stage including a plurality of CCDs for transferring charges of each pixel along the first direction is used, and in step (b), the first direction transfer stage is used. It is preferable to use a second direction transfer stage comprising a CCD that receives charges transferred from the one direction transfer stage and transfers the charges along the second direction.

  According to the solid-state imaging device of the present invention or the driving method thereof, the number of output pixel signals of a solid-state imaging device having many pixels such as a super megapixel is reduced by a pixel addition method, and the ultra-high pixel suitable for an interlace scan system The moving image imaging of the solid-state imaging device can be realized.

  Hereinafter, embodiments of the color solid-state imaging device of the present invention will be described with reference to the drawings. In each embodiment, a case where a CCD solid-state imaging device is used will be described. However, the solid-state imaging device may be a MOS solid-state imaging device. Therefore, the charge mixing in the following embodiments means one kind of operation of charge addition.

(First embodiment)
FIG. 1 is a plan view schematically showing an element arrangement in a CCD solid-state imaging device of the color solid-state imaging device according to the first embodiment. The solid-state imaging device includes a large number of pixels 11 arranged in a matrix in a vertical direction that is a first direction and a horizontal direction that is a second direction. The pixel 11 includes a photoelectric conversion element and a color filter attached to the front surface thereof. The types of the pixels 11 include a B pixel having a blue filter displayed in B in the figure, an R pixel having a red filter displayed in R in the figure, and a green pixel displayed in Gr or Gb in the figure. Gr pixels or Gb pixels having a filter are included. That is, the solid-state imaging device of this embodiment has a primary color filter array, in particular, a Bayer array structure. Here, the Gr pixel and the Gb pixel are actually pixels having filters of the same color (green). However, for convenience of explanation of the operation, the pixel sandwiched between the R pixels on both horizontal sides is defined as the Gr pixel, and the horizontal both sides are illustrated. Pixels sandwiched between B pixels are denoted as Gb pixels.

  The solid-state imaging device includes six-phase vertical transfer stages 12 (12A, 12B,...) (First direction transfer stage) configured by connecting gates V1 to V6 in series, and gates H1, H2, H3, and H4. A horizontal transfer stage W (second-direction transfer stage) configured by serially connecting the four-phase transfer gate portions W1, W2,... Configured to output charges accumulated in the horizontal transfer stage W. An output amplifier 14 and a vertical-horizontal transfer linking portion 15 having gates (V3, V3R, V3L, V5, V5R, V5L) that can be driven independently are provided in the final stage of the vertical transfer. The vertical transfer stage 12, the vertical-horizontal transfer linking unit 15, and the horizontal transfer stage W constitute means for performing a first field pixel mixing process and a second field pixel mixing process, which will be described later. The output amplifier 14 functions as means for outputting the pixel signal obtained by the pixel mixing process in the first and second fields as a signal for interlace scanning.

  Here, the gates with odd numbers such as the gates V1, V3,... In each of the vertical transfer stages 12A, 12B,... Are connected to the photoelectric conversion elements in each pixel, and charge from each pixel is transferred. The read and read charges are transferred by the gates V1 to V6.

  Further, the gates H1, H3 of the transfer gate portions W1, W2,... In the horizontal transfer stage W have a function of holding the charges transferred from the vertical-horizontal transfer joint portion 15, and the gates H2, H4 are The gates H1 and H3 function as a barrier against charge movement. Here, as will be described later, the gates H1, H2, H3... Of the transfer gate portions W1, W2,. H4 is wired independently.

  The pixels 11 arranged in a matrix are grouped into a large number of pixel mixture area units that overlap each other. In the present embodiment, the basic unit A of the pixel mixture area each composed of 5 × 5 pixels is grouped, and the color of the filter of the pixel at the center position represents the color mixed in the pixel mixture area unit. ing. The first embodiment is a case where the pixel mixture area has 5 rows and 5 columns.

  As shown in FIG. 1, in this embodiment, as a pixel mixture area unit in the first field, a Gb pixel mixture area unit A1, a B pixel mixture area unit A2, a Gr pixel mixture area unit A3, An R pixel mixture area unit A4, a Gb pixel mixture area unit A5, a B pixel mixture area unit A6, an R pixel mixture area unit A7, and a Gr pixel mixture area unit A8 are set. Note that the term “pixel mixed area unit” in this application document is defined to include an area unit for performing charge addition operation in a MOS type solid-state imaging device.

  In this example, each pixel mixed area unit overlaps two pixels in the vertical direction and in the horizontal direction. Although not shown in FIG. 1, the pixel mixed area units A1 to A8 are set to repeatedly appear while overlapping in the vertical direction and the horizontal direction.

[Pixel mixture in the first field]
Next, with respect to the procedure of the pixel mixing process in the first field in the present embodiment, referring to FIG. 2, taking as an example the case of mixing the pixels in the pixel mixing area units A1, A2,. While explaining.

-Charge mixing process for pixels in the pixel mixing area unit-
First, by applying a read pulse to the gate V3 of the vertical transfer stage 12, the upper charge in the pixel mixed area unit is read. This charge is transferred from the gate V3 to the gate V1, and then a readout pulse is applied to the gate V1 to read out the central charge in the pixel mixture area unit and mix it with the upper charge read out first. Is done.

  The charge mixed in the two pixels is transferred from the gate V1 to the gate V5, and then a readout pulse is applied to the gate V5, whereby the lower charge in the pixel mixture area unit is read out and the three pixels are mixed. The

  In this way, the charges of the three pixels in the vertical direction in the pixel mixture area unit are mixed. At this time, the charges of the three vertical pixels of the pixel mixing area units A1 to A8... Are mixed at the same time.

  However, the charge mixing method for the vertical three pixels can be various in addition to the method shown in this embodiment and the second and third embodiments described later, and other methods may be used.

  In this way, the charge mixed with the three pixels is sequentially sent in the vertical direction and accumulated in each gate of the vertical-horizontal transfer linking portion 15 disposed between the vertical transfer stage 12 and the horizontal transfer stage W.

  FIG. 2 shows that in the first field, after charges in one pixel mixed area unit mixed with three pixels in the vertical transfer stage 12 are transferred to the horizontal transfer stage W, two lines are transferred in the horizontal transfer stage W for each line. It is a figure explaining the procedure which mixes the charge in a pixel mixing area unit. In addition, since the output of one horizontal line corresponds to the output of three vertical lines, this figure is also a diagram for explaining the procedure of transferring charges mixed in two pixel mixed areas for three vertical lines all at once. is there.

  The horizontal axis in the figure represents the position of the transfer gate portion in the horizontal transfer stage W, and the vertical axis in the figure represents time. Hereinafter, the pixel mixing process in each line will be described with reference to FIG. Note that in FIG. 2 and FIGS. 6 and 10 described later, only the charges drawn from the vertical-horizontal transfer connecting portion 15 to the horizontal transfer stage W are displayed, but in the second and subsequent columns of each line, horizontal charges are displayed. The charges transferred in the transfer stage W and the charges drawn out from the vertical-horizontal transfer connecting portion 15 to the horizontal transfer stage W are sequentially mixed.

  In this embodiment, the vertical transfer stage 12 and the vertical-horizontal transfer linking part 15 are controlled by a common bias signal. However, in the second and third embodiments, the vertical transfer stage 12 12 and the vertical-horizontal transfer link 15 are individually controlled.

  In the present embodiment, only the mixing process of charges C1c to C6c, C1d to C6d, D1c to D6c, D1d to D6d, E1c to E6c, and E1d to E6d will be described. However, as shown in FIG. , D1e to D6e, and other charges such as E1e to E6e are mixed in the same procedure.

-Line 1 processing-
First, among the charges mixed in three pixels in the vertical direction in the pixel mixture area unit held by the gate in the vertical-horizontal transfer connecting portion 15, the gates V3L and V5L that can be driven independently are arranged. The charges mixed in the transfer stages (15D, 15G) are drawn out to the transfer gate portions W4, W7 (each gate H1) and held as charges C1c, C1d. Hereinafter, in FIG. 2, only the charges extracted from the vertical transfer stages are displayed, but the charges extracted from the vertical transfer stages are sequentially mixed.

  Next, after the charges C1c and C1d are transferred in two stages in the opposite direction (meaning the two stages of the transfer gate portion including the gates H1 to H4), gates V3R and V5R that can be independently driven are arranged. The charges mixed in the vertical transfer stages (15F, 15I) are drawn out to the transfer gates W6, W9 and held as charges C1c + C2c, C1d + C2d.

  Further, after the charges C1c + C2c and C1d + C2d are transferred in two stages in the reverse direction, the charges mixed in the vertical transfer stages (15H, 15K) in which the gates V3, V5 are arranged are transferred to the transfer gate portions W8, It is extracted to W11 and held as charges C1c + C2c + C3c, C1d + C2d + C3d.

  The charge C1c + C2c + C3c is a mixture of nine Gb pixels in the pixel mixture area unit A1, and the charge C1d + C2d + C3d is a mixture of nine B pixels in the pixel mixture area unit A2. It has been done. In the following description, only the further mixing process of the charges C1c + C2c + C3c and the charges C1d + C2d + C3d will be described.

  Furthermore, after the charges C1c + C2c + C3c and C1d + C2d + C3d are transferred one stage in the forward direction, they are mixed in the vertical transfer stage (15G, 15J) in which gates V3L and V5L that can be driven independently are arranged. The charges are drawn to the transfer gate portions W7 and W10 and held as charges C1c + C2c + C3c + C4c and C1d + C2d + C3d + C4d.

  Next, after the charges C1c + C2c + C3c + C4c and C1d + C2d + C3d + C4d are transferred in four stages in the forward direction, the vertical transfer stages (15C, 15F) in which gates V3R and V5R that can be independently driven are arranged. ) Are extracted to the transfer gate portions W3 and W6 and held as charges C1c + C2c + C3c + C4c + C5c, C1d + C2d + C3d + C4d + C5d.

  Next, after the charges C1c + C2c + C3c + C4c + C5c and C1d + C2d + C3d + C4d + C5d are transferred in two reverse directions, the vertical transfer stages (15E, 15H in which the gates V3, V5 are arranged) ) Is extracted to the transfer gates W5 and W8 and held as charges C1c + C2c + C3c + C4c + C5c + C6c, C1d + C2d + C3d + C4d + C5d + C6d.

  The charge C4c + C5c + C6c is a mixture of nine Gr pixels in the pixel mixture area unit A3, and the charge C1c + C2c + C3c + C4c + C5c + C6c is 18 in the pixel mixture area unit A1 + A3. The charges are mixed, and this becomes the output charge CTc. The charge C4d + C5d + C6d is a mixture of 9 R pixels in the pixel mixture area unit A4, and the charge C1d + C2d + C3d + C4d + C5d + C6d is 18 pixels in the pixel mixture area unit A2 + A4. The charges of the pixels are mixed, and this becomes the output charge CTd.

-Line 2 processing-
First, the output charges CTc and CTd generated by the charge mixing process on the first line are transferred in two stages in the forward direction and held in the transfer gate parts W3 and W6, and then the gates in the vertical-horizontal transfer connecting part 15 Among the charges mixed in the vertical direction in the pixel mixing area unit held in the above, the charges mixed in the vertical transfer stage (15D, 15G) in which the gates V3L, V5L that can be driven independently are arranged Is extracted to the transfer gate portions W4 and W7 (each gate H1) and held as charges D1c and D1d.

  Thereafter, the output charges CTc and CTd generated in the processing of the first line are transferred together with the charges to be mixed and transferred in the charge mixing processing of the second line.

  Next, the charges D1c and D1d are transferred in two stages in the opposite direction and then mixed in the vertical transfer stage (15F, 15I) in which the gates V3R and V5R that can be independently driven are arranged. , W9 and are held as charges D1c + D2c, D1d + D2d.

  Further, after the charges D1c + D2c and D1d + D2d are transferred in four stages in the forward direction, the charges mixed in the vertical transfer stages (15B, 15E) in which the gates V3, V5 are arranged are transferred to the transfer gate portions W2, W2. It is extracted to W5 and held as charges D1c + D2c + D3c, D1d + D2d + D3d.

  The charge D1c + D2c + D3c is a mixture of nine Gb pixels in the pixel mixture area unit A5, and the charge D1d + D2d + D3d is a mixture of nine B pixels in the pixel mixture area unit A6. It has been done. In the following description, only the further mixing process of charges D1c + D2c + D3c and charges D1d + D2d + D3d will be described.

  Further, after the charges D1c + D2c + D3c and D1d + D2d + D3d are transferred in the reverse direction, they are mixed in the vertical transfer stage (15D, 15G) in which the gates V3L, V5L that can be driven independently are arranged. The charges are drawn to the transfer gate portions W4 and W7 and held as charges D1c + D2c + D3c + D4c and D1d + D2d + D3d + D4d.

  Next, after the charges D1c + D2c + D3c + D4c and D1d + D2d + D3d + D4d are transferred in the reverse direction in two stages, the vertical transfer stages (15F, 15I) in which the gates V3R and V5R that can be driven independently are arranged. ) Are extracted to the transfer gates W6 and W9, and held as charges D1c + D2c + D3c + D4c + D5c, D1d + D2d + D3d + D4d + D5d.

  Next, the charges D1c + D2c + D3c + D4c + D5c, D1d + D2d + D3d + D4d + D5d are transferred in four stages in the forward direction, and then the vertical transfer stages (15B, 15E in which the gates V3, V5 are arranged. ) Are extracted to the transfer gates W2 and W5 and held as charges D1c + D2c + D3c + D4c + D5c + D6c, D1d + D2d + D3d + D4d + D5d + D6d.

  The charge D4c + D5c + D6c is a mixture of 9 R pixels in the pixel mixing area unit A7, and the charge D1c + D2c + D3c + D4c + D5c + D6c is 18 charges in the pixel mixing area unit A5 + A7. Are mixed, and this becomes the output charge DTc. The charge D4d + D5d + D6d is a mixture of 9 Gr pixels in the pixel mixture area unit A8, and the charge D1d + D2d + D3d + D4d + D5d + D6d is 18 pixels in the pixel mixture area unit A6 + A8. Are mixed, and this becomes the output charge DTd. At this time, the output charges CTc and CTd generated by the charge mixing process of the first line are held on the forward direction side by one stage from the output charges DTc and DTd generated by the mixing process of the second line.

-3rd line processing
First, the output charges CTc, CTd, DTc, DTd generated by the charge mixing process for the first line and the second line are transferred in two stages in the forward direction to transfer gate unit W-1 (not shown in FIG. 2). Are arranged on the forward direction side by two stages from the transfer gate part W1), W2 and W0 (not shown in FIG. 2, but arranged on the forward direction side by one stage from the transfer gate part W1). The gate which can be independently driven out of the charges mixed in the vertical direction in the pixel mixed area unit held below the gate in the vertical-horizontal transfer joint 15 after being held in W3. The charges mixed in the vertical transfer stages (15A, 15D) in which V3L and V5L are arranged are drawn out to the transfer gate portions W1 and W4 (each gate H1) and held as charges E1c and E1d.

  Thereafter, the output charges CTc, CTd, DTc, and DTd generated by the charge mixing process for the first line and the second line are transferred together with the charges that are sequentially mixed and transferred during the charge mixing process for the third line. .

  Next, the charges E1c and E1d are transferred in two stages in the opposite direction and then mixed in the vertical transfer stages (15C and 15F) in which the gates V3R and V5R that can be driven independently are arranged. , W6 and are held as electric charges E1c + E2c, E1d + E2d.

  Furthermore, after the charges E1c + E2c and E1d + E2d are transferred in two stages in the reverse direction, the mixed charges are transferred in the vertical transfer stages (15E, 15H) in which gates V3 and V5 that can be driven independently are arranged. It is drawn out to the gate portions W5 and W8 and held as charges E1c + E2c + E3c, E1d + E2d + E3d.

  The charge E1c + E2c + E3c is a mixture of nine Gb pixels in the pixel mixture area unit A1, and the charge E1d + E2d + E3d is a mixture of nine B pixels in the pixel mixture area unit A2. It has been done. In the following description, only further mixing processing of the charges E1c + E2c + E3c and the charges E1d + E2d + E3d will be described.

  Further, after the charges E1c + E2c + E3c and E1d + E2d + E3d are transferred one stage in the forward direction, they are mixed in the vertical transfer stage (15D, 15G) in which gates V3L and V5L that can be independently driven are arranged. The charges are drawn to the transfer gate portions W4 and W7 and held as charges E1c + E2c + E3c + E4c and E1d + E2d + E3d + E4d.

  Next, after charges E1c + E2c + E3c + E4c, E1d + E2d + E3d + E4d are transferred in four stages in the forward direction, gates V3R and V5R that can be independently driven are arranged in a vertical transfer stage (15X (vertical The transfer stage is adjacent to the transfer stage 15A on the forward direction side but is not shown in FIG. 2, and the charge mixed in 15C) is transferred adjacent to the transfer gate part W0 (the transfer gate part W1 on the forward direction side). Although it is a gate part (not shown in FIG. 2), it is drawn out to W3 and held as charges E1c + E2c + E3c + E4c + E5c, E1d + E2d + E3d + E4d + E5d.

  Next, after the charges E1c + E2c + E3c + E4c + E5c, E1d + E2d + E3d + E4d + E5d are transferred in two reverse directions, the vertical transfer stages in which gates V3 and V5 that can be driven independently are arranged The charges mixed at (15B, 15E) are drawn out to the transfer gate portions W2 and W5 and held as charges E1c + E2c + E3c + E4c + E5c + E6c, E1d + E2d + E3d + E4d + E5d + E6d.

  The charge E4c + E5c + E6c is a mixture of 9 Gr pixels in the pixel mixture area unit A3, and the charge E1c + E2c + E3c + E4c + E5c + E6c is 18 charges in the pixel mixture area unit A1 + A3. Are mixed, and this becomes the output charge ETc. The charge + E4d + E5d + E6d is a mixture of 9 R pixels in the pixel mixture area unit A4, and the charge E1d + E2d + E3d + E4d + E5d + E6d is 18 in the pixel mixture area unit A2 + A4. The charges are mixed, and this becomes the output charge ETd.

  When the processing on the third line is completed, the transfer gate unit W0 of the horizontal transfer unit W (the transfer gate unit adjacent to the transfer gate unit W1 on the forward direction side, not shown in FIG. 2), W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12,... Output charge CTc (disposed in the transfer gate portion W0 but not shown in FIG. 2) , DTc, ETc, CTd, DTd, ETc, CTd, DTd, ETd, CTe, DTe, ETe, CTf, DTf, ETf,. These charges are sequentially output from the output amplifier 14 to the outside. The output charge CTc is converted into the charge of the G pixel of the complementary color filter array display by mixing the charge of the Gb pixel of the primary color filter array display and the charge of the Gr pixel, and the output charge DTc is converted to the Gb pixel of the primary color filter array display. And the charge of the R pixel are converted into the charge of the Ye pixel in the complementary color filter array display, and the output charge ETc is converted into the complementary color filter array by the mixture of the charge of the Gb pixel and the charge of the Gr pixel in the primary color filter array display. The output charge CTd is converted into the charge of the G pixel of the complementary color filter array display by the mixture of the charge of the B pixel of the primary color filter array display and the charge of the R pixel, and the charge DTd is converted into the charge of the G pixel of the display. The charge of the B pixel in the primary color filter array display and the charge of the Gr pixel are converted into the charge of the Cy pixel in the complementary color filter array display, and the charge ETd is converted into the primary color filter array display. It is converted into a charge of Mg pixel of a complementary color filter array display by mixing with Viewing the B pixel charge and R pixel charge.

  One of the features of this embodiment is that in the above-described pixel charge mixing process, charges are transferred not only in the forward direction but also in the reverse direction in the horizontal transfer stage W. Therefore, as will be described in detail later, in the present embodiment, the gate bias wirings of the gates H1 to H4 that are charge transfer elements (CCDs) arranged in the horizontal transfer stage are separated from each other.

  FIG. 3 is a diagram for explaining an outline of pixel mixing in the first field shown in FIGS. 1 and 2. In FIG. 3, the gate is not shown, and only the color filter pattern is shown.

  As is apparent from FIG. 3 and the above description, all the charges of the Gb pixels in the pixel mixed area unit A1 in which the Gb pixel is in the center by the processing of the first line and the third line in the first field (9). And all (9) charges of the Gr pixels in the pixel mixture area unit A3 having the Gr pixel in the center are mixed to generate the charge of the G pixel used for the complementary color filter array display (output charge CTc). , ETc). Further, all the charges of the B pixels in the pixel mixture area unit A2 with the B pixel in the center (9) and all the charges of the R pixels in the pixel mixture area unit A4 with the R pixel in the center (9). Are mixed to generate the charge of the Mg pixel used for complementary color filter array display (output charges CTd, ETd).

  Further, the processing of the second line of the first field causes all of the charges of the Gb pixels in the pixel mixture area unit A5 (9) and all of the charges of the R pixels in the pixel mixture area unit A7 (9). Are mixed to generate the charge of the Ye pixel used for the complementary color filter array display (output charge DTc). All of the charges of the B pixels in the pixel mixture area unit A6 (9) and all of the charges of the Gr pixels in the pixel mixture area unit A8 (9) are mixed and used for complementary color filter array display. Pixel charge is generated (output charge DTd).

  Then, the output charge CTc of the G pixel, the output charge DTc of the Ye pixel, the output charge ETc of the G pixel, the output charge CTd of the Mg pixel, the output charge DTd of the Cy pixel, and the output charge ETd of the Mg pixel are sequentially output to the outside. It will be.

  However, in the pixel mixing process in the first field, the charge transfer order in the horizontal transfer stage W is not limited to the order shown in this embodiment, and any procedure may be used.

[Second-field pixel mixture]
Next, pixel mixing in the second field will be described. Here, diagrams corresponding to FIGS. 1 and 2 are omitted. FIG. 4 is a diagram for explaining an outline of pixel mixture in the second field. In FIG. 4, the illustration of the gate is omitted, and only the color filter pattern is shown.

  As shown in FIG. 4, the pixel mixed area units A′1, A′2, A′3, A′4, A′5, A′6, A′7, and A′8 in the second field are the first The pixel mixing area units A1, A2, A3, A4, A5, A6, A7, and A8 in the field are set so as to be shifted upward in the figure by 3 pixels.

  From each pixel mixed area unit A′1, A′2, A′3, A′4, A′5, A′6, A′7, A′8, the charge of each pixel is extracted to the vertical transfer stage, and 3 The procedure for mixing pixels is the same as in the first field. The charge mixing procedure in the horizontal transfer stage W is basically as shown in FIG. 2, and finally, six charges generated by mixing in the first to third lines are output from the output amplifier. It will be.

  In the processing of the first line, the charge of the R pixel (9) of the pixel mixture area unit A′1 and the charge of the B pixel (9) of the pixel mixture area unit A′3 are mixed to form a complementary color filter array. An output charge C′Tc of the display Mg pixel is generated, and the charge of the Gr pixel (9) in the pixel mixture area unit A′2 and the charge of the Gb pixel (9) in the pixel mixture area unit A′4 are mixed. Then, the output charge C′Td of the G pixel in the complementary color filter array display is generated.

  In the processing of the second line, the charge of the R pixel (9) of the pixel mixture area unit A′5 and the charge of the Gb pixel (9) of the pixel mixture area unit A′7 are mixed to form a complementary color filter array. The output charge D′ Tc of the display Ye pixel is generated, and the charge of the Gr pixel (9) in the pixel mixed area unit A′6 and the charge of the B pixel (9) in the pixel mixed area unit A′8 are mixed. Then, the output charge D′ Td of the Cy pixel in the complementary color filter array display is generated.

  In the process of the third line, as in the process of the first line, the charge of the R pixel (9) in the pixel mixture area unit A′1 and the charge of the B pixel (9) in the pixel mixture area unit A′3. To generate an output charge E′Tc of the Mg pixel of the complementary color filter array display, and the Gr pixel charge of the pixel mixture area unit A′2 and the Gb pixel (9) of the pixel mixture area unit A′4 The output charges E′Td of the G pixels in the complementary color filter array display are generated.

  Then, after the output charges CTc, DTc, ETc, CTd, DTd, ETd generated in the pixel mixing process of the first field are sequentially output to the outside, the output charge C′Tc of the Mg pixel, the output charge D of the Ye pixel 'Tc, Mg pixel output charge E'Tc, G pixel output charge C'Td, Cy pixel output charge D'Td, G pixel output charge E'Td are sequentially output to the outside. That is, the charge of the pixel in the first field and the charge of the pixel in the second field are transferred from the output amplifier 14 to the outside by the interlace scan method.

  In the present embodiment and second and third embodiments described later, all pixels are mixed in the first field pixel mixing process and the second field pixel mixing process. In other words, the pixel utilization rate is 100% in both the pixel mixing process in the first field and the pixel mixing process in the second field. However, in the first field pixel mixing process or the second field pixel mixing process, the following effects can be exhibited even if the pixel utilization rate is not 100%.

  According to the solid-state imaging device of the present embodiment, the pixel utilization rate is 100% in both the first field pixel mixing process and the second field pixel mixing process, so that the charge amount of the pixel is not increased. A moving image with a smaller frame afterimage can be obtained. Then, it is possible to output a moving image that can be adapted to various systems using the interless scanning method.

  In the solid-state imaging device, still images are generally processed and displayed in a primary color filter array (Bayer array), and only a moving image is subjected to pixel mixing processing of the present embodiment or a second embodiment described later. Is.

(Second Embodiment)
FIG. 5 is a plan view schematically showing an element arrangement in a CCD solid-state imaging device of a color solid-state imaging apparatus according to the second embodiment. The structure of the solid-state imaging device is as described in the first embodiment.

  As shown in FIG. 5, the pixels 11 arranged in a matrix are grouped in units of pixel mixture areas according to the processing method of the imaging data. In the present embodiment, the basic unit F of the pixel mixture area composed of 5 × 5 pixels is grouped, and the color of the filter of the pixel at the center position is representative of the color mixed in the pixel mixture area unit. ing. The second embodiment is a case where the pixel mixture area has 5 rows and 5 columns.

  In the present embodiment, as the pixel mixture area unit in the first field, the B pixel mixture area unit F1, the Gb pixel mixture area unit F2, the R pixel mixture area unit F3, and the Gr pixel mixture area unit F4. Gb pixel mixture area unit F5, B pixel mixture area unit F6, R pixel mixture area unit F7, and Gr pixel mixture area unit F8 are set.

  In this example, each pixel mixed area basic unit overlaps two pixels in the vertical direction and the horizontal direction. Although not shown in FIG. 5, the pixel mixing units F1 to F8 are set so as to repeatedly appear while overlapping in the vertical direction and the horizontal direction.

  The vertical transfer stage 12 (12A, 12B,...) And the horizontal transfer stage W in this embodiment are the same as those in the first embodiment. However, in this embodiment, the vertical transfer stage 12 and the vertical-horizontal transfer linking unit 15 are individually controlled.

[Pixel mixture in the first field]
In the present embodiment, only the number of the vertical transfer stage 12 that draws out the charges of the pixels of the pixel mixture area units F1 to F8 is different, but basically each pixel mixture area unit F1 by the same method as in the first embodiment. The charges of .about.F8 are drawn out to the gates of the vertical transfer stage 12 and then transferred downward, and the charges of the three pixels are mixed. Then, the data is transferred to the vertical-horizontal transfer connecting portion 15. Since the transfer and mixing procedures are the same as those in the first embodiment, detailed description thereof is omitted.

  FIG. 6 is a diagram for explaining a procedure for mixing charges in eight pixel mixed area units in the first field. The horizontal axis in the figure represents the position of the transfer gate portion in the horizontal transfer stage W, and the vertical axis in the figure represents time.

  In the present embodiment, only the mixing process of charges C1c to C6c, C1d to C6d, D1c to D6c, D1d to D6d, E1c to E6c, and E1d to E6d will be described, but as shown in FIG. 6, charges C1e to C6e , D1e to D6e, and other charges such as E1e to E6e are mixed in the same procedure.

-Line 1 processing-
First, gates V3R and V5R that can be independently driven out of charges mixed in three pixels in the vertical direction in the pixel mixture area unit held under the gate in the vertical-horizontal transfer connecting portion 15 are arranged. The charges mixed in the vertical transfer stages (15C, 15F) are drawn out to the transfer gate portions W3, W6 (each gate H1) and held as charges C1c, C1d. In the following, in FIG. 6, only the charges extracted from the vertical transfer stage are displayed, but the charges extracted from each vertical line are sequentially mixed.

  Next, the respective charges C1c and C1d are transferred in two stages in the opposite direction (meaning two stages of the transfer gate part including the gates H1 to H4), and then gates V3 and V5 that can be independently driven are arranged. The charges mixed in the vertical transfer stages (15E and 15H) are drawn out to the transfer gates W5 and W8 and held as charges C1c + C2c and C1d + C2d.

  Furthermore, after the charges C1c + C2c and C1d + C2d are transferred in two stages in the reverse direction, the mixed charges are transferred in the vertical transfer stage (15G, 15J) in which the gates V3L and V5L that can be driven independently are arranged. It is drawn out to the gate portions W7 and W10 and held as charges C1c + C2c + C3c and C1d + C2d + C3d.

  The charge C1c + C2c + C3c is a mixture of nine B pixels in the pixel mixing area unit F1, and the charge C1d + C2d + C3d is a mixture of nine Gb pixels in the pixel mixing area unit F2. It has been done. In the following description, only further mixing processing of the charges C1c + C2c + C3c and the charges C1d + C2d + C3d will be described.

  Further, after the charges C1c + C2c + C3c and C1d + C2d + C3d are transferred one stage in the forward direction, they are mixed in the vertical transfer stage (15F, 15I) in which gates V3R and V5R that can be independently driven are arranged. The charges are drawn to the transfer gate portions W6 and W9 and held as charges C1c + C2c + C3c + C4c and C1d + C2d + C3d + C4d.

  Next, after the charges C1c + C2c + C3c + C4c and C1d + C2d + C3d + C4d are transferred in four stages in the forward direction, the vertical transfer stages (15B and 15E) in which gates V3 and V5 that can be driven independently are arranged. ) Are extracted to the transfer gates W2 and W5 and held as charges C1c + C2c + C3c + C4c + C5c, C1d + C2d + C3d + C4d + C5d.

  Next, after the charges C1c + C2c + C3c + C4c + C5c and C1d + C2d + C3d + C4d + C5d are transferred in two reverse directions, the gates V3L and V5L that can be driven independently are arranged. The charges mixed at (15D, 15G) are drawn out to the transfer gates W4, W7 and held as charges C1c + C2c + C3c + C4c + C5c + C6c, C1d + C2d + C3d + C4d + C5d + C6d.

  The charge C4c + C5c + C6c is a mixture of 9 R pixels in the pixel mixture area unit F3, and the charge C1c + C2c + C3c + C4c + C5c + C6c is 18 charges in the pixel mixture area unit F1 + F3. Are mixed, and this becomes the output charge CTc. The charge + C4d + C5d + C6d is a mixture of nine Gr pixels in the pixel mixture area unit F4, and the charge C1d + C2d + C3d + C4d + C5d + C6d is 18 in the pixel mixture area unit F2 + F4. These charges are mixed, and this becomes the output charge CTd.

-Line 2 processing-
First, the output charges CTc and CTd generated by the charge mixing process on the first line are transferred one stage in the forward direction and held in the transfer gate parts W3 and W6, and then the gates in the vertical-horizontal transfer connecting part 15 Among the charges mixed in the vertical direction in the pixel mixing area unit held in the above, the charges mixed in the vertical transfer stage (15D, 15G) in which the gates V3L, V5L that can be driven independently are arranged Is extracted to the transfer gate portions W4 and W7 (each gate H1) and held as charges D1c and D1d.

  Thereafter, the output charges CTc and CTd generated in the processing of the first line are transferred together with the charges to be mixed and transferred in the charge mixing processing of the second line.

  Next, the charges D1c and D1d are transferred in two stages in the opposite direction and then mixed in the vertical transfer stage (15F, 15I) in which the gates V3R and V5R that can be independently driven are arranged. , W9 and are held as charges D1c + D2c, D1d + D2d.

  Furthermore, after the charges D1c + D2c and D1d + D2d are transferred in four stages in the forward direction, the mixed charges are transferred in the vertical transfer stages (15B, 15E) in which gates V3 and V5 that can be independently driven are arranged. It is drawn out to the gate portions W2 and W5 and held as charges D1c + D2c + D3c and D1d + D2d + D3d.

  The charge D1c + D2c + D3c is a mixture of nine Gb pixels in the pixel mixture area unit F5, and the charge D1d + D2d + D3d is a mixture of nine B pixels in the pixel mixture area unit F6. It has been done. In the following description, only further mixing processing of the charges D1c + D2c + D3c and the charges D1d + D2d + D3d will be described.

  Further, after charges D1c + D2c + D3c and D1d + D2d + D3d are transferred in two opposite directions, they are mixed in vertical transfer stages (15D, 15G) in which gates V3L and V5L that can be independently driven are arranged. The charges are drawn to the transfer gate portions W4 and W7 and held as charges D1c + D2c + D3c + D4c and D1d + D2d + D3d + D4d.

  Next, after the charges D1c + D2c + D3c + D4c and D1d + D2d + D3d + D4d are transferred in the reverse direction in two stages, the vertical transfer stages (15F, 15I) in which the gates V3R and V5R that can be driven independently are arranged. ) Are extracted to the transfer gates W6 and W9, and held as charges D1c + D2c + D3c + D4c + D5c, D1d + D2d + D3d + D4d + D5d.

  Next, after the charges D1c + D2c + D3c + D4c + D5c and D1d + D2d + D3d + D4d + D5d are transferred in four stages in the forward direction, the vertical transfer stage in which gates V3 and V5 that can be driven independently are arranged. The charges mixed at (15B, 15E) are drawn out to the transfer gates W2 and W5, and are held as charges D1c + D2c + D3c + D4c + D5c + D6c, D1d + D2d + D3d + D4d + D5d + D6d.

  The charge D4c + D5c + D6c is a mixture of 9 R pixels in the pixel mixed area unit F7, and the charge D1c + D2c + D3c + D4c + D5c + D6c is obtained by 18 charges in the mixed area unit F5 + F7. These are mixed, and this becomes the output charge DTc. The charge D4d + D5d + D6d is a mixture of nine Gr pixels in the pixel mixture area unit F8, and the charge D1d + D2d + D3d + D4d + D5d + D6d is eighteen in the pixel mixture area unit F6 + F8. Are mixed, and this becomes the output charge DTd.

-Line 3 processing-
First, after the output charges CTc, CTd, DTc, DTd generated by the charge mixing process for the first line and the second line are held in the transfer gate parts W1, W4, W2, W5, respectively, the vertical-horizontal transfer joint part Among the charges mixed in the vertical direction in the pixel mixture area unit held in the gate of 15 in the vertical direction, mixing is performed in the vertical transfer stage (15C, 15F) in which the gates V3L and V5L that can be driven independently are arranged. The charged charges are drawn out to the transfer gate portions W3 and W6 (each gate H1) and held as charges E1c and E1d.

  Thereafter, the output charges CTc, CTd, DTc, and DTd generated by the charge mixing process for the first line and the second line are transferred together with the charges that are sequentially mixed and transferred during the charge mixing process for the third line. .

  Next, after the charges E1c and E1d are transferred in two stages in the opposite direction (meaning two stages of the transfer gate portion including the gates H1 to H4), gates V3 and V5 that can be independently driven are arranged. The charges mixed in the vertical transfer stages (15E, 15H) are drawn out to the transfer gates W5, W8 and held as charges E1c + E2c, E1d + E2d.

  Further, after the charges E1c + E2c and E1d + E2d are transferred in two stages in the reverse direction, the mixed charges are transferred in the vertical transfer stage (15G, 15J) in which the gates V3L and V5L that can be independently driven are arranged. It is drawn out to the gate parts W7 and W10 and held as charges E1c + E2c + E3c and E1d + E2d + E3d.

  The charge E1c + E2c + E3c is a mixture of nine B pixels in the pixel mixture area unit F1, and the charge E1d + E2d + E3d is a mixture of nine Gb pixels in the pixel mixture area unit F2. It has been done. In the following description, only further mixing processing of the charges E1c + E2c + E3c and the charges E1d + E2d + E3d will be described.

  Further, after the charges E1c + E2c + E3c and E1d + E2d + E3d are transferred one stage in the forward direction, they are mixed in the vertical transfer stage (15F, 15I) in which gates V3R and V5R that can be driven independently are arranged. The charges are drawn to the transfer gate portions W6 and W9 and held as charges E1c + E2c + E3c + E4c and E1d + E2d + E3d + E4d.

  Next, after the charges E1c + E2c + E3c + E4c, E1d + E2d + E3d + E4d are transferred in four stages in the forward direction, the vertical transfer stages (15B, 15E in which gates V3, V5 that can be driven independently are arranged. ) Are extracted to the transfer gate portions W2 and W5, and held as charges E1c + E2c + E3c + E4c + E5c, E1d + E2d + E3d + E4d + E5d.

  Next, after the charges E1c + E2c + E3c + E4c + E5c, E1d + E2d + E3d + E4d + E5d are transferred in two reverse directions, gates V3L and V5L that can be driven independently are arranged. The charges mixed at (15D, 15G) are drawn out to the transfer gates W4, W7 and held as charges E1c + E2c + E3c + E4c + E5c + E6c, E1d + E2d + E3d + E4d + E5d + E6d.

  The charge E4c + E5c + E6c is a mixture of 9 R pixels in the pixel mixture area unit F3, and the charge E1c + E2c + E3c + E4c + E5c + E6c is 18 charges in the pixel mixture area unit F1 + F3. Are mixed, and this becomes the output charge ETc. The charge + E4d + E5d + E6d is a mixture of nine Gr pixels in the pixel mixture area unit F4, and the charge E1d + E2d + E3d + E4d + E5d + E6d is 18 in the pixel mixture area unit F2 + F4. The charges are mixed, and this becomes the output charge ETd.

  When the processing on the third line is completed, each charge is transferred to the forward direction side by two stages, and the transfer gate part W0 of the horizontal transfer stage W (the transfer gate part adjacent to the transfer gate part W1 on the forward direction side). (Not shown in FIG. 6), W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12,..., And output charge CTc (arranged in the transfer gate portion W0). Although not shown in FIG. 6, DTc, ETc, CTd, DTd, ETd, CTe, DTe, ETe, CTf, DTf, ETf,. These charges are sequentially output from the output amplifier 14 to the outside. The output charge CTc is converted into the charge of the Mg pixel of the complementary color filter array display by mixing the charge of the B pixel of the primary color filter array display and the charge of the R pixel, and the output charge DTc is converted to the Gb pixel of the primary color filter array display. And the charge of the R pixel are converted to the charge of the Ye pixel of the complementary color filter array display, and the output charge ETc is converted to the complementary color filter array by the mixture of the charge of the B pixel and the charge of the R pixel of the primary color filter array display. The output charge CTd is converted into the charge of the G pixel of the primary color filter array display and the charge of the Gr pixel by the mixture of the charge of the Gb pixel of the primary color filter array display, and the charge DTd The charge of the B pixel in the primary color filter array display and the charge of the Gr pixel are converted to the charge of the Cy pixel in the complementary color filter array display, and the charge ETd is converted into the primary color filter array table. Mixed with the Gb pixel charge and Gr pixel charge is converted to charge the G pixel of a complementary color filter array displayed by.

  One of the features of this embodiment is that in the above-described pixel charge mixing process, charges are transferred not only in the forward direction but also in the reverse direction in the horizontal transfer stage W. Therefore, as will be described in detail later, in the present embodiment, the gate bias wirings of the gates H1 to H4 that are charge transfer elements (CCDs) arranged in the horizontal transfer stage are separated from each other.

[Second-field pixel mixture]
Next, pixel mixing in the second field will be described. Here, diagrams corresponding to FIGS. 5 and 6 are omitted. FIG. 8 is a diagram for explaining an outline of pixel mixture in the second field. In FIG. 8, the gate is not shown, and only the color filter pattern is shown.

  As shown in FIG. 8, the pixel mixed area units F′1, F′2, F′3, F′4, F′5, F′6, F′7, and F′8 in the second field are the first Each pixel is set to be shifted upward by three pixels from the pixel mixed area units F1, F2, F3, F4, F5, F6, F7, and F8 in the field.

  The charge of each pixel is extracted from each pixel mixed area unit F′1, F′2, F′3, F′4, F′5, F′6, F′7, F′8 to the vertical transfer stage, The procedure for mixing three pixels at the lower gate 12 is the same as in the first field. The charge mixing procedure in the horizontal transfer stage W is basically as shown in FIG. 6, and finally, six charges generated by mixing in the first to third lines are output from the output amplifier. It will be.

  As is apparent from FIG. 8 and the above description, all the charges (9) of the Gr pixels in the Gr pixel mixture area unit F′1 are obtained by the processing of the first line and the third line of the second field, All (9) charges of the Gb pixels in the Gb pixel mixture area unit F′3 are mixed to generate the charges of the G pixels used for the complementary color filter array display (output charges C′Tc, E 'Tc). Further, all (9) charges of the R pixels in the R pixel mixture area unit F′2 are mixed with all (9) charges of the B pixels in the B pixel mixture area unit F′4. Thus, the charges of the Mg pixels used for the complementary color filter array display are generated (output charges C′Td, E′Td).

  Further, by the processing of the second line of the second field, all (9) charges of the R pixels in the R pixel mixture area unit F′5 and the Gb pixels in the Gb pixel mixture area unit F′7 are processed. All of the charges (nine) are mixed to generate the charge of the Ye pixel used for the complementary color filter array display (output charge D′ Tc). All of the charges of the Gr pixels in the Gr pixel mixture area unit F′6 (9) and all of the charges of the B pixels in the B pixel mixture area unit F′8 are mixed (9), The charge of the Cy pixel used for complementary color filter array display is generated (output charge D′ Td).

  Then, after the output charges CTc, DTc, ETc, CTd, DTd, ETd generated in the pixel mixing process of the first field are sequentially output to the outside, the output charge C′Tc of the G pixel, the output charge D of the Ye pixel 'Tc, G pixel output charge E'Tc, Mg pixel output charge C'Td, Cy pixel output charge D'Td, Mg pixel output charge E'Td are sequentially output to the outside. That is, the charge of the pixel in the first field and the charge of the pixel in the second field are transferred from the output amplifier 14 to the outside by the interlace scan method.

  According to the solid-state imaging device of the present embodiment, the pixel utilization rate is 100% in both the first field pixel mixing process and the second field pixel mixing process, so that the charge amount of the pixel is not increased. A moving image with a smaller frame afterimage can be obtained. Then, it is possible to output a moving image that can be adapted to various systems using the interless scanning method.

(Third embodiment)
FIG. 9 is a plan view schematically showing an element arrangement in a CCD solid-state image pickup device of a color solid-state image pickup device according to the third embodiment. The solid-state imaging device includes a large number of pixels 51 arranged in a matrix. The pixel 51 includes a photoelectric conversion element and a color filter attached to the front surface thereof. As the types of the pixels 51, there are a G pixel having a green filter displayed by G in the figure, a Cy pixel having a cyan filter displayed by Cy in the figure, and a magenta filter displayed by Mg in the figure. Mg pixels having a yellow pixel and a yellow pixel having a yellow filter indicated by Ye in the drawing are included. That is, the solid-state imaging device of this embodiment has a complementary color checkered arrangement structure.

  The solid-state imaging device includes a six-phase vertical transfer stage 52 (52A, 52B,...) (First direction transfer stage) configured by connecting gates V1 to V6 in series, and gates H1, H2, H3, and H4. A horizontal transfer stage W (second-direction transfer stage) configured by serially connecting the four-phase transfer gate portions W1, W2,... Configured to output charges accumulated in the horizontal transfer stage W. An output amplifier 54 and a vertical-horizontal transfer connecting portion 55 having gates (V3, V3R, V3L, V5, V5R, V5L) that can be independently driven are provided in the final stage of the vertical transfer. The vertical transfer stage 52, the vertical-horizontal transfer linking part 55, and the horizontal transfer stage W constitute means for performing pixel mixing processing in the first field and pixel mixing processing in the second field, which will be described later. The output amplifier 54 functions as means for outputting the pixel signal obtained by the pixel mixing process in the first and second fields as a signal for interlace scanning.

  Here, the gates with odd numbers such as the gates V1, V3,... In each of the vertical transfer stages 52A, 52B,... Are connected to the photoelectric conversion elements in each pixel, and charge from each pixel is transferred. The read and read charges are transferred by the gates V1 to V6.

  Further, the gates H1, H3 of the transfer gate portions W1, W2,... In the horizontal transfer stage W have a function of holding the charges transferred from the vertical-horizontal transfer joint portion 55, and the gates H2, H4 are The gates H1 and H3 function as a barrier against charge movement. Here, as will be described later, the gates H1, H2, H3... Of the transfer gate portions W1, W2,. H4 is independently wired.

  The pixels 51 arranged in a matrix are grouped in units of pixel mixture areas according to the processing method of the imaging data. In the present embodiment, the pixel unit area of the pixel mixture area composed of 5 × 5 pixels is grouped into the basic unit J, and the color of the filter of the pixel at the center position represents the color mixed in the pixel mixture area unit. ing. The third embodiment is a case where the pixel mixture area has 5 rows and 5 columns.

  As shown in FIG. 9, in the present embodiment, as the pixel mixture area unit in the first field, Mg pixel mixture area unit J1, G pixel mixture area unit J2, Cy pixel mixture area unit J3, The pixel mixture area unit J4 for Ye, the pixel mixture area unit J5 for G, the pixel mixture area unit J6 for Mg, the pixel mixture area unit J7 for Cy, and the pixel mixture area unit J8 for Ye are set.

  In this example, each pixel mixed area basic unit overlaps two pixels in the vertical direction and the horizontal direction. Although not displayed in FIG. 9, the pixel mixing units J1 to J8 are set so as to repeatedly appear while overlapping in the vertical direction and the horizontal direction.

  The vertical transfer stages 52A, 52B,... Perform basic transfer in the 6-phase mode. However, for the sake of pixel mixing, each vertical transfer stage 52A, 52B,... Has 12-phase independent wiring.

  In the present embodiment, the vertical transfer stage 52 and the vertical-horizontal transfer linking unit 55 are individually controlled.

[Pixel mixture in the first field]
In the present embodiment, the pixel mixture area units J1 to J8 are basically obtained by the same method as that of the first embodiment except that the numbers of the vertical transfer stages for extracting the charges of the pixels of the pixel mixture area units J1 to J8 are different. After the charge of J8 is drawn to each gate of the vertical transfer stage, it is transferred downward and the charge of three pixels is mixed. Since the transfer and mixing procedures are the same as those in the first embodiment, detailed description thereof is omitted.

  FIG. 10 is a diagram for explaining a procedure for mixing charges in eight pixel mixed area units in the first field. The horizontal axis in the figure represents the position of the transfer gate portion in the horizontal transfer stage W, and the vertical axis in the figure represents time.

  In this embodiment, only the mixing process of the charges X1c to X6c, X1d to X6d, Y1c to Y6c, Y1d to Y6d, Z1c to Z6c, Z1d to Z6d will be described, but as shown in FIG. 10, the charges X1e to X6e , Y1e to Y6e, Z1e to Z6e, and other charges are mixed in the same procedure.

-Line 1 processing-
First, gates V3R and V5R that can be independently driven out of charges mixed in the vertical direction in the pixel mixing area unit held under the gate in the vertical-horizontal transfer connecting portion 55 are arranged. The charges mixed in the vertical transfer stages (55C and 55F) are drawn out to the transfer gate portions W3 and W6 (each gate H1) and held as charges X1c and X1d. In the following, in FIG. 10, only the charges extracted from the vertical transfer stage are displayed, but the charges extracted from each vertical line are sequentially mixed.

  Next, after the charges X1c and X1d are transferred in two stages in the opposite direction (meaning two stages of the transfer gate portion including the gates H1 to H4), gates V3 and V5 that can be driven independently are arranged. The charges mixed in the vertical transfer stages (55E and 55H) are drawn out to the transfer gates W5 and W8 and held as charges X1c + X2c and X1d + X2d.

  Furthermore, after the charges X1c + X2c and X1d + X2d are transferred in two stages in the opposite direction, the mixed charges are transferred in the vertical transfer stage (55G, 55J) in which the gates V3L and V5L that can be driven independently are arranged. It is drawn out to the gate portions W7 and W10 and held as charges X1c + X2c + X3c, X1d + X2d + X3d.

  The charge X1c + X2c + X3c is a mixture of nine Mg pixels in the pixel mixing area unit J1, and the charge X1d + X2d + X3d is a mixture of nine G pixels in the pixel mixing area unit J2. It has been done. In the following description, only the further mixing process of the charges X1c + X2c + X3c and the charges X1d + X2d + X3d will be described.

  Further, after the charges X1c + X2c + X3c, X1d + X2d + X3d are transferred one stage in the forward direction, they are mixed in the vertical transfer stage (55F, 55I) in which gates V3R, V5R that can be driven independently are arranged. The charges are extracted to the transfer gate portions W6 and W9 and held as charges X1c + X2c + X3c + X4c, X1d + X2d + X3d + X4d.

  Next, after the charges X1c + X2c + X3c + X4c, X1d + X2d + X3d + X4d are transferred in four stages in the forward direction, the vertical transfer stages (55B, 55E) in which gates V3, V5 that can be independently driven are arranged. ) Are extracted to the transfer gates W2 and W5 and held as charges X1c + X2c + X3c + X4c + X5c, X1d + X2d + X3d + X4d + X5d.

  Next, after the charges X1c + X2c + X3c + X4c + X5c, X1d + X2d + X3d + X4d + X5d are transferred in two reverse directions, the gates V3L and V5L that can be driven independently are arranged. The charges mixed at (55D, 55G) are drawn out to the transfer gate portions W4 and W7 and held as charges X1c + X2c + X3c + X4c + X5c + X6c, X1d + X2d + X3d + X4d + X5d + X6d.

  The charge X4c + X5c + X6c is a mixture of 9 Cy pixels in the pixel mixing area unit J3, and the charge X1c + X2c + X3c + X4c + X5c + X6c is 18 charges in the pixel mixing area unit J1 + J3. Are mixed, and this becomes the output charge XTc. The charge X4d + X5d + X6d is a mixture of nine Ye pixels in the pixel mixture area unit J4, and the charge X1d + X2d + X3d + X4d + X5d + X6d is 18 pixels in the pixel mixture area unit J2 + J4. Are mixed, and this becomes the output charge XTd.

-Line 2 processing-
First, the output charges XTc and XTd generated by the charge mixing process on the first line are transferred one stage in the forward direction and held in the transfer gate parts W3 and W6, and then the gates in the vertical-horizontal transfer connecting part 55 Among the charges mixed in the vertical direction in the pixel mixing area unit held in the vertical direction, the charges mixed in the vertical transfer stage (55D, 55G) in which the gates V3L, V5L that can be driven independently are arranged Is extracted to the transfer gate portions W4 and W7 (each gate H1) and held as charges Y1c and Y1d.

  Thereafter, the output charges XTc and XTd generated in the first line processing are transferred together with the charges that are sequentially mixed and transferred in the charge mixing processing for the second line.

  Next, the charges Y1c and Y1d are transferred in two stages in the opposite direction and then mixed in the vertical transfer stage (55F, 55I) in which the gates V3R and V5R that can be independently driven are arranged. , W9 and are held as charges Y1c + Y2c, Y1d + Y2d.

  Furthermore, after the charges Y1c + Y2c and Y1d + Y2d are transferred in four stages in the forward direction, the mixed charges are transferred in the vertical transfer stages (55B, 55E) in which gates V3 and V5 that can be independently driven are arranged. It is drawn out to the gate portions W2 and W5 and held as charges Y1c + Y2c + Y3c and Y1d + Y2d + Y3d.

  The charge Y1c + Y2c + Y3c is a mixture of nine G pixels in the pixel mixing area unit J5, and the charge Y1d + Y2d + Y3d is a mixture of nine Mg pixels in the pixel mixing area unit J6. It has been done. Also in the following description, only further mixing processing of the charges Y1c + Y2c + Y3c and the charges Y1d + Y2d + Y3d will be described.

  Further, after the charges Y1c + Y2c + Y3c and Y1d + Y2d + Y3d are transferred in the opposite direction, they are mixed in the vertical transfer stage (55D, 55G) in which the gates V3L and V5L that can be driven independently are arranged. The charges are drawn to the transfer gate portions W4 and W7 and held as charges Y1c + Y2c + Y3c + Y4c and Y1d + Y2d + Y3d + Y4d.

  Next, after the charges Y1c + Y2c + Y3c + Y4c and Y1d + Y2d + Y3d + Y4d are transferred in the reverse direction in two stages, the vertical transfer stages (55F, 55I) in which the gates V3R and V5R that can be driven independently are arranged. ) Is extracted to the transfer gates W6 and W9 and held as charges Y1c + Y2c + Y3c + Y4c + Y5c, Y1d + Y2d + Y3d + Y4d + Y5d.

  Next, after the charges Y1c + Y2c + Y3c + Y4c + Y5c, Y1d + Y2d + Y3d + Y4d + Y5d are transferred in four stages in the forward direction, the vertical transfer stage in which gates V3, V5 that can be driven independently are arranged. The charges mixed at (55B, 55E) are drawn out to the transfer gate portions W2 and W5, and are held as charges Y1c + Y2c + Y3c + Y4c + Y5c + Y6c, Y1d + Y2d + Y3d + Y4d + Y5d + Y6d.

  The charge Y4c + Y5c + Y6c is a mixture of 9 Cy pixels in the pixel mixing area unit J7, and the charge Y1c + Y2c + Y3c + Y4c + Y5c + Y6c is obtained by 18 charges in the mixing area unit J5 + J7. These are mixed, and this becomes the output charge YTc. The charge Y4d + Y5d + Y6d is a mixture of nine Ye pixels in the pixel mixture area unit J8, and the charge Y1d + Y2d + Y3d + Y4d + Y5d + Y6d is 18 pixels in the pixel mixture area unit J6 + J8. Are mixed, and this becomes the output charge YTd.

-3rd line processing
First, the output charges XTc, XTd, YTc, YTd generated by the charge mixing process for the first line and the second line are transferred in two stages in the forward direction and held in the transfer gate portions W1, W4, W2, W5, respectively. Thereafter, gates V3R and V5R that can be independently driven out of the charges mixed in the vertical direction in the pixel mixed area unit held under the gate in the vertical-horizontal transfer connecting portion 55 are arranged. The charges mixed in the vertical transfer stages (55C, 55F) are drawn out to the transfer gate portions W3, W6 (each gate H1) and held as charges Z1c, Z1d.

  Thereafter, the output charges XTc, XTd, YTc and YTd generated by the charge mixing process for the first line and the second line are transferred together with the charges to be mixed and transferred in the charge mixing process for the third line. The

  Next, after the charges Z1c and Z1d are transferred in two stages in the opposite direction (meaning two stages of the transfer gate portion including the gates H1 to H4), gates V3 and V5 that can be independently driven are arranged. The charges mixed in the vertical transfer stages (55E and 55H) are drawn out to the transfer gates W5 and W8 and held as charges Z1c + Z2c and charges Z1d + Z2d.

  Furthermore, after the charges Z1c + Z2c and Z1d + Z2d are transferred in two stages in the reverse direction, the mixed charges are transferred in the vertical transfer stage (55G, 55J) in which the gates V3L and V5L that can be driven independently are arranged. It is extracted to the gate portions W7 and W10 and held as charges Z1c + Z2c + Z3c and charges Z1d + Z2d + Z3d.

  The charge Z1c + Z2c + Z3c is a mixture of 9 Mg pixels in the pixel mixing area unit J1, and the charge Z1d + Z2d + Z3d is a mixture of 9 G pixels in the pixel mixing area unit J2. It has been done. In the following description, only further mixing processing of the charges Z1c + Z2c + Z3c and Z1d + Z2d + Z3d will be described.

  Further, after the charges Z1c + Z2c + Z3c and Z1d + Z2d + Z3d are transferred one stage in the forward direction, they are mixed in the vertical transfer stage (55F, 55I) in which gates V3R and V5R that can be independently driven are arranged. The charges are drawn to the transfer gate portions W6 and W9 and held as charges Z1c + Z2c + Z3c + Z4c and Z1d + Z2d + Z3d + Z4d.

  Next, after the charges Z1c + Z2c + Z3c + Z4c and Z1d + Z2d + Z3d + Z4d are transferred in four stages in the forward direction, the vertical transfer stages (55B and 55E) in which gates V3 and V5 that can be driven independently are arranged. ) Are extracted to the transfer gates W2 and W5 and held as charges Z1c + Z2c + Z3c + Z4c + Z5c, Z1d + Z2d + Z3d + Z4d + Z5d.

  Next, after the charges Z1c + Z2c + Z3c + Z4c + Z5c and Z1d + Z2d + Z3d + Z4d + Z5d are transferred in two reverse directions, the gates V3L and V5L that can be driven independently are arranged. The charges mixed at (55D, 55G) are drawn out to the transfer gates W4, W7 and held as charges Z1c + Z2c + Z3c + Z4c + Z5c + Z6c, Z1d + Z2d + Z3d + Z4d + Z5d + Z6d.

  The charge Z4c + Z5c + Z6c is a mixture of 9 Cy pixels in the pixel mixing area unit J3, and the charge Z1c + Z2c + Z3c + Z4c + Z5c + Z6c is 18 charges in the pixel mixing area unit J1 + J3. Are mixed, and this becomes the output charge ZTc. The charge Z4d + Z5d + Z6d is a mixture of nine Ye pixels in the pixel mixture area unit J4, and the charge Z1d + Z2d + Z3d + Z4d + Z5d + Z6d is 18 pixels in the pixel mixture area unit J2 + J4. Are mixed, and this becomes the output charge ZTd.

  When the processing on the third line is completed, each output charge is transferred in two stages in the forward direction, and the transfer gate W0 of the horizontal transfer unit W (the transfer gate adjacent to the transfer gate W1 in the forward direction). Part, not shown in FIG. 10), W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12,. Although not shown in FIG. 10, YTc, ZTc, XTd, YTd, ZTc, XTd, YTd, ZTd, XTe, YTe, ZTe, XTf, YTf, ZTf,.

  These charges are sequentially output from the output amplifier 14 to the outside. The output charge XTc is a mixture of the charge of the Mg pixel of the complementary color filter array display and the charge of the Cy pixel, and the output charge YTc is the charge of the G pixel of the complementary color filter array display and the charge of the Cy pixel. The output charge ZTc is a mixture of the charge of the Mg pixel of the complementary color filter array display and the charge of the Cy pixel, and the output charge XTd is the charge of the G pixel of the complementary color filter array display. And the charge of the Ye pixel are mixed, the charge YTd is a mixture of the charge of the Mg pixel of the complementary color filter array display and the charge of the Ye pixel, and the charge ZTd is the charge of the complementary color filter array display. The charge of the G pixel and the charge of the Ye pixel are mixed.

  One of the features of this embodiment is that in the above-described pixel charge mixing process, charges are transferred not only in the forward direction but also in the reverse direction in the horizontal transfer stage W. Therefore, as will be described in detail later, in the present embodiment, the gate bias wirings of the gates H1 to H4 that are charge transfer elements (CCDs) arranged in the horizontal transfer stage are separated from each other.

[Second-field pixel mixture]
Next, pixel mixing in the second field will be described. Here, diagrams corresponding to FIGS. 9 and 10 are omitted. FIG. 12 is a diagram for explaining an outline of pixel mixture in the second field. In FIG. 12, the gate is not shown, and only the color filter pattern is shown.

  As shown in FIG. 12, pixel mixed area units J′1, J′2, J′3, J′4, J′5, J′6, J′7, and J′8 in the second field are the first The pixel mixing area units J1, J2, J3, J4, J5, J6, J7, and J8 in the field are set so as to be shifted upward by three pixels.

  From each pixel mixed area unit J′1, J′2, J′3, J′4, J′5, J′6, J′7, J′8, the charge of each pixel is drawn to the vertical transfer stage 12, The procedure for mixing three pixels at the bottom gate is the same as in the first field. The charge mixing procedure in the horizontal transfer stage W is basically as shown in FIG. 10, and finally, six charges generated by mixing in the first to third lines are output from the output amplifier. It will be.

  As is apparent from FIG. 12 and the above description, all the charges of the Ye pixels in the Ye pixel mixture area unit J′1 (9) are obtained by the processing of the first line and the third line of the second field, All (9) charges of the G pixel in the G pixel mixing area unit J′3 are mixed (output charge Ye + G). In addition, all of the charges of the Cy pixels in the Cy pixel mixture area unit J′2 (9) and all of the charges of the Mg pixels in the Mg pixel mixture area unit J′4 (9) are mixed. (Output charge Cy + Mg).

  Further, by the processing of the second line of the second field, all (9) charges of the Cy pixels in the Cy pixel mixture area unit J′5 and the G pixels in the G pixel mixture area unit J′7 are processed. All (9) charges are mixed (output charge Cy + G). All (9) charges of Ye pixels in the pixel mixing area unit J′6 of Ye and all (9) charges of Mg pixels in the pixel mixing area unit J′8 of Mg are mixed ( Output charge Ye + Mg).

  Then, after the output charges XTc, YTc, ZTc, XTd, YTd, ZTd generated in the pixel mixing process of the first field are sequentially output to the outside, the output charges X′Tc, Cy + G pixels of the Ye + G pixel are output Y The output charge Z′Tc of the “Tc, Ye + G pixel, the output charge X′Td of the Cy + Mg pixel, the output charge Y′Td of the Mg + Ye pixel, and the output charge Z′Td of the Mg + Cy pixel are sequentially output to the outside. That is, the charge of the pixel in the first field and the charge of the pixel in the second field are transferred from the output amplifier 14 to the outside by the interlace scan method.

  According to the solid-state imaging device of the present embodiment, the pixel utilization rate is 100% in both the first field pixel mixing process and the second field pixel mixing process, so that the charge amount of the pixel is not increased. A moving image with a smaller frame afterimage can be obtained. Then, it is possible to output a moving image that can be adapted to various systems using the interless scanning method.

  In this embodiment, the signal after the pixel mixing process is the charge signal for the complementary color filter, but may be the charge signal for the primary color filter.

[Solid-state imaging device system]
FIG. 13 is a block diagram illustrating a configuration of a solid-state imaging device common to the first to third embodiments.

  The solid-state imaging device 101 is a solid-state imaging device in each embodiment, converts received light into an electrical signal, and outputs the electrical signal to the signal conversion unit 113. The solid-state image sensor driving unit 112 controls the solid-state image sensor 101 by outputting a control signal.

  The signal conversion unit 113 performs CDS (Correlated Double Sampling), AGC (Auto Gain Control), A / D with respect to an electrical signal that is an electric charge of each pixel input from an output amplifier connected to the horizontal transfer stage of the solid-state imaging device 101. Each process of (Analog / Digital) conversion is performed. In the CDS, noise removal of the electric signal output from the solid-state image sensor 101 is performed. In AGC, the output level of a signal after noise removal by CDS processing is adjusted. A / D conversion converts solid-state imaging data after AGC level adjustment to a digital signal.

  The signal conversion unit 113 outputs the converted digital signals for three lines at a time to the rearrangement unit 115.

  An SSG (Sync Signal Generator) 114 generates a reference signal that determines the drive timing of the solid-state imaging device 101 and the signal processing unit 119. That is, the timing of the signal applied to each gate of the vertical transfer stage, extension stage, and horizontal transfer stage shown in FIG. The SSG 114 outputs a reference signal that determines the start timing of the field (screen) and the start of the horizontal line to the rearrangement unit 115.

  A DRAM (Dynamic Random Access Memory) 116 holds the digital data rearranged by the rearrangement unit 115.

  The DRAM control unit 117 reads out data related to the charges of the rearranged pixels from the DRAM 116 and outputs the data to the output signal generation unit 118.

  The output signal generation unit 118 receives Y-related data after passing through the rearrangement block, and performs Y signal processing for generating and outputting a luminance signal and C signal processing for generating and outputting a color difference signal. The output signal generation unit 118 generates and outputs a luminance signal in the Y signal processing, but the image after conversion from the data related to the charge of the pixel to the Y signal may give a clear image, so further contour correction By performing the above, contour enhancement is performed.

  The rearrangement unit 115 performs rearrangement processing on the digital signal output from the signal conversion unit 113 according to the reference signal output from the SSG 114. For example, as shown in FIG. 2, the digital signal output from the horizontal transfer unit of the solid-state imaging device 101 and processed by the signal conversion unit 113 is a pixel charge (in FIG. 2, pixel charges E6a, C6a, D6a , E6b, C6b, and D6b are output in series), and the processing for returning the signals to the original two-dimensional array is the rearrangement processing.

  Further, in each of the above embodiments, since the so-called zigzag mixing process is performed in which the pixels of the plurality of pixel mixing area basic units A1 to A8 whose vertical transfer stages of the center pixel are shifted are performed, in the rearrangement unit 115, When the image signal is reproduced, the center of gravity is also corrected as will be described later.

14A to 14C are respectively a cross-sectional view of a transfer gate portion in a horizontal transfer stage having a configuration common to the embodiments, a cross-sectional view of a conventional transfer gate portion, and a conventional transfer gate portion. 3 is a diagram showing a potential state in a cross section that crosses a p ⁺ layer 151 and an n-type semiconductor layer 150. FIG.

As shown in FIG. 14A, each transfer gate portion of the solid-state imaging device includes charge holding gates H1 and H3 each having a polysilicon electrode 153 embedded in an insulating film 152 on a semiconductor substrate, and a semiconductor substrate. Barrier gates H2 and H4 each having an Al electrode 154 provided thereon with an insulating film 152 interposed therebetween are alternately arranged in series. Below the charge holding gates H1 and H3 is an n-type semiconductor layer 150 containing a relatively low concentration n-type impurity, and below the barrier gates H2 and H4 is a P ⁺ layer containing a high concentration p-type impurity. 151. The wiring 157 connected to the Al electrode 154 and the wiring 158 connected to the polysilicon electrode 153 are separated from each other.

In the transfer gate section in the conventional solid-state imaging device, the structure of the gate H1, H2 and the semiconductor substrate is the same as the structure shown in FIG. 14 (a), the bias phi _H1 reverse phase respectively, undergo phi _H2 The wiring 157 and the wiring 158 are connected to each other. Then, as shown in FIG. 14C, since a common bias (φ _H1 or φ _H2 ) is applied to the Al electrode 154 and the polysilicon electrode 153 in one transfer gate portion, The potential difference between the n-type semiconductor region 150 and the P ⁺ layer 151 below the gate H2 is substantially constant. Therefore, in the case of the potential relationship shown in FIG. 14C, the charge is transferred to the left side, but the charge is not transferred to the right side.

On the other hand, according to the structure of the CCD of this embodiment shown in FIG. 14A, the wiring 157 connected to the Al electrode 154 and the wiring 158 connected to the polysilicon electrode 153 are separated from each other. Since the potential levels of the n-type semiconductor region 150 below the gate H1 and the p ⁺ layer 151 below the gate H2 are reversed from those when receiving a common bias, they are in the opposite direction (right side in the figure). Can also transfer charge. Therefore, according to this embodiment, in the horizontal transfer stage W, the charge is moved not only in the forward direction toward the output amplifier 14 (or 54) but also in the reverse direction away from the output amplifier 14 (or 54). be able to. As a result, the following control became possible.

FIGS. 20A and 20B are diagrams for explaining the respective biases φ _{H1 to} φ _H4 and channel potentials in the forward and backward transfer of charges in the transfer gate portion of the horizontal transfer in order. It is.

As shown in FIG. 20A, by setting φ _H1 = φ _H2 , φ _H3 = φ _H4 , φ _H1 <φ _H4 , the channel potential is in the order of gate H3, gate H4, gate H1, and gate H2. As it goes low, the charge is transferred in the forward direction.

As shown in FIG. 20B, by setting φ _H1 = φ _H4 , φ _H2 = φ _H3 , φ _H1 <φ _H2 , the channel potential is changed in the order of gate H3, gate H4, gate H1, and gate H2. As it becomes higher, the charge is transferred in the opposite direction.

FIG. 21 is a timing chart showing temporal changes in bias applied to the gates of the horizontal transfer stage W and the vertical-horizontal transfer linking portion 15. In FIG. 21, the upper end of each pulse of the horizontal transfer stage W indicates the L level (0 V), the lower end indicates the H level (3.3 V), and the upper end of each pulse of the vertical-horizontal transfer connecting portion 15 is the L level ( −8V), and the lower end indicates the H level (0V). In FIG. 21, only the pulse shape in the case of forward transfer is shown for easy understanding of the number of pulses and the number of transferred stages, and φ _H1 = φ _H2 and φ _H3 = φ _H4 are always shown. However, in the case of reverse transfer, φ _H1 = φ _H4 and φ _H2 = φ _H3 , so the actual pulse shape is different from that in FIG. FIG. 21 shows the charge mixing process from the first line to the third line of the first field in the first embodiment shown in FIG. 2 as an example. The mixing process can be easily performed only by appropriately changing the respective biases of the transfer stage and the vertical-horizontal transfer connecting portion. Hereinafter, the relationship between the bias in the charge mixing process in FIG. 2 and the charge mixing operation will be described with reference to FIG.

  First, at timings t0 to t1, charges held at V3L and V4 are drawn to the horizontal transfer stage W (charges C1b, C1c, C1d, and C1e in FIG. 2).

Then, after the timing t1, by supplying twice the pulses of the bias φ _{H1 to} φ _H4 having the elevation relationship shown in FIG. 20B, the charges in the horizontal transfer stage are transferred in two stages in the reverse direction (FIG. 2). Charge C1b, C1c, C1d, C1e). Thereafter, with the horizontal transfer stage biases φ _{H1 to} φ _H4 fixed (that is, with the charges fixed), the charges held in the gates V3R and V4 are extracted to the horizontal transfer stage W (in FIG. 2). Charges C2b, C2c, C2d, C2e) are mixed with the charges transferred in the horizontal transfer stage.

  Thereafter, by the same operation as described above, during the timing t2 to t6, in the horizontal transfer stage, reverse two-stage transfer, forward one-stage transfer, forward four-stage transfer, reverse two-stage transfer, A mixing process with the charges drawn from the vertical-horizontal transfer joint is performed. The process during this period is the charge mixing process for the first line shown in FIG.

  Next, after timing t6, the charges mixed in the first line (the output charges CTc, CTd, etc. in the first embodiment) are transferred in two stages in the forward direction, whereby the second line shown in FIG. At the start, one stage is positioned on the forward direction side from the charge transferred from the vertical-horizontal transfer joint.

  Then, during the timing t6 to t12, in the horizontal transfer stage, the reverse two-stage transfer, the forward four-stage transfer, the reverse two-stage transfer, the reverse two-stage transfer, the forward four-stage transfer, and the vertical − A mixing process with the charges extracted from the horizontal transfer joint is performed. The process during this period is the charge mixing process for the second line shown in FIG. Meanwhile, the charge mixed in the first line (the output charges CTc, CTd, etc. in the first embodiment) moves while being positioned one step ahead of the charge mixed in the second line. It will be.

  Next, after the timing t12, the charges mixed in the first line and the second line (output charges CTc, CTd, DTc, DTd, etc. in the first embodiment) are transferred in two stages in the forward direction. At the start of the third line shown in FIG. 2, it is positioned one stage forward from the charge transferred from the vertical-horizontal transfer joint.

  Then, during the timing t12 to t18, in the horizontal transfer stage, the reverse two-stage transfer, the reverse two-stage transfer, the forward one-stage transfer, the forward four-stage transfer, the reverse two-stage transfer, and the vertical − A mixing process with the charges extracted from the horizontal transfer joint is performed. This process is the charge mixing process on the third line shown in FIG. Meanwhile, the charges mixed in the first line and the second line (the output charges CTc, CTd, DTc, DTd, etc. in the first embodiment) are one order higher than the charges mixed in the third line. It moves while being located on the direction side.

  Immediately after the timing t18, the output charges are aligned as shown in the lowermost stage of FIG.

(Comparison of mixing methods in the first and second embodiments)
FIGS. 15A and 15B show the centroid position relationship in the pixel mixture of the vertical first line (odd line) and vertical second line (even line) in the first field and the second field in the first embodiment. It is a figure explaining. FIGS. 16A and 16B show the centroid positional relationship in the pixel mixture of the vertical first line (odd line) and vertical second line (even line) in the first field and the second field in the second embodiment. It is a figure explaining.

  In FIG. 15A, the centroid B1 is the centroid of pixel mixture between the pixel mixture area units A1 and A3 in the first vertical line of the first field, and the centroid B2 is the pixel in the vertical first line of the first field. The center of gravity of the pixel mixture between the mixed area units A2 and A4, the center of gravity B3 is the center of gravity of the pixel mixture between the pixel mixed area units A5 and A7 of the vertical second line of the first field, and the center of gravity B4 is the first center of gravity. This is the center of gravity of pixel mixing between the pixel mixing area units A6 and A8 on the second vertical line of the field. In FIG. 15B, the centroid B′1 is the centroid of pixel mixture between the pixel mixture area units A′1 and A′3 in the vertical first line of the second field, and the centroid B′2 is the second centroid. This is the centroid of pixel mixing between the pixel mixing area units A′2 and A′4 of the vertical first line of the field, and the centroid B′3 is the pixel mixing area unit A′5 of the vertical second line of the second field. The center of gravity of the pixel mixture between A′7, and the center of gravity B′4 is the center of gravity of the pixel mixture between the pixel mixture area units A′6 and A′8 of the second vertical line in the second field.

  In FIG. 16A, the centroid G1 is the centroid of the pixel mixture between the pixel mixture area units F1 and F3 in the first vertical line of the first field, and the centroid G2 is the pixel in the vertical first line of the first field. The center of gravity of the pixel mixture between the mixed area units F2 and F4, the center of gravity G3 is the center of gravity of the pixel mixture between the pixel mixed area units F5 and F7 of the vertical second line of the first field, and the center of gravity G4 is the first center of gravity. This is the center of gravity of pixel mixing between the pixel mixing area units F6 and F8 on the second vertical line of the field. In FIG. 16B, the centroid G′1 is the centroid of pixel mixture between the pixel mixture area units F′1 and F′3 of the vertical first line of the second field, and the centroid G′2 is the second centroid G′2. This is the centroid of pixel mixing between the pixel mixing area units F′2 and F′4 in the vertical first line of the field, and the centroid G′3 is the pixel mixing area unit F′5 in the vertical second line of the second field. The center of gravity of the pixel mixture between F′7, and the center of gravity G′4 is the center of gravity of the pixel mixture between the pixel mixture area units F′6 and F′8 of the second vertical line in the second field.

  As shown in FIG. 15A, in the horizontal direction, the position of the center of gravity B1 in the pixel mixture of the first vertical line (odd line) in the first field is the center of gravity B3 in the pixel mixture of the second vertical line (even line). , B4 at the midpoint position, and the position of the centroid B4 in the pixel mixture of the vertical second line (even number line) is at the midpoint position of the centroids B1 and B2 in the pixel mixture of the vertical first line (odd line). In other words, the centroid positions B1, B2,... In the pixel mixture of the vertical first line and the centroid positions B3, B4,... In the pixel mixture of the vertical second line are sequentially aligned at equal intervals in the horizontal coordinate. It will be. The horizontal position of the center of gravity in the pixel mixture of the third vertical line is the same as the position of the center of gravity in the pixel mixture of the first vertical line. As shown in FIG. 15B, the same applies to the pixel mixture in the second field.

  On the other hand, as shown in FIG. 16A, the horizontal position of the center of gravity G1 in the pixel mixture of the first vertical line (odd line) in the first field is the center of gravity G3 in the pixel mixture of the second vertical line (even line). , G4 are deviated from the midpoint position, and the horizontal position of the centroid G4 in the pixel mixture of the vertical second line is deviated from the midpoint position of the centroids G1 and G2 in the pixel mixture of the vertical first line. is there. As shown in FIG. 16B, the same applies to the pixel mixture in the second field.

  17 (a) and 17 (b) show the pixel mixture of the first vertical line in the case shown in FIGS. 15 (a) and 15 (b) and the case shown in FIGS. 16 (a) and 16 (b), respectively. FIG. 6 is a diagram for explaining the relationship between the center of gravity position due to and the center of gravity position due to pixel mixture in the second vertical line. As shown in FIG. 17A, when the pixel mixing process shown in FIGS. 15A and 15B is performed, the centroid positions B1, B2,... It can be seen that the center-of-gravity positions B3, B4,... In the pixel mixture on the second line are aligned at equal intervals in order in the horizontal coordinate. On the other hand, as shown in FIG. 17B, when the pixel mixing process shown in FIGS. 16A and 16B is performed, the gravity center positions G1, G2,... The center-of-gravity positions G3, G4,... In the pixel mixture of the second vertical line are arranged at irregular intervals in the horizontal coordinate.

  FIG. 18 is a block circuit diagram schematically showing the configuration of the center-of-gravity position correction circuit. 19 (a) and 19 (b) show the charge signals in units of pixel mixture areas in the cases shown in FIGS. 15 (a) and 15 (b) and in the cases shown in FIGS. 16 (a) and 16 (b), respectively. It is a figure which illustrates the process which adds and produces | generates a luminance signal.

As shown in FIG. 18, the center-of-gravity position correction circuit includes an arithmetic circuit 121 that performs an operation of (1 + z ⁻¹ ) / 2, and a switching circuit 123. When the luminance signal SA obtained by adding the charge signals of adjacent pixel mixed area units is received, when the luminance signal SA is a luminance signal of a reference line (odd line or even line), In accordance with the control signal LS, the switching circuit 123 is switched so as to connect to the lower terminal in the figure, and a signal bypassing the arithmetic circuit 121 is output as the output signal Sout. On the other hand, when the luminance signal SA is a luminance signal of a non-reference line (even number line or odd number line), the switching circuit 123 is switched to connect to the upper terminal in the figure in accordance with the control signal LS, and the calculation is performed. A signal that has undergone arithmetic processing (1 + z ⁻¹ ) / 2 for correcting the center of gravity in the circuit 121 is output as an output signal Sout. This calculation process (1 + z ⁻¹ ) / 2 is a process of interpolating a new luminance signal at the midpoint position between the luminance signals.

  In the present embodiment, when pixel mixing processing is performed in the solid-state imaging device, a pixel signal of a complementary color filter array is output. Then, it is assumed that pixel signals of colors as shown as examples on the upper side of FIGS. 19A and 19B are input as pixel signals of odd lines and even lines. At this time, in the odd lines, the Cy pixel signal, which is a pixel signal in adjacent pixel mixing area units, and the Ye pixel signal are mixed to generate a luminance signal SA1, and the pixel signal is in adjacent pixel mixing area units. The Ye pixel signal and the Cy pixel signal are mixed to generate the luminance signal SA2. In the even line, the luminance signal SA3 is generated by mixing the charge signal of the Mg pixel and the charge signal of the G pixel, which are pixel signals of adjacent pixel mixing area units, and the pixel signal of the adjacent pixel mixing area unit A certain G pixel signal and Mg pixel signal are mixed to generate a luminance signal SA4.

Then, the case where the odd line is used as a reference will be described. By the switching control of the switching circuit 123, the luminance signals SA1 and SA2 of the odd line bypass the arithmetic circuit 121 and are output as the output signal Sout. Not done. On the other hand, the luminance signals SA3 and SA4 of the even lines are input to the arithmetic circuit 121 and subjected to correction processing of the center of gravity, and then output as the output signal Sout. In that case, as shown in FIGS. 15A and 15B, in the horizontal coordinate direction, the position of the center of gravity of the charge signal after mixing in the pixel mixed area unit in the odd line and after mixing in the pixel mixed area unit in the even line. When the charge signal centroid positions are at the other midpoint position, as shown in FIG. 19A, the luminance signals SA1 and SA2 in the odd lines and the luminance signals SA3 and SA4 in the even lines are obtained. , In the center position of the other. Therefore, by the arithmetic processing (1 + z ⁻¹ ) / 2 in the arithmetic circuit 121, the gravity center positions of the even line luminance signals SA3 and SA4 are easily corrected so as to coincide with the odd line luminance signals SA1 and SA2. Is done. When the even-numbered line is used as the reference line, the process opposite to that described above is performed, and the center-of-gravity position is easily corrected.

  However, as shown in FIGS. 16A and 16B, in the horizontal coordinate direction, the barycentric position of the charge signal after mixing in the pixel mixture area unit in the odd-numbered line and the pixel mixture area unit in the even-numbered line after mixing. When the center of gravity of the charge signal is not located at the other midpoint position, as shown in FIG. 19B, the luminance signals SA1 and SA2 in the odd lines and the luminance signals SA3 and SA4 in the even lines are They are at a position deviated from the other center position. Therefore, in order to correct the center of gravity of the luminance signals SA3 and SA4 of the even lines so as to coincide with the center of gravity of the luminance signals SA1 and SA2 of the odd lines, the circuit shown in FIG. It is necessary to have a circuit configuration that performs an appropriate process.

  Accordingly, for example, two pixel mixture areas that are mixed in the pixel mixture of the first vertical line (odd line) are mixed in a so-called zigzag manner in which two pixel mixture area units mixed in the horizontal direction are shifted by one pixel from each other. Two pixel mixture areas that are non-zigzag mixed in which two pixel mixture area units that are mixed in the pixel mixture of the second vertical line (even line) are provided in the same position in the horizontal direction. In the case of the unit, the two pixel mixed area units mixed zigzag may be provided at a position shifted by one pixel in the horizontal direction with respect to the two pixel mixed area units mixed non-zigzag.

  In other words, when the repetition unit that is the basis of the arrangement of the pixel mixture area units is four pixel mixture area units arranged in the vertical direction in which two pixel additions are added, the position of one pixel mixture area unit is set in the horizontal direction. It is preferable to shift the position of one pixel mixing area unit and another pixel mixed area unit by shifting two pixels in the horizontal direction.

  According to each of the above embodiments, in moving image capturing using a color filter array ultra-high pixel solid-state image sensor having a unit arrangement of 2 rows and 2 columns, an image including a high-frequency signal is captured in both the horizontal and vertical directions of the video signal. Even in this case, the return component of the high frequency component to the low frequency is greatly reduced, and not only the false signal is greatly suppressed for both the luminance signal and the chromaticity signal, but also the pixel sampling density in the horizontal and vertical directions is reduced. Since perfect balancing can be achieved, the horizontal resolution and the vertical resolution can be made the same, and since all pixels can be output without being discarded, the sensitivity of the solid-state imaging device is greatly improved. There is an effect. Furthermore, even if the number of pixels of the solid-state image sensor increases, the optimum pixel count in the interlace scan method can be obtained by enlarging the pixel mixing area for increasing the frame rate in the vertical and horizontal directions according to the purpose. Selection becomes possible.

(Other embodiments)
In each of the above embodiments, a solid-state imaging device provided with a vertical transfer stage and a horizontal transfer stage for transferring charges by a CCD has been disclosed. However, the present invention is not limited to such an embodiment, and is based on a MOSFET. The present invention can also be applied when using a solid-state imaging device that performs charge signal addition processing.

  In addition, the solid-state imaging device is not necessarily provided with a color filter, and the present invention can be applied to processing a monochrome image. Further, even when a color filter is used, it is not necessary to have a 2 × 2 color array as a basic unit of repetition, and for example, a multicolor filter having 5 or more colors may be provided.

  In each of the above embodiments, the pixel mixture area unit is configured by 5 × 5 pixels, but the present invention is not limited to such an embodiment, and the pixel mixture area unit configured by a larger number or a smaller number of pixels. May be set and the pixel mixing process may be performed.

  In this specification, an example in which the first embodiment is applied to a solid-state imaging device having a complementary color filter array structure is not disclosed, but a filter color structure according to the second embodiment is a complementary color filter array structure. Similarly to the case where the third embodiment is established, the filter structure of the first embodiment can be a complementary color filter structure.

  In each of the embodiments described above, when the number q of pixels in the pixel mixing area unit is represented by q = 4m + 1 (m is a natural number) and the number p in the horizontal direction is represented by p = 4n + 1 (n is a natural number). , M = n = 1, and each pixel mixed area unit forms a two-dimensional repetitive array while overlapping with a shift of (p + 1) / 2 pixels in the second direction and (q + 1) / 2 pixels in the first direction. However, the number of pixels and the amount of overlap in the pixel mixture area unit of the present invention are not limited to the above embodiments.

  For example, the number q of pixels in the first direction in the pixel mixture area unit is represented by q = 4m−1, the number p in the second direction is represented by p = 4n−1 (n is a natural number), and the pixel mixture area unit is represented by The shift amount between (p-1) / 2 pixels and (p + 3) / 2 pixels is alternately repeated in the second direction, and the shift between (q-1) / 2 pixels and (q + 3) / 2 pixels in the first direction. A two-dimensional repetitive array may be formed while overlapping by shifting the amount repeatedly.

  Further, the pixel mixture area unit may include an even number × even number of pixels, for example, 6 × 6 pixels, or may include an odd number × even number of pixels.

  As described above, the solid-state imaging device of the present invention can be used for a digital still camera, a digital video camera, and the like.

  The solid-state imaging device of the present invention reduces the number of output pixel signals of a solid-state imaging device having many pixels, such as a super megapixel, by a pixel addition method, and is a moving image of an ultra-high-pixel solid-state imaging device suitable for an interless scan system Since imaging can be realized, it can be used for a digital still camera, a digital video camera, and the like.

It is a top view which shows typically the element arrangement | sequence in the CCD solid-state image sensor of the color solid-state imaging device which concerns on 1st Embodiment. It is a figure which shows the procedure of the pixel mixing process of the 1st field in 1st Embodiment. It is a figure for demonstrating the outline of the pixel mixture in the 1st field in 1st Embodiment. It is a figure for demonstrating the outline of the pixel mixture in the 2nd field in 1st Embodiment. It is a top view which shows typically the element arrangement | sequence in the CCD solid-state image sensor of the color solid-state imaging device which concerns on 2nd Embodiment. It is a figure which shows the procedure of the pixel mixing process of the 1st field in 2nd Embodiment. It is a figure for demonstrating the outline of the pixel mixture in the 1st field in 2nd Embodiment. It is a figure for demonstrating the outline of the pixel mixture in the 2nd field in 2nd Embodiment. It is a top view which shows typically the element arrangement | sequence in the CCD solid-state image sensor of the color solid-state imaging device which concerns on 3rd Embodiment. It is a figure which shows the procedure of the pixel mixing process of the 1st field in 3rd Embodiment. It is a figure for demonstrating the outline of the pixel mixture in the 1st field in 3rd Embodiment. It is a figure for demonstrating the outline of the pixel mixture in the 2nd field in 3rd Embodiment. It is a block diagram which shows the structure of the solid-state imaging device common to 1st-3rd embodiment. (A) to (c) are, respectively, a cross-sectional view of a transfer gate portion in a horizontal transfer stage, a cross-sectional view of a conventional transfer gate portion, and a p ⁺ It is a figure which shows the potential state in the cross section which cross | intersects a layer and a p-type semiconductor layer. (A), (b) is a figure explaining the gravity center position relationship in the pixel mixture of the 1st vertical line of the 1st field and 2nd field in 1st Embodiment, and the 2nd vertical line. (A), (b) is a figure explaining the gravity center positional relationship in the pixel mixture of the 1st vertical line of the 1st field and 2nd field in 2nd Embodiment, and the 2nd vertical line. (A) and (b) are the centroids due to pixel mixture of the first vertical line in the cases shown in FIGS. 15 (a) and 15 (b) and in the cases shown in FIGS. 16 (a) and 16 (b), respectively. It is a figure for demonstrating the relationship between a position and the gravity center position by the pixel mixing of the 2nd vertical line. It is a block circuit diagram which shows simply the structure of the circuit for gravity center position correction | amendment. (A) and (b) sequentially add charge signals in units of pixel mixing areas in the cases shown in FIGS. 15 (a) and 15 (b) and in the cases shown in FIGS. 16 (a) and 16 (b), respectively. It is a figure which illustrates the process which performs a luminance signal (A), (b) is a figure for demonstrating each bias and channel potential at the time of performing the forward direction and the reverse direction transfer of the electric charge in the transfer gate part of a horizontal transfer, respectively. 3 is a timing chart showing a temporal change in bias applied to each gate in order to realize the charge mixing process shown in FIG. 2 of the first embodiment.

Explanation of symbols

11 pixels 12 vertical transfer stage (first direction transfer stage)
W Horizontal transfer stage (second direction transfer stage)
W1 to W12 Transfer gate section 14 Output amplifier 15 Vertical-horizontal transfer connection section 15A to 15L Extension stage V1 to V6 Gate H1 to H4 Gate A1 to A8 Pixel mixed area unit A'1 to A'8 Pixel mixed area unit B1 to B4 Center of gravity B'1 to B'4 Center of gravity C to E Charge F1 to F8 Pixel mixed area unit F'1 to F'8 Pixel mixed area unit G1 to G4 Center of gravity G'1 to G'4 Center of gravity J1 to J8 Pixel mixed area unit J′1 to J′8 Pixel mixed area unit 51 pixels 52 vertical transfer stage (first direction transfer stage)
53 Horizontal transfer stage (second direction transfer stage)
53A to 53L Transfer gate section 54 Output amplifier 55 Vertical-horizontal transfer connection section 55A to 55L Extension stage 101 Solid-state image sensor 112 Solid-state image sensor drive section 113 Signal conversion section 114 SSG
115 Rearrangement part 116 DRAM
117 DRAM control unit 118 output signal generation unit 119 signal processing unit 121 arithmetic circuit 123 switching circuit 150 n-type semiconductor layer 151 p ⁺ layer 152 insulating film 153 polysilicon electrode 154 Al electrode 157 wiring 158 wiring

Claims (19)

A solid-state imaging device having a plurality of pixels each composed of photoelectric conversion elements arranged in a matrix and a color filter having a repetition period of 2 rows and 2 columns,
Q (q is a natural number of 2 or more) pixels arranged in the first direction of the solid-state imaging device, and p (p is a natural number of 2 or more) arranged in the second direction intersecting the first direction. And the plurality of pixels added by the pixel addition processing of the first field and the pixel addition processing of the first field. Pixel addition processing means for performing pixel addition processing in a second field for adding charges of a plurality of pixels respectively included in a plurality of pixel mixture area units different from the pixel mixture area unit;
Output means for alternately outputting signals of charges of a plurality of pixels added in the pixel addition processing of the first field and the second field as interlace scan signals,
The addition process performed in each of the first field and the second field includes the addition process of the odd lines in the first direction and the addition process of the even lines in the first direction ,
One of the addition processing of the odd lines and the addition processing of the even lines is performed by selecting a pixel mixture area shifted in the second direction, and adding the odd lines and the even lines. In the other addition processing, a pixel mixture area that is not shifted in the second direction is selected,
The barycentric position of the first region of the two pixel mixture area units in one of the addition processing of the odd lines and the addition processing of the even lines is the sum of the odd lines and the processing of the even lines. The barycentric position of the second region combining the two pixel mixture area units in the other addition processing of the addition processing, and the second region and the second direction processed simultaneously with the second region Solid-state imaging characterized by being positioned on a line along the first direction passing through the center of the center of gravity of a third region that is a combination of the two pixel mixture area units arranged adjacent to each other apparatus. The solid-state imaging device according to claim 1,
The plurality of pixel mixture area units added in the first field pixel addition process and the second field pixel addition process respectively have portions overlapping each other in the first direction and the second direction. Solid-state imaging device that is arranged. The solid-state imaging device according to claim 2,
The number of pixels in the first direction q in each pixel mixture area unit is represented by q = 4m + 1 (m is a natural number), and the number p in the second direction is represented by p = 4n + 1 (n is a natural number),
Each pixel mixed area unit is a solid-state imaging device that overlaps with a shift of (p + 1) / 2 pixels in the second direction and (q + 1) / 2 pixels in the first direction. The solid-state imaging device according to claim 2,
The number q of the pixels in each pixel mixed area unit in the first direction is represented by q = 4m−1, the number p in the second direction is represented by p = 4n−1 (n is a natural number),
Each pixel mixed area unit repeats the shift amount between (p−1) / 2 pixels and (p + 3) / 2 pixels in the second direction alternately, and (q−1) / 2 pixels in the first direction ( q + 3) A solid-state imaging device in which the amount of deviation from the pixel is repeated alternately and is shifted and overlapped. The solid-state imaging device according to claim 2,
In the first direction, the charge of each pixel included in each pixel mixed area unit is transferred while adding each other,
In the second direction, a solid-state imaging device that adds the charges of the pixels added in units of the pixel mixing areas in the first direction. In the solid-state imaging device according to any one of claims 1 to 5,
The color filter is a solid-state imaging device attached to the front surface of each photoelectric conversion element. The solid-state imaging device according to claim 6.
The array of the color filters is a 2-by-2 Bayer array,
The pixel addition processing means performs addition in a first direction transfer stage that adds charges of the plurality of pixels along the first direction for each pixel mixing area unit, and in the first direction transfer stage. the resulting charge each other and a second direction transfer stage for adding respectively along the second way direction above,
The solid-state imaging device in which each charge obtained by addition in the second direction transfer stage is each pixel signal for display of a complementary color filter array. The solid-state imaging device according to claim 6.
A solid-state imaging device in which the array of color filters of the solid-state imaging device is a combination of four colors of cyan, yellow, green, and magenta in 2 rows and 2 columns. In the solid-state imaging device according to any one of claims 1 to 5,
The pixel addition processing means includes a first direction transfer stage including a plurality of CCDs for transferring the charges of the pixels along the first direction, and charges transferred from the first direction transfer stage in the second direction. A solid-state imaging device having a second direction transfer stage composed of a CCD that transfers electric charges along the line. The solid-state imaging device according to claim 9, wherein
The second direction transfer stage is configured by alternately arranging a storage region having a first gate for holding charges and a barrier region having a second gate and serving as a barrier against charge transfer. ,
The solid-state imaging device in which the first gate and the second gate are electrically separated and receive individual biases. Q (q is a natural number of 2 or more) arranged in the first direction of a solid-state imaging device having a plurality of pixels each composed of photoelectric conversion elements arranged in a matrix and a color filter having a 2 × 2 repetition period. ) Pixels and a plurality of pixel mixed area units each composed of p (p is a natural number of 2 or more) pixels arranged in a second direction intersecting the first direction. Pixel addition processing step of the first field for adding the charges of the pixels of
A second field pixel addition processing step of adding charges of a plurality of pixels respectively included in a plurality of pixel mixture area units different from the plurality of pixel mixture area units added in the first field pixel addition processing; Alternately outputting signals about the charges of the plurality of pixels added in the pixel addition processing step in the first field and the pixel addition processing step in the second field as interlace scan signals,
The addition processing performed in each of the first field and the first field includes addition processing of the odd lines in the first direction and addition processing of the even lines in the first direction ,
One of the addition processing of the odd lines and the addition processing of the even lines is performed by selecting the pixel mixture area shifted in the second direction, and the other of the addition processing of the odd lines and the addition processing of the even lines. In the addition process, a pixel mixture area that is not shifted in the second direction is selected,
The barycentric position of the first region of the two pixel mixture area units in one of the addition processing of the odd lines and the addition processing of the even lines is the sum of the odd lines and the processing of the even lines. The barycentric position of the second region combining the two pixel mixture area units in the other addition processing of the addition processing, and the second region and the second direction processed simultaneously with the second region Solid-state imaging characterized by being located on a line along the first direction passing through the center of the center of gravity of a third region that is a combination of the two pixel mixture area units arranged adjacent to each other Device driving method. The method for driving a solid-state imaging device according to claim 11,
The plurality of pixel mixed area units added in the pixel addition processing step in the first field and the pixel addition processing step in the second field respectively have portions that overlap each other in the first direction and the second direction. A method for driving a solid-state imaging device arranged as described above. The method for driving a solid-state imaging device according to claim 11,
The pixel addition processing step of the first field and the pixel addition processing step of the second field are:
Transferring the charges of a plurality of pixels included in each pixel mixing area unit while adding the charges along the first direction (a);
The driving method of the solid-state imaging device that a plurality of pixels of charge respectively added in step (a), and step (b) to be transferred while adding along the second direction include, respectively. The method for driving a solid-state imaging device according to any one of claims 11 to 13 ,
The color filter is a driving method of a solid-state imaging device attached to the front surface of the photoelectric conversion element. The solid-state imaging device driving method according to claim 13 ,
The color filter is attached to the front surface of the photoelectric conversion element,
The array of the color filters is a 2-by-2 Bayer array,
In the step (b), the solid-state imaging device driving method for generating the pixel signal for the complementary color filter array by adding the charges of the pixels of different colors from each pixel mixing area unit. The method for driving a solid-state imaging device according to claim 14 ,
A method for driving a solid-state imaging device, wherein the arrangement of the color filters of the solid-state imaging device is a combination of four colors of cyan, yellow, green and magenta in 2 rows and 2 columns. The solid-state imaging device driving method according to claim 13 ,
In the step (a), a first direction transfer stage including a plurality of CCDs for transferring the charges of the pixels along the first direction is used.
In the step (b), the solid-state imaging device driving method using the second direction transfer stage including the CCD that receives the charge transferred from the first direction transfer stage and transfers the charge along the second direction. The solid-state imaging device according to claim 6.
A solid-state imaging device in which the arrangement of the color filters of the solid-state imaging device is a combination of three colors of red, green, and blue in 2 rows and 2 columns. The method for driving a solid-state imaging device according to claim 14 ,
A method for driving a solid-state imaging device, wherein the arrangement of the color filters of the solid-state imaging device is a combination of three colors of red, green, and blue in 2 rows and 2 columns.

Images