JP2001085664A - Solid-state image pick up device, method of driving the same and camera system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the desired vertical compression for common use in moving image sending/static image sending in the well-balanced horizontal and vertical resolution. SOLUTION: Each signal charge of a sensor group located in every other row among a plurality of sensors 11 arranged in the shape of matrix is read, for example, with vertical CCD 12 located in the left side of figure. Each signal charge of the other sensor group located in every other row is read, for example, with vertical CCD 12 located in the right side of figure, and the signal charges of sloping two pixels read from each sensor 12 are added in each vertical CCD 12 of a plurality of vertical CCDs. Moreover, the signal charges of a plurality of lines are added in the horizontal CCD 14 and are then outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image sensor, a method of driving the same, and a camera system, and more particularly to a color solid-state image sensor which can be used for both still images and moving images, a method of driving the same, and imaging of the solid-state image sensor. It relates to a camera system used as a device.

[0002]

2. Description of the Related Art In recent years, with the expectation of mounting a still function on a video camera, development of a solid-state imaging device that can be used for both still images and moving images has been advanced. Generally, it is considered that a still image is based on a square lattice and a moving image is based on 13.5 MHz. Therefore, in order to use both of them, interpolation / compression is required by either method. Here, while the still image is in the high-pixel non-format, the moving image is NTSC /
Because it is encouraged by broadcast systems such as PAL, down conversion from multi-pixel solid-state image sensors for still images
Producing television signals such as NTSC / PAL is considered most efficient.

As a technique for down-conversion (higher frame rate), signal charges of some lines are not read from the sensor unit to the vertical transfer unit, and only signal charges of other lines are read from the sensor unit to the vertical transfer unit. There are known a method of performing so-called thinning-out reading, and a method of cutting out a central area of an effective pixel area as in the case of camera shake correction.

In the former method, in a digital still camera or the like using a solid-state imaging device having a primary color filter as an imaging device, signal charges of some lines are not read out from a sensor unit to a vertical transfer unit, so that the vertical direction is prevented. The information is reduced and a high frame rate is realized, and is mainly used when outputting multi-pixel image information to a liquid crystal TV monitor. However, in this method, since the signal is thinned, the sampling frequency is lowered, and the spatial aliasing increases, so that a beautiful image cannot be obtained.
It was unsuitable for the purpose of recording and storing as moving images.

On the other hand, in the case of using the latter method, if the broadcast method is cut out at the time of multi-pixel, the change in the angle of view between a still image and a moving image becomes large and a large amount of pixel information is discarded. ineffective. For such a reason, as a method of down-conversion, a technique of performing vertical compression processing of a still image / moving image by mixing (vertical addition) in a transfer process of signal charges has conventionally been adopted.

In order to execute the vertical compression process in the process of transferring the signal charges, the biggest problem is the color coding of the color filters. That is, the primary colors R (red), G
In the case of (green) and B (blue), it is safe to perform vertical addition as vertical stripes, whereas complementary colors are C (cyan) and
Y (yellow), G (green), M (magenta) 4
The use of vertical stripes is disadvantageous in terms of color resolution in the horizontal direction. Therefore, a technique of shift addition by the horizontal transfer unit (hereinafter, referred to as horizontal shift addition) is employed to keep the horizontal drive frequency constant.

However, C, Y, G, and M are, for example, as shown in FIG.
In the complementary color checker color coding arranged as shown in FIG. 2, in order to cope with the interlace operation, the color difference signal Cr obtained by mixing signal charges of two pixels in the vertical direction (hereinafter, referred to as vertical two-pixel mixing). (G
+ C, M + Y) and Cb (M + C, G + Y) are line sequential obtained alternately in the vertical direction.
Vertical mixing while maintaining b was not possible. In addition,
In FIG. 24, the odd number (ODD) field is on the left side,
The right side shows the even (EVEN) fields.

On the other hand, in order to enable vertical mixing and realize horizontal shift addition, complementary color coding as shown in FIG. 25 has been proposed (Reference: 1997 Annual Meeting of the Institute of Image Information and Television Engineers (ITE) '97: 1997 ITE Ann
ual Convention) "Study on Single-Chip Color Imaging with Hi-Vision / NTSC Output" pp. 37-38). According to the complementary color coding, as is apparent from FIG. 25, the color difference signals Cr (G + C, M + Y) and Cb (M + C,
G + Y) in a quincunx shape.

As described above, in the conventional complementary color coding in which the color difference signals Cr and Cb are arranged in a quincunx pattern, as shown in FIG. Charge during horizontal blanking period
After shifting the bit (for two pixels), the signal charges of the next one line are line-shifted, whereby signals of the same color component can be vertically mixed. That is, the color difference signal C
Vertical mixing can be realized while maintaining r and Cb.

[0010]

However, the color difference signals Cr and Cb are arranged in a quincunx pattern, that is, the color difference signals Cr and Cb.
In the case of complementary color coding in which b is alternately obtained in the horizontal direction and the vertical direction, as described above, vertical mixing with a horizontal 2-bit shift, that is, addition of signals of the same color component separated by two pixels, Since the vertical compression processing is realized, there is a problem that the color resolution in the horizontal direction is reduced to the same degree (ie, 水平) as the horizontal four repetition coding compared to the normal horizontal two repetition coding.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to provide a moving image / still image capturing method capable of arbitrary vertical compression and having a balance between horizontal and vertical resolutions. An object of the present invention is to provide a solid-state imaging device that can be used for two purposes, a driving method thereof, and a camera system.

[0012]

A solid-state imaging device according to the present invention comprises a plurality of sensor sections arranged in a matrix and a plurality of vertical sections arranged in each column with respect to the plurality of sensor sections. The transfer unit and, among the plurality of sensor units, read each signal charge of the sensor unit group located on every other row to the vertical transfer unit located on one side of the plurality of vertical transfer units, and read the signal charges on every other row. Reading means for reading out each signal charge of the located sensor unit group to the vertical transfer unit located on the other side of the plurality of vertical transfer units. Further, each of the plurality of vertical transfer units has an addition driving unit for adding signal charges of two oblique pixels read from the plurality of sensor units.

In the solid-state image pickup device having the above-described configuration and the method of driving the same, among the plurality of pixels (sensor units), each signal charge of a pixel group located in every other row is read to, for example, a vertical transfer unit located on the left side. Is read out, for example, to a vertical transfer unit located on the right side of each pixel group located in every other row. Then, signal charges of two pixels obliquely positioned on the pixel array are read out to two adjacent transfer stages of the same vertical transfer unit. Then, by performing the same drive as the well-known field readout, the signal charges of the two adjacent transfer stages are added. That is, the addition readout of the signal charges of the two oblique pixels is performed.

In the camera system according to the present invention, among a plurality of pixels arranged in a matrix, each signal charge of a pixel group located in every other row is read out to, for example, a vertical transfer unit located on the left side, and the other charge is read out in every other row. The signal charges of the pixel group located at the right are read out to, for example, the vertical transfer unit located at the right side, and the signal charges of two oblique pixels read from each pixel can be added and output at each of the plurality of vertical transfer units. A solid-state imaging device is used as an imaging device. Further, a still image mode and a moving image mode can be selectively set for the solid-state imaging device. Then, the solid-state imaging device is driven according to the imaging mode, and at the time of setting the moving image imaging mode, signal charges of two oblique pixels in the vertical transfer unit are added.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the following description, a CCD image sensor (hereinafter, referred to as a CCD image sensor)
In the following, an example in which the present invention is applied will be described. However, the present invention is not limited to this, and is applicable to all solid-state imaging devices.

FIG. 1 shows a CCD according to an embodiment of the present invention.
FIG. 1 is a schematic configuration diagram showing an image pickup device, and shows an example in which the present invention is applied to a single-chip color CCD image pickup device of an IS (interlace scan) -IT (interline transfer) system.

In FIG. 1, a CCD imaging device 10 according to this embodiment includes a plurality of sensor units (pixels) 11 arranged in a matrix, and a plurality of vertical units arranged for each vertical column of the sensor units 11. CCD (vertical transfer unit) 12, sensor unit 11
Read gate unit 1 interposed between the vertical CCD 12
3. Horizontal CC arranged on one end side of vertical CCD 12
D (horizontal transfer unit) 14, a charge detection unit 16 and an output circuit 17 arranged at an end on the transfer destination side of the horizontal CCD 14.

Although not shown in FIG. 1, for example, a color filter 19 of complementary color checkerboard color coding is provided on an image pickup area (pixel area) 18 of the CCD image pickup device 10.
Is arranged. As shown in FIG. 2, for example, the color filter 19 has M / C / G / C for even rows and G / Y for odd rows.
/ M / Y color coding 19-1 (A), or even-numbered rows are M / C / G / Y, odd-numbered rows are G / Y / M / C color coding 19-2 (B), Color coding is repeated four times in the horizontal direction (column direction) every two pixels, and is repeated every two pixels in the vertical direction (column direction).

In the CCD image pickup device 10 having such a configuration, the sensor section 11 is composed of, for example, a PN-junction photodiode, and photoelectrically converts incident light into a signal charge having a charge amount corresponding to the light amount and stores the signal charge. For a plurality of sensor units 11 arranged in a matrix, a plurality of vertical CCDs 1
2 are arranged.

The read gate section 13 applies a read pulse XSG, which will be described later, to apply a signal charge of a sensor section group located every other row, for example, the sensor section 11 of an odd (ODD) row to one side (in this example, in this example). (The left side of the figure), the sensor unit group located in every other row, for example, the sensor unit 1 in an even (EVEN) row
One signal charge is read out to the vertical CCD 12 located on the other side (in this example, the right side of the figure). The specific configuration of the read gate unit 13 will be described later.

The vertical CCD 12 is transfer-driven by, for example, four-phase vertical transfer clocks Vφ1 to Vφ4. Among the four-phase vertical transfer clocks Vφ1 to Vφ4, the vertical transfer clocks Vφ1 and Vφ3 are as shown in the waveform diagram of FIG.
It is set to take three values of a low level (“L” level), an intermediate level (“M” level) and a high level (“H” level), and a third value (“ The pulse at H level becomes the read pulse XSG.

In the vertical CCD 12, signal charges are added between two adjacent packets and added according to the timing relationship of the four-phase vertical transfer clocks Vφ1 to Vφ4, as in the well-known field read drive. The combination of packets to be changed in the first field and the second field. Here, a packet refers to a unit (one transfer stage) that handles signal charges for one pixel.

That is, in the first field, FIG.
As shown in (A), the vertical transfer clocks Vφ1, Vφ3
After the read pulse XSG rises, the vertical transfer clocks Vφ1 to Vφ3 become “M” level and the vertical transfer clock Vφ
When 4 becomes the “L” level, signal charges are added between packets corresponding to, for example, the first and second rows, the third and fourth rows,... Of the pixel array.

In the second field, as shown in FIG. 3 (B), after the read pulse XSG rises in the vertical transfer clocks Vφ1 and Vφ3, the vertical transfer clocks Vφ1 and Vφ
3, Vφ4 is at “M” level and vertical transfer clock Vφ2 is at “L” level, so that each packet corresponding to, for example, the second and third rows, the fourth and fifth rows,... The signal charges are added between the two.

The vertical CCD 12 converts the signal charges added between two adjacent packets into a vertical transfer clock V.
The transfer drive by φ1 to Vφ4 results in FIG.
As shown in the timing chart, the data is transferred to the horizontal CCD 14 by vertical transfer (line shift) in a part of the horizontal blanking period.

The horizontal CCD 14 is transferred and driven by, for example, two-phase horizontal transfer clocks Hφ1 and Hφ2, so that the signal charges line-shifted from the vertical CCD 12 are sequentially and horizontally transferred in the horizontal scanning period after the horizontal blanking period. To the charge detection unit 16. This horizontal C
The operation of the CD 14 is a transfer operation in the normal mode.

The charge detecting section 16 is constituted by, for example, a floating diffusion amplifier.
In other words, the horizontal CCD 14 includes a floating diffusion FD into which signal charges are injected, a reset drain RD from which charges are discharged, and a reset gate RG disposed between the floating diffusion FD and the reset drain RD. The supplied signal charge is detected and converted to a signal voltage. A predetermined reset drain voltage VRD is applied to the reset drain RD.

FIG. 5 is a plan pattern diagram showing an example of a specific configuration of the sensor unit 11, the vertical CCD 12, and the read gate unit 13. In FIG. 5, the vertical CCD 12
Is a plurality of transfer channels 2 extending in parallel in the vertical direction.
1 and transfer electrodes 22-1 to 22 corresponding to four-phase vertical transfer clocks Vφ1 to Vφ4 which are sequentially arranged in a vertical direction above these transfer channels 21 and extend in parallel in the horizontal direction.
2-4. Transfer electrode 22-1 to 2
2-4 is formed using two lines (two vertical pixels) as one unit.

In these transfer electrodes 22-1 to 22-4, for example, the second-phase and fourth-phase vertical transfer clocks Vφ
2, the transfer electrodes 22-2 and 22-4 to which Vφ4 is applied are formed by the first layer of polysilicon (indicated by a dashed line in the figure), and the first and third phase vertical transfer clocks Vφ1 and Vφ
The transfer electrodes 22-1 and 22-3 to which φ3 is applied are formed of a second-layer polysilicon (indicated by a two-dot chain line in the figure). The transfer electrodes 22-2 and 22-4 made of the first-layer polysilicon and the transfer electrodes 22-1 and 22-3 made of the second-layer polysilicon overlap each other on the transfer channel 21. ing.

Here, as shown by hatching in FIG. 5, around the sensor section 11, every other row (in this example, an odd number row) of each sensor section 11o is on the left side of the figure, and every other row (this example). Each of the sensor sections 11e (even rows) has a shape excluding the channel stop section 23 for element isolation on the right side of the drawing. On the other hand, the transfer electrodes 22-1 to 22-4 are formed not only on the transfer channel 21 but also wide up to the opening edge of the sensor unit 11, so that the transfer electrodes 22-1 to 22-4 are not formed on the channel stop portion 23. The gate also serves as a gate electrode of the read gate unit 13.

In the above-described pixel structure, the readout pulse XSG is applied to the readout gate section 13 through the transfer electrodes 22-1 and 22-3, so that the signal charges are read out from each sensor section 11. Specifically, when the read pulse XSG rises in the vertical transfer clock Vφ1 of the first phase, the signal charges of the sensor units 11o in the odd rows are changed to the vertical CCDs located on the left side of FIG.
12 is read. When the read pulse XSG rises in the third-phase vertical transfer clock Vφ3, the signal charges of the sensor units 11e in the even-numbered rows are read out to the vertical CCD 12 located on the right side of the figure, as indicated by the right-pointing arrow.

As described above, four horizontal repetitions and two vertical
In the CCD imaging device 10 having the color filter 19 of the repetitive color coding, the signal charges of the sensor units located in every other row, for example, the sensor units 11o in the odd rows are located on one side (in this example, the left side in the figure). Vertical CC
By reading the signal charges from the D12 and reading out the signal charges of the sensor unit groups located in every other row, for example, the sensor units 11e in the even-numbered rows, to the vertical CCD 12 located on the other side (in this example, the right side in the figure), In the vertical CCD 12, signal charges of two adjacent packets are added. By this addition, addition of signal charges is performed between two pixels located at an angle in the pixel array.

That is, the color coding shown in FIG. 2A, that is, the odd rows are M / C / G / C, and the even rows are G / Y.
/ M / Y complementary color coding color filter 1
In the CCD image pickup device 10 having the 9-1, the color difference (chroma) signal C
r and Cb are output in dot sequence. In the present example, the color coding of the color filter 19-1 is such that
/ C / G / C and the case where the odd-numbered row is G / Y / M / Y has been described. However, the present invention is not limited to this, and FIG.
, Ie, the even lines are M / C / G /
Y, odd rows are G / Y / M / C, and even rows are M / C / M /
Color coding in which the color difference signals Cr and Cb are dot-sequential at the time of diagonal two-pixel addition, such as color coding in which Y and G / Y / G / C are used in odd rows, or where odd and even rows are replaced, may be used.

Here, the relationship between the complementary color coding and the color difference signals Cr and Cb will be described using the general complementary color coding shown in FIG. 6 as an example.

Normally, since the CCD image pickup device performs field reading, a1 and a2 are used in the first field.
The signal charges are mixed by a combination of two vertical pixels. Accordingly, the order of signal charges transferred by the horizontal CCD is (G + Cy), (Mg +
Ye), (G + Cy), (Mg + Ye),.
In the second field, a combination of two vertical pixels b is used.

In order to convert the signal charges output in this order into electric signals and process them in a subsequent color signal processing system to form a luminance signal Y and color difference signals Cr and Cb, the Y signals are adjacent to each other. To reduce the color difference signals Cr and Cb. That is, an approximate signal of Y signal = | (G + Cy) + (Mg + Ye) | × 1/2 = 1/2 (2B + 3G + 2R) is used as the Y signal. As the color difference signal Cr, an approximate signal of Cr = (Mg + Ye)-(G + Cy) is used.

Next, considering the line a2, the horizontal CCD
From (Mg + Cy), (G + Ye), (Mg + C
y), (G + Ye),..., so that the Y signal is composed as follows: Y signal = | (G + Ye) + (Mg + Cy) | × 1/2 = 1/2 (2B + 3G + 2R) , A1 line and balance. Similarly, the color difference signal Cb is approximated by Cb = (G + Ye)-(Mg + Cy). The same applies to the second field.

On the other hand, the CCD image pickup device 1 according to this embodiment
In the case of 0, the horizontal CCD 14 performs oblique two-pixel addition in the vertical CCD 12 for the complementary color coding of four horizontal repetitions and two vertical repetitions (see FIG. 2). As is clear from the operation explanatory diagram, in each line a1, a2, a3 ,? + M , G + C , Y + G, M + C, Y + M , G +
C , Y + G, M + C, Y + M , G +? Are output in this order.

The color difference signal Cr is underlined.
Are not underlined, respectively, and represent the color difference signals Cb. Here, Mg is abbreviated as M, Cy is C and Ye is abbreviated, and the same applies to the following description. FIG.
Is an operation description in the case of the first field. This first
In the field, two-pixel addition is performed between one pixel and the pixel on the upper right (the lower left).

On the other hand, in the second field, as described above, since the combination of the two packets to be added changes, two-pixel addition is performed between a certain pixel and a pixel diagonally upper left (lower right diagonally). Done. As a result, FIG.
As is clear from the operation explanatory diagram of FIG.
In ,? + M , G + C , Y + G, M + C, Y + M ,
G + C , Y + G, M + C, Y + M , G +? Are output in this order.

As described above, by performing diagonal two-pixel addition for complementary color coding of four horizontal repetitions and two vertical repetitions, the color difference signals Cr and Cb are output in dot sequence. In addition, by changing the combination of two pixels to be obliquely added in the first field and the second field, an interlace operation can be realized.

As is clear from the above description, the luminance signal is obtained by adding the Y / M / G / C pixel signals. Therefore, assuming that the signal charge output from the horizontal CCD 14 by adding two diagonal pixels is 1 bit,
A luminance signal is obtained by performing addition processing for each two bits in a subsequent signal processing circuit. At this time, although addition is performed for four pixels, since two diagonal pixels are added in the vertical CCD 12, it is substantially equivalent to two pixels in the vertical direction and three pixels in the horizontal direction.

As a result, since two pixels are added in the vertical direction and three pixels are added in the horizontal direction, the balance between the vertical resolution and the horizontal resolution is better than when four pixels are added in the horizontal direction. In addition, since only the same color exists in each of the vertical CCDs 12, it is possible to perform additional compression in the vertical direction. The frame rate can be increased by performing the additional compression in the vertical direction. The addition compression in the vertical direction can be realized by executing the vertical transfer (line shift) operation for two lines or more in the horizontal CCD 14 in a state where the horizontal transfer operation is stopped.

The above-described CCD capable of down-conversion by addition compression based on diagonal two-pixel addition.
The imaging device 10 is used as a still / moving image capturing device that can support both still image capturing and moving image capturing. Specifically, the CCD image pickup device 10 is an image pickup device having multiple pixels of a still image, and the NTS is obtained by down-conversion from the CCD image pickup device having multiple still images by adding and compressing.
A television signal corresponding to a television system such as C / PAL / HDTV is generated.

When used as a still image pickup device, the CCD image pickup device 10 according to the present embodiment has a structure on the assumption that two pixels are added diagonally. For example, the vertical transfer clock is used in the first field. The read pulse XSG is raised only at Vφ3 and only at the vertical transfer clock Vφ1 in the second field, that is, by performing the same drive as the well-known frame read, information of all pixels can be obtained independently in two fields. As a result, a high-quality still image can be obtained.

Here, as an example of producing a television signal corresponding to each television system, consider the case of the pixel configuration shown in FIG. FIG. 9 illustrates a pixel configuration in which the number of horizontal pixels is 1920 and the number of vertical pixels (number of lines) is 1440 in the effective pixel area 31. In practice,
On the upper, lower, left, and right sides of the effective pixel area 31, some effective pixels are arranged in addition to an optical black (optical black) area for obtaining black information. The horizontal drive frequency during the interlace operation is 38.25 for both NTSC / PAL.
MHz.

In the case of capturing a still image having an aspect ratio of 4: 3, the pixel information of the effective pixel area 31 is used as it is. To realize the monitoring mode at the time of capturing a still image, the NTSC system requires 144
480 lines are realized by performing 1 / 3.0 compression on 0 lines, and 576 lines are realized by performing 1 / 2.5 compression on 1440 lines in the PAL system.

In the case of capturing a moving image having an aspect ratio of 4: 3, according to the NTSC system, 1/13 for 1213 lines.
2.5 compression will be performed. At this time, a total of 227 (= 1440-1213) lines of the upper and lower parts of the effective pixel area are used for camera shake correction, and the ratio is about 19%. In the PAL system, 1150 lines are divided by 1 /
2.0 compression will be performed. At this time, 290 (= 1
440-1150) lines are used for camera shake correction, and the ratio is about 25%.

In the case of capturing a moving image having an aspect ratio of 16: 9 (HDTV), the effective pixel area has 1920 horizontal pixels and 1080 vertical pixels (lines). In the NTSC system, 1/2.
0 compression will be performed. At this time, the upper and lower 110 (= 1080-970) lines of the effective pixel area are used for camera shake correction, and the ratio is about 11%.
In the PAL system, 1 / 1.5 compression is performed on 863 lines. At this time, 217 (= 1080−8)
63) The lines are used for camera shake correction, and the ratio is about 25%.

The above compression ratios 1 / 3.0, 1 / 2.5,
Of 1 / 2.0 and 1 / 1.5, 1 / 2.0 and 1 / 2.0
Taking 2.5 as an example, the specific compression (addition)
The operation will be described.

First, the interlacing operation of 1 / 2.0 compression in the NTSC system will be described based on the operation explanatory diagram of FIG. 10 and the timing chart of FIG. In this 1 / 2.0 compression, signal charges are added between two oblique pixels in the vertical CCD 12, and the signal charges obtained by adding the two pixels are converted into signal charges for one line to the horizontal CCD 1.
Shift to line 4 by 2 lines in order (shift by 2 lines)
Signal charges for two lines (four pixels) are added in the horizontal CCD 14.

More specifically, in the first field, first, in the vertical blanking period (V-BLK), a read pulse XSG is set on the vertical transfer clocks Vφ1 and Vφ3 to thereby transfer signal charges from each sensor unit (pixel) 11. read out. When reading out this signal charge, the vertical CCD
In 12, the signal charge of each pixel in the first row and the signal charge of each pixel on the upper right of the second row are added, and the signal charge of each pixel in the third row and the signal charge on the upper right of the fourth row are added. The signal charge of each pixel is added, and so on, so that diagonal two-pixel addition is performed every two rows.

Thereafter, the signal charge in the unnecessary pixel area below the effective pixel area (on the side of the horizontal CCD 14) in the NTSC system is swept away by driving the vertical CCD 12 at high speed. This high-speed sweeping operation can be realized by using a known technique. Thereafter, the line shift operation is repeatedly performed for every two lines. By performing the line shift for the two lines, signal charges for a total of four pixels per two lines and one column are added in the horizontal CCD 14.

Thus, from the horizontal CCD 14, first,
(? + M21) + (? + M41) , (G11 + C22)
+ (G31 + C42) , (Y12 + G23) + (Y32
+ G43), (M13 + C24) + (M33 + C4
4), ..., (? + M61) + (? + M81) ,
(G51 + C62) + (G71 + C82) , (Y52 +
G63) + (Y72 + G83), (M53 + C64) +
(M73 + C84),..., The added 4
The signal charges for the pixels are sequentially output.

By repeating the above-described series of operations, 1 / 2.0 compression in the first field is performed. here,
The underlined line indicates the color difference signal Cr, and the underlined line indicates the color difference signal Cb. Further, in the operation explanatory diagram of FIG. 10, each of the four rows marked with a circle and a circle is a combination in which the signal charges are added in the first field, and the center of gravity of the line after the addition is the position marked with a triangle. .

In the second field, 1 / 2.0 compression is performed by the same operation as in the first field. However, in the second field, in the operation explanatory diagram of FIG. 10, each of the four rows marked with a triangle is a combination in which signal charges are added, and the center of gravity of the line after the addition is the position marked with a cross. Note that the first one line is swept away because addition for four pixels is not performed.

Thus, from the horizontal CCD 14, first,
(? + M41) + (? + M61) , (G31 + C42)
+ (G51 + C62) , (Y32 + G43) + (Y52
+ G63), (M33 + C44) + (M53 + C6
4), ..., (? + M81) + (? + M101) ,
(G71 + C82) + (G91 + C102) , (Y72
+ G83) + (Y92 + G103), (M73 + C8
4) + (M93 + C104),..., The added signal charges for four pixels are sequentially output.

In this example, in each of the first field and the second field, two pixels are added diagonally to the pixel on the upper right (diagonally lower left) for a certain pixel. As described with reference to the operation explanatory diagram of FIG. 2, in the second field, two pixels may be added diagonally with respect to a certain pixel with a pixel diagonally upper left (diagonally lower right). In both the first field and the second field,
You may make it perform two diagonal pixel addition with the diagonally upper left pixel (diagonally lower right).

Next, the interlacing operation of 1 / 2.5 compression in the NTSC system will be described based on the operation explanatory diagram of FIG. 12 and the timing chart of FIG. In this 1 / 2.5 compression, two pixels are added obliquely in the vertical CCD 12, and the signal charge obtained by adding the two pixels is transferred to the horizontal CCD 14 as signal charge for one line.
The shift for three lines (two-line shift / 3-line shift) is alternately repeated, and the addition of signal charges for two lines (4 pixels) / 3 lines (6 pixels) is repeatedly executed in the horizontal CCD 14.

More specifically, in the first field, in the vertical blanking period (V-BLK), a signal pulse is generated from each sensor unit (pixel) 11 by setting a read pulse XSG to the vertical transfer clocks Vφ1 and Vφ3. read out. When reading out this signal charge, the vertical CCD
In 12, the signal charge of each pixel in the first row and the signal charge of each pixel on the upper right of the second row are added, and the signal charge of each pixel in the third row and the signal charge on the upper right of the fourth row are added. The signal charge of each pixel is added, and so on, so that diagonal two-pixel addition is performed every two rows.

Thereafter, the signal charge in the unnecessary pixel area below the effective pixel area (on the horizontal CCD 14 side) in the NTSC system is swept away by driving the vertical CCD 12 at high speed. Thereafter, first, a line shift operation is performed on the signal charges for two lines, so that the signal charges for a total of four pixels for two lines are added in the horizontal CCD 14. Subsequently, a line shift operation is performed on the signal charges for the next three lines, so that a total of
The signal charges for the pixels are added.

As a result, from the horizontal CCD 14, first,
(? + M21) + (? + M41) , (G11 + C22)
+ (G31 + C42) , (Y12 + G23) + (Y32
+ G43), ..., (? + M61) + (? + M8)
1) + (? + M101) , (G51 + C62) + (G7
1 + C82) + (G91 + C102) , (Y52 + G6
3) + (Y72 + G83) + (Y93 + G103),...
... Then, (? + M121) + (? + M141) , (G
111 + C122) + (G131 + C142) , (Y1
12 + G123) + (Y132 + G143),..., The added signal charges for four pixels and the signal charges for six pixels are repeatedly output for each line.

By repeating the above-described series of operations, compression in the first field is performed. Here, the color difference signal Cr is underlined, and the color difference signal C is not underlined.
b respectively. In the operation explanatory diagram of FIG. 12, four rows marked with a circle and six rows marked with a circle each represent a combination in which signal charges are added in the first field. Is the position marked with.

In the case of the second field, compression is performed by the same operation as in the case of the first field. In the second field, however, in the operation explanatory diagram of FIG. 12, four lines marked with a triangle and six lines marked with a ▲ mark are combinations in which signal charges are added, and the line center of gravity after addition is marked with a cross. Is the position marked with. Note that the first one line is swept away because addition for four or six pixels is not performed. Then, 1 / 2.5 compression is realized in two fields. That is, in one field, 10 pixels are compressed to 、, which is 2
Since it is performed in the field, 1 / 2.5 (= 10 /
4) Compression.

Thus, from the horizontal CCD 14, first,
(? + M41) + (? + M61) , (G31 + C42)
+ (G51 + C62) , (Y32 + G43) + (Y52
+ G63), ..., (? + M81) + (? + M10)
1) + (? + M121) , (G71 + C82) + (G9
1 + C102) + (G111 + C122) , (Y72 +
G83) + (Y92 + G103) + (Y112 + G12
3), ..., (? + M141) + (? + M16)
1) , (G131 + C142) + (G151 + C16)
2) , (Y132 + G143) + (Y152 + G16
3),..., The added signal charges for four pixels and the signal charges for six pixels are repeatedly output for each line.

In this example, in each of the first field and the second field, two pixels are added diagonally to the pixel on the upper right (diagonally lower left) for one pixel. In the field, two diagonal pixel additions (see FIG. 8) may be performed with respect to a certain pixel with a pixel diagonally upper left (diagonally lower right), and both the first field and the second field may be used. Alternatively, two diagonal pixels may be added to the pixel at the upper left diagonal (lower right diagonal).

However, in the case of the above-described 1 / 2.5 compression operation, the added signal charges for 4 pixels and the added signal charges for 6 pixels are repeatedly output for each line. The line center of gravity changes between the lines, and the signal amount changes for each line. The difference between the fields of the line center of gravity is slight, and even if the correction is performed from the upper and lower lines, no significant image quality deterioration occurs. However, as for the signal amount, it is necessary to perform gain control for each line in a signal processing circuit at a subsequent stage.

Next, the operation of 1 / 2.5 compression in which the signal amount does not change for each line will be described with reference to FIG.
4 will be described with reference to FIG.

In this example, the addition is performed for the signal charges for four rows, the thinning operation is performed for the signal charges for the next one row, and the addition is performed for the signal charges for the next four rows. A 1 / 2.5 compression is realized by performing a thinning-out operation on the signal charges for one row and repeating 4-pixel addition and thinning-out, etc. Here, the thinning operation refers to an operation of not reading out signal charges in a specific row.

More specifically, in the first field, the signal charges are read out from each sensor unit (pixel) 11 every other row in units of four rows, and the signal charges are read out every five rows. Is decimated. At this time, for the read signal charges, the signal charge of each pixel in the first row and the signal charge of each upper right pixel in the second row are added in the vertical CCD 12, and each pixel in the third row is added. Is added to the signal charge of each pixel on the upper right of the fourth row, so that two pixels are added diagonally every two rows.

Thereafter, the signal charges for two lines to which the diagonal two-pixel addition has been performed are successively subjected to a line shift operation, so that the signal charges for a total of four pixels for two lines and one column in the horizontal CCD 14 are obtained. Is added. As a result, (? + M21) + (?
+ M41) , (G11 + C22) + (G31 + C4
2) , (Y12 + G23) + (Y32 + G43),..., The added signal charges for four pixels are sequentially output.

Since the signal charges for the next one row have been thinned out, even if two pixels are added diagonally to the first row of the next four rows in the vertical CCD 12,
The signal charges in the first first row are directly accumulated as an addition result. For the next four rows of signal charges,
Oblique two-pixel addition is performed between the second and third rows. Then, for the last row, two-pixel addition is performed between the next row and the next thinned row, and the signal charges of the last row are directly accumulated as an addition result.

Then, the line charge operation is continuously performed on the signal charges for the three lines, so that the horizontal C is obtained.
In the CD 14, signal charges for a total of four pixels are added for three lines and one column. Thereby, the horizontal CCD 14
From (M61) + (? + M81) + (?) , (C6
2) + (G71 + C82) + (G91) , (G63) +
(Y72 + G83) + (Y92),..., The added signal charges for four pixels are sequentially output.

By repeating the above-described series of operations, compression in the first field is performed. Here, the color difference signal Cr is underlined, and the color difference signal C is not underlined.
b respectively. Further, in the operation explanatory diagram of FIG. 14, each of the four rows marked with a circle and a circle is a combination in which the signal charges are added in the first field, and the center of gravity of the line after the addition is a position marked with a triangle. .

In the case of the second field, compression is performed by the same operation as in the case of the first field. However, in the second field, in the operation explanatory diagram of FIG. 14, each of the four rows marked with a triangle and the triangle marked is a combination in which signal charges are added, and the center of gravity of the line after addition is the position marked with a cross. . In addition, about the first one line,
Since the addition for four pixels is not performed, the pixels are swept away. Then, 1 / 2.5 compression is realized in two fields.

Thus, from the horizontal CCD 14, first,
(? + M41) + (? + M61) , (G31 + C42)
+ (G51 + C62) , (Y32 + G43) + (Y52
+ G63), ..., (M81) + (? + M101)
+ (?) , (C82) + (G91 + C102) + (G1
11) , (G83) + (Y92 + G103) + (Y11
2), ..., (? + M141) + (? + M16)
1) , (G131 + C142) + (G151 + C16)
2) , (Y132 + G143) + (Y152 + G16
3),..., The added signal charges for four pixels are sequentially output.

As described above, 1 using the thinning operation together
By performing the /2.5 compression, the added signal charges for four pixels are output for each line. Therefore, since the signal amount does not change for each line, complicated signal processing such as performing gain control for each line in a subsequent signal processing circuit does not have to be performed.

In this example, in each of the first field and the second field, for a certain pixel, two diagonal pixels are added to the diagonally upper right pixel (diagonally lower left pixel). In the field, two diagonal pixel additions (see FIG. 8) may be performed with respect to a certain pixel with a pixel diagonally upper left (diagonally lower right), and both the first field and the second field may be used. Alternatively, two diagonal pixels may be added to the pixel at the upper left diagonal (lower right diagonal).

The thinning operation used in the above 1 / 2.5 compression can be easily realized by a known technique. Specifically, as is apparent from the wiring diagram of the pixel portion in FIG. 15, two systems of vertical transfer clocks Vφ1 and Vφ are used as the first and third phase vertical transfer clocks at which the read pulse XSG rises.
1 ′ and Vφ3, Vφ3 ′ are prepared. It is assumed that the read pulse XSG does not rise for the vertical transfer clocks Vφ1 ′ and Vφ3 ′.

Further, six types of vertical transfer clocks Vφ
The six clock lines 41 to 46 are pattern-wired corresponding to Vφ1 ′, Vφ2, Vφ3, Vφ3 ′, and Vφ4. At this time, a clock line 42 or 45 for transferring the vertical transfer clock Vφ1 ′ or Vφ3 ′ is wired for the row to be decimated. In the case of 1 / 2.5 compression described with reference to FIG. 14, the clock line 42 and the clock line 45 may be wired every other row for the thinned row. In the wiring example shown in FIG. 15, a vertical transfer clock Vφ1 ′ is applied to the transfer electrode 22-1 in the (n + 2) th row, and n−
The vertical transfer clock Vφ3 'is applied to the transfer electrode 22-3 in the third row, and the (n + 2) th row and the (n-3) th row are rows to be thinned out.

In the mode in which the thinning operation is not performed, the vertical transfer clocks Vφ1, Vφ2, Vφ3, and the transfer electrodes 22-1, 22-2, 22-3, and 22-4 are applied to the transfer electrodes 22-1, 22-2, 22-3, and 22-4 through the wiring patterns 41, 43, 44, and 46, respectively. By applying Vφ4, the read pulse XSG rises in the vertical transfer clocks Vφ1 and Vφ3, so that signal charges are read from all the sensor units 11 to the vertical CCD 12 and the vertical CCD 1
2, the above-described diagonal two-pixel addition is performed.

On the other hand, in the mode in which the thinning operation is performed, the transfer electrodes 22 through the wiring patterns 41, 43, 44, and 46 are used.
-1, 22-2, 22-3, 22-4 to the vertical transfer clock Vφ
1, Vφ2, Vφ3, and Vφ4, the read pulse X is applied to the vertical transfer clocks Vφ1 ′ and Vφ3 ′.
Since SG does not rise, these vertical transfer clocks Vφ
In the row to which 1 'and Vφ3' are applied, the signal charge is not read out, but only in the other rows, the signal charge is read out, and the above-described diagonal two-pixel addition is performed in the vertical CCD 12.

Although the operation example in the case where the complementary color filter is used as the color filter 19 has been described above, the present invention is not limited to the application to the complementary color filter, but can be similarly applied to the primary color filter. Hereinafter, an operation example when a primary color filter is used as the color filter 19 will be described. FIG. 16 shows an example of color coding of, for example, four types of primary color filters 19-3 (A) to 19-6 (B).

In FIG. 16, the primary color filters 19-3
(A) is an R / G / B diagonal stripe arrangement where G is V
2 repetitions in both (vertical) and H (horizontal) directions, R / B
Indicates that color coding is repeated four times in both the V and H directions. The primary color filter 19-4 (B) has a G / R /
In the B checkerboard arrangement, each color is color-coded four times in both the V and H directions.

The primary color filter 19-5 (C) has a G diagonal stripe R / B checkerboard arrangement, in which G repeats two times in both the V and H directions, R / B repeats two times in the V direction, and color coding repeats four times in the H direction. It has become. Primary color filter 19
-6 (D) is a G / R / B checkerboard arrangement in which each color is color-coded with two repetitions in the V direction and four repetitions in the H direction.

Here, in the CCD imaging device 10 using the primary color filter 19-3 (A), the same color is added by performing diagonal two-pixel addition (mixing) as in the case of the complementary color filter, ie, G and G, R and R, B and B diagonal 2
Signal charges are added between pixels. As a result, as shown in FIG. 17, the primary colors are retained even after the addition of the two diagonal pixels, and the color coding is performed in a G vertical stripe and R / B checkered arrangement. In FIG. 17, black circles schematically indicate pixels, and addition is performed between two diagonal pixels indicated by arrows.

As described above, since the primary colors are retained even after the diagonal addition, 1 / 2PS (progressive scan;
If it is used in compression (all pixels independent reading) compression, that is, if the information obtained by adding two diagonal pixels is used as it is, the primary color separation processing in the subsequent signal processing system becomes unnecessary, which is advantageous in terms of resolution and circuit scale of the signal processing system. There is.

On the other hand, when used in 1/4 IS (interlace scan) compression, the following operation is performed. 1
In the / 4IS compression, signal charges obtained by adding two diagonal pixels are treated as signal charges for one line, vertical addition is performed in units of four lines (one-bit shift is performed as necessary at this time), and the first field and the first field are added. The combination of 4 lines is changed between 2 fields.

The 1/4 IS compression will be described with reference to the operation explanatory diagram of FIG. In FIG. 18, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the first to fourth lines, the fifth line to In the combination of the eighth line,..., In the second field (B), the third to sixth lines
Vertical addition is performed by a combination of the line, the seventh line to the tenth line, and so on.

First, in the first field (A), 1
The signal charges (G, B, G, R, ...) of the line are transferred to the horizontal CC.
Line shift to D14, then 1-bit shift for transferring one bit (one stage) by horizontal CCD 14, and then signal shift (G, R, G, B, ...) of the second line to line CCD 14 I do. Thereby, horizontal CC
In D14, two-line one-bit shift addition is performed,
The result of the addition is ..., B + G, G + R, R + G, G +
.., Cy, Ye, Ye, Cy,... Since B + G = Cy and G + R = Ye.

In this state, the signal charges (G, B, G, R,...) On the third line and the signal charges (G, R, G, B,. Line shift. Thereby, in the horizontal CCD 14, 4
The signal charges for the lines (8 pixels) are added. At this time, in the two-line addition of the third line and the fourth line, the addition result is 2G, B + R, 2G, R + B, 2G,.
Since B + R = Mg, 2G, Mg, 2
G, Mg, 2G,...

Then, the fourth to fourth lines from the first line to the fourth line
In the addition of the signal charges for the line (8 pixels), the addition result is 2G + Cy, M as shown in FIG.
g + Ye, 2G + Ye, Mg + Cy,... In addition,
In the drawing, 2G is abbreviated as G, Cy is C, Mg is M, and Ye is Y. These signal charges are sequentially transferred horizontally by the horizontal CCD 14, converted into signal voltages by the charge detection unit 16, and output to a signal processing system in the subsequent stage.

In addition of the signal charges for the four lines from the fifth line to the eighth line, first, the signal charges (G, B, G, R,...) Of the fifth line and the signal charges of the sixth line are added. The charges (G, R, G, B,...) Are shifted by two lines to the horizontal CCD 14. As a result, two-line addition is performed in the horizontal CCD 14, and the addition result is:..., B + R, 2
.., Mg, 2G, Mg, 2G,... Because R + B = Mg.

In this state, the signal charges (G, B, G, R,...) Of the seventh line are line-shifted to the horizontal CCD 14 and then shifted by one bit. , R, G, B,...)
Line shift to As a result, signal charges for four lines from the fifth line to the eighth line are added in the horizontal CCD 14. At this time, between the seventh line and the eighth line, two-line one-bit shift addition is performed.

The addition result by 2-line 1-bit shift addition between the 7th and 8th lines is..., B + G,
G + R, R + G, G + B,..., B + G = Cy, G
Since + R = Ye,..., Cy, Ye, Ye, C
y, ... Then, as shown in FIG. 18A, the addition result of the signal charges for the four lines from the fifth line to the eighth line is Mg + Cy, 2G + Ye, Mg + Ye, 2G
+ Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system. Thereafter, the same operation is repeated in the first field.

Next, the operation in the second field (B) will be described. First, the signal charges (G,
B, G, R,...) And the fourth line (G, R, G, B,.
..) Are shifted by two lines to the horizontal CCD 14. As a result, two-line addition is performed in the horizontal CCD 14, and the addition result is:..., 2G, R + B, 2G, B
+ R,... And R + B = Mg.
G, Mg, 2G, Mg,...

In this state, the signal charges (G, B, G, R,...) Of the fifth line are line-shifted to the horizontal CCD 14 and then shifted by one bit. , R, G, B,...)
Line shift to As a result, in the horizontal CCD 14, signal charges for four lines from the third line to the sixth line are added. At this time, two-line one-bit shift addition is performed between the fifth line and the sixth line.

The addition result by 2-line 1-bit shift addition between the fifth line and the sixth line is..., G + R,
R + G, G + B, B + G,..., G + R = Ye, G
Since + B = Cy,..., Ye, Ye, Cy, C
y, ... Then, as shown in FIG. 18B, the addition result of the signal charges for the four lines from the second line to the fifth line is 2G + Ye, Mg + Ye, 2G + Cy, Mg
+ Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

In addition of the signal charges for the four lines from the seventh line to the tenth line, the signal charges (G,
B, G, R,...) Are line-shifted to the horizontal CCD 14,
Next, after performing a 1-bit shift, the signal charges (G, R, G, B,...) On the eighth line are line-shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, two-line one-bit shift addition is performed.
G + R, R + G, G + B, B + G,...
Since Ye, G + B = Cy, ..., Ye, Ye,
Cy, Cy,...

In this state, the signal charges on the ninth line (G, B, G, R,...) And the signal charges on the tenth line (G, R, G, B,. Line shift. Thereby, in the horizontal CCD 14, 4
The signal charges for the lines are added. At this time, in the two-line addition of the ninth line and the tenth line, the addition result becomes B + R, 2G, R + B, 2G,.
= Mg, so Mg, 2G, Mg, 2G,...

In addition, in the addition of the signal charges for four lines (eight pixels) from the seventh line to the tenth line, the addition result is Mg + Ye, as shown in FIG.
2G + Ye, Mg + Cy, 2G + Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system. Thereafter, the same operation is repeated in the second field.

As described above, in the CCD image pickup device using the color coding primary color filter 19-4 shown in FIG. 16A, 1 / 4IS compression by 4-line addition including diagonal 2-pixel addition and 1-bit shift addition. Is performed, the color difference signal Cb (Cy
+ Mg, Ye + G) and the color difference signal Cr (Mg + Ye, G +
Thus, signals of color difference points in which Cy) are alternately arranged are obtained.

From the primary colors (R, G, B) to the complementary colors (G, Ye,
(Mg, Cy), since the spectral characteristics and signal levels are different from those of general complementary color checkers, the following signal processing of primary color separation is performed, and then processing equivalent to the normal primary color arrangement is performed. You can do it.

Mg + Cy (hereinafter referred to as MC), G + Y
e (hereinafter referred to as GY) is the color difference signal Cb, and G + C
y (hereinafter, referred to as GC) and Mg + Ye (hereinafter, referred to as MY) are color difference signals Cr, and these color difference signals Cb, Cr
Are as follows: MC = R + G + 2B GY = R + 3G GC = 3G + B MY = 2R + G + B

Therefore, the R signal is again obtained from these color difference signals.
When the GB primary color signal is obtained by calculation, G = {3 (GC + GY) − (MC−MY)} / 16 = {3 (3G + B + R + 3G) − (R + G + 2B + 2R + G + B)} / 16 R = (MY−GC + 2G) / 2 = ｛( 2R + G + B) − (3G + B) + 2G｝ / 2 B = (MC−GY + 2G) / 2 = {(R + G + 2B) − (R + 3G) + 2G} / 2.

The luminance signal Y can be easily formed from 2Y = MC + GY = GC + MY = 4G + 2R + 2B by using G in the above equation as it is or by adding the color difference signals of each line. In this equation,
Y of 2Y represents a luminance signal, and Y of GY and MY represents Ye.

Next, the case where the primary color filter 19-4 of the color coding shown in FIG. 16B is used will be described. In this case, by performing diagonal two-pixel addition,
G and G, B and G, R and B, and G and R are respectively added. As a result, as shown in FIG. 19, a color coating having a complementary color arrangement is obtained. In the figure, Ye is abbreviated as Y, Mg is abbreviated as M, and Cy is abbreviated as C.

In the color coating of the complementary color arrangement, for example, 1/2 IS compression is performed as follows. Also in this case, the combination of the two lines to be added is changed between the first field and the second field. The 1 / 2IS compression will be described with reference to the operation explanatory diagram of FIG. In the figure, (A) shows the case of the first field, and (B) shows the case of the second field.
In the first field (A), a combination of the first line and the second line, the third line and the fourth line,.
Then, a two-line shift is performed by a combination of the second and third lines, the fourth and fifth lines, and so on.

First, in the first field (A), the signal charges (G, Cy, Mg, Ye,.
The line is shifted to the CD 14, and then the horizontal CCD 14
After performing a bit shift, the signal charges (M
g, Ye, G, Cy,...) are line-shifted to the horizontal CCD 14. As a result, 2-line 1-bit shift addition is performed in the horizontal CCD 14, and the addition result is shown in FIG.
As shown in (A), Cy + Mg, Mg + Ye, Ye +
G, G + Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Subsequently, the signal charges (G, C
y, Mg, Ye,...) are line-shifted and then 1-bit shifted, and then the signal charges (Mg, Y
e, G, Cy,...) are line-shifted to the horizontal CCD 14. As a result, two-line one-bit shift addition is performed, and the addition result is Cy as shown in FIG.
+ Mg, Mg + Ye, Ye + G, G + Cy,.
These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system. Thereafter, the same operation is repeated in the first field.

Next, in the second field (B), the signal charges (Mg, Ye, G, Cy,.
The line is shifted to the CD 14, and then the horizontal CCD 14
Bit shift is performed, and then the signal charges (G, Cy, Mg, Ye,...) On the third line are line-shifted to the horizontal CCD 14. As a result, two-line one-bit shift addition is performed in the horizontal CCD 14, and the addition result is Ye + G, G + Cy, Cy +, as shown in FIG.
Mg, Mg + Ye,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Subsequently, the signal charges of the fourth line (Mg, Y
, G, Cy,...) and then 1-bit shift, and then the signal charges (G, Cy, M) on the fifth line.
g, Ye,...) are line-shifted to the horizontal CCD 14.
Thereby, two-line one-bit shift addition is performed, and the addition result is Ye + G, as shown in FIG.
G + Cy, Cy + Mg, Mg + Ye,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system. Thereafter, the same operation is repeated in the second field.

As described above, in the CCD image pickup device using the color coding primary color filter 19-4 shown in FIG. 16B, 1/2 IS compression by diagonal 2-pixel addition and 2-line 1-bit shift addition is performed. By
A color difference signal Cb (Cy + Mg / Y
e + G) and the color difference signals Cr (Mg + Ye / G + Cy) are obtained alternately.

In this example, the case of 1 / 2IS compression has been described. However, in the case of 1 / 2PS compression,
Complementary colors obtained by pixel addition (G, Ye, Mg, C
This is complementary color independent readout in which the signal charges in y) are read out independently.

Next, the case where the primary color filter 19-5 of the color coding shown in FIG. 16C is used will be described. In this case, by performing diagonal two-pixel addition,
G and G, B and B, and R and R are added. As a result, FIG.
As shown in FIGS. 1 (A) and 1 (B), the primary colors are retained even after the diagonal addition, and color coding is performed for vertical stripes of primary colors in which each color is arranged in stripes in units of G, B, G, and R.

When performing diagonal two-pixel addition, the combination of rows is changed between the first field and the second field. 21A shows the case of the first field, and FIG. 21B shows the case of the second field. In the first field, a diagonal two-pixel addition is performed between a certain pixel and a pixel on the upper right (diagonally lower left), and in the second field, a certain pixel is added with the pixel on the upper left (diagonally lower right). The diagonal two-pixel addition is performed between them.

As described above, in the CCD image pickup device using the color coding primary color filter 19-5 shown in FIG. 16C, the result of the diagonal two-pixel addition is the color coding of the vertical stripes of the primary color, so that the horizontal CCD 14 Since any number of lines can be added at the time of the addition within, an arbitrary compression ratio can be realized. Also, since the primary colors remain after the oblique addition, there is no need to separate the primary colors in the signal processing system at the subsequent stage, and the circuit scale of the signal processing system can be reduced.

In particular, since the horizontal repetition of only the R / B is reduced to 4 with respect to the primary color checkerboard arrangement, the reduction in resolution when mounted as an imaging device in a digital still camera can be suppressed to a low level. There are advantages.
Further, in the vertical direction, a decrease in resolution due to signal processing such as color difference line sequential processing is small, which is advantageous when a high compression ratio is obtained.

Next, the case where the primary color filter 19-6 of the color coding shown in FIG. 16D is used will be described. In this case, by performing diagonal two-pixel addition,
G and G, B and B, R and B, and G and R are added. As a result, as shown in FIGS. 22A and 22B, G, Cy, M
Color coding is performed on complementary vertical stripes in which each color is arranged in stripes in units of g and Ye.

Also in this case, when performing diagonal two-pixel addition, the combination of rows is changed between the first field and the second field. In FIG. 22, (A) shows the first
(B) shows the case of the second field. In the first field, a diagonal two-pixel addition is performed between a certain pixel and a pixel on the upper right (diagonally lower left), and in the second field, a certain pixel is added with the pixel on the upper left (diagonally lower right). The diagonal two-pixel addition is performed between them.

As described above, in the CCD image pickup device using the color coding primary color filter 19-6 shown in FIG. 16 (D), the result of the diagonal two-pixel addition is the color coding of the complementary color vertical stripe, and the primary color vertical stripe is obtained. As in the case of the stripe, any number of lines can be added at the time of addition in the horizontal CCD 14, so that an arbitrary compression ratio can be realized.

FIG. 23 is a block diagram showing an example of the configuration of a camera system according to the present invention using the CCD image pickup device according to the present embodiment as an image pickup device.

This camera system comprises a CCD image sensor 5
1. A lens 52 constituting a part of an optical system, a CCD driving circuit 53 for driving a CCD image pickup device 51, an image pickup mode setting section 54 for setting an image pickup mode, and a CCD image pickup device 51
And a signal processing circuit 55 that performs various kinds of signal processing on the output signal.

The CCD image pickup device 51 has the structure shown in FIG.
Complementary color coding of four horizontal repetitions and two vertical repetitions shown in (B), horizontal four repetitions shown in FIGS. 16 (A) and (B).
Repeat, vertical 4 repeat primary color coding,
Alternatively, four horizontal repetitions shown in FIGS. 16 (C) and (D),
A color filter 56 having two primary color codings is mounted.

In the camera system having such a configuration, incident light (image light) from a subject (not shown) is imaged on the imaging surface of the CCD image sensor 51 through the color filter 56 by the lens 52 of the optical system. CCD image sensor 5
As 1, a multi-pixel having a pixel configuration shown in FIG. 1 corresponding to still image capturing is used. The CCD imaging device 51 is driven by a CCD driving circuit 53 in accordance with the imaging mode set by the imaging mode setting unit 54.

Here, in the imaging mode setting section 54, a still image mode and a moving image mode can be set, and for the moving image mode, an imaging mode corresponding to each television system such as NTSC / PAL / HD can be set. It is possible. The CCD drive circuit 53 includes an imaging mode setting unit 5
4, when the still image mode is set, the CCD image pickup device 51 is driven in the same manner as in the well-known frame readout, that is, in the first field, for example, only the vertical transfer clock Vφ3, and in the second field, only the readout pulse Vφ1 XSG is set to read signal charges from each pixel, and to perform vertical transfer and horizontal transfer.

When the moving image mode is set by the image pickup mode setting section 54, the CCD drive circuit 53 further performs each conversion of NTSC / PAL / HD or the like by down conversion by addition compression from the multi-pixel CCD image pickup device 51 for still image. In order to generate a television signal corresponding to the television system, the CCD imaging device 51 is driven so as to realize the compression corresponding to each television system described above, that is, the vertical compression based on diagonal two-pixel addition. By the operation in the moving image mode, as described above, the color difference signals Cr,
A vertical compression process is performed while holding Cb, and down-conversion to a television signal corresponding to each television system is performed.

As described above, it is possible to realize a camera system capable of coping with both still image capturing and moving image capturing with one CCD image sensor 51. By using a multi-pixel CCD image pickup device for a digital still camera as an image pickup device, the NTSC or PSC
It is possible to monitor an AL-type television image. In particular, since the CCD image sensor 51 can perform arbitrary vertical compression, it is possible to obtain a moving image in which the horizontal and vertical resolutions are balanced.

[0129]

As described above, according to the present invention,
Of the plurality of pixels, each signal charge of a pixel group located in every other row is read to, for example, a vertical transfer unit located on the left side,
By reading each signal charge of a pixel group located every other row, for example, to a vertical transfer unit located on the right side, signal charges can be added between two diagonal pixels in the vertical transfer unit. In this way, it is possible to capture moving images with a balance between horizontal and vertical resolutions.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a configuration example of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of color coding of a complementary color filter.

FIG. 3 is a timing chart when two diagonal pixels are added.

FIG. 4 is a timing chart in a normal mode.

FIG. 5 is a plan pattern diagram illustrating an example of a specific configuration around a sensor unit.

FIG. 6 is a diagram illustrating general color coding.

FIG. 7 is an explanatory diagram of an operation of adding two diagonal pixels in a first field.

FIG. 8 is an explanatory diagram illustrating an operation of adding two diagonal pixels in a second field.

FIG. 9 is a diagram illustrating an example of a pixel configuration when a signal corresponding to a television system is generated.

FIG. 10 is an explanatory diagram of an operation in the case of 1 / 2.0 compression.

FIG. 11 is a timing chart in the case of 1 / 2.0 compression.

FIG. 12 is an operation explanatory diagram in the case of 1 / 2.5 compression.

FIG. 13 is a timing chart in the case of 1 / 2.5 compression.

FIG. 14 is an explanatory diagram of an operation in the case of 1 / 2.5 compression with thinning.

FIG. 15 is a wiring pattern diagram for realizing 1 / 2.5 compression with thinning.

FIG. 16 is a diagram illustrating an example of color coding of a primary color filter.

FIG. 17 is a diagram showing an addition result of diagonal two-pixel addition when a primary color filter having the color coding of FIG. 16A is used.

18 is an explanatory diagram of an operation at the time of １ ／ IS compression by a primary color filter having the color coding of FIG. 16A.

FIG. 19 is a diagram illustrating an addition result of diagonal two-pixel addition when a primary color filter having the color coding of FIG. 16B is used.

20 is an explanatory diagram of an operation at the time of 1 / 2IS compression using a primary color filter having the color coding of FIG. 16B.

FIG. 21 is a diagram illustrating an addition result of diagonal two-pixel addition when a primary color filter having the color coding of FIG. 16C is used.

FIG. 22 is a diagram illustrating an addition result of diagonal two-pixel addition when a primary color filter having the color coding of FIG. 16D is used.

FIG. 23 is a block diagram illustrating an example of a configuration of a camera system according to the present invention.

FIG. 24 shows color difference signals Cr and C in the case of the conventional example (part 1).
It is a figure showing arrangement relation of b.

FIG. 25 shows color difference signals Cr and C in the conventional example (part 2).
It is a figure showing arrangement relation of b.

FIG. 26 is a diagram illustrating the operation of vertical compression in the case of the conventional example (part 2).

[Explanation of symbols]

10, 51: CCD image pickup device, 12: Vertical CCD, 13
... Read gate section, 14 ... Horizontal CCD, 16 ... Charge detection section, 19, 56 ... Color filter, 19-1, 19-2 ...
Complementary color filters, 19-3, 19-4, 19-5, 19-6: primary color filters, 53: CCD drive circuit, 54: imaging mode setting unit

Claims (14)

[Claims] A plurality of sensor units arranged in a matrix; a plurality of vertical transfer units arranged for each column with respect to the plurality of sensor units; Read each signal charge of the sensor unit group located in every other row to the vertical transfer unit located on one side of the plurality of vertical transfer units, and read each signal charge of the sensor unit group located in every other row. A solid-state imaging device comprising: a reading unit that reads data to a vertical transfer unit located on the other side of the plurality of vertical transfer units. 2. An adding drive unit for adding signal charges of two oblique pixels read from the plurality of sensor units in each of the plurality of vertical transfer units; 2. The solid-state imaging device according to claim 1, further comprising: a horizontal transfer unit configured to receive a signal charge obtained by adding two diagonal pixels in line units and horizontally transfer the signal charge. 3. The solid-state imaging device according to claim 2, wherein signal charges for a plurality of lines are added in the horizontal transfer unit. 4. The solid-state imaging device according to claim 2, wherein said addition driving means changes a combination of oblique addition between the first field and the second field. 5. The solid-state imaging device according to claim 3, wherein, in addition for a plurality of lines in the horizontal transfer unit, a combination of addition is changed between a first field and a second field. 6. The solid-state imaging device according to claim 2, wherein said addition driving means changes a combination of oblique addition depending on a row. 7. The solid-state imaging device according to claim 2, further comprising a color filter having a color coding in which the same color is repeated every two pixels in a row direction. 8. The color filter performs color coding in which the same color is repeated every four pixels in a column direction, and a color difference signal is dot-sequential by diagonal two-pixel addition in each of the plurality of vertical transfer units. The solid-state imaging device according to claim 7, wherein: 9. A plurality of sensor units arranged in every other row among a plurality of sensor units arranged in a matrix form, each signal charge of a plurality of sensor units arranged in a column with respect to the plurality of sensor units. The signal charges are read out to the vertical transfer unit located on one side of the vertical transfer units, and each signal charge of the sensor unit group located in every other row of the plurality of sensor units is read out of the plurality of vertical transfer units. A vertical transfer unit located on the other side, wherein signal charges of two oblique pixels read from the plurality of sensor units are added in each of the plurality of vertical transfer units. Drive method. 10. A method of transferring signal charges obtained by adding two pixels obliquely in each of the plurality of vertical transfer units to a horizontal transfer unit in line units, and adding signal charges for a plurality of lines in the horizontal transfer units. The method for driving a solid-state imaging device according to claim 9, wherein: 11. A plurality of sensor units arranged in a matrix, each signal charge of a group of sensor units located in every other row,
Each of the plurality of sensor units is read out to a vertical transfer unit located on one side of a plurality of vertical transfer units arranged for each column, and each signal charge of a sensor unit group located in every other row is read. To the vertical transfer unit located on the other side of the plurality of vertical transfer units, and in each of the plurality of vertical transfer units, the signal charges of two oblique pixels read from the plurality of sensor units. A solid-state imaging device capable of adding and outputting, an imaging mode setting unit capable of selectively setting a still image mode and a moving image mode, and the solid-state imaging device according to an imaging mode set by the imaging mode setting unit And a driving means for driving the camera. 12. The solid-state imaging device includes: a horizontal transfer unit that receives a signal charge in a line unit obtained by adding two diagonal pixels in each of the plurality of vertical transfer units and horizontally transfers the signal charge; 2. The apparatus according to claim 1, wherein when the moving image mode is set by the imaging mode setting unit, the signal charges for a plurality of lines are added in the horizontal transfer unit.
2. The camera system according to 1. 13. The interlacing operation of the first field and the second field by changing the combination of diagonal addition when the moving image mode is set by the imaging mode setting means. The camera system according to claim 11. 14. The driving unit performs an interlace operation by changing a combination of addition in the horizontal transfer unit between a first field and a second field when a moving image mode is set by the imaging mode setting unit. The camera system according to claim 11, wherein: