JP2001156281A - Solid-state image pickup device, method of driving the same, and camera system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem in which color difference signals Cr and Cb are reduced in color resolution to a level as low as a horizontal four-repetition coding (that is, 1/2) in a horizontal direction as compared with a usual horizontal two-repetition coding in a gridiron layout complementary color coding. SOLUTION: Two adjacent rows of sensors 11 out of pixels (sensors 11) in a direction in which rows extend are considered as a unit, the signal charge of pixels that belong to the above adjacent rows is read out by a row unit to a vertical CCD 12 located on the same side, and two adjacent rows of sensors 11 in a row direction are considered as a unit, the signal charge of pixels that belong to the above adjacent rows is read out by a row unit to a vertical CCD 12 located on the opposite side, and the signal charge of the vertical two pixels and the signal charge of oblique two pixels of the vertical CCDs 12 are added together.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image sensor, a method of driving the same, and a camera system, and more particularly to a color solid-state image sensor which can be used for both still images and moving images, a method of driving the same, and imaging of the solid-state image sensor. It relates to a camera system used as a device.

[0002]

2. Description of the Related Art In recent years, with the expectation of mounting a still function on a video camera, development of a solid-state imaging device that can be used for both still images and moving images has been advanced. Generally, it is considered that a still image is based on a square lattice and a moving image is based on 13.5 MHz. Therefore, in order to use both of them, interpolation / compression is required by either method. Here, while the still image is in the high-pixel non-format, the moving image is NTSC /
Because it is encouraged by broadcast systems such as PAL, down conversion from multi-pixel solid-state image sensors for still images
Producing television signals such as NTSC / PAL is considered most efficient.

As a technique for down-conversion (higher frame rate), signal charges of some lines are not read from the sensor unit to the vertical transfer unit, and only signal charges of other lines are read from the sensor unit to the vertical transfer unit. There are known a method of performing so-called thinning-out reading, and a method of cutting out a central area of an effective pixel area as in the case of camera shake correction.

In the former method, in a digital still camera or the like using a solid-state imaging device having a primary color filter as an imaging device, signal charges of some lines are not read out from a sensor unit to a vertical transfer unit, so that the vertical direction is prevented. The information is reduced and a high frame rate is realized, and is mainly used when outputting multi-pixel image information to a liquid crystal TV monitor. However, in this method, since the signal is thinned, the sampling frequency is lowered, and the spatial aliasing increases, so that a beautiful image cannot be obtained.
It was unsuitable for the purpose of recording and storing as moving images.

On the other hand, in the case of using the latter method, if the broadcast method is cut out at the time of multi-pixel, the change in the angle of view between a still image and a moving image becomes large and a large amount of pixel information is discarded. ineffective. For such a reason, as a method of down-conversion, a technique of performing vertical compression processing of a still image / moving image by mixing (vertical addition) in a transfer process of signal charges has conventionally been adopted.

In order to execute the vertical compression process in the process of transferring the signal charges, the biggest problem is the color coding of the color filters. That is, the primary colors R (red), G
In the case of (green) and B (blue), it is safe to perform vertical addition as vertical stripes, whereas complementary colors are Cy (cyan), Ye (yellow), G (green), and Mg (magenta). When there are colors and vertical stripes, it is disadvantageous in terms of color resolution in the horizontal direction. Therefore, a technique of shift addition by the horizontal transfer unit (hereinafter, referred to as horizontal shift addition) is employed to keep the horizontal drive frequency constant.

However, in complementary color checkerboard color coding in which Cy, Ye, G, and Mg are arranged as shown in FIG. 45, for example, signal charges of two pixels are mixed in the vertical direction (hereinafter, referred to as interlace operation). , Vertical 2
Color difference signal C obtained by performing
r (G + Cy, Mg + Ye), Cb (Mg + Cy, G +
Ye) is line-sequentially obtained alternately in the vertical direction, so that vertical mixing while retaining the color difference signals Cr and Cb is impossible. In FIG. 45, the left side is an odd number (O
DD) field, the right side shows an even number (EVEN) field, and Cy is C, Ye is Y, Mg is M
(Hereinafter the same in each drawing).

On the other hand, in order to enable vertical mixing and realize horizontal shift addition, complementary color coding as shown in FIG. 46 has been proposed (Reference: 1997 Annual Meeting of the Institute of Image Information and Television Engineers (ITE) '97: 1997 ITE Ann
ual Convention) "Study on Single-Chip Color Imaging with Hi-Vision / NTSC Output" pp. 37-38). According to the complementary color coding, the color difference signals Cr (G + Cy, Mg + Ye) and Cb (M
g + Cy, G + Ye) are obtained in a quincunx shape.

As described above, in the conventional complementary color coding in which the color difference signals Cr and Cb are arranged in a quincunx pattern, as shown in FIG. Charge during horizontal blanking period
After shifting the bit (for two pixels), the signal charges of the next one line are line-shifted, whereby signals of the same color component can be vertically mixed. That is, the color difference signal C
Vertical mixing can be realized while maintaining r and Cb.

[0010]

However, the color difference signals Cr and Cb are arranged in a quincunx pattern, that is, the color difference signals Cr and Cb.
In the case of complementary color coding in which b is alternately obtained in the horizontal direction and the vertical direction, as described above, vertical mixing with a horizontal 2-bit shift, that is, addition of signals of the same color component separated by two pixels, Since the vertical compression processing is realized, there is a problem that the color resolution in the horizontal direction is reduced to the same degree (ie, 水平) as the horizontal four repetition coding compared to the normal horizontal two repetition coding.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to provide a moving image / still image capturing method capable of arbitrary vertical compression and having a balance between horizontal and vertical resolutions. An object of the present invention is to provide a solid-state imaging device that can be used for two purposes, a driving method thereof, and a camera system.

[0012]

A solid-state imaging device according to the present invention comprises a plurality of sensor sections arranged in a matrix and a plurality of vertical sections arranged in each column with respect to the plurality of sensor sections. A transfer unit and two signal lines adjacent to each other in the row direction among the plurality of sensor units are used as a unit to transfer each signal charge of the sensor unit group located in the two rows to the vertical side located on the same side of the plurality of vertical transfer units. A first reading unit that reads out the transfer unit in units of rows, and a plurality of vertical transfer units that transfer each signal charge of a sensor unit group located in two rows adjacent to each other in a row direction among a plurality of sensor units. A second reading unit that reads out a row unit to a vertical transfer unit located on the opposite side of the unit, and a signal charge of two vertical pixels read by the first reading unit in each of the plurality of vertical transfer units. Add And addition driving means for adding two diagonal pixel signal charges of the read out by the reading means, the vertical two pixels in each of the vertical transfer portion of the plurality of addition and two diagonal
A horizontal transfer unit is provided for receiving the signal charges subjected to the pixel addition in line units and horizontally transferring the received signal charges.

[0013] In the solid-state image pickup device and the method of driving the solid-state image pickup device having the above-described configuration, of a plurality of pixels (sensor units), two adjacent rows in the row direction (vertical direction) are used as a unit to form a group of sensor units located in these two rows. Each signal charge is read out, for example, to a vertical transfer unit located on the left side in a row unit. Then, signal charges of two pixels located in the row direction on the pixel array are read out to two adjacent transfer stages of the same vertical transfer unit. In addition, each signal charge of the sensor unit group located in the two rows is read out to the transfer unit located on the left side and the vertical transfer unit located on the right side in units of two rows adjacent to each other in the row direction. Then, signal charges of two pixels obliquely positioned on the pixel array are read out to two adjacent transfer stages of the same vertical transfer unit. Then, by performing the same drive as the well-known field readout, the signal charges of the two adjacent transfer stages are added. That is, the signal charges of two vertical pixels and the signal charges of two oblique pixels are added. These added signal charges are horizontally transferred line by line.

A camera system according to the present invention uses the solid-state imaging device having the above-described configuration as an imaging device. Further, a still image mode and a moving image mode can be selectively set for the solid-state imaging device. The solid-state imaging device is driven in accordance with the imaging mode, and when the moving image imaging mode is set, signal charges of two vertical pixels and two oblique pixels in the vertical transfer unit are added, and the added signal charges are transferred to a line. The data is transferred to the horizontal transfer unit in units, and the horizontal transfer is performed after adding a plurality of lines as needed in the horizontal transfer unit.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the following description, a CCD image sensor (hereinafter, referred to as a CCD image sensor)
In the following, an example in which the present invention is applied will be described. However, the present invention is not limited to this, and is applicable to all solid-state imaging devices.

FIG. 1 shows a CCD according to an embodiment of the present invention.
FIG. 1 is a schematic configuration diagram showing an image pickup device, and shows an example in which the present invention is applied to a single-chip color CCD image pickup device of an IS (interlace scan) -IT (interline transfer) system.

In FIG. 1, a CCD imaging device 10 according to this embodiment includes a plurality of sensor units (pixels) 11 arranged in a matrix, and a plurality of vertical units arranged for each vertical column of the sensor units 11. CCD (vertical transfer unit) 12, sensor unit 11
Read gate unit 1 interposed between the vertical CCD 12
3. Horizontal CC arranged on one end side of vertical CCD 12
D (horizontal transfer unit) 14, a charge detection unit 16 and an output circuit 17 arranged at an end on the transfer destination side of the horizontal CCD 14.

Although not shown in FIG. 1, a color filter 19 is arranged on an image pickup area (pixel area) 18 of the CCD image pickup device 10. As the color filter 19, for example, as shown in FIG. 2, a primary color filter having a color coding of a primary color checker arrangement of G / B in odd rows and R / G in even rows is used. This primary color filter has two horizontal repetitions and two vertical repetitions (2 × 2) in which the same color is repeated every two pixels in the horizontal direction (column direction) and is repeated every two pixels in the vertical direction (column direction). Color coding.

In the CCD image pickup device 10 having such a configuration, the sensor section 11 is composed of, for example, a PN-junction photodiode, and photoelectrically converts incident light into a signal charge having a charge amount corresponding to the light amount and stores the signal charge. For a plurality of sensor units 11 arranged in a matrix, a plurality of vertical CCDs 1
2 are arranged.

The read gate unit 13 applies a read pulse XSG, which will be described later, to the sensor unit group located in these two rows in units of two rows adjacent to each other in the row direction as a unit. In this case, the signal is read out to the vertical CCD 12 located on the left side of the drawing in units of rows, and the signal charges of the sensor unit groups located on these two rows are read in opposite rows (right and left sides of the drawing). ) Is read out on a row-by-row basis to the vertical CCD 12 located at the position (1).

In the example shown in FIG. 1, the signal charges of the first and second rows, the fifth and sixth rows,... Are read out by row into the vertical CCD 12 located on the opposite side, and the third and fourth rows are read out. Each of the signal charges in the fourth, seventh and eighth rows,... Is read out to the vertical CCD 12 located on the same side in units of rows. The specific configuration of the read gate unit 13 will be described later.

The vertical CCD 12 is transfer-driven by, for example, four-phase vertical transfer clocks Vφ1 to Vφ4. Among the four-phase vertical transfer clocks Vφ1 to Vφ4, the vertical transfer clocks Vφ1 and Vφ3 are as shown in the waveform diagram of FIG.
It is set to take three values of a low level (“L” level), an intermediate level (“M” level) and a high level (“H” level), and a third value (“ The pulse at H level becomes the read pulse XSG.

In the vertical CCD 12, as in the case of the well-known field readout drive, signal charges are added and added between two adjacent packets by the timing relationship of the four-phase vertical transfer clocks Vφ1 to Vφ4. The combination of packets to be changed in the first field and the second field. Here, a packet refers to a unit (one transfer stage) that handles signal charges for one pixel.

That is, in the first field, FIG.
As shown in (A), the vertical transfer clocks Vφ1, Vφ3
After the read pulse XSG rises, the vertical transfer clocks Vφ1 to Vφ3 become “M” level and the vertical transfer clock Vφ
When 4 becomes the “L” level, signal charges are added between packets corresponding to, for example, the first and second rows, the third and fourth rows,... Of the pixel array. On the other hand, in the second field, as shown in FIG.
After the read pulse XSG rises at φ1 and Vφ3, the vertical transfer clocks Vφ1, Vφ3, and Vφ4 are at the “M” level,
When the vertical transfer clock Vφ2 becomes “L” level,
For example, the second and third rows, the fourth and fifth rows of the pixel array,...
Are added between the packets corresponding to...

The vertical CCD 12 converts the signal charges added between two adjacent packets into a vertical transfer clock V.
The transfer drive by φ1 to Vφ4 results in FIG.
As shown in the timing chart, the data is transferred to the horizontal CCD 14 by vertical transfer (line shift) in a part of the horizontal blanking period.

The horizontal CCD 14 is transferred and driven by, for example, two-phase horizontal transfer clocks Hφ1 and Hφ2, so that the signal charges line-shifted from the vertical CCD 12 are sequentially and horizontally transferred in the horizontal scanning period after the horizontal blanking period. To the charge detection unit 16. This horizontal C
The operation of the CD 14 is a transfer operation in the normal mode.

The charge detecting section 16 is constituted by, for example, a floating diffusion amplifier.
In other words, the horizontal CCD 14 includes a floating diffusion FD into which signal charges are injected, a reset drain RD from which charges are discharged, and a reset gate RG disposed between the floating diffusion FD and the reset drain RD. The supplied signal charge is detected and converted to a signal voltage. A predetermined reset drain voltage VRD is applied to the reset drain RD.

FIG. 5 is a plan pattern diagram showing a first example of the configuration of the sensor unit 11, the vertical CCD 12, and the read gate unit 13. In FIG. 5, a vertical CCD 12 includes a plurality of transfer channels 21 extending in parallel in a vertical direction,
Transfer electrodes 22-1 to 22-4 corresponding to four-phase vertical transfer clocks Vφ1 to Vφ4 which are sequentially arranged in the vertical direction above these transfer channels 21 and extend in the horizontal direction.
And a configuration having: Transfer electrodes 22-1 to 22-4
Are formed with two lines (two vertical pixels) as one unit.

In these transfer electrodes 22-1 to 22-4, for example, the second-phase and fourth-phase vertical transfer clocks Vφ
2, the transfer electrodes 22-2 and 22-4 to which Vφ4 is applied are formed by the first layer of polysilicon (indicated by a dashed line in the figure), and the first and third phase vertical transfer clocks Vφ1 and Vφ
The transfer electrodes 22-1 and 22-3 to which φ3 is applied are formed of a second-layer polysilicon (indicated by a two-dot chain line in the figure). The transfer electrodes 22-2 and 22-4 made of the first-layer polysilicon and the transfer electrodes 22-1 and 22-3 made of the second-layer polysilicon overlap each other on the transfer channel 21. ing.

Here, as an example, as shown by hatching in FIG. 5, around the sensor unit 11, the channel stop unit 23 for element isolation is shown in each of the sensor units 11a in the first and sixth rows. On the right side, in each of the sensor units 11b in the second to fifth rows, the seventh row, and the eighth row, the channel stop unit 23 is removed on the left side of the drawing, and thereafter, a pattern repeated every eight rows (eight vertical pixels) It has a shape. On the other hand, the transfer electrodes 22-1 to 22-4 are formed not only on the transfer channel 21 but also wide up to the opening edge of the sensor unit 11, so that the transfer electrodes 22-1 to 22-4 are not formed on the channel stop portion 23. The gate also serves as a gate electrode of the read gate unit 13.

In the above-described pixel structure, the readout pulse XSG is applied to the readout gate section 13 through the transfer electrodes 22-1 and 22-3, so that the signal charges are read out from each sensor section 11. Specifically, when the read pulse XSG rises in the vertical transfer clock Vφ1 of the first phase, the sensor unit 11 of the second row, the fourth row, the eighth row,.
b is read out to the vertical CCD 12 located on the left side of the figure as indicated by the left-pointing arrow, and the signal charges of the sensor unit 11a on the sixth row,. Is read out to the vertical CCD 12 located on the right side of.

Since the read pulse XSG rises in the third-phase vertical transfer clock Vφ3, the signal charges of the sensor units 11a in the first row,..., Are positioned on the right side of the figure as indicated by right-pointing arrows. Read out by the vertical CCD 12,
The signal charges of the sensor units 11b in the third row, the fifth row, the seventh row,... Are read out to the vertical CCD 12 located on the left side of the figure, as indicated by the arrow pointing left.

As described above, the color filter 19 having the color filter 19 of color coding of two horizontal and two vertical repetitions.
In the CD image sensor 10, two adjacent pixels in the row direction
Each signal charge of the sensor unit group located in these two rows is read out in units of rows to the vertical CCD 12 located on the same side (in this example, the left side of the figure) in rows, and two rows adjacent in the row direction are read in units. By reading each signal charge of the sensor unit group located in these two rows into the vertical CCDs 12 located on the opposite side (right and left sides in the figure) in row units, the vertical CCDs are read out.
In 12, the signal charges of two adjacent packets are added.

By adding the signal charges between two packets in the vertical CCD 12, the addition of the signal charges between two vertically (upper and lower) pixels in the pixel array (vertical two-pixel addition) and the addition of the signal charges diagonally. The addition of signal charges between two pixels (diagonal two-pixel addition) is performed alternately. In FIG.
An example of the timing when the reading of the signal charge from the sensor unit 11 and the addition of two pixels are performed will be described. The read pulse XSG is generated during a vertical blanking (V-BLK) period.

Specifically, in the first field,
As shown in FIG. 7A, the first and second rows, the fifth and sixth rows
Addition of two diagonal pixels between each two rows (DI; Diagonal
ly Integration) is performed, and vertical two-pixel addition (VI; Vertic) is performed between each of the third and fourth rows, the seventh and eighth rows, and so on.
al Integration) is performed. In this example, the diagonal 2
Pixel addition is further shifted right and left. That is, between each of the first and second rows, the ninth and tenth rows, and the like, addition is performed between two pixels on the upper right (diagonally lower left),
The addition is performed between the two pixels on the diagonally lower right (the upper left diagonal) between the two rows of the fifth and sixth rows, the thirteenth and fourteenth rows, and so on.

On the other hand, in the second field, as shown in FIG. 7B, vertical two-pixel addition is performed between each of the second and third rows, the fourth and fifth rows,. 6th and 7th lines, 8
Two diagonal pixel additions are performed between each of the second and ninth rows. In addition, at the time of the diagonal two-pixel addition, the sixth and seventh rows,.
In each of the two rows, the upper right diagonal (lower left diagonal) two pixels
Lines 9 and 9, etc., between each two lines are diagonally lower right (diagonally upper left)
Are added.

By adding the primary colors, B + R = M
g, G + R = Ye, B + G = Cy. That is, in the CCD image pickup device 10 having the color filters 19 of the primary color 2 × 2 checkerboard arrangement shown in FIG. 2, the vertical two-pixel addition and the diagonal two-pixel addition are performed in the vertical CCD 12, so that FIGS. ), The result of the addition is color coding of a complementary color 2 × 2 array. In FIG. 7, Cy is abbreviated as C, Ye is abbreviated as Ye, Mg is abbreviated as M, and black circles schematically indicate pixels,
It is assumed that addition is performed between pixels and between two vertical pixels (the same applies to each drawing below).

In this example, the color coding of the primary color filter is described as a case where the odd rows are G / B and the even rows are R / G. However, the present invention is not limited to this.
A primary color filter may be a color coding in which B and B are interchanged, or a color coding in which odd and even rows are interchanged.

As described above, the vertical two-pixel addition and the diagonal
In color coding of a 2 × 2 array of complementary colors obtained by pixel addition, signal charges of two rows obtained by addition are treated as signal charges of one line, and each signal charge is line-by-line in one horizontal period. By repeating the operation of vertically transferring to the horizontal CCD 14 and sequentially performing horizontal transfer twice (for two lines), it is possible to realize 1 / 2PS (progressive) compression in which the signal charges added in the vertical CCD 12 are independently read out. FIG. 8 shows an example of the timing at the time of 1 / 2PS compression.
Shown in

Next, in the color coding of the complementary color 2 × 2 array obtained by the vertical two-pixel addition and the diagonal two-pixel addition, the signal charges for two rows obtained by the addition are treated as the signal charges for one line. 2 line shift to transfer to horizontal CCD 14 in 2 line units
The operation of vertical addition compression based on line addition processing in D14 will be described.

The vertical addition compression by the line addition in the horizontal CCD 14 is performed by the horizontal CCD 14.
In a state where the horizontal transfer operation is stopped, vertical transfer (a line shift operation for two lines or more can be performed. At this time, if necessary, a horizontal CCD can be used.
At 14, a one-bit shift for transferring only one bit (for one stage) is also performed.

First, the operation when 1/2 IS (interlace scan) compression is performed will be described. This 1 /
In the 2IS compression, the color coating shown in FIG. 7A is used, and the combination of lines to be shifted by two lines between the first field and the second field is changed.

The 1 / 2IS compression will be described with reference to the operation explanatory diagram of FIG. In FIG. 9, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the first and second lines (a1), (3) Lines 4 and 4 (a
2), ..., in the second field (B),
The second line is shifted by a combination of the second line and the third line (b1), the fourth line and the fifth line (b2), and so on. FIG. 10 shows an example of the timing at the time of 1/2 IS compression.

First, in the first field (A), signal charges (..., G, M) on the first line obtained by adding two pixels at an angle.
g, G, Mg,...) and 2
The signal charges on the line (..., Cy, Ye, Cy, Ye,
..) Are sequentially shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, two-line normal addition in which signal charges for two lines are added as they are (Normal)
Is performed. Then, the addition result at this time is ..., G +
Cy, Mg + Ye, G + Cy, Mg + Ye,...
These signal charges are sequentially transferred horizontally by the horizontal CCD 14, converted into signal voltages by the charge detection unit 16, and output to a signal processing system in the subsequent stage.

Subsequently, the signal charges (..., Mg, G, Mg, G,...) Of the third line obtained by the diagonal two-pixel addition and the signal charges (.
, Ye, Cy, Ye,...) are sequentially line-shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, 2
Line normal addition is performed, and the addition result is…, Mg +
Cy, G + Ye, Mg + Cy, G + Ye,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the first field. Thus, in the first field, first,..., G + Cy, Mg + Ye, G + Cy, Mg + Y
e, ..., then ..., Mg + Cy, G + Ye, Mg + C
y, G + Ye,..., and thereafter, a signal is output by repetition. Here, (G + Cy) and (Mg + Ye) are color difference signals Cr, and (Mg + Cy) and (G + Ye) are color difference signals Cb.
Therefore, the color difference signal Cr and the color difference signal Cb are output alternately in line units.

Next, in the second field (B), first, the signal charges on the first line are discarded, and then the signal charges on the second line (..., Ye, Cy, Y) obtained by vertical two-pixel addition.
e, Cy,...) are line-shifted to the horizontal CCD 14, and then signal charges (.
G, Mg, G, Mg,...) Are line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:..., Ye + G, C
y + Mg, Ye + G, Cy + Mg,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Subsequently, the signal charges (..., Ye, Cy, Ye, Cy,...) Of the fourth line obtained by the vertical two-pixel addition and the signal charges (.
Mg, G, Mg, G,...) Are sequentially line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:..., Ye + M
g, Cy + G, Ye + Mg, Cy + G,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the second field. Thereby, in the second field, first,..., Ye + G, Cy + Mg, Ye + G, Cy + M
g, ..., then ..., Ye + Mg, Cy + G, Ye + M
g, Cy + G,..., and thereafter, a signal is output by repetition. Here, (Ye + G) and (Cy + Mg) represent the color difference signal Cb, and (Ye + Mg) and (Cy + G) represent the color difference signal Cr.
Therefore, the color difference signal Cb and the color difference signal Cr are output alternately in line units.

As described above, two horizontal repetitions and two vertical
Vertical CC for repeated primary color coatings
By performing vertical two-pixel addition and diagonal two-pixel addition in D12 and performing two-line shift addition in the horizontal CCD 14, 1/2 IS compression can be realized, and the color difference signals Cr (Ye + Mg, Cy + G) and the color difference signal Cb
(Ye + G, Cy + Mg) can be output alternately in line units (color difference line sequential output). Moreover, by changing the combination of two pixels (two rows) for performing vertical two-pixel addition and diagonal two-pixel addition in the first field and the second field, an interlace operation can be realized.

From the primary colors (R, G, B) to the complementary colors (G, Ye,
Since the signal processing after conversion into Mg, Cy) is different from that of general complementary color checkers in spectral characteristics and signal level, the following signal processing for primary color separation is performed in a signal processing system at the subsequent stage, and then the normal signal processing is performed. What is necessary is just to perform processing equivalent to the primary color arrangement.

Mg + Cy (hereinafter referred to as MgCy), G
+ Ye (hereinafter referred to as GYe) is a color difference signal Cb,
G + Cy (hereinafter, referred to as GCy), Mg + Ye (hereinafter, referred to as GCy)
MgYe) is a color difference signal Cr, and the RGB signals included in the color difference signals Cb and Cr are MgCy = R + G + 2B GYe = R + 3G GCy = 3G + B MgYe = 2R + G + B.

Therefore, the R signal is again obtained from these color difference signals.
When the GB primary color signal is calculated, G = {3 (GCy + GYe) − (MgCy−MgYe)} / 16 = {3 (3G + B + R + 3G) − (R + G + 2B + 2R + G + B)} / 16 R = (MgYe−GCy + 2G) / 2 = ｛( 2R + G + B) − (3G + B) + 2G｝ / 2 B = (MgCy−GYe + 2G) / 2 = {(R + G + 2B) − (R + 3G) + 2G} / 2.

As for the luminance signal Y, G in the above equation can be used as it is or by adding the color difference signals of each line to obtain 2Y = MgCy + GYe = GCy + MgYe = 4G + 2
It can be easily made from R + 2B.

Next, the operation in the case where 1/4 IS compression is performed will be described. In the ４ IS compression according to the first example, the addition result of the vertical two-pixel addition and the diagonal two-pixel addition shown in FIG. 7A is used, and the vertical addition is performed in units of four lines. Then, the combination of four lines is changed between the first field and the second field. The operation of the 動作 IS compression according to the first example will be described with reference to the operation explanatory diagram of FIG.

In FIG. 11, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the third line to the sixth line, the seventh line to the tenth line,...
The vertical addition is performed by a combination of the fourth line, the fifth line to the eighth line, and so on. FIG. 12 shows an example of the timing at the time of 1/4 IS compression.

First, in the first field (A), first, the signal charges of the first and second lines are discarded, and then, the signal charges of the third line by diagonal two-pixel addition (...,...).
G, Mg, G, Mg,...), And then signal charges (..., Ye, Cy, Ye, C) on the fourth line by vertical two-pixel addition.
,...) are sequentially line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:..., G + Ye, Mg + Cy, G
+ Ye, Mg + Cy,...

After the normal addition of the two lines, a one-bit shift is performed, and then the signal charges (..., Mg, G, Mg, G,...) Of the fifth line obtained by the diagonal two-pixel addition are line-shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, addition of signal charges for three lines (six pixels) accompanied by 1-bit shift addition is performed, and the addition result is:..., 2G +
Ye, 2Mg + Cy, 2G + Ye, 2Mg + Cy,...

After the addition of the three lines, a 1-bit shift is performed, and then the signal charges (..., Ye, Cy, Ye, Cy,.
Line shift to Thus, in the horizontal CCD 14, addition of signal charges for 4 lines (8 pixels) accompanied by 1-bit shift addition is performed, and the addition result is:..., 2G +
2Ye, 2Mg + 2Cy, 2G + 2Ye, 2Mg + 2C
y, ...

These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a signal processing system at a subsequent stage. Thus, from line 3 to line 6, line shift → line shift → 1 bit shift → line shift → 1
Addition of signal charges for four lines is performed by the procedure of bit shift → line shift. Figure 1 shows an example of the timing.
2 (A).

In the vertical addition of the signal charges for the four lines from the seventh line to the tenth line, first, the signal charges (..., G, Mg, G, M) of the seventh line are obtained by diagonal two-pixel addition.
g,...) is line-shifted to the horizontal CCD 14 and then 1
Bit shift is performed, and then signal charges (..., Ye, Cy, Ye, Cy,...) On the eighth line by vertical two-pixel addition.
Is shifted to the horizontal CCD 14. As a result, two-line one-bit shift addition is performed in the horizontal CCD 14. The addition result is:..., G + Cy, Mg + Ye,
G + Cy, Mg + Ye,... After the two-line one-bit shift addition, the ninth line signal charges (..., Mg, G, Mg, G,. , Ye,
Cy, Ye, Cy,...) Are sequentially line-shifted to the horizontal CCD 14. As a result, signal charges for four lines are added in the horizontal CCD 14. The addition result at this time is: 2G + 2Cy, 2Mg + 2Ye, 2G + 2C
y, 2Mg + 2Ye,...

These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a signal processing system at a subsequent stage. Thus, from the seventh line to the tenth line, line shift → 1 bit shift → line shift → line shift →
Signal charges for four lines are added by the line shift procedure. FIG. 12B shows an example of the timing.

Thereafter, the same operation is repeated in the first field. Thus, in the first field, first,..., 2G + 2Ye, 2Mg + 2Cy, 2G + 2Y
e, 2Mg + 2Cy,..., 2G + 2Cy, 2
.., Mg + 2Ye, 2G + 2Cy, 2Mg + 2Ye,... Here, (Mg
+ Cy) and (G + Ye) are color difference signals Cb and (G + C
y) and (Mg + Ye) are the color difference signals Cr,
The color difference signal Cb and the color difference signal Cr are output alternately in line units.

Next, in the second field (B), first,
The signal charges of the first line (..., G,
, Mg, G, Mg,...) Are line-shifted to the horizontal CCD 14, and signal charges (..., Cy, Ye, Cy, Ye,.
Line shift to As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:
Cy, Mg + Ye, G + Cy, Mg + Ye,...

After the normal addition of the two lines, a one-bit shift is performed, and then the signal charges (..., Mg, G, Mg, G,...) Of the third line obtained by the diagonal two-pixel addition are line-shifted to the horizontal CCD 14. Thus, in the horizontal CCD 14, addition of signal charges for three lines accompanied by 1-bit shift addition is performed, and the addition result is:..., 2G + Cy, 2M
g + Ye, 2G + Cy, 2Mg + Ye,...

After the addition of the three lines, a 1-bit shift is performed, and then the signal charges (..., Cy, Ye, Cy, Ye,.
Line shift to As a result, addition of signal charges for four lines is performed in the horizontal CCD 14, and the addition result is as follows: 2G + 2Cy, 2Mg + 2Ye, 2G + 2C
y, 2Mg + 2Ye,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

In the vertical addition of the signal charges for the four lines from the fifth line to the eighth line, first, the signal charges (..., G, Mg, G, M) on the fifth line by diagonal two-pixel addition are added.
g,...) is line-shifted to the horizontal CCD 14 and then 1
Bit shift is performed, and then signal charges (..., Cy, Ye, Cy, Ye, ...) on the sixth line by vertical two-pixel addition.
Is shifted to the horizontal CCD 14. As a result, two-line one-bit shift addition is performed in the horizontal CCD 14. The result of the addition is ..., G + Ye, Mg + Cy,
G + Ye, Mg + Cy,... After the two-line one-bit shift addition, the signal charges (..., Mg, G, Mg, G,...) Of the seventh line obtained by the diagonal two-pixel addition are successively added to the signal charges of the eighth line (. , Cy, Y
e, Cy, Ye,...) are sequentially line-shifted to the horizontal CCD 14. As a result, signal charges for four lines are added in the horizontal CCD 14, and the result of the addition is:
G + 2Ye, 2Mg + 2Cy, 2G + 2Ye, 2Mg +
2Cy, ... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the second field. Thus, in the second field, first,..., 2G + 2Cy, 2Mg + 2Ye, 2G + 2C
y, 2Mg + 2Ye,..., 2G + 2Ye, 2
... Mg + 2Cy, 2G + 2Ye, 2Mg + 2Cy,... Here, (G +
Cy) and (Ye + Mg) are the color difference signals Cr and (G + Y
e), since (Mg + Cy) is the color difference signal Cb,
The color difference signal Cr and the color difference signal Cb are output alternately in line units.

In the case of １ ／ IS compression according to the second example,
The addition result of the vertical two-pixel addition and the diagonal two-pixel addition shown in FIG. 7A is used, and the vertical addition is performed in units of four lines. Then, the combination of four lines is changed between the first field and the second field. The operation of the ＩＳ IS compression according to the second example will be described with reference to the operation explanatory diagram of FIG.

In FIG. 13, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the second to fifth lines, the sixth to ninth lines,..., And in the second field (B), the fourth to seventh lines
The vertical addition is performed with a combination of the line, the eighth line to the eleventh line, and so on.

First, in the first field (A), first, the signal charges on the first line are discarded, and then the signal charges on the second line (..., Ye, Cy, Y) obtained by vertical two-pixel addition.
e, Cy,...) are line-shifted to the horizontal CCD 14, and then signal charges (.
G, Mg, G, Mg,...) Are line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:..., Ye + G, C
y + Mg, Ye + G, Cy + Mg,...

After the normal addition of the two lines, the signal charges (..., Ye, Cy, Ye,
Cy,...) Is shifted to the horizontal CCD 14 and then shifted by 1 bit, and then the signal charges (..., G, Mg, G, Mg,. I do. Thereby, horizontal CC
In D14, addition of signal charges for four lines accompanied by 1-bit shift addition is performed.
2Ye, 2Mg + 2Cy, 2G + 2Ye, 2Mg + 2C
y, ... These signal charges are sequentially transferred horizontally,
The signal is converted into a signal voltage and output to a subsequent signal processing system.

In the vertical addition of the signal charges for the four lines from the sixth line to the ninth line, first, the signal charges (..., Cy, Ye, Cy, Cy,
Ye,...) Is line-shifted to the horizontal CCD 14, and then subjected to 1-bit shift, and then the signal charges (..., Mg, G, Mg, G,. I do. Thereby, horizontal CC
In D14, two-line one-bit shift addition is performed. The result of the addition is ..., Cy + G, Ye + Mg, Cy
+ G, Ye + Mg,... After the two-line one-bit shift addition, a further one-bit shift is performed, and then the signal charges (..., Cy, Y) on the eighth line by vertical two-pixel addition.
, Cy, Ye,...) and the signal charges (..., G, Mg, G, Mg,.
Are sequentially shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, addition of signal charges for four lines accompanied by 1-bit shift addition is performed. The addition result at this time is: 2G + 2Cy, 2Mg + 2Ye, 2G +
2Cy, 2Mg + 2Ye,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the first field. Thus, in the first field, first,..., 2G + 2Ye, 2Mg + 2Cy, 2G + 2Y
e, 2Mg + 2Cy,..., 2G + 2Cy, 2
.., Mg + 2Ye, 2G + 2Cy, 2Mg + 2Ye,... Here, (G +
Ye) and (Mg + Cy) are the color difference signals Cb and (G + C
y) and (Mg + Ye) are the color difference signals Cr,
The color difference signal Cb and the color difference signal Cr are output alternately in line units.

Next, in the second field (B), first, the signal charges of the first to third lines are discarded, and then, the signal charges of the fourth line (..., Y
, Cy, Ye, Cy,...) are line-shifted to the horizontal CCD 14, followed by 1-bit shift, and then signal charges (..., Mg, G, M) on the fifth line by diagonal two-pixel addition.
g, G,...) are line-shifted to the horizontal CCD 14. Thus, two-line one-bit shift addition is performed in the horizontal CCD 14. The result of the addition is ..., Ye + G, C
y + Mg, Ye + G, Cy + Mg,...

After the two-line one-bit shift addition, a further one-bit shift is performed, and then signal charges (..., Ye, Cy, Ye, Cy,
..), And then signal charges (.., G, Mg, G, Mg,...) On the seventh line by adding two diagonal pixels sequentially to the horizontal CCD.
The line is shifted to 14. Thereby, the horizontal CCD 14
, The addition of the signal charges for the four lines accompanied by the 1-bit shift addition is performed, and the addition result is:..., 2G + 2Y
e, 2Mg + 2Cy, 2G + 2Ye, 2Mg + 2Cy,
... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

In the vertical addition of the signal charges for the next four lines from the eighth line to the eleventh line, first, the signal charges (..., Cy, Ye, C
y, Ye,...) are line-shifted to the horizontal CCD 14, and then the signal charges (.
G, Mg, G, Mg,...) Are line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14. And the result of the addition is ..., C
y + G, Ye + Mg, Cy + G, Ye + Mg,... After the normal addition of these two lines, 1
The signal charges of the 0th line (..., Cy, Ye, Cy, Ye,
..) Is shifted by 1 bit, and then signal charges (..., Mg, G, M) on the eleventh line obtained by diagonal two-pixel addition.
g, G,...) are sequentially line-shifted to the horizontal CCD 14. As a result, addition of signal charges for four lines is performed in the horizontal CCD 14, and the addition result is..., 2G + 2
Cy, 2Mg + 2Ye, 2G + 2Cy, 2Mg + 2Y
e, ... These signal charges are sequentially transferred horizontally,
The signal is converted into a signal voltage and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the second field. Thus, in the second field, first,..., 2G + 2Ye, 2Mg + 2Cy, 2G + 2Y
e, 2Mg + 2Cy,..., 2G + 2Cy, 2
.., Mg + 2Ye, 2G + 2Cy, 2Mg + 2Ye,... Here, (G +
Ye) and (Mg + Cy) are the color difference signals Cb and (G + C
y) and (Mg + Ye) are the color difference signals Cr,
The color difference signal Cb and the color difference signal Cr are output alternately in line units.

In the case of １ ／ IS compression according to the third example,
The addition result of the vertical two-pixel addition and the diagonal two-pixel addition shown in FIG. 7B is used, and the vertical addition is performed in units of four lines. Then, the combination of four lines is changed between the first field and the second field. The operation of the 1/4 IS compression according to the third example will be described with reference to the operation explanatory diagram of FIG.

In FIG. 14, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the third line to the sixth line, the seventh line to the tenth line,...
The vertical addition is performed by a combination of the fourth line, the fifth line to the eighth line, and so on.

First, in the first field (A), first, the signal charges on the first and second lines are discarded, and then the signal charges on the third line (...,.
G, Mg, G, Mg,...) Are line-shifted to the horizontal CCD 14, and then 1-bit shifted, and then signal charges (..., Mg, G, Mg,.
G,...) Is line-shifted to the horizontal CCD 14. Thus, two-line one-bit shift addition is performed in the horizontal CCD 14. The result of the addition is ..., 2G, 2Mg, 2
G, 2Mg,...

After the two-line one-bit shift addition, a one-bit shift is performed, and then the signal charges (..., Ye, Cy, Ye, Cy,.
Subsequently, the signal charges (..., Ye, Cy, Ye, Cy,.
The line is shifted to 14. Thereby, the horizontal CCD 14
, 2 lines of signal charges are added together with 1-bit shift addition, and the addition result is:..., 2G +
2Ye, 2Mg + 2Cy, 2G + 2Ye, 2Mg + 2C
y, ... These signal charges are sequentially transferred horizontally,
The signal is converted into a signal voltage and output to a subsequent signal processing system.

In the vertical addition of the signal charges of the four lines from the seventh line to the tenth line, first, the signal charges (..., G, Mg, G, M) of the seventh line are obtained by diagonal two-pixel addition.
g,...) is line-shifted to the horizontal CCD 14 and then 1
Perform a bit shift, and then add 8 pixels diagonally.
The line signal charges (..., Mg, G, Mg, G,...) Are line-shifted to the horizontal CCD 14. As a result, two-line one-bit shift addition is performed in the horizontal CCD 14. The result of the addition is ..., 2G, 2Mg, 2G, 2M
g, ... After the two-line one-bit shift addition, the signal charges (..., Ye,
Cy, Ye, Cy,...) And signal charges (..., Ye, Cy, Ye, C) on the tenth line by vertical two-pixel addition.
,...) are sequentially line-shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, addition of signal charges for four lines accompanied by 1-bit shift addition is performed. Then, the addition result is:..., 2G + 2Cy, 2Mg + 2Y
e, 2G + 2Cy, 2Mg + 2Ye,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the first field. Thus, in the first field, first,..., 2G + 2Ye, 2Mg + 2Cy, 2G + 2Y
e, 2Mg + 2Cy,..., 2G + 2Cy, 2
.., Mg + 2Ye, 2G + 2Cy, 2Mg + 2Ye,... Here, (G +
Ye) and (Mg + Cy) are the color difference signals Cb and (G + C
y) and (Mg + Ye) are the color difference signals Cr,
The color difference signal Cb and the color difference signal Cr are output alternately in line units.

Next, in the second field (B), first,
The signal charges of the first line (..., C
, Ye, Cy, Ye,...) and the signal charges (..., Ye, Cy, Ye,.
Cy,...) Are sequentially line-shifted to the horizontal CCD 14.
As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:..., 2Cy, 2Ye, 2C
y, 2Ye,...

After the normal addition of the two lines, the signal charges (..., Mg, G, Mg,.
G,...) Is line-shifted to the horizontal CCD 14 and then 1
A bit shift is performed, and then 4
The line signal charges (..., G, Mg, G, Mg,...) Are line-shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, addition of signal charges for four lines accompanied by 1-bit shift addition is performed, and the addition result is:.
Mg + 2Cy, 2G + 2Ye, 2Mg + 2Cy, 2G +
2Ye, ... These signal charges are transferred to the horizontal CCD 1
The signal is sequentially transferred in the horizontal direction by the signal detector 4, converted into a signal voltage by the charge detection unit 16, and output to a subsequent signal processing system.

In the vertical addition of the signal charges for the four lines from the fifth line to the eighth line, first, the signal charges (..., Cy, Ye, Cy, Cy,
Ye,...), And then the signal charges (..., Ye, Cy, Ye, Cy,...) Of the sixth line by vertical two-pixel addition are sequentially line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is..., 2Cy, 2Ye, 2Cy, 2Ye,. After the normal addition of the two lines, a one-bit shift is performed, and then the signal charges (...,...
Mg, G, Mg, G,...) Are line-shifted to the horizontal CCD 14. Further, the signal charges (..., G, Mg,
G, Mg,...) Are line-shifted to the horizontal CCD 14.
As a result, in the horizontal CCD 14, addition of signal charges for four lines accompanied by two 1-bit shift additions is performed. Then, the addition result is:..., 2G + 2Cy, 2M
g + 2Ye, 2G + 2Cy, 2Mg + 2Ye,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the second field. Thus, in the second field, first,..., 2Mg + 2Cy, 2G + 2Ye, 2Mg + 2C
y, 2G + 2Ye, ..., then ..., 2G + 2Cy, 2M
g + 2Ye, 2G + 2Cy, 2Mg + 2Ye,... Here, (Mg
+ Cy) and (G + Ye) are color difference signals Cb and (G + C
y) and (Mg + Ye) are the color difference signals Cr,
The color difference signal Cr and the color difference signal Cb are output alternately in line units.

In the case of １ ／ IS compression according to the fourth example,
The addition result of the vertical two-pixel addition and the diagonal two-pixel addition shown in FIG. 7B is used, and the vertical addition is performed in units of four lines. Then, the combination of four lines is changed between the first field and the second field. The operation of １ ／ IS compression according to the fourth example will be described with reference to the operation explanatory diagram of FIG.

In FIG. 15, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the second to fifth lines, the sixth to ninth lines,..., And in the second field (B), the fourth to seventh lines
The vertical addition is performed with a combination of the line, the eighth line to the eleventh line, and so on.

First, in the first field (A), first, the signal charges on the first line are discarded, and then, the signal charges on the second line (..., Ye, Cy, Y) obtained by vertical two-pixel addition.
e, Cy,...) are line-shifted to the horizontal CCD 14, and then signal charges (.
G, Mg, G, Mg,...) Are line-shifted to the horizontal CCD 14. Thereby, two-line normal addition is performed in the horizontal CCD 14, and the addition result is: Ye + G, Cy
+ Mg, Ye + G, Cy + Mg,...

After the normal addition of the two lines, a one-bit shift is performed, and then the signal charges (..., Mg, G, Mg, G,.
, Ye, and then 1-bit shift, and signal charges (..., Ye,
Cy, Ye, Cy,...) Are line-shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, addition of signal charges for four lines accompanied by 1-bit shift addition is performed, and the addition result is as follows: 2G + 2Ye, 2Mg + 2C
y, 2G + 2Ye, 2Mg + 2Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

In the vertical addition of the signal charges for the four lines from the sixth line to the ninth line, first, the signal charges (..., Ye, Cy, Ye,.
,...) Are shifted to the horizontal CCD 14 and then shifted by one bit, and then the signal charges (..., G, Mg, G, Mg,.
Line shift to D14. Thereby, the horizontal CCD 1
4, two-line one-bit shift addition is performed, and the addition result is:..., Ye + Mg, Cy + G, Ye + Mg,
Cy + G,...

After the two-line one-bit shift addition, a one-bit shift is performed. Thereafter, the signal charges (..., Mg, G, Mg, G,. Signal charge on line 9 (...,
Ye, Cy, Ye, Cy,...) Are sequentially line-shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, addition of signal charges for four lines accompanied by 1-bit shift addition is performed, and the addition result is,..., 2Mg + 2Ye,
2G + 2Cy, 2Mg + 2Ye, 2G + 2Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the first field. Thus, in the first field, first,..., 2G + 2Ye, 2Mg + 2Cy, 2G + 2Y
e, 2Mg + 2Cy,..., and then, 2Mg + 2Ye,
.., 2G + 2Cy, 2Mg + 2Ye, 2G + 2Cy,... Here, (G + Y
e), (Mg + Cy) are color difference signals Cb, (Mg + Y)
e) and (G + Cy) are the color difference signals Cr, so that the color difference signals Cb and Cr are output alternately in line units.

Next, in the second field (B), first,
The signal charges of the first to third lines are discarded, and then the signal charges of the fourth line (..., G, M
g, G, Mg,...) are line-shifted to the horizontal CCD 14, then shifted by one bit, and then signal charges (..., Cy, Ye, Cy, Ye,.
..) Is line-shifted to the horizontal CCD 14. As a result, two-line one-bit shift addition is performed in the horizontal CCD 14, and the addition result is:..., G + Ye, Mg + C
y, G + Ye, Mg + Cy,...

After the two-line one-bit shift addition, signal charges (..., Cy, Y) on the sixth line by vertical two-pixel addition
e, Cy, Ye,...), and then signal charges (..., Mg, G, Mg, G,.
Are sequentially shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, signal charges for four lines accompanied by 1-bit shift addition are added, and the addition result is..., 2G + 2Ye, 2Mg + 2Cy, 2G + 2Y.
e, 2Mg + 2Cy,... Next 8th line-11
In the vertical addition of signal charges for four lines up to the line,
First, the signal charges (..., G, Mg, G, Mg,...) On the eighth line obtained by the diagonal two-pixel addition, and then the signal charges (..., Cy, Ye, C) on the ninth line obtained by the vertical two-pixel addition.
, Ye,...) are sequentially line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:..., G + Cy, Mg + Y
e, G + Cy, Mg + Ye,...

After the normal addition of the two lines, the signal charges (..., Cy, Ye, C
, Ye,...) are line-shifted to the horizontal CCD 14, then 1-bit shifted, and then 1 is obtained by adding two diagonal pixels.
Signal charge of the first line (..., Mg, G, Mg, G, ...)
Is shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, addition of signal charges for four lines accompanied by 1-bit shift addition is performed.
2G + 2Cy, 2Mg + 2Ye, 2G + 2Cy, 2Mg
+ 2Ye,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the second field. Thus, in the second field, first,..., 2G + 2Ye, 2Mg + 2Cy, 2G + 2Y
e, 2Mg + 2Cy,..., then, 2G + 2Cy, 2M
g + 2Ye, 2G + 2Cy, 2Mg + 2Ye,... Here, (G + Y
e), (Mg + Cy) are the color difference signals Cb, (G + Cy),
Since (Mg + Ye) is the color difference signal Cr, the color difference signal Cr and the color difference signal Cb are output alternately in line units.

FIG. 16 shows a sensor section 11 and a vertical CCD 12.
FIG. 6 is a plan pattern diagram illustrating a second example of the configuration of the read gate unit 13. 16, the same parts as those in the plan pattern diagram of FIG. 5 (first example) are denoted by the same reference numerals, and the description thereof will not be repeated here.

The difference between the first example and the second example lies in the shape of the pattern of the channel stop unit 23. That is, in the case of the pattern example of the channel stop unit 23 according to the first example,
As is clear from FIGS. 7A and 7B, the diagonal addition and the vertical addition are alternately performed, and the diagonal addition is further alternately swung right and left. On the other hand, the channel stop unit according to the second example is described. In the case of the pattern example of 23, diagonal addition and vertical addition are alternately performed, and vertical addition is further alternately swung right and left.

More specifically, as shown by hatching in FIG.
In each of the sensor units 11a of the first, fifth, seventh, and eighth rows, a channel stop unit is provided on the right side of the figure, and in each of the second to fourth and sixth rows of the sensor units 11b, a channel stop unit is provided on the left side of the figure. 2
3 is removed, and thereafter, the pattern shape is repeated every eight rows (eight vertical pixels).

In the above-described pixel structure, the rise of the read pulse XSG in the first-phase vertical transfer clock Vφ1 causes the signal charges of the sensor units 11b in the second, fourth, sixth,. As shown by the arrow, the signal is read out to the vertical CCD 12 located on the left side of the figure, and the signal charge of the sensor unit 11a in the eighth row,... Is transferred to the vertical CCD 12 located on the right side of the figure as shown by the rightward arrow. Is read.

Further, since the read pulse XSG rises in the vertical transfer clock Vφ3 of the third phase, the signal charges of the sensor units 11a of the first row, the fifth row, the seventh row,... The vertical CCD 1 located on the right side of the figure
2 and the signal charges of the sensor units 11b in the third row,... Are read out to the vertical CCD 12 located on the left side of the figure, as indicated by the arrow pointing left.

Thus, the signal charges of two adjacent packets are added in the vertical CCD 12. By the addition of the signal charges, the diagonal two-pixel addition and the vertical two-pixel addition are alternately repeated, and the vertical addition is further swung right and left. Then, the result of the addition is color coding of a 2 × 2 array of complementary colors, as shown in FIG. In FIG. 17, (A) shows the case of the first field,
(B) shows the case of the second field.
Also, a first field (A) and a second field (B)
Then, the combination of rows to be subjected to two-pixel addition is changed.

Specifically, in the first field (A), diagonal two-pixel addition (DI) is performed between each of the first and second rows, the fifth and sixth rows,. Lines 3 and 4,
Vertical two-pixel addition (V
I) is performed. On the other hand, in the second field (B), vertical two-pixel addition is performed between each of the second and third rows, the eighth and ninth rows,..., And the fourth and fifth rows, 6 Lines 7
Two diagonal pixel additions are performed between each of the two rows. In addition, at the time of the diagonal two-pixel addition, two pixels diagonally upper right (diagonally lower left) are added in the first field, and two pixels diagonally lower right (diagonally upper left) are added in the second field.

Next, the operation of 1/2 IS compression in the case of color coding of the 2 × 2 array of complementary colors will be described. In the 1 / 2IS compression, the color coding shown in FIG. 17A is used, and the combination of lines for performing a 2-line shift between the first field and the second field is changed.

The 1/2 IS compression will be described with reference to the operation explanatory diagram of FIG. In FIG. 18, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the first and second lines (a1), (3) In the second field (B), the second line and the third line (b1) and the fourth line and the fifth line
A two-line shift is performed by a combination of the lines (b2),.

First, in the first field (A), signal charges (..., G, M) on the first line obtained by adding two pixels at an angle.
g, G, Mg,...) are line-shifted to the horizontal CCD 14, and then signal charges (..., Cy, Ye, Cy, Ye,.
Line shift to As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:
+ Cy, Mg + Ye, G + Cy, Mg + Ye,. These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Subsequently, the signal charges (..., G, Mg, G, Mg,.
D14, and then the signal charges of the fourth line (..., Ye, Cy, Ye, Cy,
..) Is line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and
The result of the addition is..., G + Ye, Mg + Cy, G + Y
e, Mg + Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the first field. Thus, in the first field, first,..., G + Cy, Mg + Ye, G + Cy, Mg + Y
e, ..., then ..., Mg + Cy, G + Ye, Mg + C
.., G + Ye,... Here, since (G + Cy) and (Mg + Ye) are the color difference signals Cr and (Mg + Cy) and (G + Ye) are the color difference signals Cb, the color difference signals Cr and the color difference signals Cb are output alternately in line units.

Next, in the second field (B), first, the signal charges in the first line are discarded, and then the signal charges in the second line (..., Ye, Cy, Y, Y) obtained by vertical two-pixel addition.
e, Cy,...) are line-shifted to the horizontal CCD 14, and then signal charges (.
Mg, G, Mg, G,...) Are line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:..., Mg + Ye,
G + Cy, Mg + Ye, G + Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Subsequently, the signal charges (..., Cy, Ye, Cy, Ye,...) On the fourth line obtained by the vertical two-pixel addition are then transferred to the signal charges (.
Mg, G, Mg, G,...) Are sequentially line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:..., G + Y
e, Mg + Cy, G + Ye, Mg + Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the second field. Thus, in the second field,..., Mg + Ye, G + Cy, Mg + Ye, G + C
y, ..., then ..., G + Ye, Mg + Cy, G + Ye,
Mg + Cy,..., And thereafter, a signal is output by repetition. Here, since (Mg + Ye) and (G + Cy) are the color difference signals Cr and (G + Ye) and (Mg + Cy) are the color difference signals Cb, the color difference signals Cr and the color difference signals Cb are alternately output in line units.

As described above, two horizontal repetitions and two vertical
Vertical CC for repeated primary color coatings
By performing vertical two-pixel addition and diagonal two-pixel addition in D12 and performing two-line shift addition in the horizontal CCD 14, 1/2 IS compression can be realized, and the color difference signals Cr (Ye + Mg, Cy + G) and the color difference signal Cb
(Ye + G, Cy + Mg) can be output alternately in line units (color difference line sequential output). Moreover, by changing the combination of two pixels (two rows) for performing vertical two-pixel addition and diagonal two-pixel addition in the first field and the second field, an interlace operation can be realized.

Next, the operation of the 1/4 IS compression in the case of the color coding of the complementary 2 × 2 array shown in FIG.
Examples to fourth examples will be described. In the first and second examples, the color coding shown in FIG. 17A is used, and in the third and fourth examples, the color coding shown in FIG. 17B is used. The combination of the lines to be shifted by two lines is changed.

The operation of the ＩＳ IS compression according to the first example will be described with reference to the operation explanatory diagram of FIG. In FIG. 19, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the third line to the sixth line, the seventh line to the tenth line,..., And in the second field (B), the first line to the fourth line, the fifth line ~
Vertical addition is performed by a combination of the eighth line,.

First, in the first field, first,
The signal charges on the first and second lines are discarded, and then the signal charges on the third line (..., G, M
g, G, Mg,...) and 4
The signal charges of the line (..., Ye, Cy, Ye, Cy,
..) Are sequentially shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:..., G + Ye, Mg + Cy, G +
Ye, Mg + Cy,...

After the normal addition of the two lines, the signal charges (..., G, Mg, G, M) of the fifth line obtained by the diagonal two-pixel addition
g,...) is line-shifted to the horizontal CCD 14 and then 1
After the bit shift, the signal charges (..., Cy, Ye, Cy, Ye,...) On the sixth line by vertical two-pixel addition are line-shifted to the horizontal CCD 14. Thereby, horizontal C
In the CD 14, addition of signal charges for 4 lines accompanied by 1-bit shift addition is performed, and the addition result is:.
2Ye, 2Mg + 2Cy, 2G + 2Ye, 2Mg + 2C
y, ... These signal charges are sequentially transferred horizontally,
The signal is converted into a signal voltage and output to a subsequent signal processing system.

In the vertical addition of the signal charges of the four lines from the seventh line to the tenth line, first, the signal charges (..., G, Mg, G, M) of the seventh line by diagonal two-pixel addition are obtained.
g,...) is line-shifted to the horizontal CCD 14 and then 1
After performing the bit shift, the signal charges (..., Ye, Cy, Ye, Cy,...) On the eighth line by vertical two-pixel addition are line-shifted to the horizontal CCD 14. Thereby, horizontal C
In the CD 14, two-line one-bit shift addition is performed, and the addition result is:..., G + Cy, Mg + Ye, G +
Cy, Mg + Ye,... After the two-line one-bit shift addition, a one-bit shift is performed, and then the signal charges (..., G, Mg, G, and M) on the ninth line are obtained by diagonal two-pixel addition.
g,...), and then the signal charges (..., Cy, Ye, Cy, Ye,...) of the tenth line by vertical two-pixel addition are sequentially line-shifted to the horizontal CCD 14. As a result, signal charges for four lines with one-bit shift addition are added in the horizontal CCD 14, and the addition result is:.
+ 2Cy, 2Mg + 2Ye, 2G + 2Cy, 2Mg + 2
Ye, ... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the first field. Thus, in the first field, first,..., 2G + 2Ye, 2Mg + 2Cy, 2G + 2Y
e, 2Mg + 2Cy,..., 2G + 2Cy, 2
.., Mg + 2Ye, 2G + 2Cy, 2Mg + 2Ye,... Here, (G +
Ye) and (Mg + Cy) are the color difference signals Cb and (G + C
y) and (Mg + Ye) are the color difference signals Cr,
The color difference signal Cb and the color difference signal Cr are output alternately in line units.

Next, in the second field (B), first,
The signal charges of the first line (..., G,
, Cy, Ye, Cy, Ye,..., Mg, G, Mg,.
..) Are sequentially shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:..., G + Cy, Mg + Ye, G +
Cy, Mg + Ye,...

After the normal addition of the two lines, the signal charges (..., G, Mg, G, M) of the third line are obtained by diagonal two-pixel addition.
g,...) is line-shifted to the horizontal CCD 14 and then 1
After the bit shift, the signal charges (..., Ye, Cy, Ye, Cy,...) Of the fourth line by vertical two-pixel addition are line-shifted to the horizontal CCD 14. Thereby, horizontal C
In the CD 14, addition of signal charges for four lines accompanied by 1-bit shift addition is performed.
+ 2Cy, 2Mg + 2Ye, 2G + 2Cy, 2Mg + 2
Ye, ... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

In the vertical addition of the signal charges for the four lines from the fifth line to the eighth line, first, the signal charges (..., Mg, G, Mg,.
G,...) Is line-shifted to the horizontal CCD 14 and then 1
After the bit shift, the signal charges (..., Ye, Cy, Ye, Cy,...) On the sixth line by vertical two-pixel addition are line-shifted to the horizontal CCD 14. Thereby, horizontal C
In the CD 14, two-line one-bit shift addition is performed.
The result of addition is ..., Mg + Cy, G + Ye, Mg + C
y, G + Ye,... After the two-line one-bit shift addition, a one-bit shift is performed, and then the signal charges (..., Mg, G, Mg, G,.
..) And the signal charges (..., Cy, Ye, Cy, Ye,.
Line shift to CD14. With this, horizontal CCD
In 14, the addition of signal charges for four lines accompanied by two 1-bit shift additions is performed.
Mg + 2Cy, 2G + 2Ye, 2Mg + 2Cy, 2G +
2Ye, ... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the second field. Thus, in the second field, first,..., 2G + 2Cy, 2Mg + 2Ye, 2G + 2C
y, 2Mg + 2Ye,..., then, 2Mg + 2Cy,
.., 2G + 2Ye, 2Mg + 2Cy, 2G + 2Ye,... Here, (G + C
y), (Mg + Ye) are the color difference signals Cr, (Mg + C)
Since y) and (G + Ye) are the color difference signals Cb, the color difference signals Cr and the color difference signals Cb are output alternately in line units.

The operation of the ＩＳ IS compression according to the second example will be described with reference to the operation explanatory diagram of FIG. 20A shows the case of the first field, and FIG. 20B shows the case of the second field. In the first field (A), the combination of the fourth to seventh lines, the eighth to eleventh lines,..., And in the second field (B), the second to fifth lines, the sixth line ~
Vertical addition is performed using a combination of the ninth line,.

First, in the first field, first,
The signal charges of the first to third lines are discarded, and then the signal charges of the fourth line (..., Cy, Y
e, Cy, Ye,...), and then signal charges (..., Mg, G, Mg, G,.
Are sequentially shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and
The result of addition is ..., Mg + Cy, G + Ye, Mg + C
y, G + Ye,...

After the normal addition of the two lines, a 1-bit shift is performed, and then the signal charges (..., Ye, Cy, Ye, Cy,.
4 and then 1-bit shift, and then the signal charges (..., M
g, G, Mg, G,...) are line-shifted to the horizontal CCD 14. As a result, signal charges for four lines are added in the horizontal CCD 14 together with two 1-bit shift additions, and the addition result is:..., 2Mg + 2Cy, 2G + 2
Ye, 2Mg + 2Cy, 2G + 2Ye,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

In the vertical addition of the signal charges of the four lines from the eighth line to the eleventh line, first, the signal charges (..., Ye, Cy, Y) of the eighth line by vertical two-pixel addition are added.
e, Cy,...) are line-shifted to the horizontal CCD 14 and then shifted by 1 bit.
The line signal charges (..., G, Mg, G, Mg,...) Are line-shifted to the horizontal CCD 14. As a result, two-line one-bit shift addition is performed in the horizontal CCD 14, and the addition result is:..., Mg + Ye, G + Cy, Mg
+ Ye, G + Cy,... After the two-line one-bit shift addition, the signal charges (..., Cy, Ye, Cy, Ye,...) Of the tenth line by the vertical two-pixel addition and the signal charges (...,. G,
Mg, G, Mg,...) Are sequentially line-shifted to the horizontal CCD 14. As a result, signal charges for four lines with one-bit shift addition are added in the horizontal CCD 14, and the addition result is:..., 2Mg + 2Ye, 2G + 2C
y, 2Mg + 2Ye, 2G + 2Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the first field. Accordingly, in the first field, first,..., 2Mg + 2Cy, 2G + 2Ye, 2Mg + 2C
y, 2G + 2Ye,..., then, 2Mg + 2Ye, 2
G + 2Cy, 2Mg + 2Ye, 2G + 2Cy,... Here, (Mg + C
y), (G + Ye) are the color difference signals Cb, (Mg + Ye),
Since (G + Cy) is the color difference signal Cr, the color difference signal Cb and the color difference signal Cr are output alternately in line units.

Next, in the second field (B), first,
The signal charges of the second line (..., C
, Ye, Cy, Ye,...) and signal charges (..., G, Mg, G, M) on the third line by diagonal two-pixel addition.
g,...) are sequentially line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:..., G + Cy, Mg + Ye, G
+ Cy, Mg + Ye,...

After the normal addition of the two lines, a 1-bit shift is performed, and then the signal charges (..., Ye, Cy, Ye, Cy,...) On the fourth line by the vertical 2-pixel addition are shifted by 1 bit. The signal charges (..., G, Mg, G, Mg,...) On the fifth line obtained by the addition of the rear two pixels are sequentially line-shifted to the horizontal CCD 14. Thereby, horizontal CC
In D14, addition of signal charges for four lines accompanied by two 1-bit shift additions is performed.
2G + 2Cy, 2Mg + 2Ye, 2G + 2Cy, 2Mg
+ 2Ye,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

In the vertical addition of the signal charges for the next four lines from the sixth line to the ninth line, first, the signal charges (..., Ye, Cy, Ye,.
Cy,...) Is line-shifted to the horizontal CCD 14 and then shifted by 1 bit, and then the signal charges (..., Mg, G, Mg, G,.
Is shifted to the horizontal CCD 14. As a result, two-line one-bit shift addition is performed in the horizontal CCD 14, and the addition result is:..., G + Ye, Mg + Cy, G +
Ye, Mg + Cy,... After the two-line one-bit shift addition, the signal charges (..., Cy, Ye, Cy, Ye,...) Of the eighth line by the vertical two-pixel addition are successively added to the ninth line signal charges (. , Mg,
G, Mg, G,...) Are sequentially line-shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, addition of signal charges for four lines accompanied by 1-bit shift addition is performed, and the addition result is as follows: 2G + 2Ye, 2Mg + 2C
y, 2G + 2Ye, 2Mg + 2Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the second field. Thus, in the second field, first,..., 2G + 2Cy, 2Mg + 2Ye, 2G + 2C
y, 2Mg + 2Ye,..., 2G + 2Ye, 2
... Mg + 2Cy, 2G + 2Ye, 2Mg + 2Cy,... Here, (G + C
y), (Mg + Ye) are the color difference signals Cr, (G + Ye),
Since (Mg + Cy) is the color difference signal Cb, the color difference signal Cr and the color difference signal Cb are output alternately in line units.

The operation of the ＩＳ IS compression according to the third example will be described with reference to the operation explanatory diagram of FIG. 21A shows the case of the first field, and FIG. 21B shows the case of the second field. In the first field (A), the combination of the second to fifth lines, the sixth to ninth lines,..., And in the second field (B), the fourth to seventh lines, the eighth line ~ 1
Vertical addition is performed by a combination of the first line,.

First, in the first field, first,
The signal charges on the first line are discarded, and then the signal charges on the second line (..., Mg, G, Mg, G,
..) And signal charges (..., Mg, G, Mg, G,...) On the third line by diagonal two-pixel addition.
The line is shifted to 14. Thereby, the horizontal CCD 14
Within two lines, normal addition is performed, and the addition result is
.., 2Mg, 2G, 2Mg, 2G,.

After the normal addition of the two lines, the signal charges (..., Cy, Ye, Cy, Cy,
Ye,...) Is line-shifted to the horizontal CCD 14, followed by 1-bit shift, and then the signal charges (..., Ye, Cy, Ye, Cy,. I do. As a result, addition of signal charges for four lines accompanied by one-bit shift addition is performed in the horizontal CCD 14. The result of the addition is…, 2
Mg + 2Cy, 2G + 2Ye, 2Mg + 2Cy, 2G +
2Ye, ... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

In the vertical addition of the signal charges for the four lines from the sixth line to the ninth line, first, the signal charges (..., Mg, G, Mg,.
G,...) And signal charges (..., Mg, G, Mg, G,.
Line shift to CD14. With this, horizontal CCD
.., 2G, 2Mg, 2G, 2Mg,... After the normal addition of the two lines, a one-bit shift is performed, and then the signal charges (..., Cy, Y) on the eighth line by the vertical two-pixel addition
, Cy, Ye,...), and then the signal charges (.
Ye, Cy, Ye, Cy,...) Are sequentially line-shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, addition of signal charges for four lines accompanied by 1-bit shift addition is performed, and the addition result is,..., 2Mg + 2Ye,
2G + 2Cy, 2Mg + 2Ye, 2G + 2Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the first field. Accordingly, in the first field, first,..., 2Mg + 2Cy, 2G + 2Ye, 2Mg + 2C
y, 2G + 2Ye,..., then, 2Mg + 2Ye, 2
G + 2Cy, 2Mg + 2Ye, 2G + 2Cy,... Here, (Mg + C
y), (G + Ye) are the color difference signals Cb, (Mg + Ye),
Since (G + Cy) is the color difference signal Cr, the color difference signal Cb and the color difference signal Cr are output alternately in line units.

Next, in the second field (B), first,
The signal charges on the first to third lines are discarded, and then the signal charges on the fourth line (..., Ye, C
, Ye, Cy,...) are line-shifted to the horizontal CCD 14, and then subjected to 1-bit shift, and then signal charges (.
e,...) are line-shifted to the horizontal CCD 14. As a result, two-line one-bit shift addition is performed in the horizontal CCD 14, and the addition result is:..., 2Ye, 2Cy, 2
Ye, 2Cy,...

After the two-line one-bit shift addition, the signal charges (..., G, M) on the sixth line by diagonal two-pixel addition
g, G, Mg,...) and 7
The line signal charges (..., G, Mg, G, Mg,...) Are sequentially line-shifted to the horizontal CCD 14. This allows
In the horizontal CCD 14, addition of signal charges for 4 lines accompanied by 1-bit shift addition is performed.
..., 2Mg + 2Ye, 2G + 2Cy, 2Mg + 2Ye,
2G + 2Cy,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

In the vertical addition of the signal charges for the next four lines from the eighth line to the eleventh line, first, the signal charges (..., Cy, Ye, C) on the eighth line by vertical two-pixel addition are obtained.
, Ye,...) are line-shifted to the horizontal CCD 14, then shifted by 1 bit, and then added by vertical two pixels.
The signal charges of the line (..., Ye, Cy, Ye, Cy,
..) Is line-shifted to the horizontal CCD 14. As a result, two-line one-bit shift addition is performed in the horizontal CCD 14, and the addition result is:..., 2Ye, 2Cy, 2Y
e, 2Cy,...

After the two-line one-bit shift addition, a one-bit shift is performed, and then the signal charges (..., Mg, G, Mg, G,. , Mg, G, Mg, G,.
Line shift to Thus, in the horizontal CCD 14, addition of signal charges for four lines accompanied by two 1-bit shift additions is performed, and the addition result is:..., 2Mg + 2
Cy, 2G + 2Ye, 2Mg + 2Cy, 2G + 2Ye,
... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the second field. Thus, in the second field, first,..., 2Mg + 2Ye, 2G + 2Cy, 2Mg + 2Y
e, 2G + 2Cy, ..., then ..., 2Mg + 2Cy, 2
G + 2Ye, 2Mg + 2Cy, 2G + 2Ye,... Here, (Mg
+ Ye) and (G + Cy) are the color difference signals Cr, (Mg + C)
Since y) and (G + Ye) are the color difference signals Cb, the color difference signals Cr and the color difference signals Cb are output alternately in line units.

The operation of 1 / 4IS compression according to the fourth example will be described with reference to the operation explanatory diagram of FIG. In FIG. 22, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the third line to the sixth line, the seventh line to the tenth line,..., And in the second field (B), the first line to the fourth line, the fifth line ~
Vertical addition is performed by a combination of the eighth line,.

First, in the first field, first,
The signal charges on the first and second lines are discarded, and then the signal charges on the third line (..., Mg,
G, Mg, G,...) Are line-shifted to the horizontal CCD 14, followed by 1-bit shift, and then signal charges (..., Cy, Ye, Cy, Y) on the fourth line by adding two pixels vertically.
e,...) are line-shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, two-line normal addition with 1-bit shift addition is performed, and the addition result is:
g + Ye, G + Cy, Mg + Ye, G + Cy,...

After this 2-line 1-bit shift normal addition,
Perform 1-bit shift, and then add 5 pixels by vertical 2-pixel addition.
The signal charges of the line (..., Ye, Cy, Ye, Cy,
..) And signal charges (..., Mg, G, Mg, G,...) On the sixth line by diagonal two-pixel addition.
The line is shifted to 14. Thereby, the horizontal CCD 14
, The addition of the signal charges for four lines accompanied by two 1-bit shift additions is performed, and the addition result is:
+ 2Ye, 2G + 2Cy, 2Mg + 2Ye, 2G + 2C
y, ... These signal charges are sequentially transferred horizontally,
The signal is converted into a signal voltage and output to a subsequent signal processing system.

In the vertical addition of the signal charges for the next four lines from the seventh line to the tenth line, first, the signal charges (..., Mg, G, Mg,.
G,...) And then the signal charges (..., Cy, Ye, Cy, Ye,...) Of the eighth line by vertical two-pixel addition are sequentially line-shifted to the horizontal CCD 14. Thereby, horizontal C
In the CD 14, two-line normal addition is performed, and the addition result is as follows: Mg + Cy, G + Ye, Mg + Cy, G + Y
e, ... After the normal addition of the two lines, a 1-bit shift is performed, and then the signal charges (..., Ye, Cy, Ye, Cy,.
After performing the bit shift, the signal charges (..., Mg, G, Mg, G,...) On the tenth line obtained by the diagonal two-pixel addition are sequentially line-shifted to the horizontal CCD 14. As a result, addition of signal charges for four lines accompanied by one-bit shift addition is performed in the horizontal CCD 14. The result of the addition is…, 2
Mg + 2Cy, 2G + 2Ye, 2Mg + 2Cy, 2G +
2Ye, ... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the first field. Thereby, in the first field, first,..., 2Mg + 2Ye, 2G + 2Cy, 2Mg + 2Y
e, 2G + 2Cy, ..., then ..., 2Mg + 2Cy, 2
G + 2Ye, 2Mg + 2Cy, 2G + 2Ye,... Here, (Mg + Y
e), (G + Cy) are the color difference signals Cr, (Mg + Cy),
Since (G + Ye) is the color difference signal Cb, the color difference signal Cr and the color difference signal Cb are output alternately in line units.

Next, in the second field (B), first,
The signal charges of the first line (..., C
, Y, Ye, Cy, Ye,...) are line-shifted to the horizontal CCD 14, followed by 1-bit shift, and then signal charges (..., G, Mg, G,.
..) Is line-shifted to the horizontal CCD 14. As a result, two-line one-bit shift addition is performed in the horizontal CCD 14, and the addition result is:..., Mg + Cy, G + Y
e, Mg + Cy, G + Ye,.

After the two-line one-bit shift addition, the signal charges (..., G, M) on the third line by diagonal two-pixel addition
g, G, Mg,...)
The signal charges of the line (..., Ye, Cy, Ye, Cy,
..) Are sequentially shifted to the horizontal CCD 14. As a result, in the horizontal CCD 14, addition of signal charges for four lines accompanied by 1-bit shift addition is performed, and the addition result is:..., 2Mg + 2Cy, 2G + 2Ye, 2Mg + 2C
y, 2G + 2Ye,... These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

In the vertical addition of the signal charges for the four lines from the fifth line to the eighth line, first, the signal charges (..., Cy, Ye, Cy, Cy,
Ye,...) And then the signal charges (..., G, Mg, G, Mg,.
Line shift to D14. Thereby, the horizontal CCD 1
In 4, the normal addition of two lines is performed, and the addition result is
..., G + Cy, Mg + Ye, G + Cy, Mg + Ye, ...
Becomes After the normal addition of the two lines, the signal charges (..., G, Mg, G, Mg,
..) Are line-shifted to the horizontal CCD 14, followed by 1-bit shift, and then the signal charges (..., Ye, Cy, Ye, Cy,.
Line shift to CD14. With this, horizontal CCD
In 14, addition of signal charges for four lines accompanied by 1-bit shift addition is performed, and the addition result is as follows: 2G + 2
Cy, 2Mg + 2Ye, 2G + 2Cy, 2Mg + 2Y
e, ... These signal charges are sequentially transferred horizontally,
The signal is converted into a signal voltage and output to a subsequent signal processing system.

Thereafter, a similar operation is repeated in the second field. Thus, in the second field, first,..., 2Mg + 2Cy, 2G + 2Ye, 2Mg + 2C
y, 2G + 2Ye, ..., then ..., 2G + 2Cy, 2M
g + 2Ye, 2G + 2Cy, 2Mg + 2Ye,... Here, (Mg + C
y), (G + Ye) are the color difference signals Cb, (G + Cy),
Since (Mg + Ye) is the color difference signal Cr, the color difference signal Cr and the color difference signal Cb are output alternately in line units.

The channel stop unit 23 described so far
In the first two examples of FIGS. 5 and 16, in both the first example of FIG. 5 and the second example of FIG. 16, the complementary color coding after the vertical two-pixel addition and the diagonal two-pixel addition is performed by repeating horizontal 2 × vertical 8 (see FIGS. 17), but by further changing the pattern of the channel stop section 23, as shown in FIG. 23, it is possible to perform complementary color coding in which horizontal 2 × vertical 16 are repeated.

In FIG. 23, (A) shows the first field, and (B) shows the second field, respectively, and the first field (A) and the second field (B) are used for two-pixel addition. Is changing the combination. This horizontal 2x
In the case of complementary color coding in which vertical 16 repetitions are performed, two-line normal addition and two-line 1
By the combination of bit shift addition, it is possible to perform 1 / 2IS or 1 / 4IS compression by vertical addition compression. Here, the case of 1/4 IS compression will be described as an example.

Specifically, assuming that the color coding shown in FIG. 23A is used, as shown in FIG. 24 (first example) and FIG. 25 (second example), the first field (A)
, Mg + C in both the first and second fields (B)
y, G + Ye, Mg + Cy, G + Ye,.
G + Cy, Mg + Ye, G + Cy, Mg + Ye,..., And thereafter, this is repeated, and (Mg + Cy), (G + Y
Since e) is the color difference signal Cb and (G + Cy), (Mg + Ye) is the color difference signal Cr, the color difference signal Cr and the color difference signal Cb are output alternately in line units.

As described above, two horizontal repetitions and two vertical
Vertical CC for repeated primary color coatings
By performing vertical two-pixel addition and diagonal two-pixel addition in D12 and performing four-line addition with one-bit shift in the horizontal CCD 14, １ ／ IS compression can be realized, and the color difference signals Cr (Ye + Mg, Cy + G) And color difference signals Cb (Ye + G, Cy + Mg) can be output alternately in line units (color difference line sequential output). Moreover, by changing the combination of two pixels (two rows) for performing vertical two-pixel addition and diagonal two-pixel addition in the first field and the second field, an interlace operation can be realized.

In the above, the operation example in the case where the primary color filter is used as the color filter 19 has been described. However, the present invention is not limited to the application to the primary color filter, but can be similarly applied to the complementary color filter. Hereinafter, an operation example when a complementary color filter is used as the color filter 19 will be described.

FIG. 26 shows an example of color coding of a complementary color filter. The complementary color filter according to this example is shown in FIG.
As is clear from FIG. 5, odd rows are Mg / G, and even rows are Cy.
/ Ye complementary color 2 × 2 array color coding. It should be noted that the complementary color filter is not limited to the color coding shown in FIG. 26, but may be a color coding in which Cy and Ye, Mg and G are interchanged,
Color coding in which odd and even lines are interchanged may be used.

In the complementary color filter of the color coding of the complementary color 2 × 2 array shown in FIG.
Assuming that vertical two-pixel addition and diagonal two-pixel addition are performed in the vertical CCD 12 based on the pattern example shown in FIG. 5 as in the case of the primary color filter, the addition result is as shown in FIG. , The color difference signal Cb (Ye + G, Cy + M
g) and Cr (Ye + Mg, Cy + G) are obtained in a color difference line sequence obtained alternately in line units. In FIG.
(A) shows the case of the first field, and (B) shows the case of the second field.

Specifically, in the first field (A),
An oblique two-pixel addition (DI) is performed between each of the first and second rows, the fifth and sixth rows,..., And the third and fourth rows, the seventh and eighth rows,. , Vertical two-pixel addition (VI) is performed between the two lines, and the result of the addition is that the odd lines are Mg + Ye, G +
Cy, Mg + Ye, G + Cy,.
Cy, G + Ye, Mg + Cy, G + Ye,... However, in the case of the second field (B), vertical two-pixel addition is performed between each of the second and third rows, the fourth and fifth rows,..., And the sixth and seventh rows are added. , The eighth row and the ninth row, and the diagonal two-pixel addition is performed between the two rows, so that the color difference signal C
b (Ye + G, Cy + Mg), Cr (Ye + Mg, Cy
+ G) is obtained alternately every two lines.

As described above, in the complementary color filter of the color coding of the complementary color 2 × 2 array, the color difference line-sequential addition results obtained by the vertical two-pixel addition and the diagonal two-pixel addition are sequentially output in line units during the horizontal blanking period. The vertical transfer to the horizontal CCD 14 and the horizontal transfer in order during the horizontal effective period can realize ＰＳPS compression in which the added signal charges in the vertical CCD 12 are read independently.

In the subsequent signal processing system, (Mg +
Ye), (G + Cy), (Mg + Cy), (G + Ye)
The luminance signal Y and the color difference signals Cb and Cr are calculated from the following equations from the four types of signal outputs of the two lines.

Y = (Mg + Ye) + (G + Cy) = (Mg + Cy) + (G + Ye) Cb = (Mg + Cy) − (G + Ye) Cr = (Mg + Ye) − (G + Cy) Also, the centers of the color difference signals Cb and Cr are aligned. The primary color separation is calculated based on the following equation.

R = Cr + 0.129 * Y G = Y- (Cr-Cb) B = Cb + 0.22 * (Y-Cr) Next, the operation of 1/2 IS compression will be described. In this 1/2 IS compression, the addition result of FIG. 27A is used, and 2 bits are used in the first field and the second field.
The combination of lines to be line-shifted is changed.

The 1 / 2IS compression will be described with reference to the operation explanatory diagram of FIG. In FIG. 28, (A) shows the case of the first field, (B) shows the case of the second field, and in the first field (A), the first and second lines (a1), (3) In the second field (B), the second line and the third line (b1) and the fourth line and the fifth line
A two-line shift is performed by a combination of the lines (b2),.

In the first field (A), signal charges (..., Mg + Ye,
G + Cy, Mg + Ye, G + Cy,...), And then signal charges (.
e, Mg + Cy, G + Ye, Mg + Cy,...) are sequentially line-shifted to the horizontal CCD 14. Thereby, horizontal C
In the CD 14, two-line normal addition is performed, and the addition result is: 2Ye + Mg + G, 2Cy + Mg + G, 2Y
e + Mg + G, 2Cy + Mg + G,...
MG, 2CMG, 2YMG, 2CMG, ...)
Becomes These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Subsequently, the signal charges on the third line (..., G + Cy, Mg + Ye, G + Cy, M
g + Ye,...), and then signal charges (..., G + Ye, Mg + Cy, G + Y) on the fourth line by adding two vertical pixels.
e, Mg + Cy,...) are sequentially line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the result of the addition is..., 2G + Cy +
Ye, 2Mg + Cy + Ye, 2G + Cy + Ye, 2Mg
+ Cy + Ye, ... (in the figure, ..., 2GCY, 2MCY, 2
GCY, 2MCY,...). These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the first field. Thereby, in the first field, first,..., 2Ye + Mg + G, 2Cy + Mg + G, 2Ye
+ Mg + G, 2Cy + Mg + G, ..., then ..., 2G +
Cy + Ye, 2Mg + Cy + Ye, 2G + Cy + Ye,
2Mg + Cy + Ye,..., And thereafter, a signal is repeatedly output.

Next, in the second field (B), first, the signal charges on the first line are discarded, and then the signal charges on the second line (..., Mg + Cy, G
+ Ye, Mg + Cy, G + Ye,...)
The signal charge of the third line by pixel addition (..., Mg + Y
e, G + Cy, Mg + Ye, G + Cy,...) are sequentially shifted to the horizontal CCD 14. Thereby, horizontal CC
In D14, two-line normal addition is performed, and the addition result is:..., 2Mg + Cy + Ye, 2G + Cy + Ye, 2M
g + Cy + Ye, 2G + Cy + Ye,...
MCY, 2GCY, 2MCY, 2GCY,...). These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Subsequently, the signal charges on the fourth line (..., G + Ye, Mg + Cy, G + Ye, M
g + Cy,...), and then signal charges (..., G + Cy, Mg + Ye, G + C) on the fifth line by diagonal two-pixel addition.
, Mg + Ye,...) are sequentially line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is:..., 2Ye + Mg
+ G, 2Cy + Mg + G, 2Ye + Mg + G, 2Cy +
Mg + G, ... (in the figure, ..., 2YMG, 2CMG, 2YM
G, 2CMG,...). These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the second field. Thus, in the second field, first,..., 2Mg + Cy + Ye, 2G + Cy + Ye, 2M
g + Cy + Ye, 2G + Cy + Ye,.
Ye + Mg + G, 2Cy + Mg + G, 2Ye + Mg +
G, 2Cy + Mg + G,..., And thereafter, a signal is output by repetition.

In the subsequent signal processing system, (2Mg
+ Cy + Ye), (2G + Cy + Ye), (2Ye + M
g + G) and (2Cy + Mg + G), the luminance signal Y and the color difference signals Cb and Cr are calculated from the following equations from four types of signal outputs of two lines.

2Y = (2Mg + Cy + Ye) + (2G + Cy + Ye) = (2Ye + Mg + G) + (2Cy + Mg + G) 2Cb = (2Cy + Mg + G) − (2Ye + Mg + G) + (2Mg + Cy + Ye) − (2G + CyEg) + (Mg + Cg + Cg) − (2G + Cy + Ye) + (2Ye + Mg + G) − (2Cy + Mg + G) = (Mg + Ye) − (Cy + G) Next, four examples of the ４IS compression in the first to fourth examples will be described. The operations of the first to fourth examples are basically the same as the operations of the first to fourth examples in the pattern example shown in FIG. 5 when the primary color filter is used. Detailed description of the operation is omitted here.

First, in the ＩＳ IS compression according to the first example,
The addition result of the vertical two-pixel addition and the oblique two-pixel addition shown in FIG. 27A is used, and the vertical addition is performed in units of four lines. Then, the combination of four lines is changed between the first field and the second field. The operation of the 1/4 IS compression according to the first example will be described with reference to the operation explanatory diagram of FIG.

29A shows the case of the first field, and FIG. 29B shows the case of the second field. In the first field (A), the combination of the third line to the sixth line, the seventh line to the tenth line,...
The vertical addition is performed by a combination of the fourth line, the fifth line to the eighth line, and so on.

Then, as in the case of FIG. 11, in the first field (A), after the signal charges of the first and second lines are discarded, normal addition of two lines is performed in the first four lines, and then, Two-line one-bit shift addition is performed twice, and in the next four lines, two-line one-bit shift addition is performed, then two-line normal addition is performed twice, and thereafter, the same operation is repeated. By this, first, 4G + 2C
y + 2Ye, 4Mg + 2Cy + 2Ye, 4G + 2Cy +
2Ye, 4Mg + 2Cy + 2Ye, ..., then ..., 4C
y + 2Mg + 2G, 4Ye + 2Mg + 2G, 4Cy + 2
.., Mg + 2G, 4Ye + 2Mg + 2G,...

On the other hand, in the second field (B),
From the first line, in the first four lines, two lines are normally added, two-line one-bit shift addition is performed twice, and the next four lines are added.
On the line, two-line one-bit shift addition is performed, and then two-line normal addition is performed twice, and thereafter, the same operation is repeated. Thus, first,..., 4C + 2M + 2G, 4
Y + 2M + 2G, 4C + 2M + 2G, 4Y + 2M + 2
G, ..., then ..., 4G + 2Cy + 2Ye, 4Mg + 2
Cy + 2Ye, 4G + 2Cy + 2Ye, 4Mg + 2Cy
+ 2Ye,..., And thereafter, a signal is output by repetition.

In FIG. 29, 4G + 2Cy + 2Ye is converted to 2G
CY, 4Mg + 2Cy + 2Ye is converted to 2MCY, 4Cy + 2
2CMG for Mg + 2G, 2YM for 4Ye + 2Mg + 2G
G is abbreviated (hereinafter the same in each drawing). This is the same as the addition result in the case of 1/2 IS compression. Therefore, from these signal outputs, 1 / 2IS
The luminance signal Y and the color difference signals Cb and Cr can be obtained based on the expression shown in the compression.

Even in the 1 / 4IS compression according to the second example, FIG.
It is assumed that the addition results of the vertical two-pixel addition and the diagonal two-pixel addition shown in FIG. Then, the combination of four lines is changed between the first field and the second field. This second
The operation of 1 / 4IS compression according to the example will be described with reference to the operation explanatory diagram of FIG.

In FIG. 30, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the second to fifth lines, the sixth to ninth lines,..., And in the second field (B), the fourth to seventh lines
The vertical addition is performed with a combination of the line, the eighth line to the eleventh line, and so on.

Then, as in the case of FIG. 13, in the first field (A), after the signal charge of the first line is discarded, two lines of normal addition are performed twice in the first four lines, and then two lines are added. 1-bit shift addition is performed, and the next 4
In the line, two-line 1-bit shift addition is performed twice,
Next, two-line normal addition is performed, and thereafter, the same operation is repeated. With this, first, 2GCY, 2MCY,
2GCY, 2MCY, ..., followed by ..., 2CMG, 2YM
G, 2CMG, 2YMG,..., And thereafter, a signal is output by repetition.

On the other hand, in the second field (B),
After discarding the signal charges of the first to third lines, in the first four lines, two-line one-bit shift addition is performed twice, then two-line normal addition is performed, and in the next four lines, two-line normal addition is performed. Is performed twice, then two-line one-bit shift addition is performed, and thereafter, the same operation is repeated.
Thereby, first,..., 2GCY, 2MCY, 2GC
Y, 2MCY, ..., then ..., 2CMG, 2YMG, 2
CMG, 2YMG,..., And thereafter, a signal is output by repetition.

In the 例 IS compression according to the third example, FIG.
Assume that the addition results of the vertical two-pixel addition and the diagonal two-pixel addition shown in (B) are used, and the vertical addition is performed in units of four lines. Then, the combination of four lines is changed between the first field and the second field. This third
The operation of １ ／ IS compression according to the example will be described with reference to the operation explanatory diagram of FIG.

In FIG. 31, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the third line to the sixth line, the seventh line to the tenth line,...
The vertical addition is performed by a combination of the fourth line, the fifth line to the eighth line, and so on.

Then, as in the case of FIG. 14, in the first field (A), after discarding the signal charges of the first and second lines, two-line one-bit shift addition is performed for the first four lines. Is performed twice, then normal addition is performed for two lines, and in the next four lines, one-bit shift addition is performed for two lines, then normal addition is performed twice for two lines, and thereafter, the same operation is repeated. By this, first, 2GCY,
2MCY, 2GCY, 2MCY, ..., then ..., 2CM
G, 2YMG, 2CMG, 2YMG,...

On the other hand, in the second field (B),
From the first line, in the first four lines, two-line normal addition is performed twice, then two-line one-bit shift addition is performed, and in the next four lines, two-line normal addition is performed, and then two-line one-bit shift addition is performed. Is performed twice, and the same operation is repeated thereafter. As a result, first, 2MCY,
2GCY, 2MCY, 2GCY, ..., then ..., 2CM
G, 2YMG, 2CMG, 2YMG,...

Even in the 1 / 4IS compression according to the fourth example, FIG.
Assume that the addition results of the vertical two-pixel addition and the diagonal two-pixel addition shown in (B) are used, and the vertical addition is performed in units of four lines. Then, the combination of four lines is changed between the first field and the second field. This fourth
The operation of １ ／ IS compression according to the example will be described with reference to the operation explanatory diagram of FIG.

In FIG. 32, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the second to fifth lines, the sixth to ninth lines,..., And in the second field (B), the fourth to seventh lines
The vertical addition is performed with a combination of the line, the eighth line to the eleventh line, and so on.

Then, as in the case of FIG. 15, in the first field (A), after the signal charge of the first line is discarded, normal addition is performed for two lines in the first four lines, and then one bit is added for two lines. Shift addition is performed twice, and in the next four lines, two-line one-bit shift addition is performed twice, then normal addition is performed for two lines, and thereafter, the same operation is repeated. Thereby, first,..., 2GCY, 2MCY, 2
GCY, 2MCY, ..., then ..., 2YMG, 2CM
G, 2YMG, 2CMG,..., And thereafter, a signal is output by repetition.

On the other hand, in the second field (B),
After discarding the signal charges of the first to third lines, 1-bit addition is performed in the first 4 lines, then normal addition is performed twice in the next 4 lines, and normal addition is performed twice in the next 4 lines. Then, two-line one-bit shift addition is performed, and thereafter, the same operation is repeated. Thus, first,..., 2GCY, 2MCY, 2GCY, 2MCY,..., And then,..., 2CMG, 2YMG, 2CMG, 2YMG,
, And thereafter, a signal is output by repetition.

Next, the vertical compression operation when the pattern example shown in FIG. 16 is used as the pattern example of the channel stop unit 23 will be described.

In the complementary color filter of the color coding of the complementary color 2 × 2 arrangement shown in FIG. 26, as in the case of the primary color filter, two vertical pixels are added and two
Assuming that pixel addition is performed, the result of the addition is shown in FIG.
, The color difference signal Cr (Mg + Ye, G + C
y) and Cb (Mg + Cy, G + Ye) are color difference line sequential obtained alternately in line units. In FIG.
(A) shows the case of the first field, and (B) shows the case of the second field.

More specifically, in the first field (A),
An oblique two-pixel addition (DI) is performed between each of the first and second rows, the fifth and sixth rows,..., And the third and fourth rows, the seventh and eighth rows,. , Vertical two-pixel addition (VI) is performed between the two lines, and the result of the addition is that the odd lines are Mg + Ye, G +
Cy, Mg + Ye, G + Cy,.
Cy, G + Ye, Mg + Cy, G + Ye,... However, in the case of the second field (B), vertical two-pixel addition is performed between each of the second and third rows, the eighth and ninth rows, and the fourth and fifth rows. , The sixth row and the seventh row, and the diagonal two-pixel addition is performed between the two rows, so that the color difference signal C
b (Ye + G, Cy + Mg), Cr (Ye + Mg, Cy
+ G) is obtained alternately every two lines.

Using the result of color-difference line-sequential addition obtained by the above-described vertical two-pixel addition and diagonal two-pixel addition,
First, the operation of 1/2 IS compression will be described. This one
In the / 2IS compression, the addition result shown in FIG. 33A is used, and the combination of lines on which the first field and the second field are shifted by two lines is changed.

The 1/2 IS compression will be described with reference to the operation explanatory diagram of FIG. 34, (A) shows the case of the first field, (B) shows the case of the second field, and in the first field (A), the first and second lines (a1), (3) In the second field (B), the second line and the third line (b1) and the fourth line and the fifth line
A two-line shift is performed by a combination of the lines (b2),.

In the first field (A), signal charges (..., Mg + Ye,
G + Cy, Mg + Ye, G + Cy,...), And then signal charges (.
e, Mg + Cy, G + Ye, Mg + Cy,...) are sequentially line-shifted to the horizontal CCD 14. Thereby, horizontal C
In the CD 14, two-line normal addition is performed, and the addition result is: 2Ye + Mg + G, 2Cy + Mg + G, 2Y
e + Mg + G, 2Cy + Mg + G,...
MG, 2CMG, 2YMG, 2CMG, ...)
Becomes These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Subsequently, the signal charges on the third line (..., G + Cy, Mg + Ye, G + Cy, M
g + Ye,...), and then signal charges (..., G + Ye, Mg + Cy, G + Y) on the fourth line by adding two vertical pixels.
e, Mg + Cy,...) are sequentially line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the result of the addition is..., 2G + Cy +
Ye, 2Mg + Cy + Ye, 2G + Cy + Ye, 2Mg
+ Cy + Ye, ... (in the figure, ..., 2GCY, 2MCY, 2
GCY, 2MCY,...). These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the first field. Thereby, in the first field, first,..., 2Ye + Mg + G, 2Cy + Mg + G, 2Ye
+ Mg + G, 2Cy + Mg + G, ..., then ..., 2G +
Cy + Ye, 2Mg + Cy + Ye, 2G + Cy + Ye,
2Mg + Cy + Ye,..., And thereafter, a signal is repeatedly output.

Next, in the second field (B), first, the signal charges on the first line are discarded, and then the signal charges on the second line (..., Mg + Cy, G
+ Ye, Mg + Cy, G + Ye,...)
The signal charges (..., G + Cy,
Mg + Ye, G + Cy, Mg + Ye,.
Line shift to CD14. With this, horizontal CCD
In 14, two-line normal addition is performed, and the addition result is as follows: 2Cy + Mg + G, 2Ye + Mg + G, 2Cy
+ Mg + G, 2Ye + Mg + G, ... (in the figure, ..., 2CM
G, 2YMG, 2CMG, 2YMG,...). These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Subsequently, signal charges (..., Mg + Cy, G + Ye, Mg + Cy,
G + Ye,...), And then signal charges (..., Mg + Ye, G + Cy, Mg + Y) on the fifth line by adding two pixels at an angle.
e, G + Cy,...) are sequentially line-shifted to the horizontal CCD 14. As a result, two-line normal addition is performed in the horizontal CCD 14, and the addition result is..., 2Mg + Cy +
Ye, 2G + Cy + Ye, 2Mg + Cy + Ye, 2G +
Cy + Ye, ... (in the figure, ..., 2MCY, 2GCY, 2M
CY, 2GCY,...). These signal charges are sequentially transferred horizontally, converted into a signal voltage, and output to a subsequent signal processing system.

Thereafter, the same operation is repeated in the second field. Thus, in the second field, first,..., 2Cy + Mg + G, 2Ye + Mg + G, 2Cy
+ Mg + G, 2Ye + Mg + G, ..., then ..., 2Mg
+ Cy + Ye, 2G + Cy + Ye, 2Mg + Cy + Y
e, 2G + Cy + Ye,..., and thereafter, a signal is output by repetition.

Next, operations of four examples of the first to fourth examples of 1 / 4IS compression will be described. The operations of the first to fourth examples correspond to the first operation when the primary color filter is used.
Since the operations are basically the same as those of the examples to the fourth example, detailed description of the operations is omitted here.

First, in the 1/4 IS compression according to the first example,
The addition result of the vertical two-pixel addition and the diagonal two-pixel addition shown in FIG. 33A is used, and the vertical addition is performed in units of four lines. Then, the combination of four lines is changed between the first field and the second field. The operation of the 1/4 IS compression according to the first example will be described with reference to the operation explanatory diagram of FIG.

In FIG. 35, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the third line to the sixth line, the seventh line to the tenth line,...
The vertical addition is performed by a combination of the fourth line, the fifth line to the eighth line, and so on.

Then, as in the case of FIG. 19, in the first field (A), after the signal charges of the first line and the second line are discarded, the normal addition of the two lines is performed twice in the first four lines. Then, two-line one-bit shift addition is performed, and in the next four lines, two-line one-bit shift addition is performed twice, then two-line normal addition is performed, and thereafter, the same operation is repeated. By this, first, 2GCY,
2MCY, 2GCY, 2MCY, ..., then ..., 2CM
G, 2YMG, 2CMG, 2YMG,...

On the other hand, in the second field (B),
From the first line, in the first four lines, two-line normal addition is performed twice, then two-line one-bit shift addition is performed, and in the next four lines, two-line one-bit shift addition is performed twice, and then two lines are performed. Normal addition is performed, and thereafter, the same operation is repeated. With this, first, 2 CMG,
2YMG, 2CMG, 2YMG, ..., then ..., 2MC
Y, 2GCY, 2MCY, 2GCY,..., And thereafter, a signal is output by repetition.

Even in the 1/4 IS compression according to the second example, FIG.
Assume that the addition results of the vertical two-pixel addition and the diagonal two-pixel addition shown in FIG. 7A are used, and the vertical addition is performed in units of four lines. Then, the combination of four lines is changed between the first field and the second field. This second
The operation of the ＩＳ IS compression according to the example will be described with reference to the operation explanatory diagram of FIG.

In FIG. 36, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the fourth to seventh lines, the eighth to eleventh lines,..., And in the second field (B), the second to
The vertical addition is performed by a combination of the fifth line, the sixth line to the ninth line, and so on.

Then, as in the case of FIG. 20, in the first field (A), after discarding the signal charges of the first to third lines, normal addition is performed for two lines in the first four lines, and then, Two-line one-bit shift addition is performed twice, and in the next four lines, two-line one-bit shift addition is performed, then two-line normal addition is performed twice, and thereafter, the same operation is repeated. As a result, first, 2MCY,
2GCY, 2MCY, 2GCY, ..., then ..., 2YM
G, 2CMG, 2YMG, 2CMG,...

On the other hand, in the second field (B),
First, the signal charge of the first line is discarded, and then, in the first four lines, normal addition of two lines is performed.
Bit shift addition is performed twice, and in the next four lines, 1-bit shift addition is performed for two lines, then normal addition is performed twice for two lines, and thereafter, the same operation is repeated. Thereby, first, 2CMG, 2YMG, 2CMG, 2YM
G, ..., then ..., 2GCY, 2MCY, 2GCY, 2
MCY,..., And thereafter, a signal is output by repetition.

In the ４ IS compression according to the third example, FIG.
Assume that the addition results of the vertical two-pixel addition and the diagonal two-pixel addition shown in (B) are used, and the vertical addition is performed in units of four lines. Then, the combination of four lines is changed between the first field and the second field. This third
The operation of 1 / 4IS compression according to the example will be described with reference to the operation explanatory diagram of FIG.

In FIG. 37, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the second to fifth lines, the sixth to ninth lines,..., And in the second field (B), the fourth to seventh lines
The vertical addition is performed with a combination of the line, the eighth line to the eleventh line, and so on.

Then, as in the case of FIG. 21, in the first field (A), after the signal charge of the first line is discarded, two lines of normal addition are performed twice in the first four lines, and then two lines are added. 1-bit shift addition is performed, and the next 4
In the line, two-line one-bit shift addition is performed twice after two-line normal addition, and thereafter, the same operation is repeated. As a result, first, 2MCY, 2GCY, 2MCY,
2GCY, ..., then ..., 2YMG, 2CMG, 2YM
G, 2CMG,..., And thereafter, a signal is output by repetition.

On the other hand, in the second field (B),
The signal charges of the first to third lines are discarded, two-line one-bit shift addition is performed on the first four lines, then two-line normal addition is performed twice, and two-line one-bit shift addition is performed on the next four lines. Is performed twice, then normal addition is performed for two lines, and thereafter, the same operation is repeated. Thus, first,..., 2YMG, 2CMG, 2YMG, 2CM
G, ..., then ..., 2MCY, 2GCY, 2MCY, 2
GCY,..., And thereafter, a signal is output by repetition.

Even in the 1 / 4IS compression according to the fourth example, FIG.
Assume that the addition results of the vertical two-pixel addition and the diagonal two-pixel addition shown in (B) are used, and the vertical addition is performed in units of four lines. Then, the combination of four lines is changed between the first field and the second field. This fourth
The operation of the ＩＳ IS compression according to the example will be described with reference to the operation explanatory diagram of FIG.

In FIG. 38, (A) shows the case of the first field, and (B) shows the case of the second field. In the first field (A), the combination of the third line to the sixth line, the seventh line to the tenth line,...
The vertical addition is performed by a combination of the fourth line, the fifth line to the eighth line, and so on.

Then, as in the case of FIG. 22, in the first field (A), after the signal charges of the first and second lines are discarded, two-line one-bit shift addition is performed for the first four lines. Is performed twice, then normal addition is performed for two lines, then normal addition is performed for two lines in the next four lines, and one-bit shift addition is performed twice for two lines, and thereafter, the same operation is repeated. As a result, first, 2YMG,
2CMG, 2YMG, 2CMG, ..., then ..., 2MC
Y, 2GCY, 2MCY, 2GCY,..., And thereafter, a signal is output by repetition.

On the other hand, in the second field (B),
From the first line, 1-bit addition is performed in the first 4 lines, then 2 lines normal addition is performed twice, and in the next 4 lines, 2 lines normal addition is performed twice, and then 2 lines 1-bit shift addition is performed. The same operation is repeated thereafter. Thereby, first,..., 2MCY, 2GCY, 2M
CY, 2GCY, ..., then ..., 2CMG, 2YMG,
2CMG, 2YMG,..., And thereafter, a signal is output by repetition.

As described above, in the description of the operation of the two examples of the pattern of the channel stop unit 23, the complementary color coding after the addition of two vertical pixels and the addition of two oblique pixels is repeated 2 × 8 vertically (see FIGS. 27 and 33). ), By further changing the pattern of the channel stop unit 23, as shown in FIG.
Complementary color coding of 16 vertical repetitions is also possible.

In FIG. 39, (A) shows the first field, and (B) shows the second field, respectively, where the first field (A) and the second field (B) are used to perform two-pixel addition. Is changing the combination. This horizontal 2x
In the case of complementary color coding in which vertical 16 repetitions are performed, two-line normal addition and two-line 1
By combining bit shift addition, it is possible to perform 1 / 2IS or 1 / 4IS compression by vertical addition compression. Here, the case of 1/4 IS will be described as an example.

Specifically, assuming that the color coding shown in FIG. 39A is used, as shown in FIG. 40 (first example) and FIG. 41 (second example), the first field (A)
, 2MC in both the first and second fields (B)
Y ,, 2GCY, 2MCY, 2GCY, ..., then ...
2CMG, 2YMG, 2CMG, 2YMG, ...,
It becomes the repetition.

Here, the operation of the primary color separation performed in the subsequent signal processing system will be described again. First, an arithmetic expression capable of completely separating R / G / B is, as described above, B = (MgCy−GYe + 2G) / 2 G = ｛3 (GCy + GYe) − (MgCy + MgY
e)｝ R = (Mg−GCy + 2G) / 2 FIG. 42A shows the spectral characteristics.

In the primary color separation operation formula, as the number of color components increases, the operation is performed using a wider range of signals, and the resolution is reduced. Therefore, when increasing the resolution, it is desirable to use as few color components as possible for calculation. From such a viewpoint, examples of various arithmetic expressions will be described below. In the following arithmetic expressions, Mg is abbreviated to M, Cy to C, and Ye to Y.

First, in the first example, B = (MC−GY / 2) / 2 G = {3 (GC + GY) − (MC + MY)} / 16 R = (MY−GC / 2) / 2 FIG. 42B shows the spectral characteristics. This first
In the arithmetic expression of the example, since 2G is not included in the arithmetic expressions of B and R, the resolution can be increased. However, FIG.
As is clear from the spectral characteristics of (B), the spectral curves of B and R become negative around 550 [nm], and the color reproduction is slightly increased because B swells on the long wavelength side and R swells on the short wavelength side. Sacrificed.

In the second example, B = (MC-GY / 2) / 2- (MY-GC / 2) / 8 G = (GY-1.075 * R) * 0.3 = (GC-1. 075 * B) * 0.3 R = (MY−GC / 2) / 2− (MC−GY / 2) / 8, and the spectral characteristics are shown in FIG. 42 (C). This second
In the example of the operation formula, since the undulation component of R, that is, (MY-GC / 2) / 8 is excluded for B, and the undulation component of B, that is, (MC-GY / 2) / 8 is excluded for R. In addition to being able to increase the resolution, the color reproduction can be increased. That is, the spectral characteristics and the resolution are balanced. The arithmetic expressions of B and R are common to the following third to fifth examples.

On the other hand, as for G, G is calculated from the line (GY) of the color difference signal Cb, and the line (G
G is calculated from C). That is, by independently forming G from each line of the color difference signals Cb and Cr, the resolution of G can be increased. Thus, C
Independently forming G from each line of b and Cr is common to the following third to fifth examples.

In the third example, B = (MC-GY / 2) / 2- (MY-GC / 2) / 8 G = (GY-0.1 * MC-1.175 * R) * 0.3 = (GC-0.1 * MY-1.075 * B) * 0.3 R = (MY-GC / 2) / 2- (MC-GY / 2) / 8 The spectral characteristics are shown in FIG. It is shown in (D). This third
According to the arithmetic expression in the example, the long wavelength side of the G spectral curve can be made closer to 0.

In the fourth example, B = (MC−GY / 2) / 2− (MY−GC / 2) / 8 G = MC + GY− (R + B) * 2) / 5 = ／ GC + MY− (R + B) * 2) / 5 R = (MY−GC / 2) / 2− (MC−GY / 2) / 8, and the spectral characteristics are shown in FIG. 43 (A).

In the fifth example, B = (MC-GY / 2) / 2- (MY-GC / 2) / 8 G = (GY + 0.075 * MC-R) * 0.3 = (GC + 0.075 * MY-B) * 0.3 R = (MY-GC / 2) / 2- (MC-GY / 2) / 8, and the spectral characteristics are shown in FIG. 43 (B).

The sixth example is an arithmetic expression for only G, and G = {(GC + GY) + (MC + MY)} / 9, and its spectral characteristics are shown in FIG. 43 (C). This sixth
The arithmetic expression in the example is to make G by simply adding all the colors, and has the advantage that the operation is very simple, but as is clear from the spectral characteristics of FIG. 43 (C). , G are raised on both the short wavelength side and the long wavelength side, and the spectral characteristics are sacrificed.

FIG. 44 is a block diagram showing an example of the configuration of a camera system according to the present invention using the CCD image pickup device according to the present embodiment as an image pickup device.

This camera system is composed of a CCD image pickup device 5
1. A lens 52 constituting a part of an optical system, a CCD driving circuit 53 for driving a CCD image pickup device 51, an image pickup mode setting section 54 for setting an image pickup mode, and a CCD image pickup device 51
And a signal processing circuit 55 that performs various kinds of signal processing on the output signal. The CCD image sensor 51 is provided with a color filter 56 having primary horizontal two repetition and vertical two repetition color coating shown in FIG. 2 and a complementary color horizontal two repetition and vertical two repetition color coding shown in FIG.

In the camera system having such a configuration, incident light (image light) from a subject (not shown) is imaged on the imaging surface of the CCD imaging device 51 through the color filter 56 by the lens 52 of the optical system. CCD image sensor 5
As 1, a multi-pixel having a pixel configuration shown in FIG. 1 corresponding to still image capturing is used. The CCD imaging device 51 is driven by a CCD driving circuit 53 in accordance with the imaging mode set by the imaging mode setting unit 54.

Here, in the imaging mode setting section 54, a still image mode and a moving image mode can be set, and for the moving image mode, the setting of the imaging mode corresponding to each television system such as NTSC / PAL / HD can be performed. It is possible. The CCD drive circuit 53 includes an imaging mode setting unit 5
4, when the still image mode is set, the CCD image pickup device 51 is driven in the same manner as in the well-known frame readout, that is, in the first field, for example, only the vertical transfer clock Vφ3, and in the second field, only the readout pulse Vφ1 XSG is set to read signal charges from each pixel, and to perform vertical transfer and horizontal transfer.

When the moving image mode is set by the imaging mode setting section 54, the CCD driving circuit 53 further performs each conversion such as NTSC / PAL / HD by down-conversion from the multi-pixel CCD imaging device 51 for still image by compression. In order to generate a television signal corresponding to the television system, the CCD image pickup device 51 is designed to realize compression corresponding to each of the above-described television systems, that is, vertical compression based on vertical two-pixel addition and diagonal two-pixel addition. Drive. By the operation in the moving image mode, as described above, the vertical compression process is performed while holding the color difference signals Cr and Cb, and down-conversion to a television signal corresponding to each television system is performed.

As described above, it is possible to realize a camera system capable of supporting both still image capturing and moving image capturing with one CCD image sensor 51. By using a multi-pixel CCD image pickup device for a digital still camera as an image pickup device, the NTSC or PSC
It is possible to monitor an AL-type television image. In particular, since the CCD image sensor 51 can perform arbitrary vertical compression, it is possible to obtain a moving image in which the horizontal and vertical resolutions are balanced.

[0238]

As described above, according to the present invention,
Of a plurality of pixels, each signal charge of a pixel group located in two rows adjacent to each other in the row direction is defined as:
The data is read out to the vertical transfer unit located on the same side in units of rows, and the two adjacent rows in the row direction are used as units.
Each signal charge of a pixel group located in a row is read out to a vertical transfer unit located on the opposite side in row units, and in each of these vertical transfer units, signal charges of two vertical pixels and signal charges of two oblique pixels are added. By doing so,
It is possible to capture a moving image with a balanced vertical resolution.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a CCD imaging device according to an embodiment of the present invention.

FIG. 2 is a diagram showing color coding of 2 × 2 primary colors.

FIG. 3 is a timing chart of vertical two-pixel addition and oblique two-pixel addition.

FIG. 4 is a timing chart in a normal mode.

FIG. 5 is a schematic plan view showing a first pattern example of a channel stop unit.

FIG. 6 is a timing chart when a signal charge is read from a sensor unit and two-pixel addition is performed.

FIG. 7 is a diagram illustrating the operation of vertical two-pixel addition and diagonal two-pixel addition in the case of the first pattern example using the primary color filter.

FIG. 8 shows 1/1 of the case of the first pattern example in the primary color filter.
It is a timing chart at the time of 2PS compression.

FIG. 9 shows 1/1 of the first pattern example in the primary color filter.
FIG. 3 is an explanatory diagram of the operation of 2IS compression.

FIG. 10 shows a first pattern example of a primary color filter.
6 is a timing chart at the time of / 2IS compression.

FIG. 11 shows a first pattern example of a primary color filter.
FIG. 7 is an explanatory diagram of an operation of a first example of / 4IS compression.

FIG. 12 illustrates a first pattern example of a primary color filter.
It is a timing chart at the time of / 4IS compression.

FIG. 13 shows a first pattern example of a primary color filter.
FIG. 7 is an explanatory diagram of an operation of a second example of / 4IS compression.

FIG. 14 illustrates a first pattern example of a primary color filter.
FIG. 14 is an explanatory diagram of the operation of the third example of / 4IS compression.

FIG. 15 illustrates a first pattern example of a primary color filter.
FIG. 14 is an explanatory diagram of the operation of the fourth example of / 4IS compression.

FIG. 16 is a schematic plan view showing a second pattern example of the channel stop unit.

FIG. 17 is an operation explanatory diagram of vertical two-pixel addition and oblique two-pixel addition in the case of the second pattern example using the primary color filter.

FIG. 18 illustrates a first example of the second pattern example using the primary color filter.
FIG. 4 is an explanatory diagram of the operation of the / 2IS compression.

FIG. 19 illustrates a first pattern example of the second pattern using the primary color filter.
FIG. 7 is an explanatory diagram of an operation of a first example of / 4IS compression.

FIG. 20 illustrates a first pattern example of the second pattern using the primary color filter.
FIG. 7 is an explanatory diagram of an operation of a second example of / 4IS compression.

FIG. 21 illustrates a first example of a second pattern example using a primary color filter.
FIG. 14 is an explanatory diagram of the operation of the third example of / 4IS compression.

FIG. 22 illustrates a first example of a second pattern example using a primary color filter.
FIG. 14 is an explanatory diagram of the operation of the fourth example of / 4IS compression.

FIG. 23 is a diagram illustrating an addition result in the case of another pattern example using a primary color filter.

FIG. 24 is a diagram illustrating another example of a pattern using a primary color filter.
FIG. 7 is an explanatory diagram of an operation of a first example of / 4IS compression.

FIG. 25 illustrates another pattern example of a primary color filter.
FIG. 7 is an explanatory diagram of an operation of a second example of / 4IS compression.

FIG. 26 is a diagram illustrating color coding of a complementary color 2 × 2.

FIG. 27 is an explanatory diagram of the operation of vertical two-pixel addition and diagonal two-pixel addition in the case of the first pattern example using the complementary color filter.

FIG. 28 illustrates a first example of a first pattern example using a complementary color filter.
FIG. 4 is an explanatory diagram of the operation of the / 2IS compression.

FIG. 29 illustrates a first example of the first pattern using the complementary color filter.
FIG. 7 is an explanatory diagram of an operation of a first example of / 4IS compression.

FIG. 30 shows 1 in the case of the first pattern example using the complementary color filter.
FIG. 7 is an explanatory diagram of an operation of a second example of / 4IS compression.

FIG. 31 shows 1 in the case of the first pattern example using the complementary color filter.
FIG. 14 is an explanatory diagram of the operation of the third example of / 4IS compression.

FIG. 32 illustrates a first example of the first pattern example using the complementary color filter.
FIG. 14 is an explanatory diagram of the operation of the fourth example of / 4IS compression.

FIG. 33 is a diagram illustrating the operation of vertical two-pixel addition and diagonal two-pixel addition in the case of the second pattern example using the complementary color filter.

FIG. 34 illustrates a first example of the second pattern example using the complementary color filter.
FIG. 4 is an explanatory diagram of the operation of the / 2IS compression.

FIG. 35 illustrates a first example of the second pattern example using the complementary color filter.
FIG. 7 is an explanatory diagram of an operation of a first example of / 4IS compression.

FIG. 36 illustrates a first example of the second pattern example using the complementary color filter.
FIG. 7 is an explanatory diagram of an operation of a second example of / 4IS compression.

FIG. 37 illustrates a first example of the second pattern example using the complementary color filter.
FIG. 14 is an explanatory diagram of the operation of the third example of / 4IS compression.

FIG. 38 illustrates a first example of the second pattern example using the complementary color filter.
FIG. 14 is an explanatory diagram of the operation of the fourth example of / 4IS compression.

FIG. 39 is a diagram illustrating an addition result in a case of another pattern example using a complementary color filter.

FIG. 40 shows another pattern example of a complementary color filter.
FIG. 7 is an explanatory diagram of an operation of a first example of / 4IS compression.

FIG. 41 illustrates another pattern example using a complementary color filter.
FIG. 7 is an explanatory diagram of an operation of a second example of / 4IS compression.

FIG. 42 is a diagram (part 1) illustrating spectral characteristics corresponding to respective arithmetic expressions for primary color separation.

FIG. 43 is a diagram (part 2) illustrating spectral characteristics corresponding to respective arithmetic expressions for primary color separation.

FIG. 44 is a block diagram illustrating an example of a configuration of a camera system according to the present invention.

FIG. 45 shows color difference signals Cb and C in the case of the conventional example (part 1).
It is a figure showing arrangement relation of r.

FIG. 46 shows color difference signals Cb and C of the conventional example (part 2).
It is a figure showing arrangement relation of r.

FIG. 47 is an explanatory diagram of the operation of vertical compression in the case of the conventional example (part 2).

[Explanation of symbols]

10, 51: CCD image pickup device, 12: vertical CCD (vertical transfer unit), 13: readout gate unit, 14: horizontal CCD
(Horizontal transfer section), 16: charge detection section, 19: color filter, 53: CCD drive circuit, 54: imaging mode setting section

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA10 AB01 BA13 CA02 DA11 DB03 DB08 DB11 FA06 GC08 GC09 GC14 5C024 AX01 CY09 CY12 DX01 GX03 GY01 GY04 GZ27 JX15 JX25 5C065 AA01 AA03 CC01 DD02 DD07 DD17 EE05 EE06

Claims (12)

[Claims] A plurality of sensor units arranged in a matrix; a plurality of vertical transfer units arranged for each column with respect to the plurality of sensor units; The first is to read out the signal charges of the sensor units located in the two rows in units of two rows adjacent to each other in the row direction to the vertical transfer unit located on the same side of the plurality of vertical transfer units in a row unit. Readout means, and among the plurality of sensor units, two signal lines adjacent to each other in a row direction are taken as a unit, and each signal charge of the sensor unit group located in these two lines is transferred to the opposite side of the plurality of vertical transfer units. A second readout unit that reads out the vertical transfer units located in a row on a row-by-row basis, and adding the signal charges of the two vertical pixels read out by the first readout unit in each of the plurality of vertical transfer units, The second read Adding drive means for adding the signal charges of the two oblique pixels read by the means, and receiving the signal charges obtained by the vertical two-pixel addition and the diagonal two-pixel addition in each of the plurality of vertical transfer units in line units. A solid-state imaging device, comprising: 2. The solid-state imaging device according to claim 1, wherein signal charges for a plurality of lines are added in the horizontal transfer unit. 3. The solid-state imaging device according to claim 1, wherein said addition driving means changes a combination of oblique addition between the first field and the second field. 4. The solid-state imaging device according to claim 1, wherein in addition for a plurality of lines in the horizontal transfer unit, a combination of addition is changed between a first field and a second field. 5. The addition driving means according to claim 2,
2. The solid-state imaging device according to claim 1, wherein a combination of pixel addition and diagonal two-pixel addition is changed. 6. The solid-state imaging device according to claim 1, further comprising a color filter having a color coding in which the same color is repeated every two pixels in a row direction and every two pixels in a column direction. 7. A plurality of sensor units arranged in a matrix, each of which has two rows adjacent in the row direction as a unit.
Each signal charge of the sensor unit group located in a row is read out in a row unit to a vertical transfer unit located on the same side among a plurality of vertical transfer units arranged in columns for the plurality of sensor units. In addition, each signal charge of the sensor unit group located in these two rows is read out in units of two rows adjacent to each other in the row direction to a vertical transfer unit located on the opposite side of the plurality of vertical transfer units, and In each of the plurality of vertical transfer units, the signal charges of two vertical pixels and the signal charges of two diagonal pixels read from the plural sensor units are added, and two vertical pixel addition and two diagonal pixel addition are performed. A method for driving the solid-state imaging device, wherein the signal charges are transferred to the horizontal transfer unit line by line and are transferred horizontally. 8. The method according to claim 7, wherein signal charges for a plurality of lines are added in the horizontal transfer unit. 9. Among a plurality of sensor units arranged in a matrix, two adjacent rows in the row direction are used as a unit.
Each signal charge of the sensor unit group located in a row is read out in a row unit to a vertical transfer unit located on the same side among a plurality of vertical transfer units arranged in columns for the plurality of sensor units. In addition, each signal charge of the sensor unit group located in these two rows is read out in units of two rows adjacent to each other in the row direction to a vertical transfer unit located on the opposite side of the plurality of vertical transfer units, and In each of the plurality of vertical transfer units, the signal charges of two vertical pixels and the signal charges of two oblique pixels read from the plurality of sensor units are added, and the signal charges obtained by adding the two pixels are added to a line. A solid-state imaging device that transfers the image data to the horizontal transfer unit in units and horizontally transfers the image data; an imaging mode setting unit that can selectively set a still image mode and a moving image mode; and an imaging mode set by the imaging mode setting unit. And a driving unit for driving the solid-state imaging device in accordance with (1). 10. The camera according to claim 9, wherein the driving unit adds a plurality of lines of signal charges in the horizontal transfer unit when the moving image mode is set by the imaging mode setting unit. system. 11. The interlacing operation by changing a combination of vertical two-pixel addition and diagonal two-pixel addition between the first field and the second field when the moving image mode is set by the imaging mode setting means. 10. The camera system according to claim 9, wherein: 12. The driving unit performs an interlacing operation by changing a combination of addition in the horizontal transfer unit between a first field and a second field when a moving image mode is set by the imaging mode setting unit. 10. The camera system according to claim 9, wherein: