JP4695230B1 - Static eliminator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the rising and falling of a high voltage applied to a discharge electrode in a static eliminator that outputs positive and negative ions by alternately applying a positive high voltage and a negative high voltage.
A positive side voltage rectifier circuit 11, a negative side voltage rectifier circuit 12, an output terminal 6 of the positive side voltage rectifier circuit, and an output terminal 7 of the negative side voltage rectifier circuit are connected. In the static eliminator including the static elimination electrode section 13 having one or a plurality of discharge electrodes 9 for generating negative ions and negative ions, each of the positive side voltage doubler rectifier circuit 11 and the negative side voltage doubler circuit 12 is provided. In at least one stage, a current limiting resistor R1 is connected in series to the diode D, and the capacitance value Q1 of the capacitor C1 of the stage that forms an RC parallel circuit with this current limiting resistor R1 It was made larger than the capacitance value Q0 of the capacitor C0.
[Selection] Figure 1

Description

  The present invention relates to a static eliminator for neutralizing a charged object charged with a positive or negative charge to bring the charged potential close to zero.

Conventionally, neutralization has been performed so that positive ions and negative ions are alternately output from one discharge electrode connected between the output terminal of the positive high voltage generation circuit and the output terminal of the negative high voltage generation circuit. An apparatus is known (see Patent Document 1).
Specifically, as shown in FIG. 14, switches 2a and 2b controlled by the control device 3 between an external DC power source 1 and a plus-side high-frequency boost transformer 4a and a minus-side high-frequency boost transformer 5a. Is provided.

Further, on the secondary side of each transformer, voltage doubler rectifier circuits 4b and 5b each having a plurality of pairs of diodes and capacitors are connected, and a positive high voltage consisting of the transformer 4a and voltage doubler rectifier circuit 4b is connected. A generation circuit 4 and a negative high voltage generation circuit 5 including a transformer 5a and a voltage doubler rectification circuit 5b are configured.
Then, by alternately controlling the opening and closing of the switches 2a and 2b, a high-frequency high voltage is generated alternately on the secondary side of the plus-side transformer 4a and the minus-side transformer 5a. The high voltage further boosted by the circuit is output to the output terminals 6 and 7.
Further, resistors 10 and 10 are connected to the output terminals 6 and 7 of the plus and minus high voltage generation circuits, and a needle-like discharge electrode 9 is connected to a connection point 8 between these resistors 10 and 10. .

  In such a circuit, the control device 3 controls the opening and closing of the switches 2a and 2b, so that a positive high voltage and a negative high voltage are applied to the output terminals 6 and 7 of the high voltage generation circuits 4 and 5. In response to this, positive ions and negative ions are alternately output from the discharge electrode 9.

JP 2000-058290 A JP 2008-277316 A JP 2010-165690 A JP 2008-123912 A JP 2008-135329 A JP 2008-035647 A

The above-described conventional static eliminator has a problem that the rise and fall of the voltage applied to the discharge electrode 9 is not good.
Such a problem occurs because the stray capacitance cf is formed between the discharge electrode 9 and the ground, and the output voltage is affected by the stray capacitance cf.
If the rise of the voltage applied to the discharge electrode 9 is bad, a high voltage cannot be applied to the discharge electrode 9. For example, when the rising time of the applied voltage to the discharge electrode 9 is longer than the switching cycle of plus / minus polarity, the polarity is switched before the applied voltage reaches a predetermined value. Accordingly, a high voltage necessary for the discharge electrode 9 is not applied, and the output amount of ions is reduced.
In particular, in order to remove static electricity evenly on the surface of a running film, it is required to output positive and negative ions at a frequency above a certain value, so the responsiveness of the voltage applied to the discharge electrode is poor. Is a big problem.

  The present invention relates to a static eliminator that generates positive and negative ions by alternately applying a positive high voltage and a negative high voltage to a discharge electrode. An object of the present invention is to provide a static eliminator having a good fall.

  In order to boost the high frequency voltage to a positive high voltage, the present invention provides a positive side voltage doubler rectifier circuit including a plurality of pairs of diodes and capacitors, and the positive side to boost the high frequency voltage to a negative high voltage. Negative side voltage doubler rectifier circuit comprising a plurality of pairs of diodes and capacitors opposite to the voltage doubler rectifier circuit, output terminals of these positive side voltage doubler rectifier circuit and output terminals of negative side voltage doubler rectifier circuit, And a discharge electrode having one or a plurality of discharge electrodes that generate positive ions and negative ions by application of the high voltage output of the plus side voltage rectifier circuit and the high voltage output of the minus side voltage rectifier circuit It is premised on the static elimination apparatus provided with the part.

According to a first aspect of the present invention, on the premise of the static eliminator, a current limiting resistor is connected in series with a diode in at least one stage of each of the plus side voltage doubler rectifier circuit and the minus side voltage doubler circuit, A feature is that the capacitance value Q1 of the capacitor C1 of the stage constituting the RC parallel circuit with the current limiting resistor is made larger than the capacitance value Q0 of the capacitor C0 in the other stage.
The above-mentioned “configuration of the RC parallel circuit” means that a capacitor in the stage of the voltage doubler rectifier circuit and a current limiting resistor connected in series to the diode are connected in parallel.

According to the present invention, a resistor is connected in series to the diode of the voltage doubler rectifier circuit, and the capacitor in parallel with this resistor is increased in capacity so that the capacitor that performs the boosting function in the voltage doubler rectifier circuit is used as a speed-up capacitor. The function of can be demonstrated. Thereby, the rising and falling of the high voltage output from the plus / minus voltage doubler rectifier circuit can be accelerated, that is, the responsiveness of the voltage applied to the discharge electrode can be improved.
Therefore, even if the switching frequency for alternately switching between the plus side voltage doubler rectifier circuit and the minus side voltage doubler rectifier circuit is increased, a plus / minus high voltage is alternately applied with good response to the static elimination electrode part. -The negative ion amount increases, and the static elimination performance can be improved.

In addition, the present invention provides a resistor in the plus side voltage doubler rectifier circuit and the minus side voltage rectifier circuit, and increases the capacitance of the capacitor constituting the voltage doubler rectifier circuit so that the voltage applied to the static elimination electrode unit is increased. Therefore, it is not necessary to separately form a circuit for improving the rise and fall of the voltage outside the voltage doubler rectifier circuit. For example, the number of components can be reduced as compared with the case where an RC parallel circuit including a capacitor in parallel with the resistor 10 is formed outside the output portion of the voltage doubler rectifier circuit shown in FIG.
Further, when the current limiting resistor is divided and provided in a plurality of stages, the withstand voltage of each current limiting resistor can be lowered and the circuit design can be widely handled.

FIG. 1 is an electric circuit diagram of an embodiment of the present invention. FIG. 2 is a graph of the output voltage as a result of the verification experiment using Example 1 of the present invention. FIG. 3 is a result of the verification experiment of Example 1, where (a) is a graph in which the rising portion of FIG. 2 is enlarged and (b) is an enlarged graph of the falling portion. FIG. 4 is a circuit diagram of the first comparative example. FIG. 5 is a result of the verification experiment of Comparative Example 1, in which (a) is a graph in which the rising portion of the output voltage is enlarged, and (b) is an enlarged graph of the falling portion of the output voltage. 6A and 6B show the output voltage of Comparative Example 2. FIG. 6A is a graph in which the rising portion of the output voltage is enlarged, and FIG. 6B is an enlarged graph of the falling portion of the output voltage. FIG. 7 is a circuit diagram of the second embodiment. FIG. 8 shows the results of the verification experiment of the second embodiment, where (a) is a graph in which the rising portion of the output voltage is enlarged, and (b) is a graph in which the falling portion of the output voltage is enlarged. FIG. 9 is a circuit diagram of the third and fourth embodiments. 10A and 10B show the results of the verification experiment of the third embodiment. FIG. 10A is a graph in which the rising portion of the output voltage is enlarged, and FIG. 10B is an enlarged graph of the falling portion of the output voltage. FIG. 11 shows the results of the verification experiment of the third comparative example, in which (a) is a graph in which the rising portion of the output voltage is enlarged, and (b) is an enlarged graph of the falling portion of the output voltage. FIGS. 12A and 12B show the results of the verification experiment of the fourth embodiment. FIG. 12A is a graph in which the rising portion of the output voltage is enlarged, and FIG. 12B is an enlarged graph of the falling portion of the output voltage. FIG. 13 shows the results of verification experiments of the fourth comparative example, in which (a) is a graph in which the rising portion of the output voltage is enlarged and (b) is an enlarged graph of the falling portion of the output voltage. FIG. 14 is a circuit diagram of a conventional static eliminator.

FIG. 1 is a circuit diagram showing a first embodiment of the static eliminator of the present invention.
As shown in FIG. 1, the static eliminator includes a high-frequency boost transformer T1 that further boosts the high-frequency voltage on the positive side and a high-frequency boost transformer T2 that further boosts the high-frequency voltage on the negative side. The voltage doubler rectifier circuits 11 and 12 are connected to the secondary side of T2.
The step-up transformers T1 and T2 have a function of further boosting a high-frequency voltage from an external high-frequency voltage source, similarly to the high-frequency step-up transformers 4a and 5a in FIG. Although not shown, a high-frequency voltage source and a switch mechanism that alternately switches a high-frequency voltage input between a plus side and a minus side are connected as in FIG.

  Each of the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12 includes a plurality of stages each including a capacitor and a diode D. As the number of stages increases, the step-up rate of the voltage input from the secondary side of the high-frequency step-up transformers T1 and T2 increases, and a high voltage can be output from the voltage doubler rectifier circuits 11 and 12. However, the number of stages may be set according to the required voltage. In this embodiment, the number of stages is 14, and the diodes D provided in each stage are all the same. However, in FIG. 1, some of the steps are omitted.

Further, each stage of the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12 is provided with a capacitor C0 or C1, and each of the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12 is finally provided. A current limiting resistor R1 is connected in series to a 14th-stage diode D which is a stage.
In FIG. 1, the capacitor at the stage to which the current limiting resistor R1 is connected is represented as C1, and the capacitor at the other stage is represented as C0.
Therefore, an RC parallel circuit including a current limiting resistor R1 and a capacitor C1 connected in series to the diode D is configured in the final stage.

Further, the output terminal 6 of the plus side voltage doubler rectifier circuit 11 and the output terminal 7 of the minus side voltage doubler circuit 12 are connected without a resistor, and a neutralization electrode section 13 is connected to the intermediate connection point 8. Yes.
The static elimination electrode unit 13 includes a needle-like discharge electrode 9 that generates positive or negative ions according to the output voltages of the positive side voltage doubler rectifier circuit 11 and the negative side voltage doubler rectifier circuit 12. . In this embodiment, 60 discharge electrodes 9 are used, but the number thereof may be any number.

Furthermore, a current limiting resistor R2 is connected to each discharge electrode 9 in series. The reason why the current limiting resistor R2 is connected is to prevent a large current from flowing through the discharge electrode 9.
By connecting the current limiting resistor R2 in this way, even if a person accidentally contacts the discharge electrode 9 to which a high voltage is applied, a large current does not flow and safety is ensured. high. However, the current limiting resistor R2 is not essential.
Further, since stray capacitance is generated between each discharge electrode 9 and the ground, it is illustrated as a stray capacitance cf using a capacitor symbol.

In the static eliminator of the first embodiment, in the voltage doubler rectifier circuits 11 and 12 of FIG. 1, the capacitor C1 having the RC parallel circuit provided with the current limiting resistor R1 is replaced with a capacitor in another stage. It is larger than the capacity of C0.
In this way, the capacitance of the capacitor C1 constituting the RC parallel circuit is made larger than the capacitance of the capacitor C0 in the other stages, so that it is applied to the output voltage of the output terminals 6 and 7, that is, the static elimination electrode section 13. The rise and fall of the high voltage is improved, and the output voltage response is improved.

Next, an experiment for confirming that the responsiveness of the high voltage output from the output terminals 6 and 7 is improved by the static eliminator of the first embodiment will be described.
Specific experimental conditions are as follows.
In the circuit of FIG. 1, the resistance value Ra of the current limiting resistor R1 is 50 [MΩ], the capacitance value Q0 of the capacitor C0 is 100 [pF], and the capacitance value Q1 of the capacitor C1 is 330 [pF]. That is, the capacitance value Q1 of the capacitor C1 constituting the RC parallel circuit> the capacitance value Q0 of the capacitor C0 in another stage.

The resistance value of the current limiting resistor R2 connected to each discharge electrode 9 of the static elimination electrode portion 13 was set to 10 [MΩ].
The load resistance value Rb and the stray capacitance value Qf of the static elimination electrode 13 are values of the static elimination electrode section 13 including 60 discharge electrodes 9, respectively, and the values of the individual current limiting resistors R2 and the stray capacitance cf. is not. Specifically, as the number of the discharge electrodes 9 increases, the load resistance value Rb decreases and the stray capacitance value Qf increases.
The load resistance value Rb includes the resistance of the discharge electrode 9 itself, the wiring resistance, and the like.

  In the static eliminator of the first embodiment, a high frequency voltage of 0.5 [Hz] is applied to the primary side of the step-up transformers T1 and T2, and the output of the plus side voltage doubler rectifier circuit 11 is applied. Between the terminal 6 and the output terminal 7 of the negative side voltage doubler rectifier circuit 12, the output voltage at the connection point 8 to which the static elimination electrode portion 13 was connected was measured. In addition, the form of the said static elimination electrode part 13 connects 60 discharge electrodes 9 as above-mentioned.

The measurement results are shown in FIGS. FIG. 2 is a graph showing the change with time of the output voltage at the connection point 8. FIG. 3A is a graph in which the rising portion A of the output voltage shown in FIG. 2 is enlarged, and FIG. Is a graph in which the falling portion B of the output voltage is enlarged.
As shown in FIGS. 2 and 3, in the static eliminator of the first embodiment, the rise time of the output voltage was 9 [ms] and the fall time was 11 [ms].
In the first embodiment, the rise time and the fall time are 20 [ms] in one cycle, so that the output voltage can be handled until the switching frequency between the positive side and the negative side of the input voltage is 50 [Hz]. Become.

Next, as Comparative Example 1, the rise and fall of the output voltage were measured for the static eliminator shown in FIG. Comparative Example 1 corresponds to the conventional circuit shown in FIG.
In the static eliminator of Comparative Example 1, the current limiting resistor R1 is not connected in the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12, and the output is similar to the circuit described in Patent Document 1. A pair of current limiting resistors R1, R1 are connected between the terminals 6,7. And the static elimination electrode part 13 similar to Example 1 is connected to the connection point 8 between said pair of current limiting resistance R1, R1.
The capacitors C0 in the plus side and minus side voltage doubler rectifier circuits 11 and 12 all have the same capacitance Q0 = 100 [pF].
The rest of the configuration was the same as in Example 1, and the output voltage output to the connection point 8 was measured under the same experimental conditions.

The results are shown in FIGS. 5 (a) and 5 (b). 5A is a graph in which the rising portion A of the output voltage is enlarged, and FIG. 5B is a graph in which the falling portion B is enlarged.
As shown in FIG. 5, in Comparative Example 1, the rise time is 18 [ms] and the fall time is 18 [ms]. The rise and fall times are 36 [ms] in one cycle, and cannot correspond to a switching frequency of 27 [Hz] or more.
Thus, it has been found that the static eliminator of the first embodiment of the present invention has better responsiveness of the output voltage applied to the static elimination electrode unit 13 than the comparative example 1 which is a conventional static eliminator.

Next, an experiment using Comparative Example 2 was performed in order to confirm the effect of increasing the capacitance of the capacitor C1 constituting the RC parallel circuit than the capacitance of the capacitor C0 in the other stage.
Comparative Example 2 is a static eliminator in which the capacitance value Q1 of the capacitor C1 constituting the RC parallel circuit of the circuit shown in FIG. 1 is the same as the capacitance value Q0 of the other capacitor C0. That is, in this comparative example 2, the current limiting resistor R1 is provided in the plus side and minus side voltage doubler rectifier circuits 11, 12, but the capacitance of the capacitor C1 of the RC parallel circuit configured by the current limiting resistor R1. Q1 = Q0 = 100 [pF] without making it larger than other capacitors C0.

Also in the comparative example 2, the output voltage at the connection point 8 was measured under the same experimental conditions as in the first embodiment. The results are shown in FIGS. 6 (a) and (b). 6A is a graph in which the rising portion A of the output voltage is enlarged, and FIG. 6B is a graph in which the falling portion B is enlarged.
As shown in FIG. 6, in this comparative example 2, the rise time is 18 [ms] and the fall time is 18 [ms], and the switching frequency of 27 [Hz] or more is supported as in the comparative example 1. It was impossible.
From this, it was confirmed that the responsiveness of the output voltage cannot be improved only by connecting the current limiting resistor R1 in the plus side voltage doubler rectifier voltage circuit 11 and the minus side voltage doubler current circuit 12.

As described above, the current limiting resistor R1 is provided at any stage in the plus side and minus side voltage doubler rectifier circuits 11 and 12, and the capacitance of the capacitor C1 constituting the RC parallel circuit together with this R1 is changed to the other level. It was found that the response of the output voltage is improved by increasing the capacitance of the capacitor C0 in the stage.
This result is due to the fact that by increasing the capacitance of the capacitor C1 constituting the RC parallel circuit, the capacitor C1 exhibited a function as a speed-up capacitor as well as a boosting function in the voltage doubler rectifier circuit.
In the first embodiment, since the capacitor in the voltage doubler rectifier circuit can also function as a speed-up capacitor, a separate circuit for eliminating the influence of the stray capacitance in the static elimination electrode unit 13 is provided. As shown in FIG. 14, it is not necessary to configure outside the output terminals 6 and 7. Therefore, as compared with the case where a separate circuit is provided, there are advantages that the number of parts can be reduced and the circuit configuration can be simplified.

In addition, the capacitor C1 that exhibits the speed-up capacitor function and the current limiting resistor R1 can improve the response of the output voltage in the same manner regardless of the stage in the voltage doubler rectifier circuits 11 and 12. all right. Although details of each are not shown, a current limiting resistor R1 is provided in the intermediate stage of the voltage doubler rectifier circuits 11 and 12 and the stage on the transformer T1 and T2 side, and the capacitance of the capacitor C1 in that stage constituting the RC parallel circuit is set. The effect of improving the responsiveness has also been confirmed by experiments for circuits that are larger than the capacitance of the capacitor C0 in other stages.
The stage where the current limiting resistor R1 is provided may not be the same stage in the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12.

FIG. 7 is a circuit diagram of a second embodiment in which a plurality of resistors r1 are used as the current limiting resistors R1 provided in each of the voltage doubler rectifier circuits 11 and 12.
In the second embodiment, instead of the current limiting resistor R1 of the first embodiment, 10 [MΩ] current limiting resistors r1 are provided in the middle five stages of the voltage doubler rectifier circuits 11 and 12, respectively. . That is, the sum of the resistance values of the current limiting resistor r1 is made the same as the resistance value 50 [MΩ] of the current limiting resistor R1. That is, in both the first and second embodiments, the total current limiting resistance value Ra is 50 [MΩ].
The capacitor C1 at the stage to which the current limiting resistor r1 is connected is 330 [pF], and the capacitor C0 at the other stage is 100 [pF].
Other configurations are the same as those of the first embodiment shown in FIG. An experiment was performed under the same conditions as in the first embodiment, and the output voltage at the connection point 8 was measured.

The result is shown in FIG. 8A is a graph in which the rising portion A of the output voltage is enlarged, and FIG. 8B is a graph in which the falling portion B is enlarged.
As shown in FIG. 8, in the second embodiment, the rise time is 12 [ms] and the fall time is 13 [ms]. The rise and fall time of one cycle is 25 [ms], which can correspond to the switching frequency of the input voltage of 40 [Hz], which is inferior to the first embodiment shown in FIG. 3, but the comparative example shown in FIGS. Responsiveness was improved as compared with 1 and Comparative Example 2 in FIG.

Thus, even when current limiting resistors are provided in a plurality of stages in the plus side and minus side voltage doubler rectifier circuits 11 and 12, the capacity of the corresponding capacitor C1 is larger than the capacity of the capacitor C0 in the other stages. By doing so, it has been found that the capacitor C1 exhibits a function as a speed-up capacitor as well as a boosting function.
In the case where the current limiting resistors are divided into a plurality of pieces as in the second embodiment, the response is worse than the first embodiment in which the current limiting resistors are combined into one, and the capacity is reduced. Although there is a demerit that a large number of large capacitors C1 are required, there is an advantage that by disposing the resistors, it is possible to disperse the heat generation part and to suppress the temperature rise of the apparatus. Furthermore, there is an advantage that the withstand voltage of each current limiting resistor r1 can be reduced.
Further, even when the current limiting resistor r1 is provided in a plurality of stages and the RC parallel circuit is configured as in the second embodiment, the stage configuring the RC parallel circuit may be anywhere.

As described above, the static eliminator of the present invention connects the current limiting resistor to the diode in series at any stage of the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12 as described above, It is necessary that the relationship between the capacitance value Q1 of the capacitor C1 and the capacitance value Q0 of the capacitor C0 in the other stage, which constitutes the RC parallel circuit with this current limiting resistor, maintain Q1> Q0. In such a static eliminator, in order to confirm the influence of the load resistance value Rb and the stray capacitance value Cf, which are the resistance values on the static elimination electrode unit 13 side, on the responsiveness of the output voltage, the third and second shown in FIG. Experiments using four embodiments were conducted.
The results will be described below.

The static eliminator of the third embodiment shown in FIG. 9 is connected to a load resistance Rb having a resistance value of 100 [MΩ] instead of the static elimination electrode portion 13 of the first embodiment shown in FIG. ].
Other configurations are the same as those in the first embodiment, and the same reference numerals as those in FIG. 1 are used for the same components as those in the first embodiment.
And also about the static elimination of this 3rd Embodiment, the output voltage in the said connection point 8 was measured on the same conditions as the said 1st Embodiment.
The result is shown in FIG. 10A is a graph in which the rising portion A of the output voltage is enlarged, and FIG. 10B is a graph in which the falling portion B is enlarged.

  As shown in FIG. 10, in the third embodiment, the rise time is 6 [ms] and the fall time is 6 [ms]. The rise and fall time of one cycle is 12 [ms], which can correspond to the input voltage switching frequency of 83 [Hz].

The capacitance value Q1 of the capacitor C1 constituting the RC parallel circuit in the voltage doubler rectifier circuits 11 and 12 of the third embodiment shown in FIG. 9 is equal to the capacitance value Q0 of the other capacitor C0, and Q1 = Q0 = The static eliminator with 100 [pF] is referred to as Comparative Example 3. The static eliminator of Comparative Example 3 is the same as that of the third embodiment except that the capacitance value Q1 of the capacitor C1 is set to Q0.
For the static eliminator of Comparative Example 3, the output voltage at the connection point 8 was measured under the same conditions as in the third embodiment.
The result is shown in FIG. 11A is a graph in which the rising portion A of the output voltage is enlarged, and FIG. 11B is a graph in which the falling portion B is enlarged.

As shown in FIG. 11, in Comparative Example 3, the rise time was 11 [ms] and the fall time was 11 [ms]. The rise and fall time of one cycle is 22 [ms], and cannot cope with the switching frequency of the input voltage of 46 [Hz] or more. That is, in Comparative Example 3 in which the capacitance value Q1 of the capacitor C1 and the capacitance value Q0 of the capacitor C0 are equal, the responsiveness is poor as compared with the third embodiment that can handle the switching frequency of the input voltage up to 86 [Hz]. I understood it.
From the experimental results of the third embodiment and the comparative example 3, the output voltage rises and falls by making the capacitance value Q1 of the capacitor C1 constituting the RC parallel circuit larger than the capacitance value Q0 of the other capacitors C0. Was confirmed to improve.

The fourth embodiment is a static eliminator having the same configuration as that of the third embodiment except that the resistance value Rb of the load resistor Rb is 300 [MΩ] in the circuit shown in FIG.
Also in the fourth embodiment, the output voltage at the connection point 8 was measured by the same experiment as in the other embodiments.
The result is shown in FIG. 12A is a graph in which the rising portion A of the output voltage is enlarged, and FIG. 12B is a graph in which the falling portion B is enlarged.

  As shown in FIG. 12, in the fourth embodiment, the rise time is 9 [ms] and the fall time is 9 [ms]. The rise and fall time of one cycle is 18 [ms], and it is possible to deal with the switching frequency of the input voltage of 56 [Hz] as in the third embodiment.

The capacitance value Q1 of the capacitor C1 constituting the RC parallel circuit in the voltage doubler rectifier circuits 11 and 12 of the fourth embodiment is equal to the capacitance value Q0 of the other capacitor C0, and Q1 = Q0 = 100 [pF] This static eliminator is referred to as Comparative Example 4. The static eliminator of Comparative Example 4 is the same as that of the fourth embodiment except that the capacitance value Q1 of the capacitor C1 is set to Q0. That is, the load capacitance Cf is set to 100 [pF], the resistance value Rb is set to 300 [MΩ], and the capacitance values Q1 of the capacitors C1 and C0 in the voltage doubler rectifier circuits 11 and 12 are set to Q1 = capacitance value Q0 = 100 [pF]. .
For the static eliminator of Comparative Example 4, the output voltage at the connection point 8 was measured under the same conditions as in the fourth embodiment.
The result is shown in FIG. 13A is a graph in which the rising portion A of the output voltage is enlarged, and FIG. 13B is a graph in which the falling portion B is enlarged.

As shown in FIG. 13, in Comparative Example 4, the rise time was 18 [ms] and the fall time was 18 [ms]. The rise and fall time of one cycle is 36 [ms], and cannot cope with the switching frequency of the input voltage of 27 [Hz] or more. That is, in the comparative example 4 in which the capacitance value Q1 of the capacitor C1 and the capacitance value Q0 of the capacitor C0 are equal, Q1> Q0 and the switching frequency of the input voltage can be up to 56 [Hz] compared to the fourth embodiment. It was found that the responsiveness was bad.
From the experimental results of the fourth embodiment and the comparative example 4, the rising and falling edges of the output voltage are obtained by making the capacitance value Q1 of the capacitor C1 constituting the RC parallel circuit larger than the capacitance value Q0 of the other capacitors C0. Was confirmed to improve.

  The third and fourth embodiments have different load resistance values Rb, but the other configurations are exactly the same. Even if the load resistance values are different, an RC parallel circuit is formed in the voltage doubler rectifier circuits 11 and 12, and the capacitance value Q1 of the capacitor C1 constituting the RC parallel circuit is changed to the capacitance value Q0 of the other capacitor C0. It was confirmed that the capacitor C1 can increase the rise and fall of the output voltage by exhibiting the speed-up function as well as the boost function.

In addition, when the above-described static elimination apparatus is used for a long time, dust adheres to the tip of the discharge electrode 9 of the static elimination electrode portion 13. In the initial stage of use, since there is no dust adhering to the discharge electrode 9, a large discharge current flows and the load resistance Rb is substantially small. As a result, a phenomenon occurs in which the load resistance Rb increases.
Therefore, in the verification experiments of the third and fourth embodiments, the load resistance Rb is changed to 100 [MΩ] and 300 [MΩ], and the output voltage at the connection point 8 is changed even if the load resistance value changes. Even if it is confirmed that the rise and fall can be done quickly, and the static elimination electrode portion 13 becomes dirty and the value of the load resistance Rb increases from 100 [MΩ] to 300 [MΩ] by using the static elimination device for a long time, 56 It was confirmed that it was possible to cope with the switching frequency of the input voltage higher than [Hz].

In the first to fourth embodiments, the current limiting resistance value Ra provided in the voltage doubler rectifier circuits 11 and 12, the capacitance value Q1 of the capacitor C1 constituting the RC parallel circuit, and the capacitance values Q0 of the other capacitors C0 are: It is necessary to set an appropriate value according to the necessary output voltage applied to the static elimination electrode part 13, the load resistance value Rb of the static elimination electrode part 13, and the stray capacitance value Qf.
However, in order to improve the response delay due to the stray capacitance of the static elimination electrode section 13, the capacitance value Q1 of the capacitor C1 in the RC parallel circuit> the capacitance value Q0 of the other capacitor C0 in the voltage doubler rectifier circuit. It is necessary to satisfy the relationship.

Further, the primary side circuit of the high frequency step-up transformers T1 and T2 is not limited to that shown in FIG. 14, and any circuit can be used as long as a high frequency voltage can be alternately input to the plus side and the minus side.
In the above embodiment, the voltage boosted by the high frequency boosting transformers T1 and T2 is input to the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12, and further boosted to output a high voltage. However, the step-up transformer is not essential if the desired high voltage can be output.

  Since the static eliminator according to the present invention has high responsiveness to the high voltage applied to the discharge electrode of the static elimination electrode part, the amount of ions generated is large and can be applied to uniform static elimination of a moving charged object.

9 Discharge electrode 11 Positive voltage doubler rectifier circuit 12 Negative voltage doubler rectifier circuit C0 Capacitor C1 Capacitor D Diode R1 Current limiting resistor r1 Current limiting resistor 13 Static elimination electrode part R2 Current limiting resistor Ra (connected to the discharge electrode) Ra (Double voltage) Current limiting resistance value Rb (in the clear current circuit) Load resistance value cf (over the entire static elimination electrode section) cf Floating capacitance Qf Floating capacitance value (over the static elimination electrode section)

Claims (1)

  In order to boost the high-frequency voltage to a positive high voltage, the positive-side voltage doubler rectifier circuit including a plurality of pairs of diodes and capacitors, and the positive-side voltage doubler rectifier circuit to boost the high-frequency voltage to a negative high voltage. Are connected to the negative side voltage doubler rectifier circuit having a plurality of pairs of diodes and capacitors reversed in direction, and to the output terminal of the positive side voltage doubler rectifier circuit and the output terminal of the negative side voltage doubler rectifier circuit, A neutralization electrode section having one or a plurality of discharge electrodes that generate positive ions and negative ions by application of the high voltage output of the plus side voltage doubler rectifier circuit and the high voltage output of the minus side voltage doubler rectifier circuit. In the static eliminator, a current control is performed on the diode in at least one stage of each of the positive voltage doubler rectifier circuit and the negative voltage doubler circuit. With connecting use resistors in series, the capacitance value Q1 stage capacitor C1 constituting the RC parallel circuit between the current limiting resistor, a discharge device is made larger than the capacitance value Q0 of the capacitor C0 in the other stages.

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