JP5791319B2 - Power supply circuit for static eliminator - Google Patents

Description

  The present invention relates to a power supply circuit for a static eliminator for neutralizing a charged object charged with a positive or negative charge to bring the charged potential close to zero.

Conventionally, neutralization has been performed so that positive ions and negative ions are alternately output from one discharge electrode connected between the output terminal of the positive high voltage generation circuit and the output terminal of the negative high voltage generation circuit. An apparatus is known (see Patent Document 1).
Specifically, as shown in FIG. 13, switches 2a and 2b controlled by the control device 3 between an external DC power source 1 and a plus-side high-frequency boost transformer 4a and a minus-side high-frequency boost transformer 5a. Is provided.

Further, on the secondary side of each transformer, voltage doubler rectifier circuits 4b and 5b each having a plurality of pairs of diodes and capacitors are connected, and a positive high voltage consisting of the transformer 4a and voltage doubler rectifier circuit 4b is connected. A generation circuit 4 and a negative high voltage generation circuit 5 including a transformer 5a and a voltage doubler rectification circuit 5b are configured.
Then, by alternately controlling the opening and closing of the switches 2a and 2b, a high-frequency high voltage is generated alternately on the secondary side of the plus-side transformer 4a and the minus-side transformer 5a. The high voltage further boosted by the circuit is output to the output terminals 6 and 7.
Further, resistors 10 and 10 are connected to the output terminals 6 and 7 of the plus and minus high voltage generation circuits, and an electrode portion having a discharge electrode (not shown) is connected to a connection point 8 between these resistors 10 and 10. Use.

  In such a circuit, the control device 3 controls the opening and closing of the switches 2a and 2b, so that a positive high voltage and a negative high voltage are applied to the output terminals 6 and 7 of the high voltage generation circuits 4 and 5. In response to this, positive ions and negative ions are alternately output from the electrode portion.

JP 2000-058290 A JP 2008-277316 A JP 2010-165690 A JP 2008-123912 A JP 2008-135329 A JP 2008-035647 A

The conventional static eliminator described above has a problem that the rise and fall of the voltage output to the connection point 8 is not good.
Such a problem occurs because a stray capacitance cf is formed between the electrode connected to the connection point 8 and the ground, and the output voltage is affected by the stray capacitance cf. .
If the output voltage rises at the connection point 8, the high voltage cannot be applied to the electrode portion. For example, when the rise of the output voltage is larger than the switching cycle of the plus / minus polarity, the polarity is switched before the output voltage at the connection point 8 reaches a predetermined value. Therefore, a high voltage necessary for the discharge electrode is not applied, and the output amount of ions is reduced.
In particular, it is required to output positive and negative ions at a frequency above a certain value in order to eliminate static electricity on the running film surface, etc., so the responsiveness of the applied voltage to the electrode is poor. Is a big problem.

  The present invention relates to a power supply circuit for a static eliminator that generates positive and negative ions by alternately applying a positive high voltage and a negative high voltage to an electrode portion, and a high voltage applied to a discharge electrode. It is an object of the present invention to provide a power supply circuit for a static eliminator with good rise and fall of voltage.

In order to boost the high frequency voltage to a positive high voltage, the present invention provides a positive side voltage doubler rectifier circuit including a plurality of pairs of diodes and capacitors, and the positive side to boost the high frequency voltage to a negative high voltage. Negative side voltage doubler rectifier circuit comprising a plurality of pairs of diodes and capacitors opposite to the voltage doubler rectifier circuit, output terminals of these positive side voltage doubler rectifier circuit and output terminals of negative side voltage doubler rectifier circuit, An electrode unit having one or a plurality of discharge electrodes that generate positive ions and negative ions by applying a high voltage output of the plus side voltage rectifier circuit and a high voltage output of the minus side voltage rectifier circuit And connecting all the capacitors constituting the positive side voltage doubler rectifier circuit and the negative side voltage doubler rectifier circuit with the same capacity. , A in each of the at least one stage of the positive voltage doubler rectifier circuit and the negative-side voltage doubler circuit, diodes to the output terminal in series are connected, and connected in parallel with the capacitor in the stage In this circuit , a current limiting resistor is connected in series with the diode, and the capacitor constituting the RC parallel circuit with this current limiting resistor is allowed to exhibit the boosting function and the speed-up capacitor function. To do.

In the present invention, by connecting a resistor in series to the diode of the voltage doubler rectifier circuit, the capacitor that exhibits the boosting function in the voltage doubler rectifier circuit can function as a speed-up capacitor. Thereby, the rising and falling of the high voltage output from the plus / minus voltage doubler rectifier circuit can be accelerated, that is, the responsiveness of the voltage applied to the discharge electrode can be improved.
Therefore, even if the switching frequency for alternately switching between the plus side voltage doubler rectifier circuit and the minus side voltage doubler rectifier circuit is increased, a plus / minus high voltage is alternately applied with good response to the static elimination electrode part. -The negative ion amount increases, and the static elimination performance can be improved.

Moreover, the present invention improves the rising and falling of the voltage applied to the electrode portion by providing a resistor in the plus side voltage doubler rectifier circuit and the minus side voltage doubler rectifier circuit. It is not necessary to separately form a circuit for improving the rise and fall of the voltage outside the circuit. For example, the number of parts can be reduced as compared with the case where an RC parallel circuit including a capacitor in parallel with the resistor 10 is formed outside the output portion of the voltage doubler rectifier circuit shown in FIG.
Further, when the current limiting resistor is divided and provided in a plurality of stages, the withstand voltage of each current limiting resistor can be lowered and the circuit design can be widely handled.
When the limiting resistor is provided in one stage of each voltage doubler rectifier circuit as in the second aspect of the invention, the applied voltage to the electrode portion is compared with the case where the limiting resistor is divided into a plurality of stages. The rise and fall of can be further improved.

FIG. 1 is an electric circuit diagram of an embodiment of the present invention. FIG. 2 is a graph of output voltage as a result of a verification experiment using the first embodiment of the present invention. FIG. 3 is a result of the verification experiment of the first embodiment, where (a) is a graph in which the rising portion of FIG. 2 is enlarged and (b) is a graph in which the falling portion is enlarged. FIG. 4 is a circuit diagram of a verification experiment of a comparative example. 5A and 5B show the results of the verification experiment of the comparative example, where FIG. 5A is a graph in which the rising portion of the output voltage is enlarged, and FIG. 5B is an enlarged graph of the falling portion of the output voltage. FIG. 6 is a circuit diagram of the second embodiment. FIG. 7 shows the results of the verification experiment of the second embodiment, where (a) is a graph in which the rising portion of the output voltage is enlarged, and (b) is a graph in which the falling portion of the output voltage is enlarged. FIG. 8 is a circuit diagram of the third embodiment. FIG. 9 shows the results of the verification experiment of the third embodiment, where (a) is a graph in which the rising portion of the output voltage is enlarged, and (b) is a graph in which the falling portion of the output voltage is enlarged. FIG. 10 is a circuit diagram of the fourth embodiment. FIG. 11 shows the results of the verification experiment of the fourth embodiment, where (a) is a graph in which the rising portion of the output voltage is enlarged, and (b) is a graph in which the falling portion of the output voltage is enlarged. FIG. 12 shows an example of use of the power supply circuit for the static eliminator in this invention. FIG. 13 is a circuit diagram of a conventional static eliminator.

FIG. 1 is a circuit diagram showing a first embodiment of a power supply circuit for a static eliminator of the present invention.
As shown in FIG. 1, the static eliminator includes a high-frequency boost transformer T1 that further boosts the high-frequency voltage on the positive side and a high-frequency boost transformer T2 that further boosts the high-frequency voltage on the negative side. The voltage doubler rectifier circuits 11 and 12 are connected to the secondary side of T2.
The step-up transformers T1 and T2 have a function of further boosting a high-frequency voltage from an external high-frequency voltage source, similarly to the high-frequency step-up transformers 4a and 5a in FIG. Although not shown, a high-frequency voltage source and a switch mechanism that alternately switches a high-frequency voltage input between a plus side and a minus side are connected as in FIG.

  The plus-side voltage doubler rectifier circuit 11 and the minus-side voltage doubler rectifier circuit 12 each include a plurality of sets of capacitors C0 and C1 and diodes D. As the number of stages increases, the step-up rate of the voltage input from the secondary side of the high-frequency step-up transformers T1 and T2 increases, and a high voltage can be output from the voltage doubler rectifier circuits 11 and 12. However, the number of stages may be set according to the required voltage. In this embodiment, the number of stages is 14, and the diodes D provided in each stage are all the same. However, in FIG. 1, some of the steps are omitted.

Further, each stage of the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12 is provided with capacitors C0 and C1 having the same capacity, and the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12 are provided. A current limiting resistor R1 is connected in series to the 14th-stage diode D, which is the final stage of each. Note that the capacitor at the stage to which the current limiting resistor R1 is connected is denoted as C1.
Therefore, an RC parallel circuit including a current limiting resistor R1 and a capacitor C1 connected in series to the diode D is configured in the final stage.

Further, the output terminal 6 of the plus side voltage doubler rectifier circuit 11 and the output terminal 7 of the minus side voltage doubler circuit 12 are connected without a resistor, and a connection point 8 for connecting an electrode portion (not shown) in between is connected. I have.
In the same manner as in the conventional electrode unit, this electrode unit receives positive or negative ions output from the connection point 8 in accordance with the output voltages of the positive side voltage rectifier circuit 11 and the negative side voltage rectifier circuit 12. A needle-like discharge electrode is provided.

  In this way, the current limiting resistor R1 is connected to the final stage of each of the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12, and an RC parallel circuit is formed by the current limit resistor R1 and the capacitor C1. By configuring, the rising and falling of the output voltage at the connection point 8 are improved, that is, the response of the high voltage applied to the electrode portion connected to the connection point 8 is improved.

Next, an experiment for confirming that the high voltage responsiveness at the connection point 8 has been improved by the power supply circuit for the static eliminator of the first embodiment will be described.
Specific experimental conditions are as follows.
The resistance value of the current limiting resistor R1 in the circuit of FIG. 1 is 50 [MΩ], and the capacities of all the capacitors C0 and C1 constituting the positive side and negative side voltage doubler rectifier circuits 11 and 12 are equal to 100 [pF]. It is said.
In this verification experiment, the output voltage at the connection point 8 was measured without connecting the electrode part to the connection point 8.

  In the power supply circuit of the first embodiment, a high frequency voltage having a positive and negative repetition period of 0.5 [Hz] is applied to the primary side of the step-up transformers T1 and T2, and the output of the positive side voltage doubler rectifier circuit 11 is applied. The output voltage at the connection point 8 between the terminal 6 and the output terminal 7 of the negative side voltage doubler rectifier circuit 12 was measured.

The measurement results are shown in FIGS. FIG. 2 is a graph showing the change with time of the output voltage at the connection point 8. FIG. 3A is a graph in which the rising portion A of the output voltage shown in FIG. 2 is enlarged, and FIG. Is a graph in which the falling portion B of the output voltage is enlarged.
As shown in FIGS. 2 and 3, in the power supply circuit of the first embodiment, the rise time of the output voltage at the connection point 8 is 2.5 [ms] and the fall time is 2.5 [ms].
In the first embodiment, the rise time and the fall time are 5.0 [ms] in one cycle, so that the output voltage can cope with the switching frequency between the positive side and the negative side of the input voltage up to 200 [Hz]. become.

Next, as Comparative Example 1, the rise and fall of the output voltage were measured for the static eliminator shown in FIG. The comparative example 1 corresponds to the conventional circuit shown in FIG.
In the static eliminator of Comparative Example 1, the current limiting resistor R1 is not connected in the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12, and the output is similar to the circuit described in Patent Document 1. A pair of current limiting resistors R1, R1 are connected between the terminals 6,7. A connection point 8 for connecting an electrode unit (not shown) is provided between the pair of current limiting resistors R1 and R1.
Other than that, the output voltage output to the connection point 8 was measured under the same experimental conditions while having the same configuration as that of the first embodiment.

The results are shown in FIGS. 5 (a) and 5 (b). 5A is a graph in which the rising portion A of the output voltage is enlarged, and FIG. 5B is a graph in which the falling portion B is enlarged.
As shown in FIG. 5, in this comparative example, the rise time is 7 [ms] and the fall time is 7 [ms]. The rise and fall times are about three times that of the circuit of the first embodiment. That is, it has been found that the circuit of this comparative example has poor rise and fall of the output voltage as compared with the first embodiment.
In other words, it is understood that the power supply circuit for the static eliminator of the first embodiment has a better response of the output voltage to be applied to the electrode portion than the comparative example that is a power supply circuit for the conventional static eliminator. It was.

FIG. 6 is a circuit diagram showing a second embodiment of the power supply circuit for the static eliminator of the present invention.
In the power supply circuit of the second embodiment, a current limiting resistor R1 for constituting an RC parallel circuit is provided in the transformer T1, T2 side stage of the plus side and minus side voltage doubler rectifier circuits 11, 12. . A capacitor on the transformer side provided with the current limiting resistor R1 is indicated by C1. The configuration other than the position where the current limiting resistor R1 is provided is the same as that of the first embodiment. The resistance value of the current limiting resistor R1 = 50 [MΩ], and the plus side and minus side voltage doubler rectifier circuits 11 and 12 are The capacities of all the capacitors C0 and C1 constituting the same are 100 [pF].

Also in the second embodiment, the output voltage at the connection point 8 was measured under the same experimental conditions as in the first embodiment. The results are shown in FIGS. 7 (a) and (b). 7A is a graph in which the rising portion A of the output voltage is enlarged, and FIG. 7B is a graph in which the falling portion B is enlarged.
As shown in FIG. 7, in the circuit of the second embodiment, the rise time is 3 [ms] and the fall time is 3 [ms], which indicates that the rise and fall are better than those in the comparative example. It was.

The power supply circuit according to the third embodiment shown in FIG. 8 includes an RC parallel circuit in which a current limiting resistor R1 is provided in the central stage in the plus side and minus side voltage doubler rectifier circuits 11 and 12. A capacitor on the transformer side provided with the current limiting resistor R1 is indicated by C1.
Except for the position where the limiting resistor R1 is provided, the configuration is the same as in the first and second embodiments. The resistance value of the current limiting resistor R1 is 50 [MΩ], and the positive side and negative side voltage doubler rectifier circuits 11 are used. , 12 have the same capacitance, which is 100 [pF].

Also in the third embodiment, the output voltage at the connection point 8 was measured under the same experimental conditions as in the first embodiment. The results are shown in FIGS. 9 (a) and 9 (b). 9A is a graph in which the rising portion A of the output voltage is enlarged, and FIG. 9B is a graph in which the falling portion B is enlarged.
As shown in FIG. 9, in the circuit of the third embodiment, the rise time is 2.5 [ms] and the fall time is 2.5 [ms]. It was found that the rise and fall are better than those.

As described above, the current limiting resistor R1 is provided in any one of the positive side and negative side voltage doubler rectifier circuits 11 and 12, and the RC parallel circuit is configured together with the capacitor C1 and the current limiting resistor R1 in this stage. As a result, it was found that the response of the output voltage at the connection point 8 is improved.
As a result, the RC parallel circuit is configured by providing the current limiting resistor R1 at any stage in the plus side and minus side voltage doubler rectifier circuits 11 and 12, and thus the capacitor C1 at this stage becomes the voltage doubler rectifier circuit 11. , 12 together with the boosting function, it can be considered that the function as a speed-up capacitor was exhibited.

Further, from the verification experiments of the first to third embodiments, the stage constituting the RC parallel circuit may be any stage in the voltage doubler rectifier circuits 11 and 12 in order to cause the capacitor C1 to exhibit the speed-up capacitor function. I understood that. In other words, it has been found that the output voltage response is improved in the same manner regardless of the stage provided with the current limiting resistor R1.
The stage where the current limiting resistor R1 is provided may not be the same stage in the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12.

FIG. 10 is a circuit diagram of a fourth embodiment in which a plurality of resistors r1 are used as the current limiting resistors R1 provided in the voltage doubler rectifier circuits 11 and 12.
In the fourth embodiment, instead of the current limiting resistor R1 of the first to third embodiments, 10 [MΩ] current limiting resistors r1 are respectively provided in the middle five stages of the voltage doubler rectifier circuits 11 and 12. Provided. The sum of the resistance values of the current limiting resistor r1 is made the same as the resistance value 50 [MΩ] of the current limiting resistor R1 of the other embodiment. That is, in all of the first to fourth embodiments, the total current limiting resistance value is 50 [MΩ].

A capacitor on the transformer side provided with the current limiting resistor r1 is denoted by C1.
In this way, the configuration other than providing a plurality of current limiting resistors r1 is the same as that of the other embodiments, and the capacities of all the capacitors C0 and C1 constituting the plus side and minus side voltage doubler rectifier circuits 11 and 12 are equal. 100 [pF].
An experiment was performed under the same conditions as in the first embodiment, and the output voltage at the connection point 8 was measured.

The result is shown in FIG. 11A is a graph in which the rising portion A of the output voltage is enlarged, and FIG. 11B is a graph in which the falling portion B is enlarged.
As shown in FIG. 11, in the fourth embodiment, the rise time is 5 [ms] and the fall time is 5 [ms]. The rise and fall time of one cycle is 10 [ms], and the rise and fall are slower than those of the other embodiments, but it has been confirmed that the responsiveness is improved compared to the comparative example shown in FIGS. did it.

Thus, even when the current limiting resistors are provided in a plurality of stages in the plus side and minus side voltage doubler rectifier circuits 11 and 12, the capacitor C1 constituting the RC parallel circuit functions as a speed-up capacitor as well as a boost function. It is thought that it demonstrates.
Further, even when the current limiting resistor r1 is provided in a plurality of stages and the RC parallel circuit is configured as in the fourth embodiment, the stage configuring the RC parallel circuit may be anywhere.

  When the current limiting resistors are divided into a plurality of parts as in the fourth embodiment, the response is worse than that of the first embodiment in which the current limiting resistors are combined into one, and the current limiting resistors are combined. There is a demerit that a large number of resistors r1 are required. However, by providing the resistors in a distributed manner, there is an advantage that the heat generation portion can be dispersed and the temperature rise of the apparatus can be suppressed. Furthermore, there is an advantage that the withstand voltage of each current limiting resistor r1 can be reduced. Furthermore, there is an advantage that the withstand voltage of each current limiting resistor r1 can be reduced.

  In the first to fourth embodiments, since the capacitor in the voltage doubler rectifier circuit can also function as a speed-up capacitor, the influence of the stray capacitance in the electrode portion connected to the connection point 8 is eliminated. It is not necessary to configure a separate circuit for the purpose outside the output terminals 6 and 7. Therefore, as compared with the case where a separate circuit is provided, there are advantages that the number of parts can be reduced and the circuit configuration can be simplified.

  As described above, the power supply circuit for the static eliminator of the present invention has a current limiting resistor connected in series to the diode at any stage of the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12. The responsiveness of the output voltage at the connection point 8 between the plus side and minus side voltage doubler rectifier circuits 11 and 12 can be improved.

When a power supply unit is connected to the connection point 8, the rise and fall of the output voltage at the connection point 8 is affected by the impedance.
For example, if the number of discharge electrode needles constituting the power supply unit increases, the stray capacitance of the power supply unit increases and the resistance value decreases. Therefore, when the power supply circuits of the first to fourth embodiments are used in an actual discharge device, the same output voltage responsiveness as that in the verification experiment is not always obtained. However, regardless of the impedance value of the power supply unit, the power supply circuit of the above embodiment does not change the output voltage responsiveness better than the power supply circuit of the comparative example shown in FIGS. .

Further, the primary side circuit of the high frequency step-up transformers T1 and T2 is not limited to that shown in FIG. 13, and any circuit that can alternately input a high frequency voltage to the plus side and the minus side may be used.
Furthermore, in the above embodiment, the voltage boosted by the high frequency boosting transformers T1 and T2 is input to the plus side voltage doubler rectifier circuit 11 and the minus side voltage doubler rectifier circuit 12, and further boosted to output a high voltage. However, the step-up transformer is not essential if the desired high voltage can be output.

An example of use of the power supply circuit of the first to fourth embodiments is shown in FIG.
FIG. 12 is an external view of a blower type static eliminator incorporating a power supply unit connected to the connection point 8 of the power supply circuit of the above embodiment.
This apparatus includes a fan 15 that is rotated by a motor 14 fixed in the center of the main body frame 13. When the fan 15 rotates, air is blown out of the main body from the opening 13a of the main body frame 13.
Further, a cover is provided outside the main body frame 13 so that a human hand or the like does not enter the main body frame 13. The cover is provided with an opening that does not obstruct air blowing from the opening 13a and air suction from the back side.

Further, sockets 16 are fixed to the back side of the fan 15 corresponding to the four corners of the main body frame 13. The four sockets 16 are each attached with a discharge electrode needle 17 whose tip is directed toward the center of the main body frame 13, and a high voltage cable 18 connected in parallel to the connection point 8 in the power supply circuit of the above embodiment. doing.
Therefore, a high voltage output from the power supply circuit is applied to the electrode needles 17.

Since such a blow-type static eliminator has good response of the output voltage output from the power supply circuit, the discharge electrode needle 17 has a positive high voltage and a negative high voltage that are sufficiently boosted. It is applied alternately. Therefore, a sufficient amount of ions are generated by each discharge electrode needle 17 and the ions are radiated by the fan 15, so that efficient and reliable neutralization can be performed.
Although the blower type static eliminator provided with the fan 15 shown in FIG. 12 has been described here, the power supply circuit of each of the above embodiments is not limited to this type of static eliminator.
Further, the number of discharge electrodes connected to the connection point 8 is not limited to the above use example.

  Since the power supply circuit for the static eliminator of the present invention has high responsiveness to the high voltage applied to the discharge electrode of the electrode part, the amount of ions generated is large and can be applied to uniform static elimination of the moving charged object.

8 Connection point 11 Positive side voltage rectifier circuit 12 Negative side voltage rectifier circuit C0 Capacitor C1 Capacitor D Diode R1 Current limiting resistor r1 Current limiting resistor

Claims (2)

In order to boost the high-frequency voltage to a positive high voltage, the positive-side voltage doubler rectifier circuit including a plurality of pairs of diodes and capacitors, and the positive-side voltage doubler rectifier circuit to boost the high-frequency voltage to a negative high voltage. Between the negative side voltage doubler rectifier circuit provided with a plurality of pairs of diodes and capacitors that are opposite to each other, and between the output terminal of the positive side voltage doubler rectifier circuit and the output terminal of the negative side voltage doubler rectifier circuit, To connect an electrode portion having one or a plurality of discharge electrodes that generate positive ions and negative ions by application of a high voltage output of the plus side voltage doubler rectifier circuit and a high voltage output of the minus side voltage doubler rectifier circuit. And the capacitances of all the capacitors constituting the plus side voltage doubler rectifier circuit and the minus side voltage doubler rectifier circuit are equalized, and A in each of the at least one stage side voltage doubler rectifier circuit and the negative-side voltage doubler circuit, said output terminal in series with the diode is connected, and, connected in parallel with the capacitor in the stage circuit during, and connect the current-limiting series resistor to the diode, to the capacitor constituting the RC parallel circuit between the current limiting resistor, the boost function and discharging device, characterized in that to exert the function of the speed-up capacitor Power supply circuit. The current limiting resistor is connected to a diode connected in series with the output terminal in one stage of each of the plus side voltage doubler rectifier circuit and the minus side voltage doubler circuit, and a capacitor in the stage. The power supply circuit for the static eliminator according to claim 1, wherein a current limiting resistor is connected in series with the diode in a circuit connected in parallel with the diode.

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