JP4684149B2 - Manufacturing method of surface mount module - Google Patents

Manufacturing method of surface mount module Download PDF

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JP4684149B2
JP4684149B2 JP2006087803A JP2006087803A JP4684149B2 JP 4684149 B2 JP4684149 B2 JP 4684149B2 JP 2006087803 A JP2006087803 A JP 2006087803A JP 2006087803 A JP2006087803 A JP 2006087803A JP 4684149 B2 JP4684149 B2 JP 4684149B2
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electronic component
resin
resin film
wiring board
conductive pad
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JP2007266212A (en
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国英 岩元
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Kyocera Corp
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

本発明は、配線基板の表面に電子部品を実装する表面実装モジュールの製造方法に関し、特に電子部品実装領域に加えて、電子部品と配線基板とを電気的に接続する導電パッドが配線基板の表面に形成された表面実装モジュールの製造方法に関する。   The present invention relates to a method for manufacturing a surface mount module for mounting an electronic component on the surface of a wiring board, and in particular, in addition to the electronic component mounting area, a conductive pad for electrically connecting the electronic component and the wiring board is provided on the surface of the wiring board. The present invention relates to a method for manufacturing a surface mount module formed in the above.

近年、半導体チップやコンデンサなどの電子部品を配線基板の上面に実装した表面実装モジュールが開発されており、この表面実装モジュールの小型化に伴い、これに実装される電子部品の小型化、実装密度を高めることが要求されて、電子部品を配線基板の上面に直接半田付けする方法が用いられている。   In recent years, surface mount modules in which electronic components such as semiconductor chips and capacitors are mounted on the upper surface of a wiring board have been developed. With the miniaturization of this surface mount module, the size and mounting density of electronic components mounted thereon are reduced. Therefore, a method of directly soldering an electronic component to the upper surface of a wiring board is used.

また、上記表面実装モジュールにおいては、電子部品と配線基板とを電気的に接続するための導電パッドを電子部品実装領域に加えて配線基板の表面に形成して、電子部品実装した後で電子部品と導電パッドとをボンディングワイヤで電気的に接続することが行われている。なお、この導電パッドは配線基板の表面に剥き出しで存在する。   Further, in the surface mount module, a conductive pad for electrically connecting the electronic component and the wiring board is formed on the surface of the wiring board in addition to the electronic component mounting area, and the electronic component is mounted after the electronic component is mounted. And a conductive pad are electrically connected by a bonding wire. The conductive pads are exposed on the surface of the wiring board.

かかる表面実装モジュールにおける電子部品の半田付け方法は、半田粉末にフラックスを混練した半田ペーストを配線基板の所定の位置にスクリーン印刷法などによって印刷塗布した後、この上面に電子部品を載置してリフロー炉を通し、リフロー炉内で半田ペーストを溶融させて配線基板と電子部品とを半田付けする方法が採られている。   A soldering method for electronic components in such a surface mount module is to apply a solder paste obtained by kneading flux to solder powder to a predetermined position of a wiring board by screen printing or the like, and then place the electronic component on this upper surface. A method of soldering a wiring board and an electronic component by passing a reflow furnace and melting a solder paste in the reflow furnace is employed.

上記方法においては、半田ペーストが溶融する際にその一部が飛散して、導電パッドの上面に付着してしまい、これが導電パッドとボンディングワイヤとの接着を阻害して電気的接続の信頼性が損なわれるという不具合があった。そこで、従来この種の実装方法では、半田付けした後にモジュールごと洗浄して飛散した半田粒を除去する工程を追加せざるを得ず、不経済であるとともに大量の洗浄液を使用するために環境に悪影響を及ぼす等の問題があった。   In the above method, when the solder paste is melted, a part of the solder paste is scattered and adheres to the upper surface of the conductive pad. This obstructs the adhesion between the conductive pad and the bonding wire, and the reliability of the electrical connection is increased. There was a problem of being damaged. Therefore, in this conventional mounting method, it is necessary to add a process of cleaning the module after soldering and removing scattered solder particles, which is uneconomical and uses a large amount of cleaning liquid. There were problems such as adverse effects.

そのため、リフロー加熱時に導体パッドの表面に半田が付着することを防止するために、耐熱性を有する樹脂膜で導電パッドの表面を覆ってリフロー加熱し、リフロー加熱後に樹脂膜を剥がすことが行われている。   Therefore, in order to prevent the solder from adhering to the surface of the conductor pad during reflow heating, the surface of the conductive pad is covered with a heat-resistant resin film and then reflow heated, and the resin film is peeled off after reflow heating. ing.

ところが、従来の樹脂膜では、リフロー加熱した後で樹脂膜を導電パッドの表面から剥離する際に剥離した後に樹脂膜の一部の有機物成分が残留して樹脂残りとなってしまい、導電パッドとボンディングワイヤとの接合状態が悪くなることから、溶剤等で洗浄をする必要があった。また、樹脂膜の耐熱性が悪い場合には、樹脂膜の引っ張り強度や引き裂き強度が低下して剥離できないという不具合があった。特に、環境を考慮した鉛を含まないいわゆる「鉛フリー半田」を用いた場合には、半田の融点が高くてリフロー炉の温度を高く設定する必要があり、樹脂膜の樹脂残りや強度低下が顕著であった。   However, in the conventional resin film, after peeling off the resin film from the surface of the conductive pad after reflow heating, a part of the organic component of the resin film remains and remains as a resin. Since the bonding state with the bonding wire is deteriorated, it is necessary to clean with a solvent or the like. In addition, when the heat resistance of the resin film is poor, there is a problem that the tensile strength and tear strength of the resin film are lowered and the resin film cannot be peeled off. In particular, when using so-called “lead-free solder” that does not contain lead in consideration of the environment, the melting point of the solder is high and the temperature of the reflow furnace needs to be set high. It was remarkable.

そこで、特許文献１では、プリント配線基板の表面に半田付けする際に、半田耐熱用マスキングテープとして、含浸紙と繊維とを混抄した支持基材の片面にシリコンアクリル共重合体樹脂とアクリル酸エステル共重合体樹脂とを混合した樹脂を塗工したものが開示され、樹脂の残存がなくかつテープを剥がすときに途中で切れたりすることがないことが記載されている。
特開２００５−２５５９２２号公報 Therefore, in Patent Document 1, when soldering to the surface of a printed wiring board, a silicon acrylic copolymer resin and an acrylate ester are provided on one side of a supporting base material obtained by mixing impregnated paper and fibers as a solder heat-resistant masking tape. A coating of a resin mixed with a copolymer resin is disclosed, and it is described that there is no residual resin and that the resin is not cut off when the tape is peeled off.
JP 2005-255922 A

しかしながら、特許文献１の耐熱用マスキングテープでは、マスキングテープに塗布される時点でシリコンアクリル共重合体樹脂とアクリル酸エステル共重合体樹脂の一部が重合などの架橋反応が未反応で、加熱によって架橋反応が進行するために粘弾率を高めて樹脂残りを防止しているものの、架橋反応する際に表面に−ＯＨ基が多数存在する配線基板を用いた場合には配線基板の−ＯＨ基と未反応の樹脂とが反応して強固に固着することがあった。また、マスキングテープを剥がした際に導電パッドの表面において目視できるほどの樹脂残りはなくなるものの、目視できない程度の有機物成分を除去することはできず、その後に導電パッドの表面にてボンディングワイヤを接着する際に接続不良が発生する場合があった。   However, in the heat-resistant masking tape of Patent Document 1, when the silicone acrylic copolymer resin and the acrylate copolymer resin are partially applied to the masking tape, the crosslinking reaction such as polymerization is unreacted, and by heating Although the viscoelasticity is increased to prevent the resin residue because the crosslinking reaction proceeds, the -OH group of the wiring board is used when a wiring board having a large number of -OH groups on the surface during the crosslinking reaction is used. And unreacted resin may react and be firmly fixed. Also, when the masking tape is peeled off, there is no visible resin residue on the surface of the conductive pad, but organic components that cannot be visually observed cannot be removed, and then the bonding wire is bonded to the surface of the conductive pad. In some cases, poor connection may occur.

本発明は上記課題を解決するためになされたもので、配線基板の表面に樹脂が残ってボンディングワイヤを接続する際の接続不良を発生することがない表面実装モジュールの製造方法を提供することを目的とする。   The present invention has been made to solve the above-described problems, and provides a method for manufacturing a surface-mount module in which a resin remains on the surface of a wiring board and connection failure does not occur when bonding wires are connected. Objective.

本発明の表面実装モジュールの製造方法は、（ａ）配線基板の表面に、第１の電子部品を半田付けにより前記配線基板に設けられた配線と電気的に接続するための半田付け用導電パッドと、前記配線基板の前記表面の第２の電子部品実装領域に固定される第２の電子
部品の接続端子とボンディングワイヤを介して接続される、前記第２の電子部品と前記配線基板に設けられた配線とを電気的に接続するワイヤボンディング接続用導電パッドとを形成する工程と、（ｂ）前記ワイヤボンディング接続用導電パッドの表面に、アクリル樹脂をモノマー換算した時のモル数をｍＡ、リン酸エステルのモル数をｍＰとしたときのｍＰの比率（ｍＰ／（ｍＡ＋ｍＰ））が０．３〜０．５の割合からなり、かつ合計量が８０質量％以上のアクリル樹脂とリン酸エステルを含有する樹脂ペーストを塗布して、前記ワイヤボンディング接続用導電パッドの表面を樹脂膜で覆うとともに、前記半田付け用導電パッドの表面に半田ペーストを塗布する工程と、（ｃ）（ｂ）工程で得られた前記半田ペーストを塗布した半田付け用導電パッドに前記第１の電子部品を載置した状態でリフロー加熱して半田付けするとともに、前記第２の電子部品実装領域に前記第２の電子部品を固定する工程と、（ｄ）（ｃ）工程で得られた配線基板から前記樹脂膜を剥離するとともに、前記ワイヤボンディング接続用導電パッドの表面の有機物成分を除去する工程と、（ｅ）（ｄ）工程で露出した前記ワイヤボンディング接続用導電パッドと前記第２の電子部品の接続端子とをボンディングワイヤにて接続する工程とを具備することを特徴とするものである。 The method for manufacturing a surface mount module according to the present invention includes: (a) a soldering conductive pad for electrically connecting a first electronic component to a wiring provided on the wiring board by soldering on the surface of the wiring board; And a second electronic component connected to a connection terminal of a second electronic component fixed to the second electronic component mounting region on the surface of the wiring substrate via a bonding wire, and provided on the wiring substrate forming a wire bonding connection conductive pads for connecting wires and which is electrically, (b) in the wire bonding connection conductive surface of the pad, the number of moles of when the acrylic resin was in terms of monomer m a the ratio of m P when the number of moles of phosphoric acid ester and a m P (m P / (m a + m P)) consists ratio of 0.3 to 0.5, and the total amount is 80 mass% or more Acrylic tree Applying a resin paste containing fat and phosphate ester, covering the surface of the wire bonding connection conductive pad with a resin film, and applying the solder paste to the surface of the soldering conductive pad; ) In the state where the first electronic component is placed on the soldering conductive pad to which the solder paste obtained in the step (b) is applied, it is soldered by reflow heating, and the second electronic component mounting region Fixing the second electronic component to the substrate, and removing the resin film from the wiring substrate obtained in steps (d) and (c), and removing organic components on the surface of the wire bonding connection conductive pad. And a step of connecting the wire bonding connection conductive pad exposed in steps (e) and (d) and a connection terminal of the second electronic component with a bonding wire. It is characterized in that it comprises a.

ここで、上記構成において、前記樹脂ペースト中にさらに無機質フィラーを３〜１０質量％の割合で添加することが望ましい。   Here, in the said structure, it is desirable to add an inorganic filler in the ratio of 3-10 mass% further in the said resin paste.

また、上記構成において、（ｂ）工程において、樹脂ペーストを厚みが４０〜１００μｍで塗布することが望ましい。   Moreover, in the said structure, it is desirable to apply | coat resin paste with a thickness of 40-100 micrometers in the (b) process.

本発明の表面実装モジュールの製造方法によれば、導電パッドの表面に樹脂膜を形成するための樹脂ペーストとして、アクリル樹脂とリン酸エステルを総量で８０質量％以上含有するものとすることによって、加熱によって架橋反応が起こることがないので、表面に−ＯＨ基が多数存在する配線基板を用いた場合であっても配線基板表面の−ＯＨ基と未反応の樹脂とが反応して強固に固着してしまうことがなく、樹脂膜を剥がした時にボンディングワイヤを接続するための導体パッドの表面に目視できるような樹脂残りが発生することがない。また、樹脂膜を剥がした際に導電パッドの表面に存在してボンディングワイヤの接続不良を生じるような有機物成分を除去することができて、その後に導電パッドの表面にてボンディングワイヤを接合しても接続不良が発生することなく、良好な接続状態とすることができる。   According to the method for manufacturing a surface mount module of the present invention, as a resin paste for forming a resin film on the surface of a conductive pad, the acrylic resin and phosphate ester are contained in a total amount of 80% by mass or more. Since no cross-linking reaction occurs by heating, even when a wiring board having many —OH groups on the surface is used, the —OH group on the wiring board surface reacts with the unreacted resin and is firmly fixed. Therefore, when the resin film is peeled off, no visible resin residue is generated on the surface of the conductor pad for connecting the bonding wire. In addition, organic components that exist on the surface of the conductive pad when the resin film is peeled off and cause bonding failure of the bonding wire can be removed, and then the bonding wire is bonded on the surface of the conductive pad. Also, a good connection state can be obtained without causing connection failure.

ここで、前記樹脂ペースト中にさらに無機質フィラーを３〜１０質量％の割合で添加することによって、樹脂ペーストの印刷性および保形性が良く、樹脂膜の外周部ににじみやダレが発生することを抑制できる。   Here, by further adding an inorganic filler in a proportion of 3 to 10% by mass in the resin paste, the printability and shape retention of the resin paste are good, and bleeding and sagging occur in the outer peripheral portion of the resin film. Can be suppressed.

また、（ｂ）工程において、樹脂ペーストを厚みが４０〜１００μｍで塗布することによって、樹脂膜を剥がす際に樹脂膜が破れたりしない。また、リフロー加熱する前に樹脂ペーストを印刷してから半田ペーストを印刷する場合には、印刷した樹脂膜の存在によって半田ペーストの印刷性が阻害されることもない。   Moreover, in the step (b), the resin film is not torn when the resin film is peeled off by applying the resin paste with a thickness of 40 to 100 μm. In addition, when the solder paste is printed after the resin paste is printed before the reflow heating, the printability of the solder paste is not hindered by the presence of the printed resin film.

以下、本発明の表面実装モジュールの製造方法の好適例を示す工程毎の断面図である図１（ａ）〜（ｅ）を参照しつつ詳細に説明する。   Hereinafter, it demonstrates in detail, referring FIG.1 (a)-(e) which is sectional drawing for every process which shows the suitable example of the manufacturing method of the surface mount module of this invention.

（ａ）工程
まず、図１に示す例においては、（ａ）工程に用いる配線基板１は、絶縁基板１ａと導体配線層１ｂと裏面保護膜１ｃとで構成されている。絶縁基板１ａとしては、Ａｌ２Ｏ３、ＡｌＮ、Ｓｉ３Ｎ４、ガラスセラミックス等のセラミックス、または有機樹脂が用いられるが、中でも、後述する第１の電子部品や第２の電子部品が動作することによって発熱して配線基板１が高温になる場合には、Ａｌ２Ｏ３、ＡｌＮまたはＳｉ３Ｎ４のセラミック配線基板が好適である。また、単層または複数層の絶縁基板１ａの表面および内部に形成される導体配線層１ｂは、主成分がＷ、ＭｏまたはＣｕからなり所定の配線パターンをなしている。 (A) Process First, in the example shown in FIG. 1, the wiring board 1 used for the (a) process is comprised by the insulating substrate 1a, the conductor wiring layer 1b, and the back surface protective film 1c. As the insulating substrate 1a, ceramics such as Al 2 O 3 , AlN, Si 3 N 4 , glass ceramics, or organic resins are used, and among them, the first electronic component and the second electronic component described later operate. When the wiring board 1 becomes hot due to heat generation, a ceramic wiring board made of Al 2 O 3 , AlN or Si 3 N 4 is preferable. The conductor wiring layer 1b formed on the surface and inside of the single-layer or multiple-layer insulating substrate 1a is mainly composed of W, Mo, or Cu and forms a predetermined wiring pattern.

また、配線基板１の上面には配線パターンの一部として導体パッド２が形成されている。図１（ａ）に示す例においては、導体パッド２として、第１の電子部品４の接続端子４ａと半田付けによって接続される導体パッド２ａ、第２の電子部品５を接着固定する導体パッド２ｂ、第２の電子部品５の上面に存在する接続端子５ａとワイヤボンディングにより接続されるワイヤボンディング接続用導体パッド（以下、ＷＢ導体パッドと略す。）２ｃが形成される。なお、導体パッド２は、導体配線層１ｂと同じく、主成分がＷ、ＭｏまたはＣｕからなり、所望により、その表面にニッケル（Ｎｉ）メッキや金（Ａｕ）メッキ（図示せず）を施したものからなる。   A conductor pad 2 is formed on the upper surface of the wiring board 1 as a part of the wiring pattern. In the example shown in FIG. 1A, as the conductor pad 2, a conductor pad 2a connected to the connection terminal 4a of the first electronic component 4 by soldering, and a conductor pad 2b for bonding and fixing the second electronic component 5 together. Then, a wire bonding connection conductor pad (hereinafter abbreviated as WB conductor pad) 2c connected to the connection terminal 5a existing on the upper surface of the second electronic component 5 by wire bonding is formed. The conductor pad 2 is composed of W, Mo or Cu as the main component, like the conductor wiring layer 1b, and the surface thereof is subjected to nickel (Ni) plating or gold (Au) plating (not shown) as desired. Consists of things.

さらに、図１（ａ）に示す例においては、絶縁基板１ａの下面に導体配線層１ｂのサイズを調整（トリミング）して抵抗の大きさを調整した抵抗パターン等（図示せず）が形成されており、このトリミングの際に生じる傷を保護するための裏面保護膜１ｃが配線基板１の下面のほぼ全面にわたって形成されている。   Further, in the example shown in FIG. 1A, a resistance pattern or the like (not shown) is formed on the lower surface of the insulating substrate 1a by adjusting (trimming) the size of the conductor wiring layer 1b to adjust the resistance. A back surface protective film 1c for protecting scratches generated during the trimming is formed over almost the entire lower surface of the wiring board 1.

（ｂ）工程
次に、少なくともＷＢ導体パッド２ｃの表面に樹脂ペーストを塗布して樹脂膜８を被着形成する。本発明によれば、樹脂ペーストとして、アクリル樹脂をモノマー換算した時のモル数をｍＡ、リン酸エステルのモル数をｍＰとしたときのｍＰの比率（ｍＰ／（ｍＡ＋ｍＰ））が０．３〜０．５の割合からなり、かつ合計量が８０質量％以上のアクリル樹脂とリン酸エステルを含有するものを用いること、すなわち架橋反応を起こす成分の含有量がほとんどないことが、樹脂膜８がＷＢ導体パッド２ｃの表面の−ＯＨ基と反応して固着することなく、樹脂膜８をＷＢ導体パッド２ｃの表面から剥がす際に樹脂膜８の一部が樹脂残りとして残存することを防止するために重要である。これによって、後述するリフロー加熱によっても架橋反応が起こることがないので、絶縁基板１ａの表面に−ＯＨ基が多数存在する場合であっても絶縁基板１ａと反応することがなく、樹脂膜８を剥がした際にも目視できるような樹脂残りが発生することがない。また、樹脂膜８を後述するリフロー加熱した後で剥がした際にも、ＷＢ導体パッド２ｃの表面に存在してボンディングワイヤ７の接続不良を生じるような有機物成分を除去することができて、その後にＷＢ導体パッド２ｃの表面にてボンディングワイヤ７を接合しても接続不良が発生することなく、良好な接続状態とすることができる。 (B) Step Next, a resin paste is applied to at least the surface of the WB conductor pad 2c to form a resin film 8 thereon. According to the present invention, as the resin paste, the number of moles of when the acrylic resin was in terms of monomer m A, the ratio of m P when the number of moles of phosphoric acid ester and a m P (m P / (m A + m P )) Is composed of a ratio of 0.3 to 0.5, and the total amount is 80% by mass or more containing an acrylic resin and a phosphate ester, that is, there is almost no content of a component that causes a crosslinking reaction. However, when the resin film 8 is peeled off from the surface of the WB conductor pad 2c without the resin film 8 reacting and fixing with the -OH group on the surface of the WB conductor pad 2c, a part of the resin film 8 becomes a resin residue. It is important to prevent it from remaining. As a result, a cross-linking reaction does not occur even by reflow heating described later, so that even if a large number of -OH groups are present on the surface of the insulating substrate 1a, the resin film 8 is not reacted with the insulating substrate 1a. Resin residue that can be visually observed even when peeled off does not occur. In addition, even when the resin film 8 is peeled off after reflow heating described later, organic components that are present on the surface of the WB conductor pad 2c and cause poor connection of the bonding wire 7 can be removed. Even if the bonding wire 7 is bonded to the surface of the WB conductor pad 2c, a good connection state can be obtained without causing a connection failure.

なお、樹脂ペーストに含有されるリン酸エステルは加熱によって一部が分解してリン酸を生成し、生成したリン酸がＷＢ導体パッド２ｃの表面に存在する有機物成分を吸収する作用を持つことから、ＷＢ導体パッド２ｃの表面の有機物成分が樹脂膜８内部に拡散によって移動する。その結果、リフロー加熱した後に樹脂膜８を剥離すると樹脂膜８とともに有機物成分も除去されて、ＷＢ導体パッド２ｃの表面の有機物分が除かれて清浄化される。   The phosphoric acid ester contained in the resin paste is partially decomposed by heating to generate phosphoric acid, and the generated phosphoric acid has an action of absorbing organic components present on the surface of the WB conductor pad 2c. The organic component on the surface of the WB conductor pad 2c moves into the resin film 8 by diffusion. As a result, when the resin film 8 is peeled after reflow heating, the organic component is also removed together with the resin film 8, and the organic matter on the surface of the WB conductor pad 2c is removed and cleaned.

ここで、上記ｍＰの比率（ｍＰ／（ｍＡ＋ｍＰ））が０．３よりも低いと、樹脂膜８の耐熱性が低下してリフロー加熱により樹脂膜８が変質するか、またはＷＢ導体パッド２ｃの表面の浄化作用が低下してボンディングワイヤの接合強度が低下する可能性がある。一方、ｍＰの比率（ｍＰ／（ｍＡ＋ｍＰ））が０．５を超えると、樹脂膜８の保形性や引張り強度が低下してリフロー加熱の後に絶縁基板１ａの表面から樹脂膜８を引き剥がすことができない。さらに、アクリル樹脂とリン酸エステルの合計量が８０質量％よりも少ないと、樹脂膜８の保形性や引張り強度が低く、また、樹脂ペースト中に加熱によって架橋反応を起こす樹脂を含有せしめた場合には、加熱した際の架橋反応によって樹脂膜８がＷＢ導体パッド２ｃと反応して強固に固着してＷＢ導体パッド２ｃの表面に樹脂膜８の一部が樹脂残りとして残ってしまうことがある。 Here, the ratio of the m P (m P / (m A + m P)) is less than 0.3, or a resin film 8 by reflow heating heat-resistant resin film 8 is lowered is altered, or There is a possibility that the purification effect of the surface of the WB conductor pad 2c is lowered and the bonding strength of the bonding wire is lowered. On the other hand, when the ratio of m P (m P / (m A + m P)) exceeds 0.5, the resin from the surface of the insulating substrate 1a shape retention and tensile strength of the resin film 8 is lowered after the reflow heating The film 8 cannot be peeled off. Furthermore, if the total amount of the acrylic resin and the phosphate ester is less than 80% by mass, the shape retention and tensile strength of the resin film 8 are low, and the resin paste contains a resin that causes a crosslinking reaction by heating. In some cases, the resin film 8 reacts with the WB conductor pad 2c and is firmly fixed by a crosslinking reaction when heated, and a part of the resin film 8 remains as a resin residue on the surface of the WB conductor pad 2c. is there.

ここで、樹脂ペースト中にさらに無機質フィラー（図示せず）を３〜１０質量％の割合で添加せしめることによって、樹脂ペーストの印刷性および保形性が良く、樹脂ペーストを印刷した樹脂膜８の外周部ににじみやダレが発生することを抑制することができる。   Here, by adding an inorganic filler (not shown) in the resin paste at a ratio of 3 to 10% by mass, the printability and shape retention of the resin paste are good, and the resin film 8 on which the resin paste is printed. It is possible to suppress bleeding and sagging at the outer peripheral portion.

また、樹脂ペーストを厚みが４０〜１００μｍで塗布すると、樹脂膜８を剥がす際に樹脂膜８が破れたりしない。また、リフロー加熱する前に樹脂ペーストを印刷してから半田ペーストを印刷する場合には、印刷した樹脂膜８の存在によって半田ペーストの印刷性が阻害されることもない点で望ましい。   Further, when the resin paste is applied with a thickness of 40 to 100 μm, the resin film 8 is not torn when the resin film 8 is peeled off. Further, when the solder paste is printed after the resin paste is printed before the reflow heating, it is desirable that the printability of the solder paste is not hindered by the presence of the printed resin film 8.

さらに、樹脂ペーストは架橋反応が発生することがないので、樹脂ペーストの粘度が、２５℃、湿度６０％の環境下で１２０日放置した前後における上昇率が２００％以下と経時変化が小さく、安定した印刷性を有する結果、作製日によって印刷された樹脂膜８の形成状態が変動することなく、均一な厚みの樹脂膜８の形成が可能である。   Furthermore, since no cross-linking reaction occurs in the resin paste, the increase rate before and after leaving the resin paste in an environment of 25 ° C. and 60% humidity for 120 days is 200% or less, and the change with time is small and stable. As a result of having the printability, it is possible to form the resin film 8 having a uniform thickness without changing the formation state of the printed resin film 8 depending on the production date.

なお、図２に（ア）（ｂ）工程における配線基板を上から見た平面図であり、樹脂膜８の形成領域の一例を示す図（参考として（イ）本実施態様を経て得られる表面実装モジュール２０を上から見た平面図）に示すように、ＷＢ導体パッド２ｃが複数個近接して存在する場合には、これらを一括して１つの樹脂膜８で被覆することもできる。   2 is a plan view of the wiring board in the steps (a) and (b) as seen from above, and shows an example of the formation region of the resin film 8 (for reference, (b) the surface obtained through this embodiment. As shown in the plan view of the mounting module 20 as viewed from above, when a plurality of WB conductor pads 2c are present close to each other, they can be collectively covered with one resin film 8.

そして、図１によれば、第１の電子部品に接続される導体パッド２ａの上面に半田ペーストを用い、スクリーン印刷法、ディスペンサ法、転写法等にて半田パターン３を形成する。なお、この工程において、樹脂膜８の塗布工程と半田ペーストの塗布工程とは順序を入れ替えて、半田ペーストを塗布した後に樹脂膜８を塗布してもよい。   Then, according to FIG. 1, a solder paste 3 is formed on the upper surface of the conductor pad 2a connected to the first electronic component, using a screen printing method, a dispenser method, a transfer method, or the like. In this step, the resin film 8 application step and the solder paste application step may be interchanged, and the resin film 8 may be applied after the solder paste is applied.

（ｃ）工程
次に、図１（ｃ）に示すように、第１の電子部品４をこの半田パターン３の上面に第１の電子部品４の接続端子４ａが配置されるように載置する。図１における電子部品は、抵抗やコンデンサ、ダイオード等の一般の電子部品や、下面に接続端子を有するチップ部品等の第１の電子部品４と、図１（ｃ’）以降に示した、上面側の表面に３００μｍ以下の間隙で複数個の電極を具備するチップ部品等の第２の電子部品５とに大別される。 (C) Process Next, as shown in FIG.1 (c), the 1st electronic component 4 is mounted so that the connection terminal 4a of the 1st electronic component 4 may be arrange | positioned on the upper surface of this solder pattern 3. FIG. . The electronic components in FIG. 1 are a general electronic component such as a resistor, a capacitor, and a diode, a first electronic component 4 such as a chip component having a connection terminal on the lower surface, and the upper surface shown in FIG. It is roughly classified into a second electronic component 5 such as a chip component having a plurality of electrodes with a gap of 300 μm or less on the side surface.

なお、半田粒６は、半田ペーストを用いこれを加熱して半田付けする時、半田の溶融に伴って半田ペースト中のフラックス成分が蒸発するが、このフラックス成分が蒸発する際に溶融した半田が一緒に飛び散ることによって発生する直径３００μｍ以下の粒状の半田である。   The solder particles 6 are soldered using a solder paste, and when the solder is soldered, the flux component in the solder paste evaporates as the solder melts. It is a granular solder having a diameter of 300 μm or less generated by scattering together.

そして、図１（ｃ’）に示すように、第１の電子部品４の下面に形成された接続端子４ａを配線基板１の半田パターン３の上面に位置するように第１の電子部品４を載置した状態で配線基板１をリフロー加熱する。これによって、半田パターン３中の半田成分を溶融させて第１の電子部品４の接続端子４ａを配線基板１上面の導体パッド２ａに半田層２１で半田付けして、第１の電子部品４を配線基板１の上面に実装する。   Then, as shown in FIG. 1C ′, the first electronic component 4 is placed so that the connection terminals 4a formed on the lower surface of the first electronic component 4 are positioned on the upper surface of the solder pattern 3 of the wiring board 1. The wiring board 1 is reflow-heated in the mounted state. As a result, the solder component in the solder pattern 3 is melted, and the connection terminals 4a of the first electronic component 4 are soldered to the conductor pads 2a on the upper surface of the wiring board 1 by the solder layer 21, thereby the first electronic component 4 is mounted. Mounted on the upper surface of the wiring board 1.

ここで、このリフロー加熱時には、半田パターン３中の半田成分が溶融すると同時に半田パターン３中のフラックス成分が半田成分とともに周囲に飛散して、樹脂膜８の表面や第１の電子部品４の周囲、上面等にランダムに半田粒６が付着する。   Here, at the time of the reflow heating, the solder component in the solder pattern 3 is melted, and at the same time, the flux component in the solder pattern 3 is scattered around with the solder component, so that the surface of the resin film 8 and the first electronic component 4 are surrounded. The solder particles 6 randomly adhere to the upper surface or the like.

従来の半田付け方法であれば、この飛散して付着した半田粒６を洗浄により除去するのであるが、本発明によれば、この工程で得られた第１の電子部品４が半田付けされた配線基板１を洗浄することなく、樹脂膜８の表面に付着した半田粒６を樹脂膜８ごと除去することができる。また、図１に示す本実施態様によれば、第２の電子部品５はリフロー炉を通すことなくかつ局所的に半田付けされているので、上面に半田粒６が付着すると短絡するおそれのある第２の電子部品５にも半田粒６が付着することがない。   According to the conventional soldering method, the scattered solder particles 6 are removed by washing. According to the present invention, the first electronic component 4 obtained in this step is soldered. The solder particles 6 attached to the surface of the resin film 8 can be removed together with the resin film 8 without cleaning the wiring substrate 1. In addition, according to the present embodiment shown in FIG. 1, the second electronic component 5 is locally soldered without passing through a reflow furnace, so there is a risk of short circuit if the solder particles 6 adhere to the upper surface. The solder particles 6 do not adhere to the second electronic component 5 as well.

次に、本実施態様では、図１（ｃ’’）に示すように、第１の電子部品４を実装した配線基板１に対して、第１の電子部品４からの最短距離が１〜１０ｍｍ離間した位置に加熱によって第２の電子部品５を半田付けする半田層２２を形成する半田箔を載置し、半田箔の上面に第２の電子部品５を載置して、半田箔を赤外線照射またはレーザー照射によって加熱して第２の電子部品５を配線基板１の上面に半田付けして第２の電子部品５を配線基板１の上面に固定することによって、配線基板１の上面に第１の電子部品４と第２の電子部品５とを実装することができる。   Next, in this embodiment, as shown in FIG. 1C ″, the shortest distance from the first electronic component 4 to the wiring board 1 on which the first electronic component 4 is mounted is 1 to 10 mm. A solder foil for forming a solder layer 22 for soldering the second electronic component 5 by heating is placed at a spaced position, the second electronic component 5 is placed on the upper surface of the solder foil, and the solder foil is infrared The second electronic component 5 is soldered to the upper surface of the wiring substrate 1 by heating by irradiation or laser irradiation, and the second electronic component 5 is fixed to the upper surface of the wiring substrate 1, so that the second electronic component 5 is fixed on the upper surface of the wiring substrate 1. One electronic component 4 and second electronic component 5 can be mounted.

（ｄ）工程
上記工程で電子部品４，５を半田付けした後、配線基板１の表面からテープ状に接着している樹脂膜８を端から引っ張って引き剥がす。これによって、表面が清浄化されたＷＢ導体パッド２ｃが露出する。本発明によれば、樹脂膜８は耐熱性が高くかつ引張強度が高いので、樹脂膜８を剥離する際に樹脂膜８が切れたり、樹脂膜８が変質して残ったりすることがない。 (D) Process After the electronic components 4 and 5 are soldered in the above process, the resin film 8 bonded in a tape shape from the surface of the wiring substrate 1 is pulled from the end and peeled off. As a result, the WB conductor pad 2c whose surface is cleaned is exposed. According to the present invention, since the resin film 8 has high heat resistance and high tensile strength, the resin film 8 is not cut when the resin film 8 is peeled off, and the resin film 8 is not altered and remains.

（ｅ）工程
（ｄ）工程で露出したＷＢ導体パッド２ｃと電子部品５の電極パッド５ａとをボンディングワイヤ７にて接続する。ボンディングワイヤ７は金やアルミニウム等の金属からなり、ＷＢ導体パッド２ｃの表面に直接金属間接合によって接合される。本発明によれば、ＷＢ導体パッド２ｃの表面が清浄化されているので、ボンディングワイヤ７の電気的な接続状態も良好である。 (E) Step WB conductor pad 2c exposed in step (d) and electrode pad 5a of electronic component 5 are connected by bonding wire 7. The bonding wire 7 is made of a metal such as gold or aluminum, and is directly bonded to the surface of the WB conductor pad 2c by metal-to-metal bonding. According to the present invention, since the surface of the WB conductor pad 2c is cleaned, the electrical connection state of the bonding wire 7 is also good.

アルミナ質セラミックスにて構成された厚み２００μｍの絶縁層を７層積層してなる絶縁基板の表面および内部にタングステンを主成分とした導体配線層にて所定の配線パターンを形成した配線基板を準備した。なお、絶縁基板の下面にはトリミングの傷を保護するためのエポキシ樹脂膜を形成した。配線基板の上面には、第１の電子部品である抵抗、コンデンサ、ダイオード、下面に接続端子を有するチップ部品と半田付けにより電気的に接続する導体パッドと、第２の電子部品である上面に接続端子を有するチップ部品を半田付けして固定するための導体パッドと、第２の電子部品の接続端子とボンディングワイヤを介して電気的に接続するためのＷＢ導体パッドとを形成した。   A wiring board was prepared in which a predetermined wiring pattern was formed with a conductive wiring layer mainly composed of tungsten on the surface and inside of an insulating board formed by laminating seven 200 μm thick insulating layers made of alumina ceramics. . An epoxy resin film was formed on the lower surface of the insulating substrate to protect the trimming flaw. On the upper surface of the wiring board, there are a resistor, a capacitor, a diode, which are first electronic components, a conductor pad which is electrically connected to a chip component having a connection terminal on the lower surface by soldering, and an upper surface which is a second electronic component. A conductor pad for soldering and fixing a chip component having a connection terminal and a WB conductor pad for electrical connection to the connection terminal of the second electronic component via a bonding wire were formed.

次に、ＷＢ導体パッドの表面に表１に示す樹脂ペーストを用いて樹脂膜パターンを印刷した。そして、第１の電子部品と半田付けにより電気的に接続する導体パッドにＳｎ−Ａｇ−Ｃｕ系半田粒子とフラックスとを混練した半田ペーストをスクリーン印刷法により印刷、塗布して半田パターンを形成した。   Next, a resin film pattern was printed on the surface of the WB conductor pad using the resin paste shown in Table 1. Then, a solder pattern in which Sn-Ag-Cu solder particles and flux were kneaded was printed and applied to a conductor pad electrically connected to the first electronic component by soldering to form a solder pattern. .

さらに、この半田パターンの上面に第１の電子部品の接続端子を載置して、この第１の電子部品を載置した配線基板を２５０℃でリフロー加熱して半田パターン中の半田成分を溶融させて第１の電子部品を配線基板の上面に半田付けした。   Further, the connection terminal of the first electronic component is placed on the upper surface of the solder pattern, and the wiring board on which the first electronic component is placed is reflow-heated at 250 ° C. to melt the solder component in the solder pattern. The first electronic component was soldered to the upper surface of the wiring board.

そして、この第１の電子部品が実装された配線基板の上面の所定位置に、ディスペンサ法によって１００μｍ厚みの半田フラックス層を形成した状態で、Ｓｎ−Ａｇ−Ｃｕ系の２．５ｍｍ×３．５ｍｍ×厚み５０μｍで中央部に直径１ｍｍの円形の貫通孔を有する半田箔を載置した。この時、半田箔を載置した位置は最も近接した第１の電子部品を実装した位置から１．５ｍｍとした。また、半田箔の上面に第２の電子部品を載置した時、上面視で第２の電子部品の外周からはみ出した半田箔の外周部の平均幅を１００μｍとした。   Then, with a solder flux layer having a thickness of 100 μm formed by a dispenser method at a predetermined position on the upper surface of the wiring board on which the first electronic component is mounted, the Sn—Ag—Cu-based 2.5 mm × 3.5 mm X A solder foil having a thickness of 50 μm and a circular through hole having a diameter of 1 mm in the center was placed. At this time, the position where the solder foil was placed was set to 1.5 mm from the position where the closest electronic component was mounted. Further, when the second electronic component was placed on the upper surface of the solder foil, the average width of the outer peripheral portion of the solder foil protruding from the outer periphery of the second electronic component in the top view was set to 100 μm.

次に、２種類、計１０個の第２の電子部品をそれぞれの半田箔の上面に載置した。   Next, two types of a total of ten second electronic components were placed on the upper surface of each solder foil.

そして、第２の電子部品の半田箔が加熱されて半田付けされるように２７０℃で１０秒間赤外線照射することによって加熱して第２の電子部品を配線基板の上面に半田付けした。その後、樹脂膜を剥がした。この時、樹脂膜の変色の有無を目視で確認し耐熱性の良し悪しを評価した。表１中、変色がなかったものは○、少し変色が見られたものは△、全体的に変色したものは×で示した。また、樹脂膜を剥がした時の樹脂残りの有無を５０倍の顕微鏡観察にて確認し、試料数５０個に対して樹脂残りがあったＷＢ導体パッドの数を測定した。   Then, the second electronic component was soldered to the upper surface of the wiring board by heating by irradiation with infrared rays at 270 ° C. for 10 seconds so that the solder foil of the second electronic component was heated and soldered. Thereafter, the resin film was peeled off. At this time, the presence or absence of discoloration of the resin film was visually confirmed to evaluate whether the heat resistance was good or bad. In Table 1, those with no discoloration are indicated with ◯, those with a slight discoloration are indicated with Δ, and those with a general discoloration are indicated with ×. In addition, the presence or absence of the resin residue when the resin film was peeled off was confirmed by microscopic observation at 50 times, and the number of WB conductor pads having the resin residue was measured for 50 samples.

さらに、露出したＷＢ導体パッドと第２の電子部品の接続端子とをボンディングワイヤによって接続して表面実装モジュールを作製した。得られた表面実装モジュールに対して、ＷＢ導体パッドと接着したボンディングワイヤ（直径３００μｍのアルミニウムワイヤ、ワイヤがＷＢ導体パッドに接合した部分は長さ：約７５０μｍ×幅：約４５０μｍ）に対して、ワイヤ接合部の横方向からＷＢ導体パッドの表面と平行な方向に荷重を負荷しながら押してゆき、ワイヤが剥離したときの荷重（いわゆるシェア強度）を接着強度として測定した。   Further, the exposed WB conductor pad and the connection terminal of the second electronic component were connected by a bonding wire to produce a surface mount module. For the obtained surface mount module, a bonding wire bonded to a WB conductor pad (a 300 μm diameter aluminum wire, a portion where the wire is bonded to the WB conductor pad is length: about 750 μm × width: about 450 μm), The load was pushed from the lateral direction of the wire joint in a direction parallel to the surface of the WB conductor pad, and the load when the wire peeled (so-called shear strength) was measured as the adhesive strength.

また、用いた樹脂ペーストを２５℃、湿度６０％の条件下で６０日間保存し、保存前後の粘度をそれぞれ測定して、保存前の樹脂ペーストの粘度を１として保存後の樹脂ペーストの粘度の上昇率を算出した。それぞれの結果は表１に示した。

Figure 0004684149
Also, the resin paste used was stored for 60 days under the conditions of 25 ° C. and humidity 60%, the viscosity before and after storage was measured, and the viscosity of the resin paste before storage was set to 1 as the viscosity of the resin paste before storage. The rate of increase was calculated. The results are shown in Table 1.
Figure 0004684149

表１に示す結果から明らかなとおり、本発明の工程を経て表面実装モジュールを作製した実施例の試料Ｎｏ．１〜３は、いずれも耐熱性が良好で、樹脂残りもなく、また、ボンディングワイヤの接着強度も高いものであった。   As is clear from the results shown in Table 1, the sample No. of the example in which the surface mount module was manufactured through the process of the present invention. 1 to 3 all had good heat resistance, no resin residue, and high bonding strength of the bonding wires.

これに対して、ｍｐ比が０．３よりも小さい試料Ｎｏ．４では、樹脂膜の耐熱性が低くて樹脂膜が変質してしまい、樹脂膜を剥がすときにその一部がＷＢ導体パッドの表面に残存して樹脂残りとなってしまった。また、ｍｐ比が０．５を超える試料Ｎｏ．５では、樹脂膜の保形性が悪くなり、樹脂膜を剥がすことができなくなった。さらに、架橋反応が一部未反応のシリコンアクリル共重合樹脂とアクリル酸エステル共重合樹脂とを混合した樹脂を樹脂ペーストとして用いた試料Ｎｏ．６では、耐熱性は良好であったが、５０個中５個のＷＢ導体パッドの表面に樹脂残りが発生してしまい、また、ボンディングワイヤの接着硬度も低いものであった。また、加熱によって重合反応する樹脂ペーストを用いた試料Ｎｏ．７では、５０個中４８個のＷＢ導体パッドの表面に樹脂残りが発生してしまい、ボンディングワイヤの接着強度も低いものであった。 In contrast, the samples m p ratio is less than 0.3 No. In No. 4, the heat resistance of the resin film was low and the resin film deteriorated, and when the resin film was peeled off, a part of the resin film remained on the surface of the WB conductor pad, leaving a resin residue. Further, the sample m p ratio exceeds 0.5 No. In No. 5, the shape retention of the resin film deteriorated and the resin film could not be peeled off. Further, sample No. 1 was obtained by using, as a resin paste, a resin obtained by mixing a partially unreacted silicon acrylic copolymer resin and an acrylic ester copolymer resin. In No. 6, the heat resistance was good, but resin residue was generated on the surface of 5 out of 50 WB conductor pads, and the bonding hardness of the bonding wire was low. Sample No. using a resin paste that undergoes a polymerization reaction upon heating was used. In No. 7, resin residue was generated on the surface of 48 out of 50 WB conductor pads, and the bonding strength of the bonding wires was low.

さらに、試料Ｎｏ．１〜３については、所定環境下で６０日間保存した後の粘度上昇率が２００％以下であり、長期間にわたって樹脂ペーストの印刷性がよく、安定して使用できるものであることがわかった。これに対して、試料Ｎｏ．４，５では、６０日間保存した後の粘度上昇率がそれぞれ３２０％、３９０％と高く、長期間の保存に耐えられないものがあることがわかった。   Furthermore, sample no. About 1-3, it turned out that the rate of increase in the viscosity after storage for 60 days in a predetermined environment is 200% or less, the resin paste has good printability over a long period of time, and can be used stably. In contrast, sample no. In Nos. 4 and 5, the rate of increase in viscosity after storage for 60 days was as high as 320% and 390%, respectively, indicating that some of them could not withstand long-term storage.

（ａ）〜（ｅ）は、それぞれ本発明の表面実装モジュールの製造方法の好適例を示す工程毎の断面図である。(A)-(e) is sectional drawing for every process which shows the suitable example of the manufacturing method of the surface mount module of this invention, respectively. （ア）（ｂ）工程における配線基板を上から見た平面図であり、樹脂膜８の形成領域の一例を示す図であり、（イ）本実施態様を経て得られる表面実装モジュール２０を上から見た平面図である。(A) (b) It is the top view which looked at the wiring board in a process from the top, and is a figure which shows an example of the formation area of the resin film 8, (A) The surface mounting module 20 obtained through this embodiment is turned up It is the top view seen from.

符号の説明Explanation of symbols

１ 配線基板
１ａ 絶縁基板
１ｂ 導体配線層
１ｃ 裏面保護膜
２ 導体パッド
２ａ 第１の電子部品に接続される導体パッド
２ｂ 第２の電子部品を固定する導体パッド
２ｃ ワイヤボンディング接続用導体パッド（ＷＢ導体パッド）
３ 半田パターン
４ 第１の電子部品
４ａ 接続端子
５ 第２の電子部品
５ａ 接続端子
６ 半田粒
７ ボンディングワイヤ
８ 樹脂膜
２０ 表面実装モジュール
２１ 半田層（第１の電子部品を半田付けする）
２２ 半田層（第２の電子部品を半田付けする） DESCRIPTION OF SYMBOLS 1 Wiring board 1a Insulating board 1b Conductor wiring layer 1c Back surface protective film 2 Conductor pad 2a Conductor pad connected to 1st electronic component 2b Conductor pad which fixes 2nd electronic component 2c Wire bonding connection conductor pad (WB conductor) pad)
3 Solder Pattern 4 First Electronic Component 4a Connection Terminal 5 Second Electronic Component 5a Connection Terminal 6 Solder Grain 7 Bonding Wire 8 Resin Film 20 Surface Mount Module 21 Solder Layer (Solds First Electronic Component)
22 Solder layer (solders the second electronic component)

Claims (3)

（ａ）配線基板の表面に、第１の電子部品を半田付けにより前記配線基板に設けられた配線と電気的に接続するための半田付け用導電パッドと、前記配線基板の前記表面の第２の電子部品実装領域に固定される第２の電子部品の接続端子とボンディングワイヤを介して接続される、前記第２の電子部品と前記配線基板に設けられた配線とを電気的に接続するワイヤボンディング接続用導電パッドとを形成する工程と、（ｂ）前記ワイヤボンディング接続用導電パッドの表面に、アクリル樹脂をモノマー換算した時のモル数をｍＡ、リン酸エステルのモル数をｍＰとしたときのｍＰの比率（ｍＰ／（ｍＡ＋ｍＰ））が０．３〜０．５の割合からなり、かつ合計量が８０質量％以上のアクリル樹脂とリン酸エステルを含有する樹脂ペーストを塗布して、前記ワイヤボンディング接続用導電パッドの表面を樹脂膜で覆うとともに、前記半田付け用導電パッドの表面に半田ペーストを塗布する工程と、（ｃ）（ｂ）工程で得られた前記半田ペーストを塗布した半田付け用導電パッドに前記第１の電子部品を載置した状態でリフロー加熱して半田付けするとともに、前記第２の電子部品実装領域に前記第２の電子部品を固定する工程と、（ｄ）（ｃ）工程で得られた配線基板から前記樹脂膜を剥離するとともに、前記ワイヤボンディング接続用導電パッドの表面の有機物成分を除去する工程と、（ｅ）（ｄ）工程で露出した前記ワイヤボンディング接続用導電パッドと前記第２の電子部品の接続端子とをボンディングワイヤにて接続する工程とを具備することを特徴とする表面実装モジュールの製造方法。 (A) A soldering conductive pad for electrically connecting the first electronic component to the wiring provided on the wiring board by soldering on the surface of the wiring board, and a second of the surface of the wiring board. A wire for electrically connecting the second electronic component and a wiring provided on the wiring board, which is connected to the connection terminal of the second electronic component fixed to the electronic component mounting area of the second electronic component via a bonding wire Forming a bonding connection conductive pad; (b) on the surface of the wire bonding connection conductive pad, m A is the number of moles of acrylic resin converted to monomer, and m P is the number of moles of phosphate ester. resin ratio of m P when the (m P / (m a + m P)) consists ratio of 0.3 to 0.5, and the total amount contains more than 80 wt% acrylic resin and phosphoric acid ester paste And coating the surface of the conductive pad for wire bonding connection with a resin film, and applying a solder paste to the surface of the conductive pad for soldering, and the step obtained in the steps (c) and (b) The first electronic component is placed on the soldering conductive pad to which the solder paste is applied and soldered by reflow heating, and the second electronic component is fixed to the second electronic component mounting region. And (e) and (d) steps, a step of peeling the resin film from the wiring substrate obtained in the steps (d) and (c), and removing organic components on the surface of the conductive pads for wire bonding connection. And a step of connecting the conductive pad for wire bonding connection exposed at step 1 and the connection terminal of the second electronic component with a bonding wire. Method of manufacturing Lumpur. 前記樹脂ペースト中にさらに無機質フィラーを３〜１０質量％の割合で添加することを特徴とする請求項１記載の表面実装モジュールの製造方法。   2. The method for manufacturing a surface mount module according to claim 1, wherein an inorganic filler is further added to the resin paste at a ratio of 3 to 10% by mass. （ｂ）工程において、樹脂ペーストを厚みが４０〜１００μｍで塗布することを特徴とする請求項１または２記載の表面実装モジュールの製造方法。   3. The method for manufacturing a surface mount module according to claim 1, wherein in the step (b), the resin paste is applied with a thickness of 40 to 100 [mu] m.
JP2006087803A 2006-03-28 2006-03-28 Manufacturing method of surface mount module Expired - Fee Related JP4684149B2 (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5150463A (en) * 1974-10-29 1976-05-04 Marukon Denshi Kk KONSEISHUSEKIKAIRONO SEIZOHOHO
JPS5941349A (en) * 1982-09-01 1984-03-07 Mitsubishi Rayon Co Ltd Flame-retardant acrylic resin composition and its preparation
JPS5949269A (en) * 1982-08-12 1984-03-21 ザ　グリデン　カンパニー Water-dispersed coating composition and manufacture
JPH06279606A (en) * 1993-03-24 1994-10-04 Mitsubishi Kasei Vinyl Co Agricultural vinyl chloride resin film
JPH08172110A (en) * 1994-12-16 1996-07-02 Nippondenso Co Ltd Manufacture of circuit board
JP2001106839A (en) * 1999-10-13 2001-04-17 Du Pont Mitsui Polychem Co Ltd Thermoplastic resin composition
JP2003258191A (en) * 2002-02-26 2003-09-12 Kyocera Corp Circuit board and method for manufacturing the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5150463A (en) * 1974-10-29 1976-05-04 Marukon Denshi Kk KONSEISHUSEKIKAIRONO SEIZOHOHO
JPS5949269A (en) * 1982-08-12 1984-03-21 ザ　グリデン　カンパニー Water-dispersed coating composition and manufacture
JPS5941349A (en) * 1982-09-01 1984-03-07 Mitsubishi Rayon Co Ltd Flame-retardant acrylic resin composition and its preparation
JPH06279606A (en) * 1993-03-24 1994-10-04 Mitsubishi Kasei Vinyl Co Agricultural vinyl chloride resin film
JPH08172110A (en) * 1994-12-16 1996-07-02 Nippondenso Co Ltd Manufacture of circuit board
JP2001106839A (en) * 1999-10-13 2001-04-17 Du Pont Mitsui Polychem Co Ltd Thermoplastic resin composition
JP2003258191A (en) * 2002-02-26 2003-09-12 Kyocera Corp Circuit board and method for manufacturing the same

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