JP4680156B2 - Digital modulation circuit and electronic device - Google Patents

Description

  The present invention relates to a digital modulation circuit and an electronic apparatus using the same, and more particularly to a digital modulation circuit that generates a multi-value digital modulation signal by digital signal processing and an electronic apparatus using the digital modulation circuit.

  PSK (Phase Shift Keying) modulation is for phase modulation of a carrier wave with a digital signal, and is used for high-speed communication in a narrow frequency band. For this reason, PSK modulation is adopted in many systems including mobile communication.

  In PSK modulation, the phase and amplitude at the time of modulation are expressed in a coordinate system with the in-phase component (I component) and the quadrature component (Q component) of the carrier wave as coordinate axes. These coordinate systems are called “signal spaces”, and the coordinate points of these coordinate systems are called “signal points”. Also, assigning any combination of digital signal data to signal points in the signal space is called “mapping” (see, for example, Patent Document 1).

  One example of PSK modulation is QPSK (Quadrature Phase Shift Keying) modulation. In QPSK modulation, 2-bit data is transmitted by one modulation. FIG. 4 shows a block configuration example of the QPSK modulation circuit.

  When data such as a baseband signal is input to the modulation circuit, the mapping circuit 2 assigns signal points according to the digital signal. The assigned signal point data is distributed to I component and Q component data by the in-phase / quadrature distribution circuit 3 and is represented by 1-bit digital data.

  The data of the I component and the Q component are input to the ROM filters 4a and 4b as input data shown in (i) of FIG. 5 (here, only the I component is shown). The ROM filters 4a and 4b output time response waveform data as shown in (ii) of FIG. 5 (only the I component is shown here).

  The time response waveform data output from the ROM filters 4a and 4b are converted into analog signals by the D / A converters 6a and 6b shown in FIG. 4, respectively, and become the I component and Q component of the band-limited baseband signal. . From these signals, high frequency components are removed by the low-pass filters (LPF) 7a and 7b, the carrier wave is multiplied by the quadrature modulator 8, and output as a QPSK modulated wave.

Japanese Patent Publication No. 7-73288

  In the digital modulation described above, before the start of the modulation or after the end of the modulation, the data is mapped to the coordinates (0, 0) to stop the modulation, and the data output section as shown by A in FIG. It is desirable to make the outside output zero. However, in the above-described conventional digital modulation circuit, generally, at the time of modulation, mapping is performed to coordinates other than the coordinates (0, 0) on the two-dimensional signal space. At this time, if the coordinates of coordinates (0, 0) in the two-dimensional signal space are to be set in a storage means such as a ROM filter, a level of “0” is added to both the I component and the Q component, and more storage means Therefore, there is a problem that the circuit scale is greatly increased.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a digital modulation circuit capable of stopping modulation without significantly increasing the circuit scale, and an electronic apparatus using the digital modulation circuit. To do.

  The digital modulation circuit according to the present invention outputs mapping means for assigning an input digital signal to any one of a plurality of predetermined signal points on a two-dimensional signal space, and two series of digital data representing the coordinates of the signal points Coordinate data output means, waveform output means for outputting a waveform corresponding to each of the two series of digital data, and orthogonal modulation means for modulating the waveform output by the waveform output means, the waveform output means Includes a first storage means for storing a first response waveform for each of the two series of digital data, and a second before or after the start of the modulation signal corresponding to the data output section of the first response waveform. And a subtracting unit for subtracting the second response waveform from the first response waveform, and subtracted by the subtracting unit. Output waveform, characterized in that it is modulated by the quadrature modulation means.

  The electronic device according to the present invention includes mapping means for assigning an input digital signal to any one of a plurality of predetermined signal points on a two-dimensional signal space, and two series of digital data representing the coordinates of the signal points. Coordinate data output means for outputting, waveform output means for outputting a waveform corresponding to each of the two series of digital data, and orthogonal modulation means for modulating the waveform output by the waveform output means, the waveform output Means for storing a first response waveform for each of the two series of digital data; and a first storage waveform before or after the start of the modulation signal corresponding to the data output section of the first response waveform. And a subtracting unit for subtracting the second response waveform from the first response waveform, and subtracted by the subtracting unit. Force waveform, characterized in that it comprises a digital modulation circuit which is modulated by the quadrature modulation means. Other features of the present invention are described in detail below.

  According to the present invention, it is possible to obtain a digital modulation circuit capable of stopping modulation without significantly increasing the circuit scale, and an electronic apparatus using the digital modulation circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is simplified or omitted.

Embodiment.
FIG. 1 shows a block configuration of a digital modulation circuit according to an embodiment of the present invention. This digital modulation circuit has a mapping circuit 2 as mapping means for assigning an input digital signal to any of a plurality of predetermined signal points on a two-dimensional signal space. The digital modulation circuit also has an in-phase / quadrature distribution circuit 3 as coordinate data output means for outputting two series of digital data representing the coordinates of the signal points. The digital modulation circuit has waveform output means 11 for outputting a waveform corresponding to each of the two series of digital data. Further, this digital modulation circuit has a quadrature modulator 8 as a quadrature modulation means for modulating each waveform output by the waveform output means 11.

  Next, the operation of the digital modulation circuit according to this embodiment will be described. When a baseband signal (data 1) is input to the digital modulation circuit, this signal is assigned to each signal point by the mapping circuit 2 and mapped. Here, an example of performing QPSK (Quadrature Phase Shift Keying) modulation is shown.

  As shown in FIG. 2, the in-phase component (hereinafter referred to as “I component”) and the quadrature component (hereinafter referred to as “Q component”) of the carrier wave are respectively binary data (1, 1) (1, −1) ( −1, −1) (−1,1) are mapped so as to be any signal point. That is, the I component and the Q component are each represented by 1-bit digital data. Next, the in-phase / quadrature distribution circuit 3 distributes the data of the signal points assigned by the mapping circuit 2 into I component and Q component data.

  The output data distributed to the I component and the Q component is input to the addresses of the ROM filters 4a and 4b (first storage means) as a data string extending over several bits, respectively. At this time, the input data of the I component has, for example, a waveform shown in (i) of FIG. In the data output section, the input data is “−1” or “1”, and has a rectangular waveform. Although not shown, the same applies to the Q component.

  Next, the ROM filters 4a and 4b store and output the first response waveform for each of the two series of digital data of the I component and the Q component. The first response waveform of the I component is as shown in (ii) of FIG.

  The digital modulation circuit according to the present embodiment first calculates and stores the second response waveform before or after the start of the modulation signal corresponding to the data output section of the first response waveform described above. 2 storage means (non-period data storage means 10a, 10b). As this storage means, for example, a ROM, FIR (Finite Impulse Response) filter or the like is used. Then, the second storage means pre-calculates and stores the second response waveform before or after the start of the modulation signal, that is, the waveform shown in (iii) of FIG.

  The first response waveform (the waveform of (ii) in FIG. 3) output from the ROM filter 4a and the second response waveform (the waveform of (iii) in FIG. 3) stored in the out-of-period data storage means 10a are: Input to the subtractor 5a. Then, the subtracter 5a subtracts the second response waveform from the first response waveform and outputs the waveform. As a result, an output waveform of the I component is obtained as shown in (iv) of FIG.

  Similarly, the subtracter 5b subtracts the second response waveform input from the out-of-period data storage means 10b from the first response waveform input from the ROM filter 4b, and outputs the waveform. Then, an output waveform (not shown) of the Q component is obtained. That is, the subtracters 5a and 5b subtract the second response waveforms of the out-of-period data storage means 10a and 10b from the first response waveforms of the ROM filters 4a and 4b, respectively, and output an output waveform.

  That is, in the digital modulation circuit according to the present embodiment, as the waveform output unit 11, the ROM filters 4a and 4b (first filters) that store the first response waveforms for the two series of digital data of the I component and the Q component, respectively. Storage means), out-of-period data storage means 10a, 10b (second storage means) for storing the second response waveform before or after the start of the modulation signal, and the second response waveform from the first response waveform. Are subtracters 5a and 5b.

  The output waveforms subtracted by the subtractors 5a and 5b are converted into analog signals by the D / A converters 6a and 6b, respectively, and further modulated by the above-described quadrature modulator 8 via the low-pass filters 7a and 7b. Is done.

  In the present embodiment, the ROM filters 4a and 4b are configured not to have a level of “0”, and a section other than the data output section is set to a value of “1” or “−1” as out-of-period data. 1 response waveform is output. Then, the second response waveform (subtraction data) stored in the out-of-period data storage means 10a, 10b is subtracted from the first response waveform.

  Here, the number of ROMs required by each of the ROM filters 4a and 4b will be described. When the data is only “+1” and “−1” in the QPSK modulation, it can be expressed by 1 bit because it has two amplitudes, and can be configured by one ROM. When the data is “+1”, “0”, and “−1”, since there are three amplitudes, two bits are required for expression and two ROMs are required. In this embodiment, since the “0” level is not set, it can be constituted by one ROM, and the capacity of the ROM can be halved as compared with the case where the “0” level is set in the ROM filter.

  Since π / 4 shift QPSK has five amplitudes, three bits are required for expression, and three ROMs are required. In this embodiment, since the “0” level is not set, it can be configured by two ROMs, and the capacity of the ROM can be reduced to 2/3 as compared with the case where the “0” level is set in the ROM filter.

  In this way, in the digital modulation circuit shown in FIG. 1, since the out-of-period data may be all “−1” or all “+1”, there is no need to set the level of “0”, and the ROM filters 4a and 4b. That is, the storage capacity of the first storage means can be reduced. Therefore, modulation can be stopped without significantly increasing the circuit scale.

  It is also conceivable to forcibly set the outputs of the ROM filters 4a and 4b to the “0” level. However, since there is an impulse response waveform from the data section in the vicinity of the data section, there is a possibility that the spectrum may be spread if it is forcibly set to the “0” level. On the other hand, in the present embodiment, since the same waveform is subtracted from the impulse response waveform corresponding to “1” or “−1” outside the data interval, the impulse response from the data in the data interval remains. And there is no effect on the spectrum.

  Therefore, the modulation can be stopped by setting the “0” level outside the data output section without greatly increasing the capacity of the ROM filter and without affecting the desired spectrum.

  As described above, according to the digital modulation circuit of this embodiment, modulation can be stopped without significantly increasing the circuit scale.

  Note that although the digital modulation circuit has been described in this embodiment, an electronic device that includes this digital modulation circuit and performs communication has the same effect.

It is a figure which shows the block configuration of the modulation circuit of this invention. It is a figure explaining arrangement | positioning of the signal point of QPSK modulation. It is a figure which shows the input data of the digital modulation circuit of this invention, an output waveform, subtraction data, and output data. It is a figure which shows the block configuration of the conventional modulation circuit. It is a figure which shows the input data, output waveform, subtraction data, and output data of the conventional modulation circuit.

Explanation of symbols

1 input data, 2 mapping circuit, 3 in-phase / quadrature distribution circuit, 4a, 4b ROM filter, 5a, 5b subtractor, 8 quadrature modulator.

Claims (2)

Mapping means for assigning an input digital signal to any of a plurality of predetermined signal points on a two-dimensional signal space;
Coordinate data output means for outputting two series of digital data representing the coordinates of the signal points;
Waveform output means for outputting a waveform corresponding to each of the two series of digital data;
Orthogonal modulation means for modulating the waveform output by the waveform output means,
The waveform output means includes first storage means for storing a first response waveform for each of the two series of digital data;
Second storage means for storing a second response waveform before or after the start of the modulation signal corresponding to the data output section of the first response waveform;
Subtracting means for subtracting the second response waveform from the first response waveform,
The digital modulation circuit, wherein the output waveform subtracted by the subtracting means is modulated by the quadrature modulation means. Mapping means for assigning an input digital signal to any of a plurality of predetermined signal points on a two-dimensional signal space;
Coordinate data output means for outputting two series of digital data representing the coordinates of the signal points;
Waveform output means for outputting a waveform corresponding to each of the two series of digital data;
Orthogonal modulation means for modulating the waveform output by the waveform output means,
The waveform output means includes first storage means for storing a first response waveform for each of the two series of digital data;
Second storage means for storing a second response waveform before or after the start of the modulation signal corresponding to the data output section of the first response waveform;
Subtracting means for subtracting the second response waveform from the first response waveform,
An electronic apparatus comprising: a digital modulation circuit in which an output waveform subtracted by the subtracting means is modulated by the quadrature modulation means.

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