JP4672702B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to, for example, a nonvolatile ferroelectric memory.

  Today, semiconductor memories are used everywhere from the main memory of large computers to personal computers, home appliances, mobile phones, and the like. As types of semiconductor memory, volatile DRAM (Dynamic Random Access Memory), SRAM (Static RAM), nonvolatile MROM (Mask Read Only Memory), Flash EEPROM (Electrically Erasable Programmable ROM), etc. are on the market. . In particular, although DRAM is a volatile memory, it is superior in terms of its low cost (cell area 1/4 compared to SRAM) and high speed, and occupies most of the market. The rewritable and nonvolatile Flash EEPROM is nonvolatile and can store information even when the power is turned off. However, the number of times of rewriting (number of times of W / E) is about 10 6, the writing time takes about microseconds, and a high voltage (12 V to 22 V) needs to be applied for writing. Therefore, the market is not as open as DRAM.

  On the other hand, a non-volatile memory using a ferroelectric capacitor is non-volatile and has a rewrite frequency of 10 12, read / write time of about 3V. There are advantages such as ~ 5V operation. For this reason, there is a possibility of replacing the entire memory market, and since it was proposed in 1980, each manufacturer has been developing.

FIG. 44 shows a memory cell having a one-transistor + 1-capacitor configuration of a conventional ferroelectric memory and its cell array configuration. The memory cell configuration of a conventional ferroelectric memory is a configuration in which a transistor and a capacitor are connected in series. The cell array includes bit lines BL for reading data, word lines WL for selecting memory cell transistors, and plate lines PL for driving one end of the ferroelectric capacitor. In this ferroelectric memory, as shown in FIGS. 45 and 46, a memory cell has a folded bit line configuration in which one memory cell is arranged at two intersections between a word line and a bit line. For this reason, there is a problem that the minimum cell size is limited to 2F × 4F = 8F ² where the wiring width and the distance between the wirings are F.

  Further, in order to prevent the destruction of the polarization information of the ferroelectric capacitor of the non-selected cell, the plate line needs to be divided for each word line and driven individually. Further, since a plurality of ferroelectric capacitors are connected to each plate line in the word line direction, the load capacitance is large. Further, since the pitch of the plate line drive circuit is very narrow for each word line, the size of the plate line drive circuit cannot be increased. For these reasons, as shown in FIG. 47, there is a large delay at the rise and fall of the plate line, resulting in a problem of slow operation.

  FIG. 48 shows a configuration in which the plate lines are shared. FIG. 49 shows a phenomenon of disturbance generated in the ferroelectric capacitor of the non-selected cell, which is caused by the configuration of FIG. As shown in FIG. 48, by sharing the plate line and the plate driving circuit with cells connected to different word lines, the speed can be increased and the number of plate driving circuits can be reduced.

  However, for example, when the word line WL0 is selected, since the plate line PL is shared, the potential Vss when the connection node between the ferroelectric capacitor of the cell connected to the non-selected word line WL1 and the plate line PL is also active. To the internal power supply potential Vaa. At this time, the node SN1 of the non-selected cell also rises to the potential Vaa due to the coupling of the ferroelectric capacitor. Here, the node SN1 has a value slightly smaller than the potential Vaa due to the coupling ratio corresponding to the parasitic capacitance of the node SN1, but there is no problem because the parasitic capacitance value is smaller than the capacitance of the ferroelectric capacitor.

  However, as shown in FIG. 49, when the long active time, the short standby time, the long active time, and the short standby time are repeated, the potential of the node SN1 gradually decreases due to the junction leak. Therefore, at the next standby time, the potential of the plate line PL falls to the potential Vss, and the node SN1 becomes a negative value. When the standby time is long, this negative potential tends to return to 0 V due to a junction leak or the like. However, the active time is usually about 10 μs, the standby time is about 20 ns minimum, and the time ratio is 500. For this reason, the potential of the node SN1 hardly returns to the original state, and a static disturb voltage is applied to the non-selected ferroelectric capacitor, and the cell information is destroyed.

  As described above, the potential of the node SN1 continues to decrease when a long active operation is repeated. However, when the potential of the node SN1 increases to some extent, the junction leakage during standby stops in the forward direction. Since the embedded potential is about 0.6V, the disturb voltage is about 0.3V. Note that when the leakage current from the ferroelectric capacitor is larger than the junction leakage current, a decrease in the potential of the node SN1 can be suppressed. However, even in this case, the current amounts of the two leaks have distributions. That is, like the pause characteristic of DRAM, cells with a large junction leak exist in the distribution due to defects and the like, and even in the ferroelectric capacitor, a cell with a small leak from the crystal boundary exists in the distribution. Therefore, there are cells where two adverse conditions overlap, and as a result, polarization information is destroyed in some cells.

  For this reason, it is difficult to obtain the configuration of FIG. As a result, the conventional ferroelectric memory has a problem that the driving speed of the plate line is slow and the operation of the memory is slow.

In order to solve the above problem, the inventor has proposed a nonvolatile ferroelectric memory in "JP-A-10-255483", "JP-A-11-177036", and "JP-A2000-22010". According to these ferroelectric memories (hereinafter, the memory of the prior application), (1) a small 4F ² size memory cell, (2) a planar transistor that is easy to manufacture, and (3) a versatile high-speed random access function 3 points can be achieved simultaneously.

FIG. 50 shows a memory configuration of the prior application. As shown in FIG. 50, one memory cell is constituted by a cell transistor and a ferroelectric capacitor connected in parallel, and one memory cell block has a configuration in which a plurality of memory cells are connected in series. One end of the memory cell block is connected to a bit line via a block selection transistor, and the other end is connected to a plate. With this configuration, a memory cell having a minimum size of 4F ² can be realized as shown in FIGS.

  The operation of the memory having this configuration will be described. During standby, the cell transistors Q0 to Q3 are turned on by setting all the word lines WL0 to WL3 to a high level, and the block selection transistors are turned off by setting the block selection signal BS to a low level. By doing so, both ends of the ferroelectric capacitor are short-circuited by the cell transistor that is turned on, so that a potential difference between both ends does not occur, and the polarization information of the memory cell is stably maintained.

  When active, only the cell transistor connected in parallel to the ferroelectric capacitor to be read is turned off, and the block selection transistor is turned on. Thereafter, the plate line PL is set to the high level, so that the potential difference between the plate line PL and the bit line BL is applied only to both ends of the ferroelectric capacitors connected in parallel to the turned-off memory cell transistors. As a result, the polarization information of the ferroelectric capacitor is read out to the bit line.

  As described above, even if the memory cells are connected in series, information held in any ferroelectric capacitor can be read out by selecting any word line. That is, complete random access can be realized.

  Since the cell transistor of the non-selected cell is on, both ends of the ferroelectric capacitor of the non-selected cell are shorted by the cell transistor that is on. Therefore, even if the plate line PL is shared by all the memory cells of the memory cell block, the disturb voltage problem in the conventional ferroelectric memory can be avoided. Therefore, by sharing the plate line PL, the area of the plate line driving circuit can be increased while reducing the chip size, so that high-speed operation can be realized. For example, if a plate line is shared by 16 cells, the (plate line drive circuit area) · (plate line delay) product can be reduced to 1/16.

  The prior application memory has the following problems. Although the plate line PL can realize a large high-speed operation, the read charge and the write charge move between the memory cell and the bit line BL via a plurality of cell transistors connected in series, so that the delay of the cell transistor Ingredients are generated. This limits the high speed operation of the memory. This delay is reduced by reducing the number of memory cells, but the benefits of chip reduction are reduced.

  As described above, the conventional ferroelectric memory has a problem that the plate line cannot be shared, the speed is low, and the cell size is large. The memory of the prior application also has a problem that the maximum speed is limited by the number of cells connected in series, while the cell size can be reduced, the plate line can be shared, and the high-speed operation can be performed.

Prior art document information related to the invention of this application includes the following.
Japanese Patent Laid-Open No. 10-255483 Japanese Patent Laid-Open No. 11-177035 Japanese Unexamined Patent Publication No. 2000-22010

  The present invention has been made in view of the above circumstances, and an object of the present invention is to realize a small memory cell, share a plate line, and eliminate delay due to serial connection of memory cells. A semiconductor integrated circuit device capable of high-speed operation is provided.

Each of the semiconductor integrated circuit devices according to the first aspect of the present invention includes a cell transistor having a gate terminal connected to a word line, and a ferroelectric capacitor having one end connected to the source terminal of the cell transistor. A plurality of memory cells, and a drain terminal of each cell transistor of each of the plurality of memory cells as a plate line and the other end of each ferroelectric capacitor as a local bit line, and a source terminal connected to the plate line And a block selection transistor having a drain terminal connected to the local bit line and a source terminal connected to the local bit line and a drain terminal connected to the bit line. It has a cell block, and the cell transistor is on during standby Is a, the reset transistor is turned on, the active, the cell transistors of the selected memory cell of said memory cell block selected is turned on, and is selected in the memory cell block selected The cell transistor of the memory cell not selected is turned off, the cell transistor of the memory cell block not selected is turned on, and the block selection transistor of the selected memory cell block is turned on; The block selection transistor of the unselected memory cell block is turned off, the reset transistor of the selected memory cell block is turned off, and the reset transistor of the unselected memory cell block is turned on. Condition That, characterized in that.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device capable of operating at high speed with a small memory cell area.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
FIG. 1 shows a circuit configuration of a semiconductor integrated circuit device (FeRAM) according to the first embodiment of the present invention. As shown in FIG. 1, one memory cell is composed of one cell transistor and one ferroelectric capacitor connected in series. That is, each memory cell is composed of cell transistors Q0 to Q3 and ferroelectric capacitors C0 to C3. Cell transistors Q0-Q3 have their gates connected to word lines WL0-WL3. Each memory cell is connected in parallel, and one end of each memory cell is connected to a plate line PL and the other end is connected to a local bit line LBL.

  A reset transistor QR is connected between the plate line PL and the local bit line LBL. The reset transistor QR is controlled by a reset signal RST. A block selection transistor QS is connected between the local bit line LBL and the bit line BL. The block selection transistor QS is controlled by a block selection signal BS.

  As described above, a plurality of cell transistors Q0 to Q3, a plurality of ferroelectric capacitors C0 to C3, a reset transistor QR, a block selection transistor QS, and a local bit line LBL constitute one cell block CB. The row decoder RD controls the potential of the connected wiring (such as word lines WL0 to WL3). The plate line driver PLD drives the plate line.

  Next, the operation of the semiconductor integrated circuit device of FIG. 1 will be described. At the time of standby, the cell transistors Q0 to Q3 in the cell block CB are turned on. For this reason, the potential of the plate line PL is transmitted to the cell nodes SN0 to SN3. The reset transistor QR is turned on. For this reason, the potential of the local bit line LBL in the cell block CB is also equal to the potential of the plate line PL. Therefore, the potentials at both ends of the ferroelectric capacitors C0 to C3 of all the memory cells in the cell block CB are the same as the plate line PL, and no voltage is applied to the ferroelectric capacitors C0 to C3 during standby.

  When active, the reset transistor QR in the cell block CB is turned off, the cell transistors of the non-selected cells (eg, cell transistors Q0, Q2, Q3) are turned off, the block selection transistor QS is turned on, and the plate line PL Is driven. As a result, since only the cell transistor (eg, cell transistor Q1) of the selected cell is turned on, the potential of the plate line PL is applied to one end of the ferroelectric capacitor (eg, ferroelectric capacitor C1) of the selected cell. The other end is applied with the potential of the bit line BL. Therefore, a voltage is applied across the ferroelectric capacitor C1. The ferroelectric capacitor C1 undergoes polarization inversion by this voltage, and as a result, cell information is read from the ferroelectric capacitor C1. This cell information is read out to the bit line BL via the local bit line LBL. This read signal is amplified by a sense amplifier (not shown).

  After the cell information is read, if the read information is “0” data, the data is written back to the ferroelectric capacitor C1 while the potential of the plate line PL is at a high level. In the case of “1” data, writing is performed after the potential of the plate line PL is set to the low level. Thereafter, the block selection transistor QS is turned off, and the reset transistor QR and the cell transistors Q0 to Q3 are turned on, thereby shifting to the standby state.

  When active, nodes of non-selected cells (eg, cell nodes SN0, SN2, SN3) are floating. Further, since the plate line PL is shared by all the memory cells in the cell block CB, the plate line PL of the non-selected cell is also at the high level. As a result, the potential of the node of the non-selected cell decreases due to the junction leak, and the disturb voltage is applied to the ferroelectric capacitors (eg, ferroelectric capacitors C0, C2, C3) of the non-selected cell. However, when returning to the standby state, the potential difference between both ends of each of the ferroelectric capacitors C0 to C3 is reset to 0V. Therefore, the disturb voltage is limited to a voltage at which the cell nodes SN0 to SN3 drop during only one active time (up to 10 μs). The decrease in the potentials of the cell nodes SN0 to SN3 is a negligible value (0.1 V or less) considering that the cell charge is held for at least about several hundreds of ms in DRAMs or the like.

  According to the semiconductor integrated circuit device of the first embodiment, the plate line PL is shared by all the memory cells in the cell block CB. Therefore, it is possible to realize a significant reduction in signal delay on the plate line PL, a reduction in the area of the plate line PL drive circuit PLD, and an improvement in drive capability.

  In addition, according to the first embodiment, when active, a disturb voltage is applied to the ferroelectric capacitors of the non-selected cells, but each time the standby state is entered, the potential difference across the ferroelectric capacitors C0 to C3 is Reset to 0V. Therefore, the period during which the disturb voltage is applied is short, and the decrease in the potential of the cell node of the non-selected cell is negligibly small. For this reason, it is possible to avoid the data of the memory cell being destroyed by the disturb voltage.

  Further, according to the first embodiment, in the above-described series of operations in the active state, two cell transistors Q0 to Q3 and a block selection transistor QS are provided between the ferroelectric capacitors C0 to C3 and the bit line BL. Only through the transistor. Therefore, unlike the memory cell of the memory of the prior application, there is no problem of delay due to the plurality of memory cells connected in series. Therefore, since the delay due to the cell transistors connected in series does not occur while sharing the plate line PL, it is possible to perform reading and writing at a higher speed than the conventional and previous applications.

  In addition, according to the first embodiment, since the cell block CB is connected to the bit line BL, the number of contacts of the bit line BL can be greatly reduced. Therefore, since the capacity of the bit line BL can be reduced, many memory cells can be connected to one bit line BL. Therefore, the area of the sense amplifier can be reduced and the signal on the bit line BL can be increased.

According to the first embodiment, since one cell can be arranged at the intersection of the bit line BL and each of the word lines WL0 to WL3, a memory cell as small as 6F ² can be realized.

(Second Embodiment)
The second embodiment relates to an example of a driving method of the plate line PL of the semiconductor integrated circuit device of the first embodiment (FIG. 1). More specifically, the present invention relates to the case where the potential of the plate line PL during standby is the potential Vss, and the potential during driving is the internal power supply potential Vaa.

  FIG. 2 shows a second embodiment of the present invention and shows the operation of the semiconductor integrated circuit device of FIG. Taking the case where information is read from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 2, at the time of standby, the reset signal RST and the word lines WL0 to WL3 are set to the potential Vpp (high level), and the block selection signal BS is set to the potential Vss (low level). Further, the plate line PL and the bit line BL are set to the potential Vss. Therefore, the cell transistors Q0 to Q3 and the reset transistor QR are turned on, and the potential of the local bit line LBL in the cell block CB is also equal to the potential of the plate line PL. Therefore, during standby, the potentials at both ends of the ferroelectric capacitors C0 to C3 of all the memory cells in the cell block CB are the same as the plate line PL, and no voltage is applied to the ferroelectric capacitors C0 to C3.

  When active, the reset signal RST is set to the low level, and the word lines WL0, WL2, WL3 of the non-selected cells are set to the low level. The word line WL1 of the selected cell maintains a high level. Therefore, the reset transistor QR is turned off, and the cell transistors Q0, Q2, Q3 of the non-selected cells are turned off. Next, when the block selection signal BS is set to the high level, the block selection transistor QS is turned on.

  In this state, the plate line PL is driven to the internal power supply potential Vaa. Note that the internal power supply potential Vaa is a potential generated from the power supply potential Vdd, and the power supply potential Vdd can also be used. As a result of driving the plate line PL, a voltage is applied to only both ends of the ferroelectric capacitor C1 of the selected cell, so that the potential corresponding to the information “0” or “1” is local from the ferroelectric capacitor C1. Data is read out to the bit line BL via the bit line LBL. The potential read to the bit line BL is amplified by a sense amplifier (not shown). When the read information is “0”, the potential on the bit line is amplified to the potential Vss (typically ground potential). When the read information is “1”, the potential on the bit line BL is amplified to the internal power supply potential Vaa.

  In the case of “0” information, since the bit line BL is at the potential Vss, rewriting is performed while the plate line PL is at the potential Vaa. In the case of “1” information, since the bit line BL is at the potential Vaa, rewriting is performed by setting the plate line PL to the potential Vss. Thereafter, the block selection signal BS is set to the low level, and the reset signal RST and the word lines WL0, WL2, and WL3 are set to the high level, thereby shifting to the standby state.

  During standby, the reset signal RST and the word lines WL0 to WL3 are at a relatively high potential Vpp, so that a large electric field is applied to the gate oxide films of the reset transistor QR and the cell transistors Q0 to Q3. Reliability becomes a problem. Therefore, as shown in FIG. 3, during standby, the reset signal RST and the word lines WL0 to WL3 are set to potential Vpp or lower (for example, potential Vaa), and the word line potential of the selected cell transistor is raised to Vpp when active. It is desirable to do. The same applies to the following embodiments.

  According to the semiconductor integrated circuit device of the second embodiment, the same effect as that of the first embodiment can be obtained.

(Third embodiment)
The third embodiment relates to an example of a driving method of the plate line PL of the semiconductor integrated circuit device of the first embodiment (FIG. 1). More specifically, the present invention relates to the case where the potential of the plate line PL is fixed to ½ Vaa.

  FIG. 4 shows a third embodiment of the present invention and shows the operation of the semiconductor integrated circuit device of FIG. Taking the case where information is read out from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 4, the standby state is the same as that of the second embodiment except that the plate line PL is driven to ½ Vaa. When active, the reset signal RST and the word lines WL0, WL2, WL3 are set to low level. In this state, when the block selection signal BS is set to the high level, the potential of the plate line PL (= 1/2 Vaa) is applied to one end of the ferroelectric capacitor C1, and the potential of the bit line BL (= Vss) to the other end. ) Is applied. Therefore, information is read from the ferroelectric capacitor C1 to the bit line BL, and then the potential of the bit line BL is amplified to the potential Vss or the potential Vaa.

  In the case of “0” information, since the bit line BL is at the potential Vss and the potential of the plate line PL is ½ Vaa, the “0” information is rewritten to the ferroelectric capacitor C1. In the case of “1” information, since the bit line BL is at the potential Vaa and the potential of the plate line PL is ½ Vaa, the “1” information is rewritten to the ferroelectric capacitor C1. Thereafter, the block selection signal BS is set to the low level, and the reset signal RST and the word lines WL0, WL2, and WL3 are set to the high level, thereby shifting to the standby state.

  According to the semiconductor integrated circuit device of the third embodiment, the same effect as that of the first embodiment can be obtained. Further, according to the third embodiment, since a potential higher than Vss is always applied to the plate line PL, the potentials of the source and drain of the cell transistors Q0 to Q3 are the same as those of the plate line PL during standby. It becomes. Therefore, during standby, the voltage applied to the cell transistors Q0 to Q3 decreases, and the electric field applied to the gate oxide films of the cell transistors Q0 to Q3 can be relaxed. As a result, the problem that the reliability of the semiconductor integrated circuit device is reduced can be avoided.

(Fourth embodiment)
The fourth embodiment relates to an example of a driving method of the plate line PL of the semiconductor integrated circuit device of the first embodiment (FIG. 1).

  As described in the first embodiment, both ends of the ferroelectric capacitors C0 to C3 are set to the same potential during standby. For this reason, the “1” information held in the ferroelectric capacitors C0 to C3 is not destroyed by the potential of the cell nodes SN0 to SN3 being lowered during standby. Therefore, the potential of the plate line PL during standby can be set arbitrarily. The fourth embodiment utilizes this feature and is a modification of the second embodiment.

  FIG. 5 shows a fourth embodiment of the present invention and shows the operation of the semiconductor integrated circuit device of FIG. Taking the case where information is read from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 5, the standby state is the same as that of the second embodiment except that the plate line PL is set to an arbitrary potential, for example, the potential ref. When active, the reset signal RST, the word lines WL0, WL2, and WL3 are set to the low level, and the block selection signal BS is set to the high level. In this state, the plate line PL is driven to the internal power supply potential Vaa, whereby information is read from the ferroelectric capacitor C1. In the case of “0” information, rewriting is performed while the plate line PL is being driven. In the case of “1” information, rewriting is performed by setting the plate line PL to the potential Vss. Thereafter, the block selection signal BS is set to the low level, the reset signal RST, the word lines WL0, WL2, and WL3 are set to the high level, and the plate line PL is driven to the potential ref to shift to the standby state. .

  According to the semiconductor integrated circuit device of the fourth embodiment, the same effect as that of the first embodiment can be obtained. Further, according to the fourth embodiment, the potential of the plate line PL in standby is set higher than the potential Vss. Accordingly, since the voltage applied to the cell transistors Q0 to Q3 is lowered during standby, the problem of reduced reliability can be avoided by relaxing the electric field applied to the gate oxide films of the cell transistors Q0 to Q3.

(Fifth embodiment)
The fifth embodiment relates to an example of a driving method of the plate line PL of the semiconductor integrated circuit device of the first embodiment (FIG. 1). The fifth embodiment uses the same features as the fourth embodiment and is a modification of the second embodiment.

  FIG. 6 shows a fifth embodiment of the present invention and shows the operation of the semiconductor integrated circuit device of FIG. Taking the case where information is read from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 6, the standby state is the same as that of the second embodiment except that the plate line PL is driven to the internal power supply potential Vaa. When active, the reset signal RST and the word lines WL0, WL2, WL3 are set to low level. In this state, when the block selection signal BS is set to the high level, a voltage is applied to both ends of the ferroelectric capacitor C1, and information is read from the ferroelectric capacitor C1 to the bit line BL. The read information is amplified by a sense amplifier. In the case of “0” information, rewriting is performed while the plate line PL is being driven. In the case of “1” information, rewriting is performed by setting the plate line PL to the potential Vss. Thereafter, the plate line PL is driven and shifts to a standby state. Thereafter, the block selection signal BS is set to the low level, the reset signal RST, the word lines WL0, WL2, and WL3 are set to the high level, and the plate line PL is driven to the potential Vaa to shift to the standby state. .

  According to the semiconductor integrated circuit device of the fifth embodiment, the effect obtained by combining the first embodiment and the fourth embodiment can be obtained.

(Sixth embodiment)
The sixth embodiment relates to a folded bit line configuration. FIG. 7 shows a circuit configuration of a semiconductor integrated circuit device according to the sixth embodiment of the present invention. As shown in FIG. 7, cell blocks CB0 and CB1 having the same configuration as the cell block CB of FIG. 1 are provided for bit lines / BL and BL (bit line pairs), respectively. Bit lines BL and / BL are connected to sense amplifier SA.

  Cell block CB0 is constituted by cell transistors Q0 to Q3, ferroelectric capacitors C0 to C3, reset transistor QR0, block selection transistor QS0, and local bit line / LBL. Memory cells composed of cell transistors Q0 to Q3 and ferroelectric capacitors C0 to C3 are connected in parallel, and each memory cell is connected between a plate line / PL and a local bit line / LBL. A reset transistor QR0 is connected between the plate line / PL and the local bit line / LBL. Block select transistor QS0 is connected between local bit line / LBL and bit line / BL.

  The cell block CB1 is configured by the cell transistors Q4 to Q7, the ferroelectric capacitors C4 to C7, the reset transistor QR1, the block selection transistor QS1, and the local bit line LBL. Memory cells composed of cell transistors Q4 to Q7 and ferroelectric capacitors C4 to C7 are connected in parallel, and each memory cell is connected between a plate line PL and a local bit line LBL. A reset transistor QR1 is connected between the plate line PL and the local bit line LBL. A block selection transistor QS1 is connected between the local bit line LBL and the bit line BL.

  Cell transistors Q0, Q4 have their gates connected to word line WL0. The gates of the cell transistors Q1, Q5 are connected to the word line WL1. Cell transistors Q2, Q6 have their gates connected to word line WL2. The gates of cell transistors Q3 and Q7 are connected to word line WL3. The reset transistors QR0 and QR1 are controlled by a reset signal RST. Block selection transistors QS0 and QS1 are controlled by block selection signals / BS and BS, respectively.

  Next, the operation will be described. The operations in the cell blocks CB0 and CB1 are the same as those in the first embodiment. In the case of reading a memory cell in the cell block CB0, only the block selection transistor QS0 is turned on and the block selection transistor QS1 is kept off. In this state, only the plate line / PL is driven, and the plate line PL is not driven. As a result, cell information is read out to the bit line / BL. The potential on the bit line BL is used as a reference potential. The potential on the bit line / BL is amplified by the sense amplifier SA using the potential on the bit line BL. The same applies to reading of memory cells in the cell block CB1.

  According to the semiconductor integrated circuit device of the sixth embodiment, by adopting the folded bit line configuration, the same effect as that of the first embodiment can be obtained while reducing the area of the sense amplifier and the noise of the memory cell array. can get.

(Seventh embodiment)
The seventh embodiment relates to an example of a method for driving the plate lines PL, / PL of the semiconductor integrated circuit device of the sixth embodiment (FIG. 7). More specifically, as in the second embodiment, the plate lines PL and / PL relate to the case where the standby potential is the potential Vss and the driving potential is the internal power supply potential Vaa. The operation is also the same as the combination of the sixth embodiment and the second embodiment.

  FIG. 8 shows a seventh embodiment of the present invention and shows the operation of the semiconductor integrated circuit device of FIG. Taking the case where information is read out from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 8, at the time of standby, the reset signal RST and the word lines WL0 to WL3 are set to the high level, and the block selection signals BS and / BS are set to the low level. The plate lines PL and / PL are set to the potential Vss.

  When active, the reset signal RST is set to the low level, and the word lines WL0, WL2, WL3 of the non-selected cells are set to the low level. The word line WL1 of the selected cell maintains a high level. Next, the block selection signal / BS is set to the high level, whereby the block selection transistor QS0 is turned on. The block selection signal BS maintains a low level.

  In this state, the cell information is read from the ferroelectric capacitor C1 to the bit line / BL by driving the plate line / PL to the internal power supply potential Vaa. The plate line PL maintains the potential Vss. The potential read to the bit line / BL is amplified by the sense amplifier SA, and then a rewrite operation is performed as in the second embodiment. Thereafter, the reset signal RST and the word lines WL0, WL2, and WL3 are set to the high level, and the block selection signal / BS is set to the low level, thereby shifting to the standby state.

  According to the semiconductor integrated circuit device of the seventh embodiment, the effect obtained by combining the sixth embodiment and the second embodiment can be obtained.

(Eighth embodiment)
The eighth embodiment relates to an example of a method for driving the plate lines PL, / PL of the semiconductor integrated circuit device of the sixth embodiment (FIG. 7). More specifically, it relates to the case where the potentials of the plate lines PL and / PL are fixed to ½ Vaa as in the third embodiment.

  FIG. 9 shows an eighth embodiment of the present invention, and shows the operation of the semiconductor integrated circuit device of FIG. Taking the case where information is read from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 9, the standby state is the same as that of the seventh embodiment except that the plate lines PL and / PL are driven to the potential ½ Vaa. When active, the reset signal RST and the word lines WL0, WL2, WL3 are set to low level. In this state, when the block selection signal / BS is set to the high level, information is read out to the bit line / BL. The block selection signal BS maintains a low level. Subsequently, the potential on the bit line / BL is amplified, and then a rewrite operation is performed in the same manner as in the third embodiment, and then the standby state is entered in the same manner as in the seventh embodiment.

  According to the semiconductor integrated circuit device of the eighth embodiment, the same effect as that of the sixth embodiment can be obtained.

(Ninth embodiment)
The ninth embodiment relates to an example of a method for driving the plate lines PL, / PL of the semiconductor integrated circuit device of the sixth embodiment (FIG. 7). More specifically, the plate lines PL and / PL are driven as in the fourth embodiment. FIG. 10 shows the ninth embodiment of the present invention and shows the operation of the semiconductor integrated circuit device of FIG. . Taking the case where information is read out from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 10, the standby state is the same as that of the seventh embodiment except that the plate lines PL and / PL are driven to the potential ref. When active, the reset signal RST, the word lines WL0, WL2, and WL3 are set to the low level, and the block selection signal / BS is set to the high level. The block selection signal BS maintains a low level. In this state, the plate line / PL is driven to the internal power supply potential Vaa, whereby information is read from the ferroelectric capacitor C1. The plate line PL maintains the potential ref. Subsequently, the potential on the bit line / BL is amplified, and then a rewrite operation is performed in the same manner as in the fourth embodiment, and then the standby state is entered in the same manner as in the seventh embodiment.

  According to the semiconductor integrated circuit device of the ninth embodiment, the effect obtained by combining the sixth embodiment and the fourth embodiment can be obtained.

(10th Embodiment)
The tenth embodiment relates to an example of a method for driving the plate lines PL, / PL of the semiconductor integrated circuit device of the sixth embodiment (FIG. 7). More specifically, the plate lines PL and / PL are driven as in the fifth embodiment.

  FIG. 11 shows the tenth embodiment of the present invention and shows the operation of the semiconductor integrated circuit device of FIG. Taking the case where information is read from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 11, the standby state is the same as that of the seventh embodiment except that the plate lines PL and / PL are driven to the internal power supply potential Vaa. When active, the reset signal RST and the word lines WL0, WL2, WL3 are set to low level. In this state, when the block selection signal / BS is set to the high level, information is read from the ferroelectric capacitor C1 to the bit line / BL. Block selection signal BS maintains a low level, and plate line PL maintains internal power supply potential Vaa. Subsequently, the potential on the bit line / BL is amplified, and then a rewrite operation is performed in the same manner as in the fifth embodiment, and then the standby state is entered in the same manner as in the seventh embodiment.

  According to the semiconductor integrated circuit device of the tenth embodiment, the effect obtained by combining the sixth embodiment and the fifth embodiment can be obtained.

(Eleventh embodiment)
In the eleventh embodiment, in addition to the configuration of the sixth embodiment (FIG. 7), the plate line / PL is shared by two cell blocks connected to the bit line / BL. Similarly, the plate line PL is shared by two cell blocks connected to the bit line BL.

  FIG. 12 shows a circuit configuration of a semiconductor integrated circuit device according to the eleventh embodiment of the present invention. As shown in FIG. 12, cell blocks CB2 and CB3 similar to the cell block CB of FIG. 1 are provided for the bit lines / BL and BL, respectively.

  The cell blocks CB0 and CB1 are the same as those in FIG. 7 except that the local bit line / LBL is the local bit line / LBL0 and the local bit line LBL is the local bit line LBL0. The selection transistors QR0 and QR1 are controlled by a reset signal RST0. Block selection transistors QS0 and QS1 are controlled by block selection signals / BS0 and BS0, respectively.

  Cell block CB2 is constituted by cell transistors Q8 to Q11, ferroelectric capacitors C8 to C11, reset transistor QR2, block selection transistor QS2, and local bit line / LBL1. Memory cells composed of cell transistors Q8 to Q11 and ferroelectric capacitors C8 to C11 are connected in parallel, and each memory cell is connected between a plate line / PL and a local bit line / LBL1. A reset transistor QR2 is connected between the plate line / PL and the local bit line / LBL1. Block select transistor QS2 is connected between local bit line / LBL1 and bit line / BL.

  The cell block CB3 is configured by the cell transistors Q12 to Q15, the ferroelectric capacitors C12 to C15, the reset transistor QR3, the block selection transistor QS3, and the local bit line LBL1. Memory cells composed of cell transistors Q12 to Q15 and ferroelectric capacitors C12 to C15 are connected in parallel, and each memory cell is connected between a plate line PL and a local bit line LBL1. A reset transistor QR3 is connected between the plate line PL and the local bit line LBL1. A block selection transistor QS3 is connected between the local bit line LBL1 and the bit line BL.

  Cell transistors Q8 and Q12 have their gates connected to word line WL4. Cell transistors Q9 and Q13 have their gates connected to word line WL5. The gates of cell transistors Q10 and Q14 are connected to word line WL6. Cell transistors Q11 and Q15 have their gates connected to word line WL7. The selection transistors QR2 and QR3 are controlled by a reset signal RST1. Block selection transistors QS2 and QS3 are controlled by block selection signals / BS1 and BS1, respectively.

  Next, the operation of the semiconductor integrated circuit device of FIG. 12 will be described. The operations in the cell blocks CB0 to CB3 are the same as in the first embodiment. When the memory cell in the cell block CB0 is read when active, the reset transistor QR0 (and QR1) is turned off, and the cell transistors of unselected cells are turned off. The reset transistor QR2 (and QR3) remains on.

  Next, only the block selection transistor QS0 is turned on, and the block selection transistors QS1 to QS3 are kept off. In this state, only the plate line / PL is driven, and the plate line PL is not driven. As a result, cell information is read out to the bit line / BL. The potential on the bit line / BL is amplified by the sense amplifier SA using the potential on the bit line BL as a reference potential. The same applies to reading of memory cells in the cell blocks CB1 to CB3.

  According to the semiconductor integrated circuit device of the eleventh embodiment, the same effect as that of the first embodiment can be obtained. When information is read from the ferroelectric capacitors in the cell block CB0, the plate line / PL is driven, so that the ferroelectric capacitors C8 to C11 in the non-selected cell block CB2 are also connected to the plate line / PL. A potential is applied. However, both ends of the ferroelectric capacitors C8 to C11 are short-circuited to the same potential by the reset transistor QR2 and the cell transistors Q8 to Q11. For this reason, the information of the ferroelectric capacitors C8 to C11 is not destroyed.

  According to the eleventh embodiment, the plate lines PL and / PL are shared by a plurality of cell blocks. For this reason, the area of the plate lines PL and / PL can be reduced and the resistance value can be reduced. As a result, the driving capability of the plate line driving circuit DPL can be improved over the first to tenth embodiments, and the area occupied by the plate line driving circuit DPL can be reduced.

(Twelfth embodiment)
The twelfth embodiment relates to an example of a method for driving the plate lines PL, / PL of the semiconductor integrated circuit device of the eleventh embodiment (FIG. 12). More specifically, as in the second embodiment, the plate lines PL and / PL relate to the case where the standby potential is the potential Vss and the driving potential is the internal power supply potential Vaa. The operation is also the same as the combination of the eleventh embodiment and the second embodiment.

  FIG. 13 shows the twelfth embodiment of the present invention, and shows the operation of the semiconductor integrated circuit device of FIG. Taking the case where information is read out from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 13, at the time of standby, the reset signals RST0 and RST1 and the word lines WL0 to WL7 are set to the high level, and the block selection signals BS0, / BS0, BS1, and / BS1 are set to the low level. The plate lines PL and / PL are set to the potential Vss.

  When active, the reset signal RST0 and the word lines WL0, WL2, WL3 of the non-selected cells are set to a low level. The reset signal RST1, the word line WL1 of the selected cell, and the word lines WL4 to WL7 of the unselected cell blocks CB2 and CB3 are maintained at the high level. Next, the block selection signal QS0 is turned on by setting the block selection signal / BS0 to the high level. Block selection signals BS0, / BS1, BS1 are maintained at a low level.

  In this state, the cell information is read from the ferroelectric capacitor C1 to the bit line / BL by driving the plate line / PL to the internal power supply potential Vaa. The plate line PL maintains the potential Vss. The potential read to the bit line / BL is amplified by the sense amplifier SA, and then a rewrite operation is performed as in the second embodiment. Thereafter, the reset signals RST0 and RST1 and the word lines WL0, WL2 and WL3 are set to the high level, and the block selection signal / BS0 is set to the low level to shift to the standby state.

  According to the semiconductor integrated circuit device of the twelfth embodiment, the effect obtained by combining the eleventh embodiment and the second embodiment can be obtained.

(13th Embodiment)
The thirteenth embodiment relates to an example of a method for driving the plate lines PL, / PL of the semiconductor integrated circuit device of the eleventh embodiment (FIG. 12). More specifically, it relates to the case where the potentials of the plate lines PL and / PL are fixed to ½ Vaa as in the third embodiment.

  FIG. 14 shows the operation of the semiconductor integrated circuit device of FIG. 12, showing the thirteenth embodiment of the present invention. Taking the case where information is read from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 14, the standby state is the same as that of the twelfth embodiment except that the plate lines PL and / PL are driven to the potential ½ Vaa. When active, the reset signal RST0 and the word lines WL0, WL2, WL3 of the non-selected cells are set to a low level. In this state, when the block selection signal / BS0 is set to the high level, information is read out to the bit line / BL. Next, the potential on the bit line / BL is amplified. The word lines WL4 to WL7 are maintained at a high level, and the block selection signals BS0, BS1, / BS1 are maintained at a low level. Subsequently, the potential on the bit line / BL is amplified, and then a rewrite operation is performed in the same manner as in the third embodiment, and then the standby state is entered in the same manner as in the twelfth embodiment.

  According to the semiconductor integrated circuit device of the thirteenth embodiment, the effect obtained by combining the eleventh embodiment and the third embodiment can be obtained.

(14th Embodiment)
The fourteenth embodiment relates to an example of a method for driving the plate lines PL, / PL of the semiconductor integrated circuit device of the eleventh embodiment (FIG. 12). More specifically, the plate lines PL and / PL are driven as in the fourth embodiment. FIG. 15 shows the fourteenth embodiment of the present invention and shows the operation of the semiconductor integrated circuit device of FIG. . Taking the case where information is read out from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 15, the standby state is the same as that of the twelfth embodiment except that the potentials of the plate lines PL and / PL are driven to the potential ref. When active, the reset signal RST0, the word lines WL0, WL2, and WL3 of the non-selected cells are set to the low level, and the block selection signal / BS0 is set to the high level. In this state, the plate line / PL is driven to the internal power supply potential Vaa, whereby information is read from the ferroelectric capacitor C1. The word lines WL4 to WL7 are maintained at the high level, the block selection signals BS0, BS1, and / BS1 are maintained at the low level, and the plate line PL is maintained at the potential ref. Subsequently, the potential on the bit line / BL is amplified, then a rewrite operation is performed in the same manner as in the fourth embodiment, and then the standby state is entered as in the twelfth embodiment.

  According to the semiconductor integrated circuit device of the fourteenth embodiment, the effect obtained by combining the eleventh embodiment and the fourth embodiment can be obtained.

(Fifteenth embodiment)
The fifteenth embodiment relates to an example of a method for driving the plate lines PL, / PL of the semiconductor integrated circuit device of the eleventh embodiment (FIG. 12). More specifically, the plate lines PL and / PL are driven as in the fifth embodiment.

  FIG. 16 shows the fifteenth embodiment of the present invention and shows the operation of the semiconductor integrated circuit device of FIG. Taking the case where information is read from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 16, the standby state is the same as that of the twelfth embodiment except that the plate lines PL and / PL are driven to the internal power supply potential Vaa. When active, the reset signal RST0 and the word lines WL0, WL2, WL3 of the non-selected cells are set to a low level. In this state, when the block selection signal / BS0 is set to the high level, information is read from the ferroelectric capacitor C1 to the bit line / BL. The word lines WL4 to WL7 are maintained at a high level, the block selection signals BS0, BS1, and / BS1 are maintained at a low level, and the plate line PL is maintained at the internal power supply potential Vaa. Subsequently, the potential on the bit line / BL is amplified, then a rewrite operation is performed in the same manner as in the fifth embodiment, and then the standby state is entered in the same manner as in the twelfth embodiment.

  According to the semiconductor integrated circuit device of the fifteenth embodiment, the effect obtained by combining the eleventh embodiment and the fifth embodiment can be obtained.

(Sixteenth embodiment)
The sixteenth embodiment relates to the structure of the semiconductor integrated circuit device of the first embodiment (FIG. 1). FIG. 17 shows a sixteenth embodiment of the present invention, and schematically shows a sectional structure of a cell block applicable to the semiconductor integrated circuit device of FIG. As shown in FIG. 17, source / drain regions (active regions) SD1 to SD9 are formed on the surface of the semiconductor substrate sub with a distance from each other. On the semiconductor substrate sub between the source / drain regions (diffusion layers) SD1 and SD2, a gate electrode (block selection signal line) BS is provided via a gate insulating film (not shown). Similarly, gate electrodes (word lines) WL0, WL1, WL2, and WL3 are provided above the semiconductor substrate sub between the source / drain regions SD2 and SD3, between SD4 and SD5, between SD5 and SD6, and between SD7 and SD8, respectively. . A gate electrode (reset signal line) RST is provided above the semiconductor substrate sub between the source / drain regions SD8 and SD9. Each gate electrode and two adjacent source / drain regions constitute a cell transistor QR, a block selection transistor QS, and cell transistors Q0 to Q3.

  A local bit line LBL is provided above the gate electrodes WL0 to WL3. Local bit line LBL is electrically connected to source / drain regions SD2, SD5, SD8 through contact P1. Ferroelectric capacitors C0 to C3 are provided above the local bit line LBL. The ferroelectric capacitors C0 to C3 are each composed of a lower electrode BE, a ferroelectric film FC, and an upper electrode TE. The lower electrodes BE of the ferroelectric capacitors C0 to C3 are electrically connected to the source / drain regions SD3, SD4, SD6, and SD7 through the contacts P2. The contact P2 is provided on a different surface (before or behind the contact P1) from the contact P1.

  Each upper electrode TE of the ferroelectric capacitors C0 to C3 is electrically connected to a plate line PL provided above the upper electrode TE through a contact P3. Plate line PL is electrically connected to source / drain region SD9 via contact P4.

  A bit line BL is provided above the plate electrode PL. Bit line BL is electrically connected to source / drain region SD1 through contact P5.

According to the semiconductor integrated circuit device of the sixteenth embodiment, the cell block CB of the semiconductor integrated circuit device of the first embodiment can be realized. Further, a cell size of 6F ² of 3F in the extending direction of the bit line BL and approximately 2F in the extending direction of the word lines WL0 to WL3 can be realized.

(17th Embodiment)
The seventeenth embodiment relates to a layout applicable to the sixteenth embodiment. 18 and 19 show a seventeenth embodiment of the present invention and show a layout applicable to the semiconductor integrated circuit device of FIG. A cross-sectional view taken along line XVII-XVII in FIGS. 18 and 19 corresponds to FIG.

  As shown in FIGS. 18 and 19, the active area AA1 has a substantially V-shape. Each V-shaped side is positioned so as to cross the gate electrodes BS and WL0. A source / drain region SD2 is formed at a vertex of the V shape (one end of each of the two sides), and a contact P1 is formed at this position. Source / drain regions SD1 and SD3 are formed at the other ends of the two sides, and contacts P2 and P5 are formed at these positions, respectively. The active area AA1 is not limited to the V shape, and any one of the source / drain regions SD1 and SD3 and the source / drain region SD2 may have any coordinate value on the axis along the extending direction of the gate electrode. Such a shape may be used.

  The active area AA2 is also formed in the same manner as the active area AA1 with respect to the gate electrodes WL1 and WL2. A source / drain region SD5 is formed at the apex of the active area AA2, and a contact P1 is formed at this position. Source / drain regions SD4 and SD6 are respectively formed at the other ends of the two sides of the active area AA2, and contacts P2 are respectively formed at these positions.

  The active area AA3 is formed in the same manner as the active area AA1 with respect to the gate electrodes WL3 and RST. A source / drain region SD8 is formed at the apex of the active region AA3, and a contact P1 is formed at this position. Source / drain regions SD7 and SD9 are formed at the other ends of the two sides of the active area AA3, and contacts P2 and P4 are formed at these positions, respectively.

  According to the semiconductor integrated circuit device of the seventeenth embodiment, the semiconductor integrated circuit device of FIG. 17 can be realized, and the same effect as that of the sixteenth embodiment can be obtained.

(Eighteenth embodiment)
The eighteenth embodiment relates to the structure of the semiconductor integrated circuit device of the sixth embodiment (FIG. 7) and the eleventh embodiment (FIG. 12). FIG. 20 shows a eighteenth embodiment of the present invention, and schematically shows a cross-sectional structure of a cell block CB0 applicable to the semiconductor integrated circuit device of FIGS. The cell blocks CB1 to CB3 are also realized by a similar structure.

  As shown in FIG. 20, the structure of the plate lines PL and / PL and the block selection transistor QS1 are different from the semiconductor integrated circuit device of FIG. That is, the source / drain region SD0 is formed on the surface of the semiconductor substrate sub with a distance from the source / drain region SD1. A gate electrode (block selection signal line) BS1 is provided above the semiconductor substrate sub between the source / drain regions SD0 and SD1 via a gate insulating film (not shown). Block selection transistor QS1 is configured by source / drain regions SD0 and SD1 and gate electrode BS1.

  A wiring layer M1 is provided above the gate electrode BS1. Wiring layer M1 is electrically connected to source / drain region SD1 through contact P5. Bit line / BL is electrically connected to source / drain region SD0 through contact P6.

  A wiring layer M2 is provided instead of the plate line PL of FIG. Wiring layer M2 is electrically connected to plate line / PL provided above bit line / BL via contact P7.

  When the cell block CB1 having the same configuration as the cell block CB0 of FIG. 20 is provided, the wiring layer M2 of the cell block CB1 is electrically connected to the plate line PL via the contact P7.

  In the same layer (level) as the plate line / PL, shunt wiring layers RST, WL0 to WL3, BS0, BS1 are provided. These shunt metal wiring layers RST, WL0 to WL3, BS0, BS1 can alleviate signal delay due to the resistance of the gate electrodes RST, WL0 to WL3, BS0, BS1 of the transistors. For example, the shunt wiring layers RST, WL0 to WL3, BS0, BS1 extend in the same direction as the gate electrode, and are electrically connected to the corresponding gate electrode (with the same reference number) with a certain interval in the extending direction. Connected (not shown).

  Further, a main block selection transistor wiring MBS for realizing the hierarchical word line system is provided in the same layer as the shunt metal wiring.

  Of course, it is possible to adopt a configuration using either a shunt wiring or a hierarchical word line system.

  In the present embodiment and the following embodiments related to the structure, each transistor is formed by a field transistor, but can be formed by STI (Shallow Trench Isolation).

  According to the semiconductor integrated circuit device of the eighteenth embodiment, the cell blocks CB0 to CB3 of the semiconductor integrated circuit device of the sixth and eleventh embodiments can be realized, and a folded bit line configuration can be realized.

(Nineteenth embodiment)
The nineteenth embodiment relates to a layout applicable to the eighteenth embodiment. 21 and 22 show the nineteenth embodiment of the present invention, which shows a layout applicable to the semiconductor integrated circuit device of FIG. A sectional view taken along line XX-XX in FIGS. 21 and 22 corresponds to FIG.

  21 and 22 are the same as FIGS. 18 and 19 except that the active area AA0 and the contact P6 are added. An active area AA0 is formed at a distance from the active area AA1, and a contact P6 is formed at this position. As in the seventeenth embodiment, the shapes of the active areas AA1 to AA3 are not limited to a substantially V shape.

  According to the semiconductor integrated circuit device of the nineteenth embodiment, the semiconductor integrated circuit device of FIG. 20 can be realized, and the same effect as that of the eighteenth embodiment can be obtained.

(20th embodiment)
The twentieth embodiment relates to the structure of a semiconductor integrated circuit device. In the eighteenth embodiment, the plate lines PL and / PL are provided in a hierarchy above the bit line / BL, and are electrically connected to the ferroelectric capacitors C0 to C3 via the wiring layer M2. On the other hand, in the twentieth embodiment, the plate lines PL and / PL are provided in the layer of the wiring layer M2, as in the sixteenth embodiment.

  FIG. 23 shows a twentieth embodiment of the present invention, and schematically shows a cross-sectional structure of a cell block CB0 applicable to the semiconductor integrated circuit device of FIGS. As shown in FIG. 23, in the semiconductor integrated circuit device of FIG. 20, the wiring layer M2 is the plate line / PL, and the plate line PL is provided in the same hierarchy as the plate line / PL. Different. The plate line PL extends, for example, in the same direction as the plate line / PL in a plane different from that in FIG. 23, and is electrically connected to the upper electrode TE of the cell block CB1 (not shown) via the contact P3.

  According to the twentieth embodiment, a folded bit line configuration can be realized without adding an upper wiring layer to the structure of FIG.

(21st Embodiment)
The twenty-first embodiment relates to the shapes of the plate lines PL, / PL applicable to the twentieth embodiment. FIG. 24 shows the twenty-first embodiment of the invention, and shows the planar shapes of the plate lines PL, / PL applicable to the semiconductor integrated circuit device of FIG. As shown in FIG. 24, the plate lines PL, / PL have a substantially comb shape. The portions corresponding to the comb-shaped teeth of the plate lines PL and / PL are provided at the positions of the plate lines PL and / PL extending in the horizontal direction of the drawing in FIG. The plate lines PL and / PL extend over two cell blocks in the horizontal direction of FIG. 24, and a contact P4 is formed at substantially the center of the portion corresponding to the teeth.

  According to the twenty-first embodiment, the same effect as in the twentieth embodiment can be obtained.

(Twenty-second embodiment)
The twenty-second embodiment relates to the structure of the semiconductor integrated circuit device. In the sixteenth to twentieth embodiments, the local bit line LBL (local bit lines / LBL, LBL0) is realized by a wiring layer provided above the gate electrodes WL0 to WL3. On the other hand, in the twenty-second embodiment, it is realized by an active region.

  FIG. 25 shows a twenty-second embodiment of the present invention, and schematically shows a cross-sectional structure of a cell block applicable to the semiconductor integrated circuit device of FIGS. As shown in FIG. 25, local bit line / LBL (0) and contact P1 are not provided. The source / drain regions SD2, SD5, SD8 are connected to each other by an active region on a surface different from that in FIG. 25 (that is, a front surface or a back surface). Thereby, the source / drain regions SD2, SD5 and SD8 are electrically connected.

  According to the twenty-second embodiment, the local bit line / LBL is realized by the active region. Therefore, it is not necessary to provide a wiring layer that functions as the local bit line / LBL. Therefore, the same effect as that of the twentieth embodiment can be obtained while keeping the manufacturing cost of the semiconductor integrated circuit device low.

(23rd Embodiment)
The twenty-third embodiment relates to a layout applicable to the twenty-second embodiment. 26 shows a twenty-third embodiment of the present invention and shows a layout applicable to the semiconductor integrated circuit device of FIG. As shown in FIG. 26, the active area AA4 has a first portion and a second portion. The first portion crosses the gate electrodes BS0, WL0 to WL3, RST. The second portion extends from the first portion in the extending direction of the first partial gate electrodes BS0, WL0 to WL3, RST, then extends in the same direction as the first portion, and crosses the gate electrodes WL0 to WL3. Both ends of the first portion correspond to the source / drain regions SD1 and SD9. In the second part, both sides of the gate electrode WL0 correspond to the source / drain regions SD2 and SD3. Both sides of the gate electrode WL1 correspond to the source / drain regions SD4 and SD5, and both sides of the gate electrode WL2 correspond to the source / drain regions SD5 and SD6. Both sides of the gate electrode WL3 correspond to the source / drain regions SD7 and SD8.

  According to the twenty-third embodiment, the source / drain regions SD2, SD5, SD8 are electrically connected by the first portion of the active region AA4. Therefore, the same effect as the twenty-second embodiment can be obtained.

(24th Embodiment)
The twenty-fourth embodiment relates to a modification of the first embodiment (FIG. 1). FIG. 27 shows a circuit configuration of a semiconductor integrated circuit device according to the twenty-fourth embodiment of the present invention. As shown in FIG. 27, one end of the reset transistor QR (an end opposite to the end connected to the local bit line LBL) is connected to the first power supply VPR1. During standby, the first power supply is made equal to the potential of the plate line PL, so that the same state as that of the first embodiment can be obtained. Other configurations and operations are the same as those in the first embodiment.

  According to the twenty-fourth embodiment, the same effects as in the first embodiment can be obtained.

(25th Embodiment)
The twenty-fifth embodiment relates to an example of a driving method of the plate line PL of the semiconductor integrated circuit device of the twenty-fourth embodiment (FIG. 27). More specifically, as in the second embodiment, the potential of the plate line PL during standby is the potential Vss and the potential during driving is the internal power supply potential Vaa.

  FIG. 28 shows the operation of the semiconductor integrated circuit device of FIG. 27, for illustrating the twenty-fifth embodiment of the present invention. During standby, the first power supply VPR1 is set to the potential Vss. In this state, the same operation as in the second embodiment is performed.

  According to the 25th embodiment, the same effect as in the second embodiment can be obtained.

(26th Embodiment)
The twenty-sixth embodiment has a configuration combining the sixth embodiment (FIG. 7) and the twenty-fourth embodiment (FIG. 27). FIG. 29 shows a circuit configuration of a semiconductor integrated circuit device according to the twenty-sixth embodiment of the present invention. As shown in FIG. 29, in the configuration of the sixth embodiment (FIG. 7), as in the twenty-fourth embodiment, one end of the reset transistors QR0, QR1 (opposite to the end connected to the local bit lines / LBL, LBL, respectively) Is connected to the first power supply VPR1. At the time of standby, the same state as that in the sixth embodiment can be obtained by making the potential of the first power supply VPR1 equal to the potential of the plate line PL. Other configurations and operations are the same as those in the sixth embodiment.

  According to the twenty-sixth embodiment, the same effects as in the sixth embodiment can be obtained.

(27th Embodiment)
The twenty-seventh embodiment relates to an example of a driving method of the plate lines PL, / PL of the semiconductor integrated circuit device of the twenty-sixth embodiment (FIG. 29). More specifically, as in the second embodiment, the plate lines PL and / PL relate to the case where the standby potential is the potential Vss and the driving potential is the internal power supply potential Vaa.

  FIG. 30 shows the operation of the semiconductor integrated circuit device of FIG. 29, for illustrating the twenty-seventh embodiment of the present invention. During standby, the potential of the first power supply VPR1 is set to Vss. In this state, the same operation as in the second and seventh embodiments is performed.

  According to the twenty-seventh embodiment, an effect obtained by combining the twenty-sixth embodiment and the second embodiment can be obtained.

(Twenty-eighth embodiment)
The twenty-eighth embodiment relates to an example of a method for driving the plate lines PL, / PL of the semiconductor integrated circuit device of the twenty-sixth embodiment (FIG. 29). More specifically, it relates to the case where the potentials of the plate lines PL and / PL are fixed to ½ Vaa as in the third embodiment.

  FIG. 31 shows the operation of the semiconductor integrated circuit device of FIG. 29, for illustrating the twenty-eighth embodiment of the present invention. During standby, the potential of the first power supply VPR1 is set to 1/2 Vaa. In this state, the same operation as in the third and eighth embodiments is performed.

  According to the twenty-eighth embodiment, an effect obtained by combining the twenty-sixth embodiment and the third embodiment can be obtained.

(Twenty-ninth embodiment)
The twenty-ninth embodiment relates to an example of a driving method of the plate lines PL, / PL of the semiconductor integrated circuit device of the twenty-sixth embodiment (FIG. 29). More specifically, the plate lines PL and / PL are driven as in the fourth embodiment.

  FIG. 32 shows the twenty-ninth embodiment of the present invention, and shows the operation of the semiconductor integrated circuit device of FIG. During standby, the potential of the first power supply VPR1 is driven to ref. In this state, the same operation as in the fourth and ninth embodiments is performed.

  According to the 29th embodiment, the effect obtained by combining the 26th embodiment and the fourth embodiment can be obtained.

(Thirty Embodiment)
The thirtieth embodiment relates to an example of a method for driving the plate lines PL, / PL of the semiconductor integrated circuit device of the twenty-sixth embodiment (FIG. 29). More specifically, the plate lines PL and / PL are driven as in the fifth and tenth embodiments.

  FIG. 33 shows the operation of the semiconductor integrated circuit device of FIG. 29, for illustrating the 30th embodiment of the present invention. During standby, the first power supply potential VPR is driven to the internal power supply potential Vaa. In this state, the same operation as in the fifth and tenth embodiments is performed.

  According to the thirtieth embodiment, an effect obtained by combining the twenty-sixth embodiment and the fifth embodiment can be obtained.

(Thirty-first embodiment)
In the thirty-first embodiment, no reset transistor is provided. FIG. 34 shows a circuit configuration of a semiconductor integrated circuit device according to the thirty-first embodiment of the present invention. As shown in FIG. 34, cell blocks CB0 and CB2 having a configuration in which the reset transistor QR is removed from the circuit configuration of FIG. 1 are connected to the bit line BL. One end of each of the ferroelectric capacitors C0 to C3 and C8 to C12 is connected to the plate line PL. Next, taking the case where information is read out from the ferroelectric capacitor C1 as an example, the operation will be described below.

  During standby, the same potential (potential Vss) is applied to the plate line PL and the bit line BL. In this state, the cell transistors Q0 to Q3 and Q8 to Q11 and the block selection transistors QS0 and QS2 are turned on during the standby state. Therefore, both ends of the ferroelectric capacitors C0 to C3 and C8 to C11 are set to the same potential.

  When active, the block selection transistor QS2 of the non-selected cell block CB2 is turned off, and the cell transistors Q0, Q2, Q3 other than the selected cell in the selected cell block CB0 are turned off. Next, by driving the plate line PL, information is read out only from the ferroelectric capacitor C1 of the selected cell. Thereafter, the potential on the bit line BL is amplified and rewritten in the same manner as in the first embodiment.

  According to the thirty-first embodiment, the same effect as in the first embodiment can be obtained.

(Thirty-second embodiment)
The thirty-second embodiment relates to an example of a driving method of the plate line PL of the semiconductor integrated circuit device of the thirty-first embodiment (FIG. 34). More specifically, as in the second embodiment, the potential of the plate line PL during standby is the potential Vss and the potential during driving is the internal power supply potential Vaa.

  FIG. 35 shows the operation of the semiconductor integrated circuit device of FIG. 34, for illustrating the thirty-second embodiment of the present invention. Taking the case where information is read out from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 35, during standby, the word lines WL0 to WL7 and the block selection signals BS0 and BS1 are at a high level. When active, the word lines WL0, WL2, WL3 of the cell transistors other than the selected cell in the selected cell block CB0 are set to the low level. Next, the block selection signal BS1 of the unselected cell block CB1 is set to the low level. The block selection signal BS0 of the selected cell block CB0 is kept at the high level. In this state, the cell information is read from the ferroelectric capacitor C1 to the bit line BL by driving the plate line PL to the internal power supply potential Vaa. Thereafter, the potential on the bit line BL is amplified and rewritten in the same manner as in the first embodiment. Then, when the word lines WL0, WL2, WL3 and the block selection signal BS1 are set to the high level, the standby state is entered.

  According to the 32nd embodiment, the same effect as the 31st embodiment can be obtained.

(Thirty-third embodiment)
The thirty-third embodiment relates to a configuration provided with an amplifying unit for amplifying the potentials of the bit lines BL and / BL in addition to the configuration of the sixth embodiment (FIG. 7). FIG. 36 shows a circuit configuration of a semiconductor integrated circuit device according to the thirty-third embodiment of the present invention. As shown in FIG. 36, amplification transistors QA0 and QA1 are provided in cell block CB0 (CB1). One end of the amplification transistor QA0 is connected to the bit line BL, the other end is connected to the second power supply VPR2, and the gate is connected to the local bit line / LBL. One end of the amplification transistor QA1 is connected to the bit line / BL, the other end is connected to the second power supply VPR2, and the gate is connected to the local bit line LBL. It is also possible to connect the other end of the amplifying transistor QA1 to a third power source and control the third power source to have the same potential as the second power source.

  Next, the operation will be described. The standby state is the same as in the sixth embodiment. When active, the reset transistors QR0 and QR1, and the cell transistors Q0, Q2, Q3, Q4, Q6, and Q7 are turned off. In this state, when information is read from the cells in the cell block CB0, only the plate line / PL is driven, and the plate line PL is not driven. As a result, cell information is read out to the local bit line / LBL.

  The potential read to the local bit line / LBL is supplied to the gate of the amplification transistor QA0 and amplified by the amplification transistor QA0. As a result, a signal obtained by amplifying the inverted data of the potential read to the local bit line / LBL appears on the bit line BL. The potential on the bit line BL and the reference potential on the bit line / BL are amplified by the sense amplifier SA.

  After amplification by the sense amplifier SA, the block selection transistor QS0 of the selected cell block is turned on. As a result, the potential of the bit line / BL is transferred to the local bit line / LBL via the block selection transistor QS0. Therefore, the positive logic information of the bit line / BL is rewritten to the ferroelectric capacitor of the selected cell. That is, as in the first embodiment, when the read information is “0” data, the data is written back to the ferroelectric capacitor C1 while the potential of the plate line / PL is at a high level. In the case of “1” data, writing is performed after the potential of the plate line / PL is set to the low level.

  On the other hand, when information is read from a cell in the cell block CB1, the read potential is input to the gate of the amplification transistor QA1 and amplified by the amplification transistor QA1. As a result, a signal obtained by amplifying the inverted data of the read potential appears on the bit line / BL, and then the potential on the bit lines BL and / BL is amplified by the sense amplifier SA.

  After amplification by the sense amplifier SA, the block selection transistor QS1 of the selected cell block is turned on, so that the potential of the local bit line LBL is the same as that of the bit line BL. Therefore, the positive logic information of the bit line BL is rewritten to the ferroelectric capacitor of the selected cell.

  According to the 33rd embodiment, the same effect as the sixth embodiment can be obtained. Furthermore, according to the thirty-third embodiment, amplification transistors QA0 and QA1 for amplifying the read potential on the local bit lines LBL and / LBL are provided. Therefore, the ferroelectric capacitor undergoes polarization inversion with a small load capacity of the local bit lines LBL, / LBL, and thus a read signal can be secured even when the ferroelectric capacitor is small.

(Thirty-fourth embodiment)
The thirty-fourth embodiment relates to an example of a method for driving the plate lines PL, / PL of the semiconductor integrated circuit device of the thirty-third embodiment (FIG. 36). More specifically, as in the second embodiment, the plate lines PL and / PL relate to the case where the standby potential is the potential Vss and the driving potential is the internal power supply potential Vaa.

  FIG. 37 shows the operation of the semiconductor integrated circuit device of FIG. 36, for illustrating the thirty-fourth embodiment of the present invention. Taking the case where information is read out from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 37, during standby, the reset signal RST and the word lines WL0 to WL3 are set to the high level (potential Vaa), the block selection signals BS and / BS are set to the low level, and the plate lines PL and / PL are set to the potential. Vss. Therefore, the local bit line / LBL is set to the low level, and both ends of the ferroelectric capacitors C0 to C3 are set to the same potential. The same applies to the local bit line LBL.

  When active, the reset signal RST and the word lines WL0, WL2, WL3 of the non-selected cells are set to the low level, and the word line WL1 of the selected cell is set to the potential Vpp. In this state, the plate line PL is driven to the internal power supply potential Vaa, whereby information is read from the ferroelectric capacitor C1 to the local bit line / LBL. The read potential is amplified by the amplification transistor QA0. As a result, a signal obtained by amplifying the inverted data of the potential read to the local bit line / LBL appears on the bit line BL. The potentials on the bit lines BL and / BL are amplified by the sense amplifier SA.

  After amplification, the block selection signal / BS is set to the high level. As a result, the potential of the bit line / BL is rewritten in the ferroelectric capacitor C1 by being transferred to the local bit line / LBL. Thereafter, the reset signal RST, the word lines WL0, WL2, and WL3 are set to the high level, and the block selection signal / BS is set to the low level, thereby shifting to the standby state.

  According to the 34th embodiment, the combined effect of the 33rd embodiment and the second embodiment can be obtained.

(Thirty-fifth embodiment)
The 35th embodiment has a configuration combining the 33rd embodiment (FIG. 36) and the 24th embodiment (FIG. 27). FIG. 38 shows a circuit configuration of a semiconductor integrated circuit device according to the thirty-fifth embodiment of the present invention. As shown in FIG. 38, in the configuration of the thirty-third embodiment, as in the twenty-fourth embodiment, one ends of the reset transistors QR0 and QR1 are connected to the first power supply VPR1. During standby, the potential of the first power supply VPR1 is made equal to the potential of the plate line PL. As a result, the same state as that in the thirty-fourth embodiment can be obtained. Other configurations and operations are the same as those in the thirty-fourth embodiment.

  According to the 35th embodiment, the same effect as in the 34th embodiment can be obtained.

(Thirty-sixth embodiment)
The thirty-sixth embodiment relates to an example of a method for driving the plate lines PL and / PL of the semiconductor integrated circuit device of the thirty-fifth embodiment (FIG. 38). More specifically, as in the second embodiment, the plate lines PL and / PL relate to the case where the standby potential is the potential Vss and the driving potential is the internal power supply potential Vaa.

  FIG. 39 shows the operation of the semiconductor integrated circuit device of FIG. 38, for illustrating the thirty-sixth embodiment of the present invention. As shown in FIG. 39, the first power supply VPR1 is set to the potential Vss during standby. In this state, the same operation as in the thirty-fourth embodiment is performed.

  According to the 36th embodiment, the effect obtained by combining the 35th embodiment and the second embodiment can be obtained.

(Thirty-seventh embodiment)
The thirty-seventh embodiment relates to an application example of the semiconductor integrated circuit device according to the first to thirty-sixth embodiments and the later-described first to sixth to sixth embodiments. FIG. 40 is a block diagram showing a data path portion of a digital subscriber line modem according to the thirty-seventh embodiment of the present invention. As shown in FIG. 40, the modem includes a programmable digital signal processor (DSP) 100, an analog-digital (A / D) converter 110, a digital-analog (D / A) converter 120, a transmission driver 130, And receiver amplifier 140 and the like.

  In FIG. 40, the bandpass filter is omitted. Instead, select a modem according to the line code program (encoded subscriber line information, transmission conditions, etc. executed by the DSP) (line code: QAM, CAP, RSK, FM, AM, PAM, DWMT, etc.) , Various types of optional memory are provided for holding a program to operate. As this memory, semiconductor integrated circuit devices (FeRAM) 170 of the first to thirty-sixth embodiments and the forty-first to 66th embodiments are shown.

  In this embodiment, the semiconductor integrated circuit device 170 is used as a memory for holding the line code program. However, in addition to the memory of the semiconductor integrated circuit device 170, a conventional MROM, SRAM, and flash memory are connected. It may be.

(Thirty-eighth embodiment)
The thirty-eighth embodiment relates to an application example of the semiconductor integrated circuit device according to the first to thirty-sixth embodiments and the forty-first to 66th embodiments. FIG. 41 shows a mobile phone terminal 300 according to the thirty-eighth embodiment of the present invention. As shown in FIG. 41, a communication unit 200 that realizes a communication function includes a transmission / reception antenna 201, an antenna duplexer 202, a reception unit 203, a baseband processing unit 204, a DSP 205 used as an audio codec, a speaker (handset) 206, a microphone (Transmitter) 207, transmission section 208, frequency synthesizer 209, and the like.

  In addition, the mobile phone terminal 300 includes a control unit 220 that controls each unit of the mobile phone terminal. The control unit 220 includes a CPU (Central Processing Unit) 221, a ROM 222, semiconductor integrated circuit devices (FeRAM) 223 according to the first to thirty-sixth and forty-sixth embodiments, and a flash memory 224 via a CPU bus 225. It is a microcomputer formed by connecting them. The ROM 222 stores data necessary for programs executed by the CPU 221 and display fonts in advance.

  The FeRAM 223 is mainly used for storing data in the work area and immediately before the power is turned off, and the CPU 221 stores data being calculated during the execution of the program as necessary, and exchanges data between the control unit 220 and each unit. It is used to temporarily store data while the power is off. The flash memory 224 is used for data storage such as power-on program loading because the writing speed is low. In addition, since the capacity is large, it is used for storing a large amount of data.

  The mobile phone terminal 300 also includes an audio data reproduction processing unit 211, an external output terminal 212, an LCD (Liquid Crystal Display) controller 213, a display LCD 214, and a ringer 215 that generates a ringing tone. The audio data reproduction processing unit 211 reproduces audio data input to the mobile phone terminal 300 (or audio data stored in an external memory 240 described later). The reproduced audio data is taken out by transmitting it to a headphone, a portable speaker or the like via the external output terminal 212. The LCD controller 213 receives display information from the CPU 221 via the CPU bus 225, for example, and converts it into LCD control information for controlling the LCD 214. With this control information, the LCD 214 is driven and information is displayed.

  The mobile phone terminal 300 also includes interface circuits (I / F) 231, 233, 235, an external memory 240, an external memory slot 232, a key operation unit 234, and an external input / output terminal 236. An external memory 240 such as a memory card is inserted into the external memory slot 232. The external memory slot 232 is connected to the CPU bus 225 via the interface circuit 231. Thus, by providing the slot 232 in the mobile phone terminal 300, information inside the mobile phone terminal 300 is written into the external memory 240, or information (eg, voice data) stored in the external memory 240 is stored in the mobile phone terminal. It is possible to input to 300. The key operation unit 234 is connected to the CPU bus 225 via the interface circuit 233. Key input information input from the key operation unit 234 is transmitted to the CPU 221, for example. The external input / output terminal 236 is connected to the CPU bus 225 via the interface circuit 233, and inputs various information from the outside to the mobile phone terminal 300 or outputs information from the mobile phone terminal 300 to the outside. Functions as a terminal.

  In this embodiment, the ROM 222, the FeRAM 223, and the flash memory 224 are used. However, both or one of the flash memory 224 and the ROM 222 can be replaced with FeRAM.

(Thirty-ninth embodiment)
The 39th embodiment relates to an application example of the semiconductor integrated circuit device according to the 1st to 36th embodiments and the 41st to 66th embodiments, to the 1st to 36th embodiments and the 41st to 66th embodiments. The present invention relates to an example in which such a semiconductor integrated circuit device is applied to a card for storing media contents such as smart media.

  FIG. 42 shows a memory card according to the 39th embodiment. As shown in FIG. 42, an FeRAM chip 401 is built in the memory card 400. The FeRAM chip 401 includes the semiconductor integrated circuit devices of the first to thirty-sixth embodiments and the forty-first to 66th embodiments.

(40th Embodiment)
The 40th embodiment relates to an application example of the semiconductor integrated circuit device according to the 1st to 36th embodiments and the 41st to 66th embodiments, and relates to the 1st to 36th embodiments and the 41st to 66th embodiments. The present invention relates to an example in which such a semiconductor integrated circuit device is applied to a system LSI. A so-called system LSI (Large Scale Integrated Circuit) is known in which a memory, logic, and the like are integrated on one system chip to form one system. In the system LSI, as illustrated in FIG. 43, a plurality of functional blocks 501 (core, macro, IP (Intellectual property)) such as a RAM circuit RAM and a logic circuit LOGIC are provided on a semiconductor chip (semiconductor substrate) 502. . These macros 501 construct a desired system as a whole. The RAM circuit RAM is configured by, for example, SRAM, DRAM or the like.

(41st Embodiment)
The 41st embodiment has a configuration in which one plate line PL is shared in a folded bit line configuration. FIG. 53 shows a circuit configuration of a semiconductor integrated circuit device according to the forty-first embodiment of the present invention. As shown in FIG. 53, the circuit configuration of the forty-first embodiment is the same as that of FIG. 7 showing the sixth embodiment except for the following points. That is, in FIG. 7, plate lines / PL and PL are provided for two bit lines / BL and BL, respectively. On the other hand, in FIG. 53, one plate line PL is connected to the local bit lines / LBL and LBL via the reset transistors QR0 and QR1, respectively. A reset signal / RST and a reset signal RST are supplied to the gates of the reset transistors QR0 and QR1, respectively.

  The operation is the same as in the sixth embodiment. That is, at the time of standby, the reset transistors QR0 and QR1 are turned on. When the memory cell in the cell block CB0 is read when active, the reset transistor QR0 is turned off and the cell transistors of unselected cells are turned off. Next, the block selection transistor QS0 is turned on, and the plate line PL is driven. The reset transistor QR1 is kept on, and the block selection transistor QS1 is kept off. The memory cell in the cell block CB1 is read in the same manner except that the block selection transistor QS1 is turned on and the block selection transistor QS0 is kept off.

  According to the semiconductor integrated circuit device of the forty-first embodiment, the same effect as that of the sixth embodiment can be obtained. Further, according to the forty-first embodiment, the plate line PL is shared by the two cell blocks CB0 and CB1. For this reason, the restriction | limiting of the pitch between plate lines is eased rather than the case where two plate lines PL are provided. Also in the folded bit line structure, since the number of plate lines can be further reduced as compared with the sixth embodiment, the area of the plate line drive circuit PLD can be further reduced, and the drive capability can be improved.

(Forty-second embodiment)
The forty-second embodiment relates to an example of a driving method of the plate line PL of the semiconductor integrated circuit device of the forty-first embodiment (FIG. 53). More specifically, as in the second embodiment, the potential of the plate line PL during standby is the potential Vss and the potential during driving is the internal power supply potential Vaa.

  FIG. 54 shows the operation of the semiconductor integrated circuit device of FIG. 53, for illustrating the forty-second embodiment of the present invention. Taking the case where information is read out from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 54, at the time of standby, the reset signals RST and / RST and the word lines WL0 to WL3 are set to the high level, and the block selection signals BS and BS / are set to the low level. The plate line PL is set to the potential Vss.

  When active, the reset signal / RST is set to the low level, and the word lines WL0, WL2, WL3 of the non-selected cells are set to the low level. The word line WL1 of the selected cell maintains a high level. Next, the block selection signal / BS is set to the high level, whereby the block selection transistor QS0 is turned on. During this time, the reset signal RST maintains a high level, and the block selection signal BS maintains a low level.

  In this state, the cell information is read from the ferroelectric capacitor C1 to the bit line / BL by driving the plate line PL to the internal power supply potential Vaa. The potential on the bit line / BL is amplified by the sense amplifier SA using the potential on the bit line BL as a reference potential. The same applies to reading of memory cells in the cell block CB1.

  During the reading of information from the ferroelectric capacitors C0 to C3 in the cell block CB0, the reset signal RST maintains a high level, and the block selection signal BS maintains a low level. For this reason, even if the plate line PL is driven, the local bit line LBL and the plate line PL are short-circuited, and the cell block CB1 is electrically isolated from the bit line BL. Therefore, no voltage is applied to the ferroelectric capacitors C4 to C7 in the cell block CB1.

  According to the semiconductor integrated circuit device of the forty-second embodiment, the effect obtained by combining the forty-first embodiment and the second embodiment can be obtained.

  The forty-second embodiment relates to a circuit configuration of the forty-first embodiment combined with a plate line driving method similar to that of the second embodiment. However, it is also possible to apply the plate line driving methods of the eighth to tenth embodiments to the 41st embodiment. In this case, the effects obtained by combining the forty-first embodiment and the eighth to tenth embodiments can be obtained.

(43rd embodiment)
The forty-third embodiment has a configuration in which the connection relationship between the ferroelectric capacitor and the cell transistor is reversed in one memory cell of the first embodiment (FIG. 1).

  FIG. 55 shows a circuit configuration of a semiconductor integrated circuit device according to the forty-third embodiment of the present invention. As shown in FIG. 55, the circuit configuration of the forty-third embodiment is the same as that of FIG. 1 except that the connection relationship between the ferroelectric capacitors C0 to C3 and the cell transistors Q0 to Q3 is reversed. It is. That is, in each memory cell, one end of each of the cell transistors Q0 to Q3 is connected to the ferroelectric capacitors C0 to C3, and the other end is connected to the plate line PL. The other ends of the ferroelectric capacitors C0 to C3 are connected to the local bit line LBL. The operation is exactly the same as in the first embodiment.

  The semiconductor integrated circuit device according to the forty-third embodiment can achieve the same effects as the first embodiment. The configuration of the memory cell of the forty-third embodiment can be applied to each memory cell having the circuit configuration of the sixth, eleventh, twenty-fourth, twenty-sixth, thirty-first, thirty-third, and thirty-eighth embodiments.

(44th Embodiment)
The forty-fourth embodiment relates to an example of a driving method of the plate line PL of the semiconductor integrated circuit device of the forty-third embodiment (FIG. 55). More specifically, as in the second embodiment, the potential of the plate line PL during standby is the potential Vss and the potential during driving is the internal power supply potential Vaa.

  FIG. 56 shows the operation of the semiconductor integrated circuit device of FIG. 55, for illustrating the forty-fourth embodiment of the present invention. As shown in FIG. 56, the change in potential of each signal line is the same as in the second embodiment.

According to the forty-fourth embodiment, the effect obtained by combining the forty-third embodiment and the second embodiment can be obtained. Also,
The forty-fourth embodiment relates to the circuit configuration of the forty-third embodiment combined with the same plate line driving method as the second embodiment. However, it is also possible to apply the plate line driving methods of the second to fourth embodiments to the 43rd embodiment. In this case, the effects obtained by combining the 43rd embodiment (including the sixth, eleventh, twenty-fourth, twenty-sixth, thirty-first, thirty-third and thirty-eighth embodiments) and the second to fourth embodiments are obtained. It is done.

(45th embodiment)
The 45th embodiment has a configuration in which a plurality of cell blocks having the same configuration as that of the first embodiment (FIG. 1) are connected in series. That is, first, as in the first embodiment, one memory cell is composed of a ferroelectric capacitor and a cell transistor connected in series, this memory cell is connected in parallel, and a reset transistor is connected in parallel with these memory cells. One memory cell unit is configured by connection. Such memory cell units are connected in series, and a memory cell group selection transistor is connected to the end of the end memory cell unit, thereby forming one memory cell group (cell group).

  FIG. 57 shows a circuit configuration of a semiconductor integrated circuit device according to the forty-fifth embodiment of the present invention. As shown in FIG. 57, the cell unit CU0 has the same configuration as the cell block CB0 of the first embodiment. That is, a plurality of memory cells each constituted by cell transistors Q0 to Q0 and ferroelectric capacitors C0 to C3 connected in series and a reset transistor QR0 are connected in parallel. One end of each memory cell, that is, the end of each cell transistor Q0 to Q3 opposite to the connection node with the ferroelectric capacitors C0 to C3 is connected to the local bit line LBL0. The other end of each memory cell, that is, the end of the ferroelectric capacitors C0 to C3 opposite to the connection node with the cell transistors Q0 to Q3 is connected to the local bit line LBL1.

  A cell unit CU1 is provided between the local bit line LBL1 and the local bit line LBL2. Similar to the cell unit CU0, the cell unit CU1 has a configuration in which a plurality of memory cells and a reset transistor QR1 are connected in parallel. The memory cell includes cell transistors Q4 to Q7 and ferroelectric capacitors C4 to C7 connected in series. In the memory cell of the cell unit CU1, the connection between the cell transistors Q4 to Q7 and the ferroelectric capacitors C4 to C7 is reversed from that of the cell unit CU0. Therefore, the ends of the ferroelectric capacitors C4 to C7 opposite to the connection nodes with the cell transistors Q4 to Q7 are connected to the local bit line LBL1. The ends of the cell transistors Q4 to Q7 opposite to the connection nodes with the ferroelectric capacitors C4 to C7 are connected to the local bit line LBL2.

  A cell unit CU2 is provided between the local bit line LBL2 and the local bit line LBL3. The cell unit CU2 has the same configuration as the cell unit CU0. That is, the cell transistors Q8 to Q11 correspond to the cell transistors Q0 to Q3, the ferroelectric capacitors C8 to C11 correspond to the ferroelectric capacitors C0 to C3, and the reset transistor QR2 corresponds to the reset transistor QR0.

  A cell unit CU3 is provided between the local bit line LBL3 and the plate line PL. The cell unit CU3 has the same configuration as the cell unit CU1. That is, the cell transistors Q12 to Q15 correspond to the cell transistors Q4 to Q7, the ferroelectric capacitors C12 to C15 correspond to the ferroelectric capacitors C4 to C7, and the reset transistor QR3 corresponds to the reset transistor QR3.

  Cell transistors Q0, Q4, Q8, and Q12 have their gates connected to word line WL0. Cell transistors Q1, Q5, Q9, and Q13 have their gates connected to word line WL1. The gates of the cell transistors Q2, Q6, Q10, Q14 are connected to the word line WL2. The gates of the cell transistors Q3, Q7, Q11, Q15 are connected to the word line WL3. The reset transistors QR0 to QR3 are controlled by reset signals RST0 to RST3, respectively. The reset signal lines RST0 to RST3 are connected to the reset signal line decoder RSD.

  A cell group is configured by the cell units CU0 to CU3. The cell group is connected to the bit line BL via the cell group selection transistor QS. That is, one end of the cell group selection transistor QS is connected to the local bit line LBL0, the other end is connected to the bit line BL, and the cell group selection signal BS is supplied to the gate.

  Next, the operation of the semiconductor integrated circuit device of FIG. 57 will be described with reference to FIGS. 58 and 59, taking as an example the case where information is read from the ferroelectric capacitor C6. FIG. 58 shows the standby state of the semiconductor integrated circuit device of FIG. 57, and FIG. 59 illustrates the active state.

  As shown in FIG. 58, at the time of standby, all the cell transistors Q0 to Q15 in the cell group are turned on. Therefore, the potentials at both ends of all the ferroelectric capacitors C0 to C15 are the same as the plate line PL, and no voltage is applied to the ferroelectric capacitors C0 to C15. Further, the cell group selection transistor QS is turned off.

  As shown in FIG. 59, when active, the reset transistor QR1 in the cell unit to which the ferroelectric capacitor C6 belongs is turned off, and the cell transistors Q0, Q6, Q10, Q14 other than the cell transistors Q2, Q6, Q10, Q14 in the same column as the selected cell Q1, Q3, Q4, Q5, Q7, Q8, Q9, Q11, Q12, Q13, and Q15 are turned off. Next, the cell group selection transistor QS is turned on, and the plate line PL is driven.

  During the active state, the reset transistors QR0, QR2 and QR3 are kept on, and therefore between the local bit lines LBL0 and LBL1, between the local bit lines LBL2 and LBL3, and between the local bit line LBL3 and the plate line PL. Are at the same potential. Therefore, the information of the memory cells in the cell units CU0, CU2, and CU3 is protected without being read out.

  Further, since the reset transistor QR1 is turned off, a voltage is applied to the four memory cells in the cell unit CU1. However, since only the cell transistor Q6 of the selected cell is turned on in the cell unit CU1, both the potential of the plate line PL and the potential of the bit line BL are applied only to the ferroelectric capacitor C6. That is, the potential of the plate line PL is applied to one end of the cell transistor C6 via the reset transistors QR3 and QR2 and the cell transistor Q6. The potential of the bit line BL is applied to the other end of the cell transistor C6 via the reset transistor QR0 and the cell group selection transistor QS. As a result, cell information from the ferroelectric capacitor C6 is read to the bit line BL via the local bit line LBL0. This read signal is amplified by a sense amplifier (not shown).

  After the cell information is read, if the read information is “0” data, the data is written back to the ferroelectric capacitor C6 with the potential of the plate line PL at a high level. In the case of “1” data, writing is performed after the potential of the plate line PL is set to the low level. At this time, the cell transistors Q0, Q1, Q3, Q4, Q5, Q7, Q8, Q9, Q11, Q12, Q13, Q15 are turned off, and the reset transistors QR0, QR2, QR3 are turned on. No voltage is applied to the ferroelectric capacitors other than the ferroelectric capacitor C6 of the selected cell.

  Thereafter, the cell group selection transistor QS is turned off, and the reset transistor QR1, the cell transistors Q0, Q1, Q3, Q4, Q5, Q7, Q8, Q9, Q11, Q12, Q13, and Q15 are turned on to enter standby. Transition to the state.

  During the active state, the ferroelectric capacitors other than the non-selected cells are in a floating state. For this reason, when the potential at one end of these ferroelectric capacitors fluctuates, a voltage is slightly applied to the ferroelectric capacitors by the ratio of the parasitic capacitance between the ferroelectric capacitors and the cell transistors. However, since the capacitance of the ferroelectric capacitor is large, there is no problem such as destruction of cell information.

  In the non-selected cell, the connection node between the ferroelectric capacitor and the cell transistor becomes floating. For this reason, when active, the potential of the connection node of the non-selected cell is lowered due to the junction leak, and a disturb voltage is applied to the ferroelectric capacitor of the non-selected cell. However, since the potential difference between both ends of each ferroelectric capacitor is reset to 0 V when returning to the standby state, the problem due to the disturb voltage is negligible as in the first embodiment.

  According to the semiconductor integrated circuit device of the forty-fifth embodiment, memory cells are arranged and connected two-dimensionally instead of one-dimensionally arranging memory cells as in the other embodiments. By adopting such a configuration, it is possible to read and write arbitrary memory cells, while obtaining the same effects as in the first embodiment. That is, a significant reduction in signal delay on the plate line PL, a reduction in the area of the plate line driving circuit PLD, and an improvement in driving capability can be realized.

  Further, according to the forty-fifth embodiment, since each cell group CG is connected to the bit line BL, the number of necessary bit lines is reduced, and as a result, the pitch of the bit lines is greatly relaxed. By relaxing the bit line pitch (decreasing the number of bit lines), the number of sense amplifiers is reduced by the amount of bit lines reduced. Therefore, the chip size can be reduced. In addition, since the cell group CG is connected to the bit line BL, the number of contacts of the bit line BL can be greatly reduced, and the same effect as in the first embodiment can be obtained. Since the number of memory cells connected to one bit line is smaller than that of the first embodiment connected for each cell block, the effect obtained by reducing the number of bit line contacts is even greater.

According to the forty-fifth embodiment, as in the first embodiment, it is possible to realize a memory cell having a minimum size of about 6F ² , and it is possible to avoid destruction of data in the memory cell due to the disturb voltage.

  According to the forty-fifth embodiment, the delay effect caused by the serial connection of a plurality of memory cells can be alleviated as compared with the prior application and the conventional memory when active. Therefore, the same effect as the first embodiment can be obtained. This effect will be described by taking as an example a case where the cell group is composed of N memory cells in the bit line direction and M memory cells in the word line direction. In this case, when active, only M−1 reset transistors, one cell transistor, and one cell group selection transistor that are turned on are connected in series between the plate line PL and the bit line BL. For this reason, unlike the memory cell of the prior application memory, when the number of cells in the cell group is the same, the number of transistors connected in series can be greatly reduced as compared with the memory of the prior application.

(46th Embodiment)
The forty-sixth embodiment relates to an example of a driving method of the plate line PL of the semiconductor integrated circuit device of the forty-fifth embodiment (FIG. 57). More specifically, as in the second embodiment, the potential of the plate line PL during standby is the potential Vss and the potential during driving is the internal power supply potential Vaa. The operation is the same as the combination of the 46th embodiment and the second embodiment.

  FIG. 60 shows the operation of the semiconductor integrated circuit device of FIG. 57, for illustrating the forty-sixth embodiment of the present invention. Taking the case where information is read out from the ferroelectric capacitor C6 as an example, the operation will be described below.

  As shown in FIG. 60, during standby, the reset signals RST0 to RST3 and the word lines WL0 to WL3 are set to the high level, and the cell group selection signal BS is set to the low level. The plate line PL is set to the potential Vss. Therefore, in all memory cell units CU0 to CU3, all cell transistors Q0 to Q15 are turned on, and all reset transistors QR0 to QR3 are also turned on. On the other hand, the cell group selection transistor QS is turned off. Therefore, the potentials at both ends of the ferroelectric capacitors C0 to C15 of all the memory cells are the same as the plate line PL. Therefore, during standby, no voltage is applied to the ferroelectric capacitors C0 to C15 regardless of the potential of the plate line PL, and polarization information is stably maintained.

  When active, the word lines WL0, WL1, WL3 of the non-selected cells are set to a low level, and the reset signal RST1 is set to a low level. The word line WL2 of the selected cell and the reset signals RST0, RST2, RST3 are maintained at a high level. Next, the cell group selection signal BS is set to a high level, whereby the cell group selection transistor QS is turned on.

  In this state, the cell information is read from the ferroelectric capacitor C6 to the bit line BL by driving the plate line PL to the internal power supply potential Vaa. The potential read to the bit line BL is amplified by the sense amplifier SA, and then rewritten as in the second embodiment. Thereafter, the reset signals RST0, RST2, and RST3 are set to the high level, the word lines WL0, WL1, and WL3 are set to the high level, and the cell group selection signal BS is set to the low level, thereby shifting to the standby state.

  According to the semiconductor integrated circuit device of the forty-sixth embodiment, the effect obtained by combining the forty-fifth embodiment and the second embodiment can be obtained.

(47th embodiment)
The forty-seventh embodiment relates to an example of a method for driving plate lines PL of the semiconductor integrated circuit device of the forty-fifth embodiment (FIG. 57). More specifically, the plate line PL is driven as in the fourth embodiment.

  FIG. 61 shows the operation of the semiconductor integrated circuit device of FIG. 57, for illustrating the 47th embodiment of the present invention. Taking the case where information is read out from the ferroelectric capacitor C6 as an example, the operation will be described below.

  As shown in FIG. 61, the standby state is the same as that of the forty-sixth embodiment except that the plate line PL is driven to the potential ref. When active, the word lines WL0, WL1, WL3 are set to the low level, the reset signal RST1 is set to the low level, and the cell group selection signal BS is set to the high level. In this state, information is read from the ferroelectric capacitor C6 by driving the plate line PL to the internal power supply potential Vaa. Subsequently, the potential on the bit line BL is amplified, then a rewrite operation is performed in the same manner as in the fourth embodiment, and then the standby state is entered in the same manner as in the 46th embodiment.

  According to the semiconductor integrated circuit device of the 47th embodiment, the effect obtained by combining the 45th embodiment and the fourth embodiment can be obtained.

(Forty-eighth embodiment)
In the forty-eighth embodiment, unlike the forty-fifth embodiment (FIG. 57), the reset signal line and the word line extend in the same direction.

  FIG. 62 shows a circuit configuration of a semiconductor integrated circuit device according to the forty-eighth embodiment of the present invention. The extending direction of the word lines WL0 to WL3 and the extending direction of the signal lines (reset signal lines) for supplying the reset signals RST0 and RST1 symbolize the positional relationship between the two in an actual semiconductor integrated circuit device. ing. That is, the word lines WL0 to WL3 and the reset signal line actually extend in the same direction on the chip. On the other hand, in FIG. 57, the reset signal line extends in a direction different from that of the word lines WL0 to WL3, and extends in the same direction as the bit line BL and the local bit lines LBL0 to LBL3.

  As shown in FIG. 62, the 48th embodiment is substantially the same as the 45th embodiment. That is, the cell units CU0 and CU1 are connected, and one end of the cell unit CU0 is connected to the bit line BL via the cell group selection transistor QS. The reset signal signal lines RST0 and RST1 extend in the same direction as the word lines WL0 to WL3. That is, even on an actual semiconductor integrated circuit device, the reset signal lines RST0 and RST1 and the word lines WL0 to WL3 are provided along the same direction. Therefore, the reset signal line decoder (shown together with the row decoder in the figure) is arranged at the end of the memory cell array in the direction of the word lines WL0 to WL3. The operation is the same as that of the forty-fifth embodiment.

  According to the semiconductor integrated circuit device of the forty-eighth embodiment of the present invention, the same effect as that of the forty-fifth embodiment can be obtained.

(49th Embodiment)
The forty-ninth embodiment relates to an example of a driving method of the plate line PL of the semiconductor integrated circuit device of the forty-eighth embodiment (FIG. 62). More specifically, as in the second embodiment, the potential of the plate line PL during standby is the potential Vss and the potential during driving is the internal power supply potential Vaa.

  FIG. 63 shows the operation of the 49th embodiment of the present invention, and shows the operation of the semiconductor integrated circuit device of FIG. Taking the case where information is read out from the ferroelectric capacitor C6 as an example, the operation will be described below.

  As shown in FIG. 63, at the time of standby, the reset signals RST0 and RST1, the word lines WL0 to WL3 are set to the high level, and the cell group selection signal BS is set to the low level. The plate line PL is set to the potential Vss.

  When active, the word lines WL0, WL1, WL3 of the non-selected cells are set to a low level, and the reset signal RST1 is set to a low level. The word line WL2 of the selected cell and the reset signal RST0 are maintained at a high level. Next, the cell group selection signal BS is set to a high level, whereby the cell group selection transistor QS is turned on.

  In this state, the cell information is read from the ferroelectric capacitor C6 to the bit line BL by driving the plate line PL to the internal power supply potential Vaa. The potential read to the bit line BL is amplified by the sense amplifier SA, and then rewritten as in the second embodiment. Thereafter, the reset signal RST1 is set to the high level, the word lines WL0, WL1, and WL3 are set to the high level, and the cell group selection signal BS is set to the low level, thereby shifting to the standby state.

  According to the semiconductor integrated circuit device of the forty-ninth embodiment, the effect obtained by combining the forty-eighth embodiment and the second embodiment can be obtained.

(50th Embodiment)
The 50th embodiment relates to the folded bit line configuration of the 48th embodiment. FIG. 64 shows a circuit configuration of a semiconductor integrated circuit device according to the 50th embodiment of the present invention. As shown in FIG. 64, cell groups CG0 and CG1 having the same configuration as the cell group having cell units CU0 and CU1 in FIG. 62 are provided. Cell groups CG0 and CG1 are provided for bit lines / BL and BL, respectively.

  A cell unit CU0 having the same configuration as that of the cell unit CU0 in FIG. 62 is connected between the local bit line / LBL0 and the local bit line / LBL1. A cell unit CU1 having the same configuration as the cell unit CU1 of FIG. 62 is connected between the local bit line / LBL1 and the plate line / PL (local bit line / LBL2). Group select transistor QS0 is connected between local bit line / LBL0 and bit line / BL.

  Similar to the cell unit CU0, a cell unit CU2 including ferroelectric capacitors C8 to C11, cell transistors Q8 to Q11, and a reset transistor QR2 is connected between the local bit line LBL0 and the local bit line LBL1. In the cell unit CU2, the ferroelectric capacitors C8 to C11 correspond to the ferroelectric capacitors C0 to C3, the cell transistors Q8 to Q11 correspond to the cell transistors Q0 to Q3, and the reset transistor QR2 corresponds to the reset transistor QR0.

  Similar to the cell unit CU1, the cell unit CU3 including the ferroelectric capacitors C12 to C15, the cell transistors Q12 to Q15, and the reset transistor QR3 is provided between the local bit line LBL1 and the plate line PL (local bit line LBL2). Connected to. In the cell unit CU3, the ferroelectric capacitors C12 to C15 correspond to the ferroelectric capacitors C4 to C7, the cell transistors Q12 to Q15 correspond to the cell transistors Q4 to Q7, and the reset transistor QR3 corresponds to the reset transistor QR0. A group selection transistor QS1 is connected between the local bit line LBL0 and the bit line BL.

  Cell transistors Q0, Q4, Q8, and Q12 have their gates connected to word line WL0. Cell transistors Q1, Q5, Q9, and Q13 have their gates connected to word line WL1. The gates of the cell transistors Q2, Q6, Q10, Q14 are connected to the word line WL2. The gates of the cell transistors Q3, Q7, Q11, Q15 are connected to the word line WL3. The reset transistors QR0 and QR2 are controlled by a reset signal RST0. The reset transistors QR1 and QR3 are controlled by a reset signal RST1. Cell group selection transistors QS0 and QS1 are controlled by cell group selection signals / BS and BS, respectively.

  Next, the operation will be described. The operations in the cell groups CG0 and CG1 are the same as those in the 47th embodiment (45th embodiment). When active, the reset transistor QR1 and the cell transistors Q0, Q1, Q3, Q4, Q5, and Q7 are turned off as in the 47th embodiment. Thereafter, when reading the memory cells in the cell group CG0, only the cell group selection transistor QS0 is turned on, and the cell group selection transistor QS1 is kept off. Next, only the plate line / PL is driven, and the plate line PL is not driven. As a result, cell information is read out to the bit line / BL. The potential on the bit line BL is used as a reference potential. The potential on the bit line / BL is amplified by the sense amplifier SA using the potential on the bit line BL. The same applies to reading of memory cells in the cell group CG1.

  According to the semiconductor integrated circuit device of the sixth embodiment, the folded bit line configuration makes it possible to obtain the combined effect of the 45th embodiment and the sixth embodiment.

(51st Embodiment)
The 51st embodiment relates to an example of a driving method of the plate lines PL, / PL of the semiconductor integrated circuit device of the 50th embodiment (FIG. 64). More specifically, as in the second embodiment, the plate lines PL and / PL relate to the case where the standby potential is the potential Vss and the driving potential is the internal power supply potential Vaa. The operation is also the same as the combination of the 50th embodiment and the second embodiment.

  FIG. 65 shows the operation of the semiconductor integrated circuit device of FIG. 64, for illustrating the 51st embodiment of the present invention. Taking the case where information is read out from the ferroelectric capacitor C6 as an example, the operation will be described below.

  As shown in FIG. 65, in the standby state, the reset signals RST0 and RST1 and the word lines WL0 to WL3 are set to the high level, and the cell group selection signals BS and / BS are set to the low level. The plate lines PL and / PL are set to the potential Vss.

  When active, the reset signal RST1 is set to the low level, and the word lines WL0, WL1, WL3 of the non-selected cells are set to the low level. The word line WL2 of the selected cell maintains a high level. Next, the cell group selection signal / BS is set to the high level, whereby the block selection transistor QS0 is turned on. The cell group selection signal BS maintains a low level.

  In this state, the cell information is read from the ferroelectric capacitor C6 to the bit line / BL by driving the plate line / PL to the internal power supply potential Vaa. The plate line PL maintains the potential Vss. The potential read to the bit line / BL is amplified by the sense amplifier SA, and then a rewrite operation is performed as in the second embodiment. Thereafter, the reset signal RST1, the word lines WL0, WL1, and WL3 are set to the high level, and the cell group selection signal / BS is set to the low level, thereby shifting to the standby state.

  According to the semiconductor integrated circuit device of the fifty-first embodiment, the effect obtained by combining the fifty embodiment and the second embodiment can be obtained.

(52nd embodiment)
The fifty-second embodiment is similar to the forty-fifth embodiment, and the difference is that two terminals of a memory cell are partially exchanged.

  FIG. 66 shows a circuit configuration of a semiconductor integrated circuit device according to the 52nd embodiment of the present invention. As shown in FIG. 66, compared with FIG. 57, the connection of the memory cells of the cell units CU1 and CU3 is the same as that of the cell unit CU0 (or CU2). That is, in the cell unit CU1, the ends of the cell transistors Q4 to Q7 opposite to the connection nodes with the ferroelectric capacitors C4 to C7 are connected to the local bit line LBL1. The ends of the ferroelectric capacitors C4 to C7 opposite to the connection nodes with the cell transistors Q4 to Q7 are connected to the local bit line LBL2. Similarly, in the cell unit CU3, the ends of the cell transistors Q12 to Q15 opposite to the connection nodes with the ferroelectric capacitors C12 to C15 are connected to the local bit line LBL3. The ends of the ferroelectric capacitors C12 to C15 opposite to the connection nodes with the cell transistors Q12 to Q15 are connected to the plate line PL. Other configurations are the same as those in the forty-fifth embodiment.

  According to the semiconductor integrated circuit device in the fifty-second embodiment, the same effect as in the forty-fifth embodiment can be obtained.

  In the present embodiment, the case where the cell units CU1 and CU3 have the same connection as the cell uni and CU0 (or CU2) of the 45th embodiment (FIG. 57) is illustrated. However, it is also possible to reverse them. Further, it is not essential that the connection of the two terminals of the memory cell in one cell unit is the same. Further, as derived from the present embodiment and the forty-fifth embodiment, the two terminals of the memory cell can be arbitrarily connected in each memory cell. For example, the same connection can be made for each column and row, and the same effect can be obtained even if it is completely arbitrary without having such regularity.

(53rd Embodiment)
The 53rd embodiment relates to the structure of the semiconductor integrated circuit device of the 50th embodiment (FIG. 64). 67, 68, and 69 show a 53rd embodiment of the present invention. 67 and 68 correspond to the cross-sectional structures of cell units CU0 and CU1 applicable to the semiconductor integrated circuit device of FIG. FIG. 69 schematically shows a partial planar structure of FIGS. 67 and 68.

  The structure in FIG. 67 is similar to the structure in FIG. 17, and different parts will be described. Bit line BL is connected to source / drain region SD0 via contact P6 and wiring layer M1. The source / drain region SD0 is formed at a distance from the source / drain region SD1 on the surface of the semiconductor substrate sub. A gate electrode BS1 is provided above the semiconductor substrate sub between the source / drain regions SD0 and SD1. The source / drain regions SD0 and SD1 are connected to each other by contacts P5 and P6 and a wiring layer M1. A transistor including the source / drain regions SD1 and SD2 and the gate electrode BS0 above the semiconductor substrate sub between them corresponds to the cell group selection transistor QS0.

  A local bit line / LBL1 is provided at the position of the plate line PL in FIG. Local bit line / LBL1 is connected to source / drain region SD10 via contact P4. The source / drain region SD10 is formed at a distance from the source / drain region SD9 on the surface of the semiconductor substrate sub. A transistor including the source / drain regions SD10 and SD9 and the gate electrode RST0 above the semiconductor substrate sub between them corresponds to the reset transistor QR0. A gate electrode RST0 is provided above the semiconductor substrate sub between the source / drain regions SD9 and SD8. Source / drain regions SD9 and SD8 are connected to each other by a contact P1 and a local bit line / LBL0.

  The structure of FIG. 68 is similar to the structure of FIG. 67, and is the same as FIG. 67 except for the following different parts. That is, the bit line BL does not exist in this cross-sectional structure, and the plate line / PL is provided at the position of the local bit line / LBL0 in FIG. The local bit lines / LBL1 in FIGS. 67 and 68 are connected to each other.

  Corresponding to the cell unit CU2 in FIG. 64, a structure similar to that in FIG. 67 is provided. Further, a structure similar to that of FIG. 68 is provided corresponding to the cell unit CU3 of FIG. The local bit lines / LBL0 (LBL0) and plate lines / PL (PL) having these structures are arranged as shown in FIG. That is, the island-shaped local bit line / LBL0, the plate line PL, the local bit line / LBL0, and the plate line / PL are sequentially arranged side by side. A plurality of such structures are actually arranged (not shown). The plate lines PL are connected to each other by wiring extending in the word line direction (vertical direction in the figure). The same applies to the plate line / PL.

  According to the semiconductor integrated circuit device of the 53rd embodiment of the present invention, the cell units CU0 to CU3 of the semiconductor integrated circuit device of the 50th embodiment can be realized.

(Fifty-fourth embodiment)
The 54th embodiment relates to the structure of the semiconductor integrated circuit device of the 41st embodiment (FIG. 53). 70 and 71 show a 54th embodiment of the present invention, and schematically show a cross-sectional structure of a cell block applicable to the semiconductor integrated circuit device of FIG. 70 and 71 show structures corresponding to the cell blocks CB0 and CB1 of FIG. 53, respectively. FIG. 53 illustrates four memory cells in one cell block, but FIGS. 70 and 71 illustrate eight cases. A desired number of memory cells can be realized by increasing or decreasing the number of repetitions of the structure constituting the memory cell of FIGS.

  As shown in FIG. 70, source / drain regions (active regions) SD20 to SD36 are formed at a distance from each other on the surface of the semiconductor substrate sub. Gate electrodes (cell group selection signal lines) BS and / BS are provided between the source / drain regions SD20 and SD21 and above the semiconductor substrate sub between the source / drain regions SD21 and SD22, respectively. Similarly, gate electrodes (word lines) WL0, WL1, WL2, WL3 are provided above the semiconductor substrate sub between the source / drain regions SD22 and SD23, between SD24 and SD25, between SD25 and SD26, and between SD28 and SD29, respectively. . Gate electrodes WL4, WL5, WL6, and WL7 are provided above the semiconductor substrate sub between the source / drain regions SD27 and SD28, between SD30 and SD31, between SD31 and SD32, and between SD33 and SD34, respectively.

  Gate electrodes (reset signal lines) RST and / RST are provided above the semiconductor substrate between the source / drain regions SD34 and SD35 and between the source / drain regions SD35 and SD35, respectively.

  An impurity region into which impurities are implanted is formed in the channel region between the source / drain regions SD20 and SD21, and a transistor constituted by the source / drain regions SD20 and SD21 and the gate electrode BS is a depletion type. It is said that. Similarly, the transistor constituted by the source / drain regions SD34 and SD35 and the gate electrode RST is also a depletion type.

  The source / drain regions SD23 and SD24 are connected to the lower electrode BE of the ferroelectric capacitor C provided above the source / drain regions SD23 and SD24 through contacts P21. The upper electrode TE of each ferroelectric capacitor C is connected to a plate line PL provided above the ferroelectric capacitor C via a contact P22 provided for each upper electrode. Similarly, the source / drain regions SD26, 27, SD29, SD30, SD32, and SD33 are respectively connected to the lower electrode BE of the ferroelectric capacitor C through the contact P21. Plate lines PL are provided at positions above the source / drain regions SD26, 27, above the source / drain regions SD29, 30 and above the source / drain regions SD32, 33, respectively. The plate line PL is connected to the corresponding upper electrode TE of the ferroelectric capacitor C via the contact P22 via the contact P22.

  A local bit line / LBL is provided above the plate line PL. Source / drain regions SD22, SD25, SD28, SD31, SD34 are each connected to contact P23. Each contact P23 is connected to a local bit line / LBL via a wiring layer M21 and a contact P24. The wiring layer M21 is provided as the same layer as the plate line PL. The plate line PL is also provided at a position over the source / drain regions SD35 and SD36, and is connected to the source / drain region SD36 via a contact P25.

  A bit line / BL is provided above the local bit line / LBL. Source / drain region SD20 is connected to bit line / BL via contact P26, wiring layer M21, contact P27, wiring layer M22, and contact P28. The wiring layer M22 is provided as the same layer as the local bit line / LBL.

  FIG. 71 is substantially the same as FIG. 70 except for the following points. First, a transistor constituted by the source / drain regions SD20 and SD21 and the gate electrode BS and a transistor constituted by the source / drain regions SD34 and SD35 and the gate electrode RST are of the enhancement type. On the other hand, a transistor constituted by the source / drain regions SD21 and SD22 and the gate electrode / BS and a transistor constituted by the source / drain regions SD35 and SD36 and the gate electrode / RST are of the depletion type. A local bit line LBL is positioned instead of the local bit line / LBL, and a bit line BL is positioned instead of the bit line / BL.

  According to the semiconductor integrated circuit device of the 54th embodiment of the present invention, the cell group of the semiconductor integrated circuit device of the 41st embodiment can be realized.

  Further, according to the 54th embodiment, no wiring layer is provided between the semiconductor substrate sub and the layer of the lower electrode BE. That is, in the manufacturing process, metal wiring such as copper (Cu) and aluminum (Al) is not formed before the ferroelectric capacitor is formed. In the manufacturing process, if a metal wiring layer such as Cu or Al is formed before the formation of the ferroelectric capacitor, these metal wiring layers are not constantly replaced by a thermal process when forming the ferroelectric capacitor. For this reason, when forming a wiring layer before forming a ferroelectric capacitor, it is necessary to use, for example, tungsten (W). However, in the case of an embedded memory such as an FeRAM and a logic circuit, the tungsten wiring is provided for forming the FeRAM, so that it is an extra wiring as a whole, leading to an increase in manufacturing cost. On the other hand, according to the 54th embodiment, since it is not necessary to provide such an extra wiring layer, an increase in manufacturing cost can be suppressed.

Further, according to the 54th embodiment, unlike the 17th embodiment (FIG. 18) and the 19th embodiment (FIG. 21), it is not necessary to bend the active areas AA1 to AA3. For this reason, the cell size can be further reduced, and a true size of 6F ² can be realized.

(55th Embodiment)
The 55th embodiment is used in addition to the 54th embodiment (FIGS. 70 and 71), and a shunt wiring, a main block selection transistor wiring, and the like are added.

  72 and 73 schematically show a cross-sectional structure of a semiconductor integrated circuit device according to the 55th embodiment of the present invention. 72 corresponds to the same position as FIG. 70 of the 54th embodiment, and FIG. 73 corresponds to the same position as FIG. 71 of the 54th embodiment. As shown in FIGS. 72 and 73, a main block selection transistor wiring MBS and a power supply reinforcing power supply line Vs are provided in the same layer as the local bit line LBL (/ LBL). With this power supply line Vs, a plurality of power supply lines can be arranged in the memory cell array, and the total power supply resistance can be greatly reduced. The main block selection transistor wiring MBS and the power supply line Vs are provided using a vacant space where the local bit line / LBL (LBL) is not arranged on a plane.

  Above the bit line / BL (BL), shunt wirings / RST, RST, WL0 to WL7, / BS, BS are provided. The shunt wirings / RST, RST, WL0 to WL7, / BS, BS are periodically connected (not shown) to the corresponding gate electrodes (with the same reference numerals) in the extending direction.

  Of course, any of the shunt wiring, the hierarchical word line system, and the power supply line can be adopted.

  According to the semiconductor integrated circuit device of the 55th embodiment of the present invention, the same effect as that of the 54th embodiment can be obtained. Further, the main block selection transistor wiring MBS and the power supply line Vs are arranged using the empty space at the level of the local bit line / LBL (LBL). Therefore, the main block selection transistor wiring MBS and the power supply line Vs can be provided without further increase in the metal wiring level.

(56th embodiment)
The 56th embodiment relates to a modification of the 55th embodiment (FIGS. 72 and 73).

  74 and 75 schematically show a cross-sectional structure of a semiconductor integrated circuit device according to the fifty-sixth embodiment of the present invention. 74 corresponds to the same position as FIG. 72 of the 55th embodiment, and FIG. 75 corresponds to the same position as FIG. 73 of the 55th embodiment. As shown in FIGS. 74 and 75, the main block selection transistor wiring MBS and the power supply line Vs are provided in the same layer as the shunt wirings / RST, RST, WL0 to WL7, / BS, BS.

  Of course, any of the shunt wiring, the hierarchical word line system, and the power supply line can be adopted.

  The semiconductor integrated circuit device according to the fifty-sixth embodiment of the present invention can achieve the same effect as the fifty-fifth embodiment. Further, according to the 56th embodiment, one cell block or cell group becomes large, and a plurality of signal lines (for example, main block selection transistor wiring MBS, power supply line Vs, etc.) can be arranged with a high degree of freedom. On the other hand, in the conventional structure, since one cell is a basic unit and one cell size is small, it is at most limited to provide one signal line. That is, there are large restrictions on the arrangement of signal lines.

(57th Embodiment)
In the 57th embodiment, in addition to the configuration of the 41st embodiment (FIG. 53), the plate line PL is shared by the cell blocks CB0 and CB1 and the further cell blocks connected to the bit lines BL and / BL.

  FIG. 76 shows a circuit configuration of a semiconductor integrated circuit device according to the 57th embodiment of the present invention. As shown in FIG. 76, the same configuration as FIG. 53 is provided in the right half of the figure. However, what added "A" to the end of the referential mark of each part of FIG. 53 is used.

  Further, cell blocks CB2 and CB3 similar to the cell blocks CB0 and CB1 of FIG. 53 are further provided for the bit lines / BL and BL, respectively. A memory cell including a reset transistor QR0B, ferroelectric capacitors C8 to C11, and cell transistors Q8 to Q11 is connected between the plate line PL and the local bit line / LBLB. Local bit line / LBLB is connected to bit line / BL via block select transistor QS0B.

  A memory cell including a reset transistor QR1B, ferroelectric capacitors C12 to C15, and cell transistors Q12 to Q15 is connected between the plate line PL and the local bit line LBLB. Local bit line LBLB is connected to bit line BL via block select transistor QS1B.

  Cell transistors Q8 and Q12 have their gates connected to word line WL0B. Cell transistors Q9 and Q13 have their gates connected to word line WL1B. The gates of cell transistors Q10 and Q14 are connected to word line WL2B. Cell transistors Q11, Q15 have their gates connected to word line WL3B. The reset transistors QR0B and QR1B are controlled by reset signals / RSTB and RSTB, respectively. Block selection transistors QS0B and QS1B are controlled by block selection signals / BSB and BSB, respectively.

  The operation is the same as that in the forty-first embodiment. That is, in the case of access to the memory cells in the cell blocks CB0 and CB1, the cell blocks CB2 and CB3 maintain the standby state, and the same control as that in the forty-first embodiment is performed on the cell blocks CB0 and CB1. During access to the memory cells in the cell blocks CB0 and CB1, information is not destroyed because both ends of the ferroelectric capacitors C8 to C15 in the cell blocks CB2 and CB3 are short-circuited. The operation in the case of accelerating the memory cells in the cell blocks CB2 and CB3 is the same.

  The semiconductor integrated circuit device according to the fifty-seventh embodiment of the present invention can obtain the same effects as those of the forty-first embodiment. Further, the plate line PL is shared by the cell blocks of the forty-first embodiment or more. For this reason, the area occupied by the plate line PL and the resistance value can be reduced. Further, the area occupied by the plate line driving circuits PL and / PL can be reduced.

(58th Embodiment)
The 58th embodiment relates to an example of the driving method of the plate line PL of the semiconductor integrated circuit device of the 57th embodiment (FIG. 76). More specifically, as in the second embodiment, the potential of the plate line PL during standby is the potential Vss and the potential during driving is the internal power supply potential Vaa.

  FIG. 77 shows the operation of the semiconductor integrated circuit device of FIG. 76, for illustrating the 58th embodiment of the present invention. Taking the case where information is read out from the ferroelectric capacitor C1 as an example, the operation will be described below.

  As shown in FIG. 77, at the time of standby, the reset signals / RSTA, RSTA, / RSTB, RSTB, the word lines WL0A to WL3A, WL0B to WL3B are set to the high level, and the block selection signals / BSA, BSA, / BSB, BSB are Low level. The plate line PL is set to the potential Vss.

  The operations of the reset signals / RSTA and RSTA, the word lines WL0A to WL3A, and the block selection signals / BSA and BSA from the active state to the standby state are the same as those in the forty-second embodiment (FIG. 54). During this time, the reset signals / RSTB and RSTB and the word lines WL0B to WL3B are maintained at high level, and the block selection signals / BSB and BSB are maintained at low level.

  According to the semiconductor integrated circuit device of the 58th embodiment of the present invention, the effect obtained by combining the 57th embodiment and the second embodiment can be obtained.

(59th Embodiment)
In the 59th embodiment, one bit is stored by two transistors and two ferroelectric capacitors. That is, the present invention relates to a case where the memory cell is a so-called 2T2C type. In the 2T2C type, information is stored in a state in which “0” data and “1” data are written in two memory cells, and in a state in which “1” data and “0” data are written, respectively. Even in the case of the 2T2C type, the circuit configuration is the same as that in each of the above-described embodiments, and only the control during reading and writing is different. As an example, a case where a 2T2C type memory cell is used in the semiconductor integrated circuit device of the forty-first embodiment (FIG. 53) and information is read from the ferroelectric capacitors C1 and C5 will be described as an example. It is assumed that complementary data has already been written in the ferroelectric capacitors C1 and C5.

  78 shows a semiconductor integrated circuit device according to a fifty-ninth embodiment of the present invention, and shows an operation when the semiconductor integrated circuit device of FIG. 53 is a 2T2C type memory cell system. As shown in FIG. 78, the standby state is the same as that in the forty-second embodiment (FIG. 54).

  When active, both reset signals / RST and RST are set to a low level, and unselected word lines WL0, WL2 and WL3 are set to a low level. Next, the block selection signals / BS and BS are set to the high level. In this state, when the plate line PL is driven to the internal power supply potential Vaa, information from the ferroelectric capacitors C1 and C5 is read to the bit lines / BL and BL, respectively. The potentials on the bit lines / BL and BL are amplified by the sense amplifier SA, and the information held in the memory cell is determined from the two amplified data. Thereafter, rewriting is performed, and a transition is made to the standby state.

  Although the 2T2C method has been described by taking the semiconductor integrated circuit device of the 41st embodiment as an example, the sixth (FIG. 7), the eleventh (FIG. 12), and the twenty-sixth (FIG. 29) having bit line pairs are described. The present invention can also be applied to the thirty-third (FIG. 36), thirty-five (FIG. 38), and fifty-fifth (FIG. 64) embodiments by the same technique. In this case, in addition to the same control as described in the present embodiment, the plate lines / PL and PL are driven together, so that the two ferroelectric capacitors constituting one memory cell are changed to the bit lines / BL and BL. Data is read out.

  The semiconductor integrated circuit device according to the fifty-ninth embodiment of the present invention can achieve the same effect as the forty-first embodiment. Furthermore, by using the 2T2C type memory cell system, a read margin can be increased as compared with the case of the 1T1C type.

(60th Embodiment)
In the 60th embodiment, similarly to the operation described with reference to FIG. 3 in the second embodiment, the potentials of the reset signals / RST, RST and the word lines WL0 to WL3 at the time of standby are set to the potential Vpp or lower. . Since a high level potential is continuously applied to the reset transistors QR0 and QR1 and the reset transistors Q0 to Q7 during standby, the reliability of these transistors deteriorates. Therefore, the potential applied to each transistor at the time of standby is set lower than the potential Vpp, and the potential applied to the transistor necessary at the time of active is set as the potential Vpp.

  FIG. 79 shows a semiconductor integrated circuit device according to the 60th embodiment of the present invention, and relates to another example of the control method of the semiconductor integrated circuit device of the 42nd embodiment (FIG. 53). As shown in FIG. 79, the potentials of the reset signals / RST and RST and the word lines WL0 to WL3 are set to the potential Vpp or lower (for example, Vaa) during standby. When active, the word line WL1 of the selection transistor and the reset signal RST are set to the potential Vpp. Other specific operations are the same as those in the forty-third embodiment (FIG. 54).

  According to the semiconductor integrated circuit device of the 60th embodiment of the present invention, the same effect as in the forty-second and forty-third embodiments can be obtained. Furthermore, according to the 60th embodiment, a potential lower than the potential Vpp is applied to the transistor that is turned on during standby. For this reason, it is possible to prevent the reliability from being deteriorated by continuously applying a high voltage to these transistors.

(61st Embodiment)
The 61st embodiment relates to a layout applicable to the 54th embodiment (FIGS. 70 and 71). 80 to 83 show the 61st embodiment of the present invention, and the layout applicable to the semiconductor integrated circuit device of FIGS. 70 and 71. FIG. 80 to 83 show the respective surfaces in the height direction of the cross-sectional structures of FIGS. 70 and 71 in order from the surface of the semiconductor substrate sub. Further, a cross-sectional view along the line LXX-LXX in FIGS. 80 to 83 corresponds to FIG. 70, and a cross-sectional view along the line LXXI-LXXI corresponds to FIG.

  As shown in FIG. 80, a plurality of active areas AA are provided in a matrix form separated from each other. Gate electrodes / RST, RST, WL0 to WL7, / BS, BS extend in the vertical direction in the drawing on the active region. On the active region in the rightmost column in the figure, gate electrodes BS, / BS, WL0 extend with a space therebetween. In the vicinity of the channel region where the depletion type transistor is formed, an impurity implantation region (Imp) for making the threshold value of the transistor negative is formed. In the active region AA, source / drain regions SD20 and SD21 are located on both sides of the gate electrode BS. Similarly, source / drain regions SD21 and SD22 are located on both sides of the gate electrode / BS, and source / drain regions SD22 and SD23 are located on both sides of the gate electrode WL0.

  Similarly, in each active region belonging to the same column, source / drain regions SD24 and SD25 are located on both sides of the gate electrode WL1, and source / drain regions SD25 and SD26 are located on both sides of the gate electrode WL2. Similarly, source / drain regions SD27 and SD28 are located on both sides of the gate electrode WL3, and source / drain regions SD28 and SD29 are located on both sides of the gate electrode WL4. Source / drain regions SD30 and SD31 are located on both sides of the gate electrode WL5, and source / drain regions SD31 and SD32 are located on both sides of the gate electrode WL6. Source / drain regions SD33 and SD34 are located on both sides of the gate electrode WL7, and source / drain regions SD34 and SD35 are located on both sides of the gate electrode RST. Source / drain regions SD35 and SD36 are located on both sides of the gate electrode / RST.

  A contact P26 is formed on the source / drain region SD20. A contact P23 is formed on the source / drain regions SD22, SD25, SD28, SD31, SD34. A contact P21 is formed on the source / drain regions SD23, SD24, SD26, SD27, SD29, SD30, SD32, and SD33. A contact P25 is formed on the source / drain region SD36.

  As shown in FIG. 81, for example, a rectangular wiring layer M21 is provided on the contacts P26 and P23. On each contact P21, for example, a rectangular ferroelectric capacitor C is provided. For example, a rectangular plate line PL is provided so as to cover the upper part of the two rows of ferroelectric capacitors C between the contacts P23. Each plate line PL between the contacts P21 is connected to a wiring layer (not shown) corresponding to the output terminal of the plate line drive circuit PLD.

  As shown in FIG. 82, local bit lines LBL, / LBL are formed so as to cross each plate line PL in the left-right direction in the figure. The local bit lines LBL, / LBL are provided with an interval in the vertical direction. A contact P23 provided between the plate lines PL connects the local bit lines LBL, / LBL and the wiring layer M21.

  As shown in FIG. 83, bit lines BL and / BL extend in the left-right direction in the figure with a space therebetween. Bit lines BL, / BL are connected to wiring layer M22 via contact P28.

  Of course, this embodiment can be applied to the 55th and 56th embodiments. In the case of the 55th embodiment, the main block selection transistor wiring MBS and the power supply line Vs are spaced apart from one ends of the local bit lines LBL and / LBL in FIG. Is extended. Similarly, the power supply line Vs extends in the vertical direction in the figure with a distance from each other end. Further, the shunt wirings / RST, RST, WL0 to WL7, / BS, BS of FIGS. 71 and 72 are provided in a layer further above the layer shown in FIG. In the case of the 56th embodiment, the main block selection transistor wiring MBS and the power supply line Vs are provided in the same layer as the shunt wirings / RST, RST, WL0 to WL7, / BS, BS along the same direction.

  According to the semiconductor integrated circuit device of the 61st embodiment of the present invention, the semiconductor integrated circuit device of FIGS. 70 to 75 can be realized, and the same effects as those of the 54th to 56th embodiments can be obtained.

(62nd embodiment)
The 62nd embodiment relates to a circuit configuration of a hierarchical word line system. FIG. 84 shows the circuit configuration of the semiconductor integrated circuit device according to the 62nd embodiment of the present invention, and shows the circuit configuration when the hierarchical word line method and the shunt method are combined.

  As shown in FIG. 84, for example, cell blocks CB0, CB1, bit line pairs BL, / BL, sense amplifiers SA having the same configuration as in the sixth embodiment (FIG. 7), sub row decoders and sub plate lines for controlling them. A plurality of subgroups (two are illustrated in the figure) are formed of drivers SRD. For these subgroups, a main block selection transistor line MBS connected to the main row decoder MRD is provided.

  In FIG. 84, an example in which a subgroup is configured by the same configuration as that of the sixth embodiment is shown, but it is of course possible to configure using a circuit configuration of another embodiment of the present invention.

  According to the semiconductor integrated circuit device of the 62nd embodiment of the present invention, in addition to the effects obtained by the above embodiments, the effects obtained by the hierarchical word line method and the shunt method such as the decrease in the resistance value of the signal line are obtained. It is done.

(63th Embodiment)
The 63rd embodiment relates to a wiring arrangement method of the semiconductor integrated circuit device of the 41st embodiment. FIG. 85 shows a semiconductor integrated circuit device according to the 63rd embodiment of the present invention. The circuit configuration of FIG. 85 is substantially the same as that of the forty-first embodiment (FIG. 53). In addition to this circuit configuration, in the 63rd embodiment, the column selection signal line CSL and the data line DQ are formed in the same wiring layer as the local bit lines / LBL and LBL along the bit lines (illustrated by bold lines). ). The data line DQ is provided for exchanging data between the sense amplifier and the peripheral circuit. The column selection line CSL is connected to a column decoder (not shown), and is a line for a selection signal for placing data of a selected column among cell data read by the sense amplifier SA on the data line DQ. .

  In the embodiments of the present specification, the local bit lines LBL, / LBL (hereinafter, referred to as local bit lines LBL, except when the individual bit lines are individually distinguished. Need the same). As the local bit line LBL, a wiring layer at the level of the wiring layer M22 is used as shown in FIGS. 72, 73, 74, and 75, for example.

  Since the 63rd embodiment is a cross-point type cell, the pitch of the local bit lines LBL is the same as the cell pitch. The feature is that one column selection line CSL and one data line DQ are provided for every two local bit lines LBL using the feature that the pitch of the local bit lines LBL is loose.

  As a modification, the design rule becomes strict, but it is possible to provide a column selection line CSL and a data line DQ between the local bit lines LBL. As another modification, the column selection line CSL and the data line DQ can be configured using the same wiring layer as the bit line BL. The configuration of FIG. 85 is more excellent. The reason is as follows. First, when the column selection line CSL and the data line DQ are provided between the bit lines BL, the pitch of the bit lines BL becomes strict, the wiring capacity increases, and the read signal is deteriorated. On the other hand, even when the column selection line CSL and the data line DQ are provided between the local bit lines LBL, there is a disadvantage that the capacity of the local bit line LBL is increased. However, the length of the local bit line LBL is short, and the influence is smaller in terms of an increase in load capacity during the entire reading. This is because the capacity of the local bit line LBL in the non-selected cell block CB does not contribute as a load capacity parasitic to the wiring through which a signal flows during reading.

  FIG. 85 illustrates a case where the present embodiment is applied to the embodiment of FIG. However, it is of course possible to provide the column selection line CSL and the data line DQ at the same level as the local bit line LBL by applying this embodiment to other embodiments as well.

  FIG. 86 shows an example of routing in the plurality of array mats of the column selection line CSL and the data line DQ in the embodiment of FIG. In this example, the following configuration is adopted. That is, first, the sense amplifier SA is provided between the two memory cell arrays MCA. When reading from the memory cell array MCA on both sides of the sense amplifier SA, this sense amplifier operates. A plurality of structures (two are illustrated in FIG. 86) including sense amplifiers SA sandwiched between two memory cell arrays MCA are provided in the horizontal direction of the drawing, and a column decoder CD is provided at the right end. A row decoder RD is provided at the upper end of each memory cell array MCA. Each memory cell array MCA is provided with, for example, a plurality of structures shown in FIG.

  A plurality of column selection lines CSL (only the column selection lines CSL0 and CSL1 are representatively shown) extend in the left-right direction on the paper surface, pass through each cell array MCA, and are connected to the column decoder CD. The data lines DQ, / DQ extend in the left-right direction on the paper surface, pass through each cell array MCA, and are connected to the second sense amplifier SA2. The data lines DQ and / DQ are connected to each sense amplifier SA, and transfer the data amplified by the sense amplifier SA to the second sense amplifier SA according to the signal of the column selection line CSL.

  FIG. 87 illustrates a cross-sectional view in the direction along the word line of the device structure applicable to the semiconductor integrated circuit device according to the 63rd embodiment of the invention. In this example, the plate line PL is constituted by the M1 wiring layer, the local bit line LBL is constituted by the M2 wiring layer, the bit line BL is constituted by the M3 wiring layer, the main block selection transistor wiring MBS and the shunt wirings WL0 to WL7. Etc. are constituted by the M4 wiring layer. That is, in this example, the column selection line CSL and the data line DQ shown in FIGS. 85 and 86 are formed of the same M2 wiring layer as the local bit line LBL.

  88 to 90 illustrate cross-sectional views of one cell block in the direction along the bit line of the device structure applicable to the semiconductor integrated circuit device according to the 63rd embodiment of the present invention. 88 is a cross-sectional view taken along local bit line / LBL in FIG. 85, and corresponds to a cross-sectional structure taken along LXXXVIII-LXXXVIII in FIG. 87. 89 is a cross-sectional view taken along column selection line CSL or data line DQ in FIG. 85, and corresponds to a cross-sectional structure taken along LXXXIX-LXXXIX in FIG. 90 is a cross-sectional view taken along local bit line LBL in FIG. 85 and corresponds to the cross-sectional structure taken along XC-XC in FIG. 88 and 90 are the same as FIGS. 74 and 75. 88 and 90, wiring layers / BS and BS are provided between the wiring layers M21 above the gate electrodes / BS and BS. In this way, the shunt wirings / BS, BS can also be realized by the M1 wiring layer. In the figure, both the M1 wiring layer and the M4 wiring layer are shown for convenience.

  As shown in FIG. 89, word lines BS, / BS, WL0 to WL7, RST, / RST are provided above the semiconductor substrate sub. A plate line PL is constituted by the M1 wiring layer above these word lines / BS, BS, WL0 to WL7, RST, / RST. The plate line PL is provided along the horizontal direction of the paper surface, and is connected to the plate line PL shown in FIGS. In the M1 wiring layer, the wiring layers / BS, BS extend in a direction perpendicular to the paper surface. The column selection line CSL and the data line DQ are configured by the same wiring layer as the M2 wiring layer above the M1 wiring layer, that is, the local bit lines / LBL and / LBL. The M4 wiring layer is located above the M2 wiring layer. The M4 wiring layer constitutes a main block selection transistor wiring MBS and a shunt wiring layer Vs, MBS, BS, / BS, WL0 to WL7, RST, / RST.

  According to the semiconductor integrated circuit device of the 63rd embodiment of the present invention, in each embodiment in which the local bit line LBL is provided, the column selection line CSL and the data line DQ are configured by the same wiring layer as the local bit line LBL. The For this reason, the same effect as the effect obtained by each embodiment to which this embodiment is applied can be obtained.

  Further, the column selection line CSL and the data line DQ are formed of the same wiring layer as that of the local bit line LBL, so that the following effects can be obtained. That is, in each embodiment of the present invention, since the local bit line LBL is provided, four wiring layers are required. If the column selection line CSL and the data line DQ are provided without using these wiring layers, it is necessary to provide a further wiring layer. On the other hand, in the case of the conventional method (FIG. 48) and the memory method of the inventor's earlier application (FIGS. 50 and 51), the column selection line CSL and the data are provided by the wiring layer provided in addition to the wiring layers shown in these drawings. Even if the line DQ is configured, the total number of wiring layers is four. On the other hand, according to the 63rd embodiment, the column selection line CSL and the data line DQ are provided by effectively utilizing the space between the local bit lines LBL. For this reason, the number of wiring layers including the column selection line CSL and the data line DQ is the same as that in the conventional or inventor's prior application system. Therefore, it is possible to obtain the effects (acceleration, etc.) of the embodiments of the present invention realized by using the local bit line LBL without increasing the manufacturing cost due to the increase of the wiring layer.

  According to the 63rd embodiment, since the column selection line CSL can be provided on the memory cell array MCA without increasing the number of wiring layers, the column decoder CD can be shared by a plurality of memory cell arrays. When the column selection signal from the column decoder cannot be arranged on the memory cell array, it is necessary to provide a column decoder for each memory cell array, unlike the case of FIG. As a result, the area of the semiconductor integrated circuit device increases. On the other hand, according to the present embodiment, the column decoder CD can be shared by a plurality of memory cell arrays, so that the area of the column decoder can be reduced.

  Further, according to the 63rd embodiment, it is possible to provide a large number of data lines DQ on the memory cell array while providing the data lines DQ without increasing the wiring layer. When a large number of data lines cannot be arranged on the memory cell array, unlike the case of FIG. 86, only a small amount of data can be transferred from the memory cell array to the peripheral circuit (second sense amplifier or the like), and the bandwidth is reduced. Alternatively, since a region for providing the data line is required separately, the area of the semiconductor integrated circuit device increases. On the other hand, according to the present embodiment, the data bandwidth between the sense amplifier SA and the peripheral circuit can be improved without increasing the wiring layer.

(64th embodiment)
The 64th embodiment relates to a layout applicable to the 63rd embodiment and the like (FIGS. 88 to 90). FIGS. 91 to 94 show the 64th embodiment of the present invention and show the layout applicable to the semiconductor integrated circuit device of FIGS. 88 to 90 and the like. 91 to 94 correspond to the surfaces in the height direction of FIGS. 88 to 90 except that the number of ferroelectric capacitors is different. More specifically, FIGS. 91 to 94 sequentially show planar structures at various positions from the surface of the semiconductor substrate sub to the top. 91 to 94 are substantially the same as the 61st embodiment (FIGS. 80 to 83) except that the number of capacitors is different.

  As shown in FIG. 91, the gate electrodes BS, / BS, WL0 to WL15, RST, / RST extend in the vertical direction on the paper surface with a space therebetween. A plurality of active areas AA are provided. The active area AA extends from between two adjacent gate electrodes to both outer sides of the two gate electrodes. A contact P23 is provided in the active region between the gate electrodes. A ferroelectric capacitor C is provided above the active region outside the gate electrode. Each active region outside the gate electrode and the lower electrode BE of each ferroelectric capacitor C above them are connected by a contact P21.

  FIG. 92 mainly shows the M1 wiring layer. As shown in FIG. 92, the plate line PL and the wiring layer M21 are configured by an M1 wiring layer. Further, the plate line PL has a rectangular main part and a connection part that connects the main parts to each other. A plurality of wiring layers 21 composed of M1 wiring layers are provided between the main parts of the plate line PL. The main part of the plate line PL covers the upper part of the two rows of ferroelectric capacitors C between the wiring layers M21 and extends in the vertical direction of the drawing. The connecting portion extends in the left-right direction on the paper surface and connects adjacent main portions to each other. A connection part is provided for every two wiring layers M21 of the up-down direction of a paper surface, for example. In addition, wiring layers BS and / BS made of M1 wiring layers are provided above the gate electrodes BS and / BS in FIG. The wiring layer M21 adjacent to the wiring layer BS is composed of the M1 wiring layer.

  FIG. 93 mainly shows the M2 wiring layer above the M1 wiring layer. As shown in FIG. 93, the local bit lines / LBL0, LBL0, / LBL1, and LBL1 extend over the left and right sides of the paper above the main part of the plate line PL. Local bit lines / LBL0, LBL0, / LBL1, and LBL1 are configured by an M2 wiring layer. A column selection line CSL or a data line DQ is provided between the local bit line / LBL0 and the local bit line LBL0 and between the local bit line / LBL1 and the local bit line LBL1. The column selection line CSL and the data line DQ are configured by an M2 wiring layer.

  FIG. 94 mainly shows the M3 and M4 wiring layers above the M2 wiring layer. As shown in FIG. 94, bit lines / BL0, BL0, / BL1, BL1 are provided in the left-right direction on the paper surface. Bit lines / BL0, BL0, / BL1, and BL1 are configured by an M3 wiring layer. Above the bit lines / BL0, BL0, / BL1, and BL1, shunt wiring lines Vs, WL0 to WL15, / RST, and RST are provided. The shunt lines Vs, WL0 to WL15, / RST, and RST are configured by an M4 wiring layer. In the present embodiment, the shunt wirings / BS, BS correspond to the case where the shunt wirings / BS and BS are configured by the M1 wiring layer (see FIG. 92) instead of the M4 wiring layer.

  According to the semiconductor integrated circuit device of the 64th embodiment of the present invention, the same effect as that of the 61st embodiment can be obtained. Further, according to the sixty-fourth embodiment, the semiconductor integrated circuit device of FIGS. 88 to 90 can be realized.

  Further, according to the 64th embodiment, the main parts of the plate lines PL extending in the vertical direction on the paper surface are connected to each other. For this reason, the following effects can be obtained. That is, in each embodiment of the present invention, as shown by the circuit diagram, all the memory cells in one cell block CB share one plate line PL. For this reason, as a layout for realizing this, it is simplest that the wiring layer that becomes the plate line PL spreads so as to cover all the ferroelectric capacitors C connected to the plate line PL. It is a configuration. However, for example, as shown in FIGS. 81 and 92, in order to connect the active area AA (source / drain area SD) and the local bit line LBL, a wiring layer M21 including an M1 wiring layer needs to be provided. For this reason, the plate line PL is divided in the left-right direction on the paper surface. In the 64th embodiment, these divided plate lines PL (main parts of the plate line PL) are connected to each other. For this reason, when accessing the ferroelectric capacitor C, the current to be passed through the ferroelectric capacitor C to be accessed is dispersed over a wide range. For this reason, the delay of the plate line PL is reduced, so that the delay can be relaxed and the deterioration of the wiring due to electromigration can be prevented.

  In addition, the connection part of plate line PL may be provided for every 2 or more wiring layers M21 in the direction extended in the up-down direction of a paper surface. Further, it may be provided for each shunt of the shunt wiring layer and the gate electrode.

  In addition, the plate lines PL of the M1 wiring layer are connected to each other using this embodiment, but it is of course possible to adopt a configuration in which the column selection line CSL and the data line DQ are not realized by the M2 wiring layer. A cross-sectional view in this case is shown in FIG. FIG. 95 corresponds to the same position as that of the cross-sectional view of FIG. As shown in FIG. 95, compared with FIG. 89, the connection part of the plate line PL for connecting the main part of the plate line PL divided in the horizontal direction in FIG. The line CSL and the data line DQ are not configured by the wiring layer M2.

(65th embodiment)
The 65th embodiment relates to a control method applicable to each embodiment. First, two operation methods of FeRAM called a method called Return to Zero (RTZ) and Non-return to Zero (NRTZ) will be described.

  The NRTZ method can be applied to the conventional ferroelectric memory shown in FIG. In this method, the cell transistor of the selected cell shifts to the standby state while the potential state at the time of rewriting “1” data, that is, the bit line potential is in the high level state. That is, the ferroelectric capacitor enters a floating state by turning off the word line while the potential of the bit line remains at a high level. As a result, a high level charge is confined in the electrode of the ferroelectric capacitor. For this reason, the state necessary for rewriting continues even after shifting to the standby state due to this charge, so that “1” data can be reliably rewritten.

  On the other hand, in the RTZ system, the cell transistor of the selected cell shifts to the standby state after the bit line is set to the low level after the potential state for rewriting “1” data. In the ferroelectric memory of the prior application of the inventor of FIG. 50, only the RTZ method can be adopted. The reason is that even if the cell transistor of the selected cell is turned on while a high level potential is applied to one end of the ferroelectric capacitor of the selected cell, both ends of the ferroelectric capacitor of the selected cell are turned on together with the turning on of the cell transistor. Because is short-circuited. As a result, the trapped charge disappears, and the NRTZ system cannot be realized. The RTZ method cannot secure a sufficient time for rewriting “1” data as compared with the NRTZ method.

  96 to 98 show the operation of the semiconductor integrated circuit device according to the 65th embodiment of the present invention, in the case where the control method according to this embodiment is applied to the configuration of the first embodiment (FIG. 1). is there. More specifically, FIG. 96 shows an operation history. FIG. 97 shows a case in which the memory cell including the ferroelectric capacitor Q3 is selected and then shifted to standby. FIG. 98 shows a case where the memory cell including the ferroelectric capacitor Q3 is selected and then the memory cell including the ferroelectric capacitor Q2 is selected and then the standby state is entered. The 65th embodiment will be described below by taking as an example the case where it is applied to the configuration of the first embodiment.

  In FIG. 97, the state until the data is read is the same as in the other embodiments (FIG. 2, etc.). At the time of reading, when the data held in the memory cell is “1”, the polarization state moves from the point D to the point E in FIG. On the other hand, in the case of “0”, the polarization state moves from point A to point B. Thereafter, a sensing operation is performed, and in the case of “0” data, “0” data is rewritten, and the polarization state moves from point B to point C. Next, when the plate line PL is set to the low level, in the case of “1” data, “1” data is rewritten. As a result, the polarization state moves from point E to point F.

  Next, the block selection signal BS is set to the low level and the selected word line WL3 is set to the low level, so that the charge of “1” data is stored in the cell node SN3. Thereafter, the unselected word lines WL0, WL1, and WL2 are set to the high level, and the reset signal RST is set to the high level, so that both ends of the ferroelectric capacitors C0, C1, and C2 are short-circuited while the cell node SN3 is left floating. .

  Next, both ends of the ferroelectric capacitor C3 are also short-circuited by using, for example, a timer circuit so that the word line WL3 is set to a high level after a predetermined time. That is, the potential difference between both ends of the ferroelectric capacitor is always reset after a finite time. For this reason, the disturb voltage to the ferroelectric capacitors C0, C1, and C2 of the non-selected cells is not accumulated, and a problem caused by the disturb voltage does not occur.

  According to the semiconductor integrated circuit device of the 65th embodiment of the present invention, the same effect as that of the first embodiment can be obtained. According to the 65th embodiment, after reading the cell data, the ferroelectric capacitor of the selected cell is set in a floating state, and both ends of the ferroelectric capacitor of the selected cell are short-circuited after a certain time. For this reason, it is possible to secure a time during which charges are accumulated in the cell node of the selected cell. That is, the NRTZ system can be realized. As a result, rewriting can be performed more reliably, and the reliability of the semiconductor integrated circuit device is improved.

  Next, another example of the 65th embodiment will be described with reference to FIG. As shown in FIG. 98, the word line WL3 is selected in the first active operation, and then the word line WL3 is set to the low level, whereby charges are accumulated in the cell node SN3. In the next active operation, the word line WL2 is read / written while the word line WL3 is kept at the low level. Next, when the word line WL2 is set to the low level, charges are confined in the cell node SN2. Then, it shifts to the standby state again. The word line WL3 is set to the high level after a lapse of a certain time from the time when it is set to the low level. Similarly, the word line WL2 is also set to the high level after a certain time has elapsed from the time when it is set to the low level. By such control, the NRTZ system can be realized even when data is continuously read from cells in one cell block.

  In the example of FIG. 98, the word line WL3 is set to the high level at the end of the selection cycle of the word line WL2. However, the present invention is not limited to this. For example, the NRTZ system can be realized by keeping the selected word line as low as possible. The word line WL2 is in a standby state, and is returned to a high level after a certain time has elapsed.

(66th embodiment)
The 66th embodiment relates to a modification applicable to each embodiment, and particularly to each embodiment related to a circuit configuration. The case where this embodiment is applied to 1st Embodiment is taken as an example, and it demonstrates below with reference to FIG.

  FIG. 99 shows the circuit configuration of the semiconductor integrated circuit device according to the 66th embodiment of the present invention, and illustrates the case where this embodiment is applied to the first embodiment. As shown in FIG. 99, the cell transistors Q0 to Q3, the reset transistor QR, and the block selection transistor QS in FIG. 1 are replaced by transmission gates TQ0 to TQ3, TQR, and TQS, respectively. Transmission gates TQ0 to TQ3, TQR, and TQS are respectively formed by N-type MOS (NMOS) transistors QN0 to QN3, QNR, and QNS connected in parallel, and P-type MOS (PMOS) transistors QP0 to QP3, QPR, and QPS. Composed. Others are the same as in the first embodiment.

  As shown in FIG. 1, when NMOS is used as the cell transistors Q0 to Q3, the reset transistor QR, and the block selection transistor QS, the operation amplitudes of all the word lines WL0 to WL3, the reset signal RST, and the block selection signal BS are set as bit lines. It needs to be larger than BL and local bit line LBL. This is to avoid a decrease in the threshold voltages of the cell transistors Q0 to Q3, the reset transistor QR, and the block selection transistor QS (so-called threshold decrease). In this case, the reliability of the cell transistors Q0 to Q3, the reset transistor QR, and the block selection transistor QS may be reduced. In order to avoid this, the gate oxide films of the cell transistors Q0 to Q3, the reset transistor QR, and the block selection transistor QS need to be thicker than transistors of other peripheral circuits in order to secure a withstand voltage. There is.

  On the other hand, according to the 66th embodiment, since no threshold drop occurs, the operation amplitudes of all the word lines WL, the reset signal RST, and the block selection signal BS are the same as those of the bit line BL and the local bit line LBL. Can be made. Therefore, (1) the reliability of the cell transistors Q0 to Q3, the reset transistor QR, and the block selection transistor QS can be improved. Further, (2) the process cost can be reduced without requiring a transistor having a thick gate oxide film. Further, (3) since a fine transistor can be applied to the cell transistors Q0 to Q3, the operation can be speeded up.

  Of course, as described above, the case where the 66th embodiment is applied to the first embodiment has been described as an example, but the present invention can be applied to all other embodiments. Also, as shown in FIGS. 100 and 101, it is of course possible to use a PMOS transistor instead of a transmission gate.

(67th embodiment)
The 67th embodiment relates to application examples of the semiconductor integrated circuit devices according to the 1st to 36th embodiments and the 41st to 66th embodiments, and the semiconductor integrated circuit device according to these embodiments is applied to a digital camera or a digital video camera. Related to the example.

  FIG. 102 shows a digital camera or a digital video camera according to the 67th embodiment of the present invention. As shown in FIG. 102, a digital camera or digital video camera 600 includes an image input device 601, a data compression device 602, an FeRAM 603, an input / output device 604, a display device 605, a system bus BUS, and the like. The system bus BUS connects the image input device 601, the data compression device 602, the FeRAM 603, the input / output device 604, and the display device 605 to each other.

  The image input device 601 includes, for example, a CCD (Charge-Coupled Device) imager for inputting image data, a CMOS (Complementary MOS) sensor, and the like. The data compression device 602 compresses input image data. The FeRAM 603 includes the semiconductor integrated circuit device (FeRAM) of the first to thirty-sixth embodiments and the forty-first to 66th embodiments. The FeRAM 603 stores compressed image data, control codes, and the like, and is used as a buffer memory. The input / output device 604 outputs compressed image data or inputs image data from the outside. The display device 605 includes, for example, an LCD (Liquid Crystal Display) or the like, and displays an image based on input image data or compressed image data.

  Since the conventional FeRAM cannot operate at a sufficiently high speed, there is a problem that the operation becomes slow when it is applied to a control code of a digital camera or a digital video camera that requires high-speed image processing or a buffer memory. On the other hand, this problem can be solved by using the FeRAM according to each embodiment of the present invention capable of operating at higher speed than the conventional FeRAM.

(68th Embodiment)
The 68th embodiment relates to application examples of the semiconductor integrated circuit devices according to the first to 36th embodiments and 41st to 66th embodiments, and relates to an example in which the semiconductor integrated circuit device according to these embodiments is applied to a computer system.

  FIG. 103 shows a computer system according to the 68th embodiment of the present invention. As shown in FIG. 103, the computer system 701 includes a microprocessor 702, FeRAM 703, input / output device 704, RAM 705, ROM 705, system bus BUS, and the like. The system bus BUS connects the microprocessor 702, FeRAM 703, input / output device 704, RAM 705, and ROM 706 to each other.

  The microprocessor 702 performs various arithmetic processes. The FeRAM 703 includes the semiconductor integrated circuit device (FeRAM) of the first to thirty-sixth embodiments and the forty-first to 66th embodiments. The FeRAM 703 stores, for example, computer system control codes or is used as a data memory. The input / output device 704 exchanges data with an external device. As the RAM 705, for example, a high-speed SRAM or a high-speed DRAM is used when a RAM or the like whose restriction on the number of rewrites is less than that of the FeRAM is required or when a higher-speed RAM is required. The ROM 706 stores, for example, OS (Operating System) and kanji data that do not need to be rewritten.

  Since the conventional FeRAM cannot operate at a sufficiently high speed, there is a problem that the operation becomes slow when it is applied to a control code of a computer system that requires high-speed processing or a data memory. On the other hand, this problem can be solved by using the FeRAM according to each embodiment of the present invention.

(69th embodiment)
The 69th embodiment relates to application examples of the semiconductor integrated circuit device according to the first to 36th embodiments and 41st to 66th embodiments, and relates to an example in which the semiconductor integrated circuit device according to these embodiments is applied to a system LSI.

  FIG. 104 shows a microprocessor chip according to the 69th embodiment of the present invention. As shown in FIG. 104, the microprocessor chip 801 includes a microprocessor core 802, a microcode (control code) memory 803, and the like. The microprocessor core 802 and the microcode memory 803 are formed together on one chip. The microprocessor core 802 has an I / O for performing various arithmetic processes and exchanging data with other chips and the like. The microcode memory 803 is configured by the semiconductor integrated circuit device (FeRAM) of the first to thirty-sixth embodiments and the forty-first to 66th embodiments, and stores various microcodes necessary for the operation of the microprocessor core 802. . By changing the microcode, it is possible to easily change the instruction of the microprocessor core.

  Since the conventional FeRAM cannot operate at a sufficiently high speed, there is a problem that the operation becomes slow when it is applied to a microcode or the like of a microprocessor that requires high-speed processing. On the other hand, this problem can be solved by using the FeRAM according to each embodiment of the present invention.

(70th Embodiment)
The 70th embodiment relates to application examples of the semiconductor integrated circuit devices according to the first to 36th embodiments and 41st to 66th embodiments, and relates to an example in which the semiconductor integrated circuit device according to these embodiments is applied to a portable computer system. .

  FIG. 105 shows a portable computer system according to the 70th embodiment of the present invention. As shown in FIG. 105, a portable computer system 901 includes a microprocessor and a controller (hereinafter simply referred to as a microprocessor) 902, an input device 903, a transceiver 904, an antenna 905, a display device 906, an FeRAM 907, and the like.

  The microprocessor 902 performs various arithmetic processes. The input device 903 is connected to the microprocessor 902 and inputs data. As input means applied to the input device 903, for example, hand touch, key input, voice input, image input using a CCD, or the like is used. The transceiver 904 is connected to the microprocessor 902, and exchanges data with an external device via the antenna 905. As the transmitter / receiver 904, for example, a transmitter / receiver having a function of transmitting / receiving radio waves used in a mobile phone or the like is used. The display device 906 is connected to the microprocessor 902 and includes an LCD or a plasma display that displays various information. The FeRAM includes the semiconductor integrated circuit devices (FeRAM) of the first to thirty-sixth embodiments and the forty-first to 66th embodiments, and stores various control codes necessary for the operation of the microprocessor 902 or a data memory. Used as a buffer memory.

  Since the conventional FeRAM cannot operate at a sufficiently high speed, there is a problem that the operation becomes slow when it is applied to a control code memory, a data memory, a buffer memory, etc. of a portable computer system that requires high-speed processing. On the other hand, this problem can be solved by using the FeRAM according to each embodiment of the present invention.

(71st Embodiment)
The 71st embodiment relates to application examples of the semiconductor integrated circuit device according to the 1st to 36th embodiments and 41st to 66th embodiments, and relates to an example in which the semiconductor integrated circuit device according to these embodiments is applied to a logic variable LSI. .

  FIG. 106 shows a logic variable LSI according to the 71st embodiment of the present invention. As shown in FIG. 106, the logic variable LSI 1000 includes a plurality of logic units 1001 that perform different logic operations, and an FeRAM 1002 corresponding to each logic unit 1001. The logic unit 1001 and the FeRAM 1002 are formed in a mixed manner on one chip. The FeRAM 1002 includes the semiconductor integrated circuit devices (FeRAM) of the first to thirty-sixth embodiments and the forty-first to 66th embodiments, and stores logical operations.

  For example, a logic unit in an FPD (Field Programmable Gate Device), an FPGA (Field Programmable Gate Array), or the like is capable of reconfiguration of logical operations. Then, the logic storage memory of the logic variable LSI stores the information of the produced logic operation, and the stored logic operation information needs to be read at high speed. However, since the conventional FeRAM cannot operate at a sufficiently high speed, there is a problem that the operation becomes slow when it is applied to a logic storage memory of a logic variable LSI. On the other hand, this problem can be solved by using the FeRAM according to each embodiment of the present invention.

  Note that the FeRAM 1002 may be divided as shown in FIG. 106, or may be collected at one place. Further, it may be provided not for each logic unit 1001 but for each module.

(72nd Embodiment)
The 72nd embodiment relates to application examples of the semiconductor integrated circuit device according to the 1st to 36th embodiments and 41st to 66th embodiments, and relates to an example in which the semiconductor integrated circuit device according to these embodiments is applied to an IC card.

  FIG. 107 shows an IC card according to the 72nd embodiment of the present invention. As shown in FIG. 107, an IC chip 1101 is installed on the main body of the IC card 1100. The IC chip 1101 has a built-in FeRAM 1102. The FeRAM 1102 includes the semiconductor integrated circuit device (FeRAM) of the first to thirty-sixth embodiments and the forty-first to 66th embodiments, and is used as a data storage memory of the IC card 1100.

  Since conventional FeRAMs could not operate at high speed, there was a problem that the operation would be slow when applied to a data storage memory of a high-performance IC card that requires high-speed data writing. On the other hand, this problem can be solved by using the FeRAM according to each embodiment of the present invention.

(73rd embodiment)
The 73rd embodiment relates to application examples of the semiconductor integrated circuit device according to the 1st to 36th embodiments and the 41st to 66th embodiments, and applies the semiconductor integrated circuit device according to these embodiments to an automobile equipped with a navigation system. Related to the example.

  FIG. 108 shows an automobile equipped with a navigation system according to the 73rd embodiment of the present invention. As shown in FIG. 108, the navigation system 1200 includes a measuring device 1201, a computer (control device) 1202, an FeRAM 1203, a display device 1204, an operation device 1205, and the like. The automobile 1206 is equipped with such a navigation system 1200.

  The measuring device 1201 is configured to be able to collect information necessary for position measurement by, for example, GPS (Global Positioning System). Alternatively, the measurement device 1201 includes sensors embedded in various parts of the automobile. Alternatively, the measurement device 1201 includes, for example, a CCD imager, and captures image information around the automobile.

  Information captured by the measurement device 1201 is supplied to the computer 1202. The computer 1202 processes these pieces of information based on various control codes stored in the FeRAM 1203, thereby measuring the position of the automobile, recognizing the captured image, recognizing obstacles in the image, etc. I do. As the computer 1202, for example, the one shown in FIG. 103 can be used.

  In addition, when the navigation system according to the present embodiment supports automatic driving, the computer 1202 determines the situation where the automobile is placed using the captured image or the like, and guides the automobile to an appropriate position.

  The FeRAM 1203 is configured by the semiconductor integrated circuit device (FeRAM) of the first to thirty-sixth embodiments and the forty-first to 66th embodiments. The computer 1202 displays an image including the measured position information and the like on the display device 1204. The display device 1204 is composed of, for example, an LCD. Data is input to the computer 1202 from the operation device 1205 by, for example, hand touch, key input, or voice input.

  The conventional ferroelectric FeRAM cannot perform a sufficiently high-speed operation, so that high-speed navigation, automatic driving, and automatic object recognition are difficult. On the other hand, this problem can be solved by using the FeRAM according to each embodiment of the present invention.

(74th Embodiment)
The 74th embodiment relates to application examples of the semiconductor integrated circuit devices according to the 1st to 36th embodiments and the 41st to 66th embodiments, and the semiconductor integrated circuit devices according to these embodiments are used for industrial and consumer robots. It relates to the example applied to.

  FIG. 109 shows the robot according to the 74th embodiment of the present invention. As shown in FIG. 109, the robot 1300 includes an arm 1301, a driving device 1302, a computer (control device) 1303, an FeRAM 1304, a sensor device 1305, and the like.

  The arm 1301 performs various operations according to the application of the robot 1300. The driving device 1302 drives the arm 1301 and controls the operation of the arm 1301. The FeRAM 1304 stores, for example, a control code of the computer 1303 and is configured by the semiconductor integrated circuit device (FeRAM) of the first to thirty-sixth embodiments and the forty-first to 66th embodiments. The computer 1302 controls the driving device 1302 based on information such as various control codes stored in the FeRAM 1304. As the computer 1303, for example, the one shown in FIG. 103 can be used.

  The sensor device 1305 measures the position of an object as an object to be worked on, or grasps the position of the arm 1301. Information captured by the sensor device 1305 is supplied to the computer 1303. The computer 1303 recognizes the position of the object using this information and the information stored in the FeRAM, and determines the next operation of the arm 1301 such as adjustment of the arm 1301.

  A conventional ferroelectric memory cannot perform a sufficiently high-speed operation, so that high-speed arm operation and object recognition are difficult. On the other hand, this problem can be solved by using the FeRAM according to each embodiment of the present invention.

(75th embodiment)
The 75th embodiment relates to application examples of the semiconductor integrated circuit device according to the first to 36th embodiments and the 41st to 66th embodiments, and the semiconductor integrated circuit device according to these embodiments is used as an image display device such as a television or a display. It relates to the example applied to.

  FIG. 110 shows an image display apparatus according to the 75th embodiment of the present invention. As shown in FIG. 110, the image display device 1400 includes an FeRAM 1401, a computer 1402, an image processing device 1403, a display device 1404, and the like.

  The FeRAM 1401 stores, for example, a control code of the computer 1402, data for image processing, and the like, and is configured by the semiconductor integrated circuit device (FeRAM) of the first to thirty-sixth embodiments and the forty-first to 66th embodiments. The computer 1402 controls the image processing apparatus 1403 based on information such as various control codes and image processing data stored in the FeRAM 1401. For example, the image processing apparatus 1403 processes a video signal supplied via a communication line such as the Internet or a wireless radio wave or taken in from another device. The image processing device 1403 also outputs a display signal as a result of processing the video signal. The computer 1402 controls the display device 1404 using the display signal supplied from the image processing device 1403. The display device 1404 includes a display such as an LCD and its driving device, and displays an image based on the control of the computer 1402.

  Since conventional ferroelectric memories cannot operate at a sufficiently high speed, it has been difficult to perform high-definition image processing at high speed. On the other hand, this problem can be solved by using the FeRAM according to each embodiment of the present invention.

(76th embodiment)
The 76th embodiment relates to application examples of the semiconductor integrated circuit devices according to the first to 36th embodiments and 41st to 66th embodiments, and relates to an example in which the semiconductor integrated circuit device according to these embodiments is applied to an optical disc apparatus.

  FIG. 111 shows an optical disc apparatus according to the 76th embodiment of the present invention. As shown in FIG. 111, the optical disk device 1501 includes an optical head 1502, a driving device 1504, a computer 1505, an FeRAM 1506, an image processing device 1507, and the like.

  The optical head 1502 writes information on the optical disk 1503 or reads information from the optical disk 1503 using a laser beam. The driving device 1504 drives the optical head 1502. The computer 1505 controls the driving device 1504 based on information such as various control codes stored in the FeRAM 1506. As the computer 1303, for example, the one shown in FIG. 103 can be used. The FeRAM 1506 is configured by the semiconductor integrated circuit device (FeRAM) of the first to thirty-sixth embodiments and the forty-first to 66th embodiments. The image processing apparatus 1507 restores the supplied compressed image data or performs compression processing on the written image data. The FeRAM 1506 also has a function of temporarily storing image processing data.

  A conventional ferroelectric memory cannot perform a sufficiently high-speed operation, so that high-speed image processing and compression processing are difficult. On the other hand, this problem can be solved by using the FeRAM according to each embodiment of the present invention.

  Although not described with reference to the drawings in the embodiments, a large number of configurations can be realized by combining individual inventions used in all the embodiments. A conventionally proposed multi-value scheme can also be applied to each embodiment.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

1 is a diagram showing a circuit configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. The 2nd Embodiment of this invention is a figure which shows operation | movement of the semiconductor integrated circuit device of FIG. The figure which shows the modification of 2nd Embodiment of this invention, and shows the operation | movement of the semiconductor integrated circuit device of FIG. FIG. 8 is a diagram illustrating an operation of the semiconductor integrated circuit device of FIG. 1 according to the third embodiment of the present invention. The 4th Embodiment of this invention is a figure which shows operation | movement of the semiconductor integrated circuit device of FIG. The 5th Embodiment of this invention is a figure which shows operation | movement of the semiconductor integrated circuit device of FIG. The figure which shows the circuit structure of the semiconductor integrated circuit device which concerns on 6th Embodiment of this invention. The 8th Embodiment of this invention is a figure which shows operation | movement of the semiconductor integrated circuit device of FIG. The 8th Embodiment of this invention is a figure which shows operation | movement of the semiconductor integrated circuit device of FIG. The 9th Embodiment of this invention is a figure which shows operation | movement of the semiconductor integrated circuit device of FIG. The 10th Embodiment of this invention is a figure which shows operation | movement of the semiconductor integrated circuit device of FIG. The figure which shows the circuit structure of the semiconductor integrated circuit device which concerns on 11th Embodiment of this invention. The figure which shows 12th Embodiment of this invention and shows operation | movement of the semiconductor integrated circuit device of FIG. FIG. 13 is a diagram illustrating an operation of the semiconductor integrated circuit device of FIG. 12 according to the thirteenth embodiment of the present invention. FIG. 14 is a diagram illustrating an operation of the semiconductor integrated circuit device of FIG. 12 according to the fourteenth embodiment of the present invention. FIG. 23 is a diagram illustrating an operation of the semiconductor integrated circuit device of FIG. 12 according to the fifteenth embodiment of the present invention. FIG. 24 is a diagram schematically illustrating a cross-sectional structure of a cell block according to the sixteenth embodiment of the present invention, which is applicable to the semiconductor integrated circuit device of FIG. FIG. 18 is a diagram illustrating a layout applicable to the semiconductor integrated circuit device of FIG. 17 according to the seventeenth embodiment of the present invention. FIG. 18 is a diagram illustrating a layout applicable to the semiconductor integrated circuit device of FIG. 17 according to the seventeenth embodiment of the present invention. The 18th Embodiment of this invention is the figure which shows schematically the cross-section of the cell block applicable to the semiconductor integrated circuit device of FIG. 7, FIG. FIG. 21 is a diagram illustrating a layout applicable to the semiconductor integrated circuit device of FIG. 20 according to a nineteenth embodiment of the present invention. FIG. 21 is a diagram illustrating a layout applicable to the semiconductor integrated circuit device of FIG. 20 according to a nineteenth embodiment of the present invention. The 20th Embodiment of this invention is the figure which shows schematically the cross-section of the cell block applicable to the semiconductor integrated circuit device of FIG. 7, FIG. A figure showing a 21st embodiment of the present invention and a plane shape of a plate line applicable to the semiconductor integrated circuit device of Drawing 23. The figure which shows 22nd Embodiment of this invention and shows schematically the cross-section of the cell block applicable to the semiconductor integrated circuit device of FIG. 7, FIG. FIG. 26 is a diagram illustrating a layout applicable to the semiconductor integrated circuit device of FIG. 25 according to a twenty-third embodiment of the present invention. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 24th embodiment of the present invention. FIG. 28 shows the operation of the semiconductor integrated circuit device of FIG. 27, showing the twenty-fifth embodiment of the present invention. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 26th embodiment of the present invention. FIG. 30 is a diagram showing the operation of the semiconductor integrated circuit device of FIG. 29, showing the twenty-seventh embodiment of the present invention. FIG. 30 is a diagram showing an operation of the semiconductor integrated circuit device of FIG. 29, showing the twenty-eighth embodiment of the present invention. The twenty-ninth embodiment of the present invention is shown, and the operation of the semiconductor integrated circuit device of FIG. 29 is shown. FIG. 30 is a diagram illustrating the operation of the semiconductor integrated circuit device in FIG. 29 according to the thirtieth embodiment of the present invention. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 31st embodiment of the present invention. FIG. 36 illustrates the operation of the semiconductor integrated circuit device of FIG. 34, showing the thirty-second embodiment of the present invention. 42 shows a circuit configuration of a semiconductor integrated circuit device according to a thirty-third embodiment of the present invention. FIG. 38 shows the operation of the semiconductor integrated circuit device of FIG. 36, showing the thirty-fourth embodiment of the present invention. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 35th embodiment of the present invention. FIG. 39 shows the operation of the semiconductor integrated circuit device of FIG. 38, showing the thirty-sixth embodiment of the present invention. The block diagram which shows the data path part of the modem for digital subscriber lines which concerns on 37th Embodiment of this invention. The block diagram which shows the mobile telephone terminal which concerns on 38th Embodiment of this invention. The figure which shows the memory card based on 39th Embodiment of this invention. A figure showing a system LSI concerning a 40th embodiment of the present invention. The figure which shows the circuit structure of the conventional semiconductor integrated circuit device. FIG. 45 is a diagram showing a planar structure of the semiconductor integrated circuit device of FIG. 44. FIG. 45 is a view showing a cross-sectional structure of the semiconductor integrated circuit device of FIG. 44. FIG. 45 shows an operation of the semiconductor integrated circuit device of FIG. 44. The figure for demonstrating the problem of the conventional semiconductor integrated circuit device. The figure for demonstrating the problem of the conventional semiconductor integrated circuit device. The figure which shows the circuit structure of the semiconductor integrated circuit device of a prior application. The figure which shows the cross-section of the semiconductor integrated circuit device of a prior application. The figure which shows the planar structure of the semiconductor integrated circuit device of a prior application. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 41st embodiment of the present invention. FIG. 54 is a diagram showing the operation of the semiconductor integrated circuit device of FIG. 53, showing the forty-second embodiment of the present invention. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 43rd embodiment of the present invention. FIG. 56 is a diagram showing the operation of the semiconductor integrated circuit device of FIG. 55 in the forty-fourth embodiment of the present invention. The figure which shows the circuit structure of the semiconductor integrated circuit device based on 45th Embodiment of this invention. FIG. 58 shows an operation of the semiconductor integrated circuit device of FIG. 57. FIG. 58 shows an operation of the semiconductor integrated circuit device of FIG. 57. FIG. 58 is a diagram showing the operation of the semiconductor integrated circuit device of FIG. 57 in the forty-sixth embodiment of the present invention. FIG. 58 is a diagram showing the operation of the semiconductor integrated circuit device of FIG. 57, showing the forty-seventh embodiment of the present invention. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 48th embodiment of the present invention. 63 shows the 49th embodiment of the present invention, and shows the operation of the semiconductor integrated circuit device of FIG. 62. FIG. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 50th embodiment of the present invention. FIG. 67 is a diagram showing the operation of the semiconductor integrated circuit device of FIG. 64 in the fifty-first embodiment of the present invention. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 52nd embodiment of the present invention. FIG. 67 is a diagram schematically illustrating a cross-sectional structure of a cell unit according to the fifty-third embodiment of the present invention and applicable to the semiconductor integrated circuit device of FIG. 64. FIG. 67 is a diagram schematically illustrating a cross-sectional structure of a cell unit according to the fifty-third embodiment of the present invention and applicable to the semiconductor integrated circuit device of FIG. 64. FIG. 67 is a diagram showing a layout applicable to the semiconductor integrated circuit device of FIG. 64, according to a 53rd embodiment of the present invention. FIG. 54 is a diagram schematically illustrating a cross-sectional structure of a cell block according to a fifty-fourth embodiment of the present invention, which can be applied to the semiconductor integrated circuit device of FIG. FIG. 54 is a diagram schematically illustrating a cross-sectional structure of a cell block according to a fifty-fourth embodiment of the present invention, which can be applied to the semiconductor integrated circuit device of FIG. FIG. 46 is a diagram schematically showing a cross-sectional structure of a semiconductor integrated circuit device according to a fifty-fifth embodiment of the present invention. FIG. 46 is a diagram schematically showing a cross-sectional structure of a semiconductor integrated circuit device according to a fifty-fifth embodiment of the present invention. FIG. 46 is a diagram schematically showing a cross-sectional structure of a semiconductor integrated circuit device according to a fifty-sixth embodiment of the present invention. FIG. 46 is a diagram schematically showing a cross-sectional structure of a semiconductor integrated circuit device according to a fifty-sixth embodiment of the present invention. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 57th embodiment of the present invention. 76 is a diagram showing the operation of the semiconductor integrated circuit device of FIG. 76, showing the 58th embodiment of the present invention. FIG. FIG. 57 shows a semiconductor integrated circuit device according to a fifty-ninth embodiment of the present invention, and shows an operation when the semiconductor integrated circuit device of FIG. 53 is a 2T2C type memory cell system. The semiconductor integrated circuit device concerning 60th Embodiment of this invention is shown, The figure which shows the other example of the control method of the semiconductor integrated circuit device of 42nd Embodiment. FIG. 72 is a diagram showing a 61th embodiment of the present invention and a part of layout applicable to the semiconductor integrated circuit device of FIGS. 70 and 71; FIG. 72 is a diagram showing a 61th embodiment of the present invention and a part of layout applicable to the semiconductor integrated circuit device of FIGS. 70 and 71; FIG. 72 is a diagram showing a 61th embodiment of the present invention and a part of layout applicable to the semiconductor integrated circuit device of FIGS. 70 and 71; FIG. 72 is a diagram showing a 61th embodiment of the present invention and a part of layout applicable to the semiconductor integrated circuit device of FIGS. 70 and 71; A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 62nd embodiment of the present invention. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 63rd embodiment of the present invention. A plan view of a semiconductor integrated circuit device according to a 63rd embodiment of the present invention. The figure which shows schematically the cross-section of the device structure which can be applied to the semiconductor integrated circuit device based on 63rd Embodiment of this invention. The figure which shows schematically the cross-section of the device structure which can be applied to the semiconductor integrated circuit device based on 63rd Embodiment of this invention. The figure which shows schematically the cross-section of the device structure which can be applied to the semiconductor integrated circuit device based on 63rd Embodiment of this invention. The figure which shows schematically the cross-section of the device structure which can be applied to the semiconductor integrated circuit device based on 63rd Embodiment of this invention. FIG. 90 is a diagram showing a part of a layout that can be applied to the semiconductor integrated circuit device of FIGS. 87 to 90 according to the sixty-fourth embodiment of the present invention. FIG. 90 is a diagram showing a part of a layout that can be applied to the semiconductor integrated circuit device of FIGS. 87 to 90 according to the sixty-fourth embodiment of the present invention. FIG. 90 is a diagram showing a part of a layout that can be applied to the semiconductor integrated circuit device of FIGS. 87 to 90 according to the sixty-fourth embodiment of the present invention. FIG. 90 is a diagram showing a part of a layout that can be applied to the semiconductor integrated circuit device of FIGS. 87 to 90 according to the sixty-fourth embodiment of the present invention. Sectional drawing which shows the modification of 64th Embodiment of this invention. The figure which shows the operation | movement locus | trajectory of the semiconductor integrated circuit device concerning 65th Embodiment of this invention. The figure which shows operation | movement of the semiconductor integrated circuit device based on 65th Embodiment of this invention. The figure which shows operation | movement of the semiconductor integrated circuit device based on 65th Embodiment of this invention. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 66th embodiment of the present invention. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 66th embodiment of the present invention. A figure showing a circuit composition of a semiconductor integrated circuit device concerning a 66th embodiment of the present invention. The figure which shows the digital camera or digital video camera which concerns on 67th Embodiment of this invention. A figure showing a computer system concerning a 68th embodiment of the present invention. A figure showing a microprocessor chip concerning a 69th embodiment of the present invention. The figure which shows the portable computer system which concerns on 70th Embodiment of this invention. A figure showing a logic variable LSI concerning a 71st embodiment of the present invention. The figure which shows the IC card which concerns on 72nd Embodiment of this invention. The figure which shows the motor vehicle carrying the navigation system which concerns on 73rd Embodiment of this invention. The figure which shows the robot which concerns on 74th Embodiment of this invention. The figure which shows the image display apparatus which concerns on 75th Embodiment of this invention. The figure which shows the optical disk storage device based on 76th Embodiment of this invention.

Explanation of symbols

Q0 to Q15 ... cell transistors, C, C0 to C15 ... ferroelectric capacitors, WL0 to WL15 ... word lines, BL, / BL ... bit lines, PL, / PL ... plate lines, LBL, / LBL, LBL0, / LBL , LBL1, / LBL1, LBL2, /LBL2...Local bit lines, QR, QR0 to QR3 ... Reset transistors, RST, RST0 to RST3 ... Reset signals (lines), BL, /BL...Bit lines, QS, QS0 to QS3 ... Block selection transistor (cell group selection transistor), BS, / BS, BS0, / BS0, BS1, / BS1 ... Block selection signal, CB, CB0 to CB3 ... Cell block, SN0 to SN3 ... Cell node, CNT ... Controller, PLD ... Plate line driver, SA ... sense amplifier, sub ... semiconductor substrate, D to SD10, SD20 to SD36 ... source / drain regions, P1 to P7, P21 to P28 ... contacts, BE ... lower electrode, F ... ferroelectric film, TE ... upper electrode, AA0-AA3 ... active region, M0-M2 M21, M22 ... wiring layer, QA0, QA1 ... amplification transistor, 100 ... programmable digital signal processor, 110 ... analog-to-digital converter, 120 ... digital-to-analog converter, 130 ... transmission driver, 140 ... receiver amplifier, 170, 223 DESCRIPTION OF SYMBOLS ... Semiconductor integrated circuit device, 200 ... Communication part, 201 ... Transmission / reception antenna, 202 ... Antenna duplexer, 203 ... Reception part, 204 ... Baseband processing part, 205 ... DSP, 206 ... Speaker, 207 ... Microphone, 208 ... Transmission part 209: Frequency synthesizer 21 ... Audio data reproduction processing unit 212... External output terminal 213. LCD controller 214 214 LCD 215 Ringer 220 Control unit 221 CPU 222 ROM 224 Flash memory 231, 233, 235 Interface circuit, 232 ... external memory slot, 234 ... key operation unit, 236 ... external output terminal, 240 ... external memory, 300 ... mobile phone terminal, 400 ... memory card, 401 ... FeRAM chip, 501 ... macro, 502 ... semiconductor chip CG, CG0, CG1 ... cell group, CU0 to CU3 ... cell unit, RSD ... reset signal line decoder, Imp ... impurity implantation region, MBS ... main block selection transistor wiring, Vss ... power supply line, MRD ... main row decoder, SRD ... Sub-row decoder, CSL ... column selection line, DQ, / DQL ... data line, TQ0 to TQ3, TQR, TQS ... transmission gate, QN0 to QN3, QNR, QNS ... NMOS transistor, QP0 to QP3, QPR, QPS ... PMOS transistor, 600 ... digital camera Or a digital video camera, 601... Image input device, 602... Data compression device, 603, 703, 907, 1002, 1102, 1203, 1304, 1401, 1506 ... FeRAM, 604. Device, BUS ... System bus, 701 ... Computer system, 702 ... Microprocessor, 704 ... I / O device, 705 ... RAM, 705 ... ROM, 801 ... Microprocessor chip, 802 ... Microprocessor core, 803 ... Ma Black code memory, 901 ... portable computer system, 902 ... microprocessor and controller, 903 ... input device, 904 ... transceiver, 905 ... antenna, 906 ... display device, 1000 ... logic variable LSI, 1001 ... logic unit, 1100 ... IC Card 1101 IC chip 1200 Navigation system 1201 Measuring device 1202 1303 1402 1505 Computer 1205 Operation device 1206 Automobile 1300 Robot 1301 Arm 1302 1504 Driving device DESCRIPTION OF SYMBOLS 1305 ... Sensor apparatus, 1400 ... Image display apparatus, 1403 ... Image processing apparatus, 1501 ... Optical disk apparatus, 1502 ... Optical head, 1503 ... Optical disk, 1507 ... Image processing apparatus.

Claims (5)

A plurality of memory cells each comprising a cell transistor having a gate terminal connected to a word line, and a ferroelectric capacitor having one end connected to the source terminal of the cell transistor;
The drain terminal of each cell transistor of each of the plurality of memory cells is a plate line, the other end of each ferroelectric capacitor is a local bit line, the source terminal is connected to the plate line, and the drain terminal is the A reset transistor connected to the local bit line;
A block select transistor having a source terminal connected to the local bit line and a drain terminal connected to the bit line;
A memory cell block comprising:
During standby, the cell transistor is turned on, the reset transistor is turned on ,
When active, the cell transistor of the selected memory cell of the selected memory cell block is turned on, and the cell transistor of the unselected memory cell of the selected memory cell block is turned off. The cell transistor of the memory cell block that is not selected is turned on, the block selection transistor of the selected memory cell block is turned on, and the block selection of the memory cell block that is not selected The transistor is turned off, the reset transistor of the selected memory cell block is turned off, and the reset transistor of the memory cell block that is not selected is turned on.
A semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1 , wherein two adjacent memory cell blocks connected to the bit line are connected to the plate line. 2. The semiconductor integrated circuit device according to claim 1 , wherein the local bit line is formed in a layer above the ferroelectric capacitor. 2. The semiconductor integrated circuit device according to claim 1 , wherein the local bit line is formed in a lower layer than the ferroelectric capacitor. The semiconductor integrated circuit device according to any one of claims 1 to 4 , formed on a semiconductor substrate;
A logic circuit formed on the semiconductor substrate;
A semiconductor integrated circuit device comprising:

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