JP2003218237A - Semiconductor device and electronic apparatus using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing the possibilities of soft errors due to alpha rays or the like and also of suppressing the leakage current. <P>SOLUTION: The semiconductor device 1000 includes a plurality of memory cells formed on a p-type semiconductor substrate 540, each cell comprising a p<SP>-</SP>well 530 wherein an NMOS transistor Q3 is formed and which is set to the ground potential; an n<SP>-</SP>well 532 wherein a PMOS transistor Q5 is formed and which is adjacent to the p<SP>-</SP>well 530 and is set to a power supply potential Vdd; and an n-type buried layer 538 which is separated from the p<SP>-</SP>well 532, and separates lower parts of the p<SP>-</SP>well 530 and the n<SP>-</SP>well 532 from the semiconductor substrate 540. The buried layer 538 is set to a potential Vbn lower than the power supply potential Vdd. The NMOS transistor Q3 and the PMOS transistor Q5 are connected in series to form an inverter and constitute part of a flip-flop circuit. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an SRAM (static
The present invention relates to a semiconductor device including a random access memory) and electronic equipment using the same.

[0002]

Background Art and Problems to be Solved by the Invention In the natural world, radiation is pouring in almost every place although it is a very small amount. In addition, substances such as ceramics used in IC packages emit a very small amount of α rays. It is known that when radiation such as α-rays passes through each layer of a semiconductor, positive and negative charges are generated in the path to generate electrons and holes. If such electrons or holes gather in the storage region of the memory cell that stores data as a predetermined potential in the semiconductor device, the potential of the storage region may be affected and the stored data may be inverted. Such errors are called soft errors because they are temporary, unlike hard errors, which are permanently destroyed.

In order to reduce such soft errors, a technique is known in which a deep region of a semiconductor substrate and a surface region where a transistor or the like is formed are separated by a buried layer. However, the addition of the buried layer increases the number of PN junctions in the reverse bias state, leading to an increase in leak current and an increase in standby current. Also, the possibility of latch-up increases.

The present invention has been made in view of the above points, and a semiconductor device capable of reducing the possibility of a soft error and suppressing a leak current, and a semiconductor device thereof. It is to provide an electronic device used.

[0005]

(1) A semiconductor device according to the present invention is a semiconductor device having a plurality of memory cells formed on a p-type semiconductor substrate, wherein each memory cell is an NMOS transistor. Of the p-well and the n-well are separated from the n-well and the n-well adjacent to the p-well, which is adjacent to the p-well and has the power supply potential. And an n-type buried layer separating the lower part from the semiconductor substrate.

According to the present invention, if a reverse bias is applied between the buried layer and the p-type semiconductor substrate, charges are generated in the region of the semiconductor substrate below the p well and the n well due to the influence of α rays. As a result, charges are transferred from the region under the buried layer to the NMOS transistor or the PMOS.
Reaching the transistor can be greatly reduced. As a result, it is possible to significantly reduce the possibility that such charges affect the NMOS transistor and the PMOS transistor and destroy the data stored in the memory cell.

Further, since the n-type buried layer is separated from the n well, the buried layer can be set to a potential independent of the n well. Therefore, by setting the reverse bias voltage between the buried layer and the semiconductor substrate to be lower than the reverse bias between the n-well and the semiconductor substrate, it is possible to reduce the leak current generated due to the reverse bias state. .

(2) Each of the memory cells may include a flip-flop circuit.

(3) The flip-flop circuit may include a CMOS inverter formed by connecting the NMOS transistor and the PMOS transistor in series.

(4) In (1) to (3), the buried layer may be set to a potential lower than the power supply potential.

As a result, the reverse bias voltage between the buried layer and the semiconductor substrate is set to be smaller than the potential difference between the power supply potential and the ground potential, which is the reverse bias voltage between the n-well and the semiconductor substrate. It is possible to reduce the leakage current generated due to the reverse bias state, as compared with the case where the layer is set to have substantially the same potential as the n well.

(5) In (1) to (3), the reverse bias voltage between the buried layer and the semiconductor substrate is
It may be set lower than the reverse bias voltage between the n-well and the semiconductor substrate.

As a result, as compared with the case where the reverse bias voltage between the buried layer and the semiconductor substrate is set equal to the reverse bias voltage between the n-well and the semiconductor substrate, the voltage between the buried layer and the semiconductor substrate is increased. Leakage current can be reduced.

(6) In (1) to (3), the low power source is supplied to the buried layer when a low power source potential which is lower than the rated power source potential by a predetermined potential difference or more is supplied as the power source potential. The potential may be set to be substantially equal to the potential.

In the state of the low power supply potential, the amount of electric charge accumulated in the diffusion region holding the data in the NMOS transistor or the PMOS transistor becomes small. Therefore, the potential of the diffusion region is likely to be affected by the charge generated in the memory cell due to the α ray or the like, and the possibility of a soft error increasing. According to the present invention, in such a low power supply potential state, the buried layer is set to a potential substantially equal to the low power supply potential, so that the buried layer and the p-type substrate are in a reverse biased state, and are below the buried layer. It is possible to significantly reduce the amount of electric charge in the region reaching the NMOS transistor and the PMOS transistor, and reduce the possibility of occurrence of a soft error.

(7) In (6), the buried layer may be grounded when a potential higher than the potential lower than the rated power source potential by the predetermined potential difference is supplied as the power source potential. .

As a result, the reverse bias state between the buried layer and the semiconductor substrate is eliminated, so that the leak current can be reduced.

(8) In (6) or (7), a power supply potential determination circuit for determining whether or not the power supply potential is the low power supply potential is further provided, and the potential of the buried layer is determined by the power supply potential determination. You may make it set based on the determination result of a circuit.

(9) In (6) or (7), the power supply potential signal input terminal to which a power supply potential signal indicating whether the power supply potential is the low power supply potential is input is further provided, and the buried layer is provided. The potential may be set based on the power supply potential signal.

(10) An electronic apparatus according to the present invention is equipped with any one of the semiconductor devices described above.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described more specifically with reference to the drawings.

1. First Embodiment 1.1 Schematic Configuration of SRAM Chip FIG. 1 shows an SRAM as a semiconductor device according to the present embodiment.
3 is a block diagram showing a schematic configuration of a chip 1000. FIG.
As shown in this figure, the SRAM chip 1000 has an address input circuit 100 as an address input unit, a data input circuit 200, a data output circuit 300, and a control circuit 40.
0, row decoder 550, column decoder 570, write driver 250, memory cell array 500, sense amplifier 3
50 and a large number of terminals 601-604.

In the memory cell array 500, for example, 16
Megabit memory cells are arranged. The memory cell array 500 additionally includes redundant memory cells for replacing and repairing defective memory cells found in a chip state.

The terminals 601 to 604 are formed as metal pads, and most of them are connected to external terminals of the package through bumps, bonding wires, etc. in the packaging process. These terminals are roughly classified into address input terminals 601 to which address signals A0 to A19 are input, that is, data input / output terminals 602 for inputting / outputting data, which are terminals I / O1 to I / O16, and control signal terminals. 603, a power supply terminal 604 including a Vdd terminal and a GND terminal.

The control signal terminal 603 has a φ terminal to which a clock signal is input, a / CS terminal to which a chip select signal is input, and a / W input to which a write enable signal is input.
E terminal is included. Chip select signal / CS
And the write enable signal / WE is active low. Each terminal of the control signal terminal 603, that is, the φ terminal,
The control signal input to the / CS terminal and the / WE terminal is input to the control circuit 400. Then, the control circuit 400
Various control signals for controlling data writing and data reading in the SRAM chip 1000 are generated.

The address input circuit 100 as an address input unit outputs a (internal) address signal for selecting a part of the memory cell based on the input external address signals A0 to A19 or independently to the row decoder 550. To the column decoder 570.

The row decoder 550 includes the address input circuit 1
A row selection signal is generated based on the address signal output from 00. The column decoder 570 also generates a column decode signal based on the address signal output from the address input circuit 100.

An external data signal is input to the data input circuit 200 via the data input / output terminal 602 when writing data. Then, the data input circuit 200 outputs the data signal to the write driver 250.

A signal obtained by amplifying the data signal of the memory cell by the sense amplifier 350 at the time of reading data is input to the data output circuit 300. Then, the data output circuit 3
00 outputs data to the outside via the data input / output terminal 602.

1.2 Memory Cell Array The memory cell array 500 of the SRAM chip 1000 according to the present embodiment has four memory cell mats 510, that is, upper eight data, as shown in the schematic diagram of FIG.
Two memory cell mats 510 corresponding to the bits and two memory cell mats 510 corresponding to the lower 8 bits of the data are provided. Then, each memory cell mat 5
Reference numeral 10 is composed of a plurality of memory blocks.

FIG. 3 is a schematic diagram showing one memory block 520 and peripheral circuits in memory cell mat 510 in which the upper 8 bits of data are stored. This memory block 520 includes memory cells MC of 128 kbits.
20 are arranged in an array. Such a memory block 520 has 32 memory blocks in each memory cell mat 510.
The memory capacity of the entire memory cell array 500, which is arranged in blocks and includes four memory cell mats 510, is 16 Mbits.

The memory block 520 includes a plurality of word lines WL1 to WL2048 and a plurality of bit line pairs (BL1, / BL1) to (BL64, which intersect these word lines).
/ BL64) and memory cells MC provided corresponding to the intersections of these word lines and these bit line pairs.

In addition, around the memory block 520,
Data buses (DB1, / DB1) to (DB8, / DB)
8) and decode signal lines (Y1, / Y1) to (Y8, / Y8) for transmitting the output signal from the column decoder 570 are also provided. Data bus pair (DB1, / DB1) ~
Each of (DB8, / DB8) is connected to a bit line pair for every eight bit line pairs. Data bus pair (DB1,
/ DB1) as an example, the data bus pair (DB1, / D
B1) is a bit line pair (BL1, / BL1), (BL
9, / BL9), (BL17, / BL17) ... (B5
7, / BL57) via a column gate CG composed of a transmission gate. The connection control between the bit line pair and the data bus pair by the column gate CG is performed by the decode signal (Y
1, / Y1) to (Y8, / Y8). Also, data bus pairs (DB1, / DB1) to (DB
8, / DB8) is connected to the write driver 250 and the sense amplifier 350.

Since FIG. 3 shows one memory block 520 in the memory cell mat 510 in which the upper 8 bits of data are stored, the data bus pair to which each bit line pair is connected is (DB1, / DB1). ) ~ (DB8, / D
It was either B8). However, in the memory cell mat 510 in which the lower 8 bits of data are stored,
In each memory block 520, the data bus pairs to which each bit line pair is connected are (DB9, / DB9) to (DB1).
6, / DB16).

1.3 Memory Cell As shown in FIG. 4, each memory cell is composed of six MOS transistors of transfer transistors Q1 and Q2, drive transistors Q3 and Q4, and load transistors Q5 and Q6. In this example, the transfer transistors Q1 and Q2 and the drive transistors Q3 and Q4 are NMOS transistors, and the load transistors Q5 and Q6 are PMOS transistors. This memory cell has a configuration in which a flip-flop composed of load transistors Q5 and Q6 and drive transistors Q3 and Q4 is connected to a pair of bit lines BLn and / BLn via transfer transistors Q1 and Q2. A word line WL is connected to the gates of the transfer transistors Q1 and Q2.

More specifically, the load transistor Q5
And the drive transistor Q3 are connected in series between the power supply potential Vdd and the ground potential to form a CMOS inverter, and the load transistor Q6 and the drive transistor Q4 are similarly connected to form another CMOS inverter. The gates of the load transistor Q5 and the drive transistor Q3 are both connected to the connection point between the drains of the load transistor Q6 and the drive transistor Q4. Similarly, the gates of the load transistor Q6 and the drive transistor Q4 are both connected to the connection point between the drains of the load transistor Q5 and the drive transistor Q3.
With such a configuration, when one of the drain connection points becomes the H level, the other drain connection point operates as the flip flop, which operates as the L level. Then, the states of the respective drain connection points are output to the bit lines, for example, BLn and / BLn, via the transfer transistors Q1 and Q2 when the word line WL is driven to the H level.

FIG. 5 is a diagram schematically showing, as an example of an inverter formed in each memory cell, an inverter constituted by a drive transistor Q3 and a load transistor Q5, the structure around it and a potential application state. . As shown in this figure, this inverter has a p-well 530
And the n-well 532 adjacent to the p-well 530.
And a load transistor Q5 which is a PMOS transistor formed in the above. The n-type buried layer 538 is separated from the p-well 530 and the n-well 532.
Are formed. The buried layer 538 is the p-well 53.
The lower parts of the 0 and n wells 532 are formed so as to be separated from the p-type semiconductor substrate. Also, p-well 530
An element isolation region 536 formed of, for example, a silicon oxide film is formed in the n well 532.

Then, the semiconductor substrate 540 and the p well 53
0 and the source Q3S of the drive transistor Q3 are grounded. Also. The power supply potential Vdd is applied to the n-well 532 and the source Q5S of the load transistor Q5. The n-type buried layer 538 has a potential Vbn lower than the power supply potential Vdd. For example, when the power supply potential Vdd is 3V, the potential V of the buried layer 538 is
bn is set to 1V. The potential Vbn of the buried layer
For example, as shown in FIG. 6, the potential may be lower than the power supply potential Vdd, and may change corresponding to the power supply potential Vdd.

In each memory cell, the structure of the inverter formed by the drive transistor Q4 and the load transistor Q6, the surrounding structure, and the potential application state are the same as above.

In such a memory cell, the buried layer 5
A reverse bias is applied between the No. 38 and the p-type semiconductor substrate 540. The potential of the buried layer 538 is a positive potential (potential that prevents electrons from flowing into the p-well 530).
Therefore, even if electrons are generated in the buried layer 538 and the silicon substrate 540 due to the influence of α rays, the electrons flow from the silicon substrate 540 and the buried layer 538 through the n well 532 to the power supply voltage Vdd side. Therefore, the electrons flowing into the drain Q3D of the drive transistor Q3 are only the electrons generated in the p well 530. In this way, p-well 530 and n-well 5
Even if electrons are generated in the region below 32, the arrival of the electrons in the NMOS transistor Q3 can be significantly reduced.

In a semiconductor device having no buried layer 50, all the electrons generated on the trajectory of α rays flow into the drain. The distance of this locus is a value obtained by adding the depth of the p-well and the depth of the silicon substrate. On the other hand, in the semiconductor device shown in FIG. 5, there is only the depth of the p well 530. Therefore, in the semiconductor device of this embodiment, the drop in the drain voltage is significantly smaller than that in the semiconductor device having no buried layer 538, and as a result, the retained data is not destroyed. The holes flow to the ground line V _SS connected to the silicon substrate 540, the ground line V _SS connected to the p-well 530, and the like. As described above, in the present embodiment, since the embedded layer 358 is provided, the α ray does not adversely affect the data holding function.

Since the n type buried layer 538 is separated from the n well 532, the buried layer 538 is n
The potential can be set independently of that of the well 532. Utilizing this, in the present embodiment, the buried layer 5
And the reverse bias voltage between the semiconductor substrate 540 and the semiconductor substrate 540 is n
Since it is set to be smaller than the reverse bias between the well 532 and the semiconductor substrate 540, the leakage current generated due to the reverse bias state is smaller than that in the case where the buried layer 538 is set to substantially the same potential as the n well 532. Can be reduced. As a result, the power consumption of the SRAM chip 1000, particularly the power consumption in the standby mode, can be reduced.

2. Second Embodiment An SRAM chip as a semiconductor device of the second embodiment is
Except for the points described below, the SRAM chip is configured and operates similarly to the SRAM chip of the first embodiment. Note that, in the drawings, corresponding parts are designated by the same reference numerals as those in the first embodiment.

FIG. 7 is a block diagram showing an outline of the configuration of an SRAM chip 1010 as a semiconductor device according to this embodiment. As shown in this figure, in addition to the components described in the first embodiment, a power supply potential determination circuit 700 and a voltage control circuit 710 are provided.

The power supply potential determination circuit 700 includes a power supply terminal 60.
It is determined whether the power supply potential supplied to 4 is a low power supply potential lower than the rated power supply potential by a predetermined potential difference or more. The voltage control circuit 710 sets and supplies the potential applied to the buried layer 538 based on the determination result of the power supply potential determination circuit 700.

FIG. 8 is a graph showing an example of the potential applied to the buried layer 538 by the operation of the power supply potential determination circuit 700 and the voltage control circuit 710 as a relationship with the power supply potential. In this example, the rated power supply potential is 3.0 V, and when the power supply potential exceeds 1.4 V, the buried layer 5
38 is grounded, and when the power supply potential is 1.4 V or less, the buried layer 538 has a potential substantially equal to the power supply potential. That is, the power supply potential determination circuit 700 determines that the power supply potential is lower than the rated power supply potential of 3.0 V by 1.6 V or more as a low power supply potential state, and the voltage control circuit 710 responds to the determination by the power supply potential determination circuit 700. A potential equal to the potential is applied to the buried layer 538. Further, the power supply potential determination circuit 700 determines that the power supply potential is higher than the rated power supply potential of 3.0 V and higher than 1.4 V, which is 1.6 V lower than the rated power supply potential of 3.0 V, as a low power supply potential. In response to the determination, the voltage control circuit 710 applies the ground potential to the buried layer 538.

When the power supply potential is low, for example,
Diffusion regions Q3D and Q holding data in the NMOS transistor Q3 or the PMOS transistor Q5
The amount of charge accumulated in 5D is reduced. Therefore, the potential of the diffusion region Q3D or Q5D is easily affected by the charge generated in the memory cell due to the α ray or the like,
Increases the likelihood of soft errors. In this embodiment, in such a low power supply potential state, the buried layer 538 is set to a potential substantially equal to the power supply potential, so that the buried layer 538 and the p-type substrate 540 are in a reverse bias state, and the buried layer 538 is in a reverse bias state. The charge in the region of the lower semiconductor substrate 540 is, for example, the NMOS transistor Q.
3 and the PMOS transistor Q5 can be significantly reduced, and the possibility of occurrence of a soft error can be reduced. As a result, the SRAM chip 1010
In the retention mode, which is a mode in which the power supply voltage is reduced, the possibility that a soft error will occur can be reduced.
In addition, the retention mode is the SRAM chip 1010.
It is often used to save power when there is no need to write or read data to.

Further, the buried layer 538 is grounded when the power supply potential not lower than the rated power supply potential by a predetermined potential difference or more is supplied. As a result, at such a power supply potential, the reverse bias state between the buried layer 538 and the semiconductor substrate 540 is eliminated, and the leak current is reduced. This also reduces the standby current. In addition, the number of pn junctions in the reverse bias state is reduced, so that the possibility of latch-up is reduced.

3. <Electronic Device> FIGS. 9A, 9B, and 9C are external views showing an example of an electronic device using the SRAM chip in any of the above-described embodiments. FIG. 9A shows a mobile phone 88.
9B is a wristwatch 92, and FIG.
Is a portable information device 96.

These electronic devices include the SRAM chip and the CPU (central processing unit) in the above-described embodiments.
nit), a display driver for driving the display unit 98, and the like. The respective parts including these are connected to each other by a bus line or other signal transmission means.

The electronic device in which the SRAM chip in any of the above-described embodiments is used is not limited to a mobile phone, a wrist watch, and a portable information device, but a notebook computer, an electronic notebook, a pager, a calculator, a POS terminal. ,
Various electronic devices such as IC cards and mini disc players can be considered.

4. <Modifications> 4.1 In each of the above-described embodiments, the example of the SRAM chip is shown as the semiconductor device according to the present invention. However, the semiconductor device according to the present invention is a system semiconductor chip including the SRAM chip. It may be.

4.2 In the second embodiment, the voltage control circuit 710 sets and supplies the potential applied to the buried layer 538 based on the determination result of the power supply potential determination circuit 700. However, the power source potential signal input terminal to which a power source potential signal indicating whether or not the power source potential is lower than the rated power source potential by a predetermined potential difference or more is input is S.
It may be provided in the RAM chip, and the voltage control circuit 710 may set and supply the potential applied to the embedded layer 538 based on the power supply potential signal.

4.3 In each of the above-described embodiments, the example in which the flip-flop of each memory cell includes an NMOS transistor and a PMOS transistor has been shown. However, if each memory cell is configured to include an NMOS transistor and a PMOS transistor, the flip-flop of each memory cell is NMO.
It may be configured to include only one of the S transistor and the PMOS transistor. For example, in the example of the memory cell shown in FIG. 4, the load transistors Q5 and Q6 are
Can also be replaced with resistance elements.

4.4 The present invention is not limited to the embodiments described above, and various modifications can be made within the scope of the gist of the present invention or the equivalent range of the claims. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a configuration of an SRAM chip in a first embodiment.

FIG. 2 is a schematic diagram showing a memory cell array including four memory cell mats.

FIG. 3 is a schematic diagram showing a memory block and peripheral circuits.

FIG. 4 is a circuit diagram showing a configuration of each memory cell.

FIG. 5 is a diagram schematically showing an example of an inverter formed in each memory cell, a structure around the inverter, and a potential application state.

FIG. 6 is a graph showing an example of setting the potential of a buried layer.

FIG. 7 is a block diagram showing a schematic configuration of an SRAM chip according to a second embodiment.

FIG. 8 is a graph showing an example of setting the potential of a buried layer.

9A, 9B, and 9C are external views showing examples of electronic devices using the SRAM chip in any of the embodiments.

[Explanation of symbols]

100 address input circuit 200 data input circuit 300 data output circuit 350 sense amplifier 400 control circuit 500 memory cell array 510 memory cell mat 520 memory block 530 p well 532 n well 536 element isolation region 538 buried layer 540 semiconductor substrate 550 row decoder 570 column decoder 601 Address input terminal 602 Data input / output terminal 603 Control signal terminal 604 Power supply terminal 700 Power supply potential determination circuit 710 Voltage control circuit 1000, 1010 SRAM chip CG Column gate MC Memory cell Q1, Q2 Transfer transistor Q3, Q4 Drive transistor (NMOS transistor) Q3S, Q5S Source Q3D, Q5D Drain Q5, Q6 Load transistor (PMOS transistor)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/10 481 H01L 27/08 321B 491 27/11

Claims (10)

[Claims] 1. A semiconductor device having a plurality of memory cells formed on a p-type semiconductor substrate, wherein each memory cell has an NMOS transistor formed therein and is set to a ground potential.
A well, an n-well in which a PMOS transistor is formed, is adjacent to the p-well, and has a power supply potential, and the p-well and the n-well are separated from the n-well.
A semiconductor device comprising: an n-type buried layer separating the lower part of the well from the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein each memory cell includes a flip-flop circuit. 3. The semiconductor device according to claim 2, wherein the flip-flop circuit includes a CMOS inverter formed by connecting the NMOS transistor and the PMOS transistor in series. 4. The semiconductor device according to claim 1, wherein the buried layer is set to a potential lower than the power supply potential. 5. The reverse bias voltage between the buried layer and the semiconductor substrate is set to be smaller than the reverse bias voltage between the n-well and the semiconductor substrate according to any one of claims 1 to 3. Semiconductor device. 6. The buried layer according to claim 1, wherein the embedded layer is supplied with a low power source potential which is lower than a rated power source potential by a predetermined potential difference or more as a power source potential. A semiconductor device that is set to a potential approximately equal to the low power supply potential. 7. The semiconductor device according to claim 6, wherein the buried layer is grounded when a potential exceeding a potential lower than the rated power source potential by the predetermined potential difference is supplied as the power source potential. 8. The power supply potential determination circuit according to claim 6 or 7, further comprising: a power supply potential determination circuit that determines whether or not the power supply potential is the low power supply potential. A semiconductor device set based on a determination result. 9. The power supply potential signal input terminal to which a power supply potential signal indicating whether or not the power supply potential is the low power supply potential is input, further comprising: A semiconductor device set based on the power supply potential signal. 10. An electronic apparatus including the semiconductor device according to claim 1.