JP4671796B2 - Microcomputer timer adjustment mechanism - Google Patents

Description

  The present invention relates to a timer adjustment mechanism in a microcomputer, in particular, a microcomputer that performs application (program) processing using a timer value by a timer.

  FIG. 8 is a diagram illustrating an example of a configuration of a general microcomputer. For example, a case where the microcomputer is mounted on an ECU (Electronic Control Unit) is illustrated. In the figure, reference numeral 1 indicates a microcomputer (hereinafter also referred to as “microcomputer”), which is mounted on the ECU 7 to control the entire ECU. The microcomputer 1 is roughly divided into a processing unit 2 that executes the application process and a real-time pulse unit 3 that forms an IO resource.

  The processing unit 2 has a well-known configuration, and includes a CPU 11, a ROM 12 that stores the program, and a RAM 13 that temporarily stores input / output data. On the other hand, the real-time pulse unit 3 includes a free-run timer 15, a capture function unit 16 that latches a timer value when a valid edge of a pulse is input, for example, calculates a pulse period, and pulses using the timer value. It comprises a compare function unit 17 and the like for performing pulse output processing such as designating output timing as a reserved time, and an IO register 18.

  Both the capture function unit 16 and the compare function unit 17 operate according to the timer value of the timer 15, receive the pulse input from the IO driver 5, and send the pulse output from the IO driver 6. The timer 15 for setting the timer value is driven by the external oscillator 4.

  Here, when attention is paid to the processing unit 2, in the application processing (pulse input processing / pulse output processing) by the processing unit 2, time calculation or the like is performed by a timer reference clock based on the timer 15, in this case, It is assumed that the timer reference clock is a predetermined constant clock. For example, it is assumed that the LSB (Least Significant Bit) of the timer 15 is a constant value of 1 μs.

  In addition, as a well-known technique relevant to this invention, there exist the following [patent documents 1 and 2]. Patent Document 1 discloses a control processing device that enables timer output processing of the number of built-in timers or more, allows the timer output function to be used freely and widely, and can be configured inexpensively as a whole. In addition, Patent Document 2 discloses an intelligent timer that can be set to an appropriate software timer value each time the clock frequency is changed.

JP-A-8-44406 JP-A-8-292822

  As described above, the application process in the processing unit 2 is premised on that the process is performed with a predetermined constant timer reference clock (for example, timer LSB = 1 μs). Therefore, it is not usually assumed for the microcomputer 1 that the timer reference clock changes. However, there is often a need to change the timer reference clock.

  The first example of the need is to increase the frequency of the external oscillator 4. This is due to needs such as when improvement in processing speed of the microcomputer 1 is required. The second example of the need is a need to change the timer function unit when the microcomputer is changed.

  When the LSB of the timer 15 that is the basis of the time calculation used in the application process changes according to such needs, a wide variety of logic in the software related to the application, particularly the use of the timer value for the time calculation, etc. It is necessary to change all the logic in the location, and the amount of logic change, that is, the amount of software correction becomes enormous. This causes a problem that a large-scale logic conversion work is required. For example, if the LSB of the timer reference clock is ½ (for example, 0.5 μs), a logic conversion process is required to convert the pulse period of the calculation result to double.

  Thus, it is not easy to change the timer reference clock, and the following restrictions (i) and (ii) are imposed, for example.

  (I) When improvement of the microcomputer processing capability by increasing the clock frequency is required, it is limited to the clock change that can be realized without changing the timer reference clock. (Ii) When selecting a new microcomputer, It is limited to a microcomputer having a timer reference clock applicable to application processing.

  Therefore, in view of the above problems, the present invention provides a microcomputer that performs application processing using a timer value, even when the timer reference clock that is the basis of the timer value has to be changed. An object of the present invention is to provide a timer adjustment mechanism capable of changing the timer reference clock without changing any application processing logic executed in the microcomputer.

  In other words, an object of the present invention is to provide a microcomputer having a mechanism that absorbs the change of the timer reference clock in software.

  FIG. 1 is a diagram schematically showing a timer adjustment mechanism according to the present invention. Throughout the drawings, similar components are denoted by the same reference numerals or symbols.

  In the figure, the upper part schematically represents the microcomputer 1 with the clock source “before change”, the software processing in the processing unit 2 in FIG. 8 is represented as “application AP”, and the reference clock for executing this application Is generated by the real timer tim. This is formed in the IO register 18 in response to the output of the free-run timer 15 of FIG.

  If the clock source is changed as described above, the configuration changes like the microcomputer 1 of the clock source “after change” in the lower part of FIG. This lower configuration is the configuration according to the present invention, and the characteristic configuration is in the timer adjustment mechanism 20. The timer adjustment mechanism 20 performs an application (AP) process to be executed with a clock (for example, LSB = 1 μs) predetermined by the actual timer tim, and a clock (for example, LSB = 0.0.0) of the actual timer TIM different from the clock. 8 μs), and the mechanism 20 converts the real timer TIM into a virtual timer TIMv proportional to a predetermined clock conversion coefficient α, and the above application process is converted into the converted virtual It is executed by the clock of the timer TIMv. Thus, the application AP that must be executed under the real timer tim can be executed under the real timer TIM after changing the clock source without changing any logic in the application AP. All that is done is the relatively simple timer adjustment mechanism 20 described above.

  More specifically, the timer adjustment mechanism 20 performs a “virtual timer generation process” VIR (virtual) using the clock conversion coefficient α as a parameter for the timer output of the real timer TIM. A virtual timer TIMv is formed by this processing VIR. The virtual timer TIMv can be realized by writing the virtual timer value obtained by the above processing into, for example, the RAM 13 in FIG. Here, a clock source timer exactly equivalent to the real timer tim before the clock source change is realized by this virtual timer TIMv. That is, the process P in FIG. 1 absorbs the influence caused by the clock source change in the microcomputer 1. Then, the application AP switches from the real timer (TIM) access to the virtual timer (TIMv) access via the “switching process” SW in the figure, and can cooperate with a new timer source, that is, the virtual timer TIMv.

  According to the present invention, even if the timer is changed to a timer whose frequency is increased in order to improve the processing speed of the microcomputer 1 only by introducing the timer adjustment mechanism 20, for example, the application originally executed by the microcomputer 1 has no logic. The clock source can be freely changed at any time without worrying about the previous constraints (i) and (ii) described above.

  FIG. 2 is a timing diagram showing the adjustment process of the timer adjustment mechanism 20 according to the present invention in an analogy in an easy-to-understand manner. In this figure, the vertical axis is the timer value, and the horizontal axis is the time. This timer value repeatedly changes like a sawtooth wave with the passage of time. In the figure, a sawtooth waveform R represented by a solid line represents the movement of a real timer (TIM in FIG. 1), while a sawtooth waveform V represented by a dotted line represents a virtual timer (TIMv in FIG. 1). Represents the movement. Note that the pulse input process (capture) and the pulse output process (compare) described in FIG. 8 are shown as pulses CAPT and COMP in FIG. 2, respectively (upward arrows represent the above-mentioned effective edges). The intersections with the waveform R specify the capture time (reference) and compare time (setting), respectively. Although the real timer (R) is shown, the same applies to the virtual timer (V). The timer adjustment mechanism 20 of the present invention roughly performs two processes. One is “periodic timing processing”, and the other is “application access processing”. In FIG. 2, the occurrence of “periodic timing processing” is indicated by “A” surrounded by a square, and the occurrence of “access processing from an application” is indicated by “B” enclosed by a square. The latter “access processing from an application” B further includes two processes B1 and B2. “B1” is the above-described capture process (time reference read process), and “B2” is the above-described compare process (time setting write process). Here, main reference operations (“A”, “B1”, and “B2”) in the present invention are listed in the following [1] to [8].

-Regarding the basic operation "A" [1] Each timer value of the real timer TIM and the virtual timer TIMv is both a timer zero value ("0" at the lower left end of FIG. 2) and a constant timer upper limit value (0xFFFFFF at the upper left end of FIG. When the timer operation is repeated so as to return to the timer zero value ("0") when the timer upper limit value is reached, it is periodically read at the regular timing "A". By setting the timer value of the real timer (R) as the real timer reference value Tbase and calculating and updating the virtual timer reference value Tbasev based on the real timer reference value Tbase and the clock conversion coefficient α, the virtual timer A TIMv is formed.

  [2] The previous virtual timer reference value Tbasev (the value obtained by multiplying the difference (Tbaser (current) -Tbaseer (previous)) by the clock conversion coefficient α between the actual timer reference values read each time the previous time and the current time. By adding (previous), the current virtual timer reference value Tbasev is calculated.

  [3] When starting the real timer TIM and the virtual timer TIMv, the timer values of the real timer and the virtual timer are initially set to the same timer value (see “Initial setting” at the lower left of FIG. 2).

  [4] The period of the periodic timing A is set to such a length that the timer overflow “OF” that reaches the above-mentioned timer upper limit value does not occur twice or more within the period (AA).

-Regarding basic operation "B1" [5] If a capture time reference request is generated in application processing,
Based on the update timing t0 of the virtual timer (v) most recently at the reference time t1, the actual timer reference value Tbaser, which is the actual timer value at the reference point, and the current actual timer value Treal acquired at the reference time t1 Based on the actual timer relative value ΔTreal which is the difference between the two (Treal-Tbase) and the clock conversion coefficient α, the virtual timer value Tvir according to the reference request is calculated, and the virtual timer value Tvir is returned to the application process. Like that.

  [6] The virtual timer relative value ΔTvir is obtained by multiplying the real timer relative value ΔTreal by the clock conversion coefficient α, and the virtual timer relative value ΔTvir is added to the virtual timer reference value Tbasev to obtain the reference time t1. A virtual timer value Tvir is obtained.

-Regarding basic operation "B2" [7] If a request to set a compare time is generated in application processing,
Between a virtual timer reference value Tbasev that is a virtual timer value at the base point and the virtual timer value Tvir at the setting request time point t1 with the update timing t0 of the virtual timer (V) most recently at the setting request time point t1 as a base point Based on the virtual timer relative value ΔTvir which is the difference (Tvir−Tbasev) and the reciprocal 1 / α of the clock conversion coefficient α, the actual timer value Treal related to the setting request is calculated, and the actual timer value Treal is calculated as the above application. Return it to the process.

  [8] The virtual timer relative value ΔTvir is multiplied by the inverse 1 / α of the clock conversion coefficient α to obtain the actual timer relative value ΔTreal, and the actual timer reference value Tbase is added to the actual timer relative value ΔTreal. An actual timer value Treal related to the setting request is obtained.

  The main items of the above basic operation are summarized as follows by using mathematical formulas.

(A) Periodic (update) timing processing 1) At each periodic timing A, the timer value (actual timer value) of the actual timer TIM is read and stored as an actual timer reference value. “Tbaser” in FIG. 2 is the actual timer reference value.

  2) A reference value of the corresponding virtual timer TIMv is generated as a virtual timer reference value Tbasev from the actual timer reference value Tbase. “Tbasev” in FIG. 2 is the virtual timer reference value.

In the initial setting of this periodic timing process (see “Initial setting” in FIG. 2),
Tbasev = Tbaser
And

  At the normal time of the periodic timing process, the current timer reference value Tbase difference between each adjacent two periodic timings (AA), the clock conversion coefficient α, and the previous virtual timer reference value The virtual timer reference value Tbasev is calculated and updated at each regular timing. Therefore, this calculated Tbasev is expressed by the following equation.

Tbasev = Tbasev (previous) +
(Tbaser (current) -Tbaser (previous)) × α
(B) Access processing from application (AP) B1) At reference (capture / read processing)
The current virtual timer value (Tvir in FIG. 2) is calculated from the actual timer reference value Tbaser, the virtual timer reference value Tbasev, and the current actual timer value (Treal in FIG. 2). This calculation is represented by the following formula.

Tvir = Tbasev + (Treal−Tbase) × α
= Tbasev + ΔTreal × α
= Tbasev + ΔTvir
However, ΔTreal is the aforementioned real timer relative value, and ΔTvir is the aforementioned virtual timer relative value. Here, the current virtual timer value Tvir related to the reference request at the time of reference is obtained.

B2) When setting the time (compare / write processing)
The actual timer value Treal to be set is calculated from the actual timer reference value Tbase and the virtual timer reference value Tbasev and the time setting value calculated by the application AP, that is, the virtual timer value Tvir. This calculation is represented by the following formula.

Treal = Tbase + (Tvir−Tbasev) × 1 / α
= Tbaser + ΔTvir × 1 / α
= Tbaser + ΔTreal
Here, the actual timer value Treal at the time setting time is obtained.

  Next, an example of a flowchart for executing the above basic operations will be described.

FIG. 3 is a flowchart showing the initialization processing operation. In this figure,
Step S11: Start the real timer TIM,
Step S12: Read the timer value of the real timer TIM at the time of activation.

Step S13: The read timer value is set as the initial value of the actual timer reference value Tbase,
Step S14: The same read timer value is set as the initial value of the virtual timer reference value Tbasev.

  The subsequent steps S15 and S16 are “initialization processing” steps in the scheduled interrupt processing (FIG. 4) described below. This scheduled interrupt process is a general interrupt process in a microcomputer. For example, a scheduled interrupt is performed every 1 ms. In this case, if the LSB of the timer is 1 μs as described above, the interval time of 1 ms is originally determined based on this 1 μs. However, if this 1 μs is shortened to 0.8 μs as in the above example (frequency increase), the 1 ms cannot be maintained and will shift.

Therefore, the present invention diverts the basic operation “B2” (compare process) described above, and this compare process replaces the setting of 1 ms. Returning to FIG.
Step S15: The compare process (B2) is activated,
Step S16: A value (Tint × α) obtained by multiplying the above 1 ms (interval time Tint) by the above-mentioned clock conversion coefficient is set as an initial value of the comparison process.

  To summarize the above, when performing a fixed interval (Tint) scheduled interrupt in the existing timer interrupt processing included as one of the application (AP) processing, the above-mentioned basic operation B1, that is, the compare processing executed at the time of setting the compare time Is set as the initial value of the comparison, a predetermined interval time multiplied by the clock conversion coefficient α is set (Tint × α), and the timer interrupt process is initialized. Thereafter, normal processing of timer interrupt processing starts.

FIG. 4 is a flow chart showing the scheduled interrupt process and the virtual timer reference value calculation (the basic operation “A”, that is, the normal process of the periodic timing process) linked to this. In this figure,
Step S21: Start the scheduled interrupt process (Tint),
Step S22: The fixed time (Tint × α) is set by the compare function based on the basic operation “B2”.

  Step S23: Divide the timing by the above Tint × α and execute a periodic timing process (the basic operation “A”) of, for example, 1 sec corresponding to the real timer. When the 1 sec is not reached, END is reached, and 1 sec The next step S24 is entered each time.

Step S24: In this step, the previous values Tbasev_o and Tbasev_o of the actual timer reference value Tbaser and the virtual timer reference value Tbasev are held,
Step S25: In this step, the actual timer value Tbase (current) at the current timing is read,
Step S26: In this step, the above-described calculation formula Tbasev = Tbasev (previous) +
(Tbaser (current) -Tbaser (previous)) × α
Thus, the virtual timer reference value Tbasev is calculated and updated at regular intervals.

  After the initialization in the timer interrupt process Tint by the above steps S16, S21 and S22, the normal process is executed by calculating the output set value at every constant interval (Tint × α) multiplied by the clock conversion coefficient α. . Further, in the above steps S23 to S26, the value obtained by multiplying the difference (Tbaser (current) -Tbaseer (previous)) between the respective real timer reference values read the previous time and the current time by the clock conversion coefficient α is stored. The current virtual timer reference value Tbasev is calculated by adding the virtual timer reference value Tbasev (previous). Considering step S23 above, the timing time in the periodic timing process ("A") is sufficient to be long enough that the actual timer does not overflow. This is because even if the timing time is shortened (even if it is a high-speed regular timing), the accuracy of the timer value is not improved so much. For this purpose, “frequency division” in step S23 is performed. This also reduces the software processing load.

  Further, considering the “overflow”, the timer overflow “OF” (FIG. 2) that reaches the timer upper limit value does not occur twice or more in one cycle (AA) of the periodic timing A as described above. Set to a reasonable length. If the timer overflow “OF” occurs two or more times within the one cycle, it becomes difficult to calculate the difference between Tbase (current) and Tbase (previous), especially the processing of steps S24 to S26 in FIG. Because it becomes.

  As described above, “periodic timing processing” “A” is executed, and “access processing from application” “B” is executed based on the periodic timing, and read processing (capture) “B1” at the time of reference is performed. Time setting processing (compare) “B2” is performed.

FIG. 5 is a flowchart showing a reading process (capture) operation at the time of reference.
FIG. 6 is a flowchart showing the write processing (compare) operation at the time setting.

First referring to FIG.
Step S31: Assume that a capture time “reference request” is generated in the application process.
Step S32: The current real timer value is acquired and stored as Treal,
Step S33: An actual timer relative value ΔTreal which is a difference between the actual timer value Treal and the actual timer reference value Tbase is calculated.
Step S34: The calculated ΔTreal is multiplied by α (clock conversion coefficient),
Step S35: The ΔTreal is added to the virtual timer reference value Tbasev to obtain a virtual timer value Tvir,
Step S36: The Tvir is returned as a return value to the reference request source application.

  After all, the series of steps is as follows. Assuming that a capture time reference request is generated in the application process, the actual timer reference value Tbase, which is the actual timer value at the base point, with the update timing t0 of the virtual timer (v) closest to the reference time t1 as the base point, Based on the actual timer relative value ΔTreal which is a difference (Treal−Tbase) from the current actual timer value Treal acquired at the reference time t1, and the clock conversion coefficient α, the virtual timer value Tvir related to the reference request is calculated. The calculated virtual timer value Tvir is returned to the application process. In this case, the virtual timer relative value ΔTvir is obtained by multiplying the real timer relative value ΔTreal by the clock conversion coefficient α, and the virtual timer reference value Tbasev is added to the virtual timer relative value ΔTvir to obtain the reference time t1. A virtual timer value Tvir is obtained.

Next, referring to FIG.
Step S41: In the application process, if a “time setting request” occurs with the setting value Tvir as a parameter,
Step S42: The difference between the Tvir and the virtual timer reference value Tbasev is calculated to obtain the virtual timer relative value ΔTvir,
Step S43: ΔTvir is multiplied by 1 / α (clock conversion coefficient) (1 / α) to obtain an actual timer relative value ΔTreal,
Step S44: The ΔTreal is added to the actual timer reference value Tbase to obtain the actual timer value Treal,
Step S45: Set the Treal in the IO register (FIG. 1),
Step S46: The Treal is returned to the application that is the time setting request source.

  After all, the series of steps is as follows. Assuming that a comparison time setting request is generated in the application process, a virtual timer reference value Tbasev that is a virtual timer value at the base point with the update timing t0 of the virtual timer (v) closest to the setting request time point t1 as a base point; Based on the virtual timer relative value ΔTvir which is a difference (Tvir−Tbasev) from the virtual timer value Tvir at the setting request time point t1, and the reciprocal 1 / α of the clock conversion coefficient α, The timer value Treal is calculated and the actual timer value Treal is returned to the application process. In this case, the virtual timer relative value ΔTvir is multiplied by the inverse 1 / α of the clock conversion coefficient α to obtain the actual timer relative value ΔTreal, and the actual timer reference value Tbase is added to the actual timer relative value ΔTreal. An actual timer value Treal related to the setting request is obtained.

  As described above, the initialization process, the scheduled interrupt process, the read process (capture), and the write process (compare) have been described with reference to FIGS. 3 to 6. The parameters essential for any of these processes are the clock conversion coefficient. α. Therefore, it is convenient if the new clock frequency is set so that the clock conversion coefficient α is automatically reflected in all the above processes.

  That is, the clock conversion coefficient α is defined by the virtual clock frequency / real clock frequency from the real clock frequency (Hz) of the real timer TIM and the virtual clock frequency (Hz) of the virtual timer TIMv. The conversion coefficient α is held in a predetermined place. The various processes included in the application process (FIGS. 3 to 6) can use the clock conversion coefficient α as a common multiplier.

  In the above-described calculation formulas and the like, there is no problem in the case of floating-point arithmetic, but in the case of fixed-point arithmetic, the decimal part is truncated, so that the arithmetic accuracy may be lowered. Therefore, in order to ensure the calculation accuracy, a predetermined constant such as “256” is multiplied (8-bit left shift), and the required calculation such as the above-described calculation formula is performed. It is preferable to use an algorithm such as division (8-bit right shift).

  3 again in FIG. 3 to FIG. 6, in the normal processing in the timer interrupt processing, the value of Tint × α may not be an integer depending on the value of α, and a fraction may be generated. If such fractions are generated and accumulated at every scheduled interrupt, the accumulated error becomes unacceptable, and eventually the interrupt cannot be maintained for a certain time.

  Therefore, in the above-described normal processing in the timer interrupt processing, when a fraction occurs every time in the output set value of the constant interval Tint × α due to the value of the clock conversion coefficient α as described above, The fraction corresponding to n times is accumulated, and the accumulated value is added to the (n + 1) th output setting value. This makes it possible to always maintain the required constant interval time in the long run.

  FIG. 7 is a diagram illustrating the fraction processing of Tint × α in step S22 of FIG. In this figure, the fraction generated in each calculation from the first time to the nth time is rounded down every time. n is, for example, n = 10. Then, the fraction β accumulated for n times is added to the (n + 1) th calculated value as a correction value. Thereby, the above-mentioned cumulative error is periodically eliminated.

  3 to 6 again, with respect to the first step S41, the virtual timer is updated immediately before the compare time setting process, and the above-mentioned base point is changed to the latest update timing. It is preferable. In this comparison time setting process, it is desirable that the setting range has a sufficient margin so that one period of the periodic timing (A-A in FIG. 2) can be used to the maximum.

  Therefore, the real timer reference value Tbaser and the virtual timer reference value Tbasev are generated again immediately before the compare time setting, so that the compare time can be set in almost the entire range of the one cycle AA.

  3 again in FIG. 3 to FIG. 6, regarding the second step S42, in the setting of the compare time, it is defined in the real timer TIM corresponding to the maximum settable range defined in the virtual timer TIMv. The maximum settable range to be set is preferably changed according to the value of the clock conversion coefficient α. That is, the “guard” setting reflects the clock conversion coefficient α.

  In application processing, the time setting range is determined based on the value of the virtual timer used directly. The maximum settable range is up to the time ahead of one cycle (AA) of the virtual timer. However, since the settable range in the real timer changes depending on the value of the clock conversion coefficient α, the guard for the settable range in the real timer is newly set.

  In the above-described setting of the compare time, the set time may exceed the above maximum settable range. In such a case, the compare time setting process is suspended and only the setting request is stored. The setting request may be re-executed at the next periodic timing.

  That is, when setting the timer time value, if the set time exceeds the settable range, the setting process is temporarily suspended and only the setting request is stored. Then, in the next scheduled processing, the hold time is subtracted from the set time, and the stored setting request is re-executed, thereby enabling processing even with a value exceeding the settable range. If the re-execution still exceeds the settable range, the execution is once again suspended and re-executed in the next scheduled processing. This is repeated until the set time falls within the settable range.

  As described above in detail, according to the present invention, when the timer source is changed, the influence of the change of the timer source can be absorbed in software without changing the application at all.

It is a figure showing the timer adjustment mechanism concerning the present invention diagrammatically. FIG. 6 is a timing diagram that represents the adjustment process of the timer adjustment mechanism 20 in an analog manner. It is a flowchart showing the initialization processing operation. It is a flowchart showing a periodic interrupt processing and a periodic timing processing operation linked to this. It is a flowchart showing the reading process (capture) operation | movement at the time of reference. It is a flowchart showing the writing process (compare) operation | movement at the time of time setting. It is a figure showing the fraction process in step S22 of FIG. It is a figure which shows one structural example of a general microcomputer.

Explanation of symbols

1 Microcomputer (microcomputer)
2 Processing unit 3 Real-time pulse unit 4 External oscillator 11 CPU
12 ROM
13 RAM
15 Timer 16 Capture Function Unit 17 Compare Function Unit 20 Timer Adjustment Mechanism

Claims (10)

A microcomputer that executes application processing configured to operate based on a predetermined clock,
A processing unit that is driven by a first clock output from the oscillator and that executes application processing based on a second clock different from the first clock;
A timer for performing count processing based on the first clock, and a real timer for repeatedly executing count processing up to a predetermined number,
In the periodic interrupt process activated in the first cycle, the processing unit converts the count value of the real timer to the count value of the virtual timer corresponding to the second clock based on a predetermined clock conversion coefficient. Perform virtual timer conversion processing to convert,
The virtual timer conversion process performed in the periodic interrupt process is executed in a second cycle longer than the first cycle in which an overflow in which the count value of the real timer reaches the predetermined number does not occur twice or more. A microcomputer characterized by that.   The processing unit does not execute the virtual timer conversion process if the second period has not elapsed since the previous execution of the virtual timer conversion process when the periodic interrupt process is started. The microcomputer according to claim 1.   3. The microcomputer according to claim 1, wherein the first period and the second period are timed based on the second clock. Provided with a compare processing unit that activates a predetermined process when the set timer value matches the timer value counted by the real timer,
The periodic interrupt process is counted based on the first clock based on the first period converted from the second clock to correspond to the first clock, and a real timer. 3. The microcomputer according to claim 1, wherein the microcomputer is started at the timing when the timer value coincides with the timer value.   Each timer value, which is the count value of the real timer and the virtual timer, increases with a respective slope between the timer zero value and a constant timer upper limit value, and when the timer upper limit value is reached, the timer zero value again When repeating the timer operation such as returning to, the timer value of the real timer read periodically by the periodic interrupt process is used as the real timer reference value, and the virtual value is calculated based on the real timer reference value and the clock conversion coefficient. 3. The microcomputer according to claim 1, wherein the virtual timer is formed by calculating and updating a timer reference value. When a capture time reference request occurs in the application process,
Based on the update timing of the virtual timer that is closest to the reference time, the actual timer reference value that is the actual timer value at the reference point and the actual timer value that is acquired at the reference time is an actual difference. 6. The capture processing unit according to claim 5, further comprising: a capture processing unit that calculates a virtual timer value related to the reference request based on a timer relative value and the clock conversion coefficient and returns the virtual timer value to the application process. Microcomputer. When a compare time setting request occurs in the application process,
A virtual value that is a difference between the virtual timer reference value that is the virtual timer value at the base point and the virtual timer value at the setting request time point, based on the update timing of the virtual timer that is closest to the setting request time point The comparison processing unit according to claim 5, further comprising: a compare processing unit that calculates an actual timer value for the setting request based on a timer relative value and an inverse number of the clock conversion coefficient and returns the actual timer value to the application process. Microcomputer. A timer adjustment mechanism in a microcomputer in which application processing to be executed with a predetermined clock is executed with a clock of an actual timer different from the clock,
The timer adjustment mechanism converts the real timer into a virtual timer proportional to a predetermined clock conversion coefficient, and causes the application process to be executed with the converted clock of the virtual timer,
Both the timer values of the real timer and the virtual timer increase with respective gradients between the timer zero value and a constant timer upper limit value, and return to the timer zero value again when the timer upper limit value is reached. When repeating the timer operation, the timer value of the actual timer read periodically at regular timing is used as the actual timer reference value, and the virtual timer reference value is calculated based on the actual timer reference value and the clock conversion coefficient. And by forming the virtual timer,
When a compare time setting request occurs in the application process,
A virtual value that is a difference between the virtual timer reference value that is the virtual timer value at the base point and the virtual timer value at the setting request time point, based on the update timing of the virtual timer that is closest to the setting request time point Based on the timer relative value and the reciprocal of the clock conversion coefficient, the actual timer value for the setting request is calculated and the actual timer value is returned to the application process,
A microcomputer timer adjustment mechanism, wherein the virtual timer is updated immediately before the compare time setting process, and the base point is changed to the latest update timing. A timer adjustment mechanism in a microcomputer in which application processing to be executed with a predetermined clock is executed with a clock of an actual timer different from the clock,
The timer adjustment mechanism converts the real timer into a virtual timer proportional to a predetermined clock conversion coefficient, and causes the application process to be executed with the converted clock of the virtual timer,
Both the timer values of the real timer and the virtual timer increase with respective gradients between the timer zero value and a constant timer upper limit value, and return to the timer zero value again when the timer upper limit value is reached. When repeating the timer operation, the timer value of the actual timer read periodically at regular timing is used as the actual timer reference value, and the virtual timer reference value is calculated based on the actual timer reference value and the clock conversion coefficient. And by forming the virtual timer,
When a compare time setting request occurs in the application process,
A virtual value that is a difference between the virtual timer reference value that is the virtual timer value at the base point and the virtual timer value at the setting request time point, based on the update timing of the virtual timer that is closest to the setting request time point Based on the timer relative value and the reciprocal of the clock conversion coefficient, the actual timer value for the setting request is calculated and the actual timer value is returned to the application process,
In the setting of the compare time, the maximum settable range defined in the real timer corresponding to the maximum settable range defined in the virtual timer is changed according to the value of the clock conversion coefficient. Microcomputer timer adjustment mechanism.   In the setting of the compare time, when the set time exceeds the maximum settable range, the compare time setting process is suspended and only the setting request is stored, and the setting request is requested at the next periodic timing. 10. The timer adjustment mechanism for a microcomputer according to claim 9, wherein the timer is re-executed.

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