JP2014153860A - Multi-thread processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-thread processor capable of preventing the program execution speed from decreasing when a thread operates with an authority other than a user authority.SOLUTION: In a multi-thread processor, each thread operates with a user authority or an authority other than the user authority, for each cycle. A thread scheduler 160 switches between threads for execution, for each cycle. A schedule adjustment unit 192 sets a thread that is to be executed in a second period other than a first period in which a thread to be executed by an operating system or hypervisor is set. The schedule adjustment unit 192 performs adjustment so that a thread which operated with the authority other than the user authority is to be supplementally executed in the second period.

Description

  The present invention relates to a multi-thread processor, and more particularly to a multi-thread processor in which each thread operates with user authority or authority other than user authority every cycle.

  In a computer system such as a control system that requires high reliability and real-time performance, a device is prepared for each required function, and a plurality of these devices operate together to constitute one system. In recent years, a technique is known in which a plurality of functions are integrated and executed by a single processor.

  For example, a multi-thread processing device disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2011-128767) monitors a processing load of each thread and a bandwidth setting unit that sets a bandwidth that is an operation ratio of the thread for a plurality of threads And a bandwidth control means for instructing the bandwidth setting means to change the bandwidth so that the processing load of each thread is leveled.

  The multi-thread execution device of Patent Document 2 (Japanese Patent Laid-Open No. 2010-286898) stores target instruction execution speed information for each program and monitors the instruction execution completion speed. The feedback control means causes the instruction issuing means to issue an instruction so that the execution completion speed substantially matches the target execution speed information.

JP 2011-128767 A JP 2010-286898 A

  Each program operating in a multi-thread environment is assigned to a corresponding thread. Each thread is assigned an execution cycle in consideration of the priority of the corresponding program.

  However, by calling a supervisor or hypervisor from a program operating in a thread, the supervisor or hypervisor consumes an execution cycle assigned to the thread. As a result, the number of cycles in which the program operates is reduced by the number of cycles operated with supervisor authority or hypervisor authority other than user authority. Therefore, there is a problem that the execution speed of the program decreases.

  Therefore, an object of the present invention is to provide a multi-thread processor that can prevent a decrease in the execution speed of a program when a thread operates with an authority other than a user authority.

  In order to solve the above problems, a multi-thread processor of the present invention is a multi-thread processor in which each thread operates with user authority or authority other than user authority every cycle, and a scheduler that switches threads to be executed in units of cycles. A schedule adjusting unit that sets a thread to be executed in a second period other than the first period in which a thread to be executed by the operating system or the hypervisor is set. The schedule adjustment unit adjusts the thread that has been operated with an authority other than the user authority to be supplementarily executed in the second period.

  According to the multi-thread processor of the present invention, it is possible to prevent the execution speed of a program from being lowered when a thread operates with an authority other than the user authority.

It is an example of schematic structure of the multithread processor of 1st Embodiment. It is a figure showing the example of a schedule table. It is a figure showing the example of an execution cycle number table. It is a flowchart which shows the operation | movement procedure in each cycle of an execution cycle number addition part. It is a flowchart which shows the operation | movement procedure for every schedule update period of the schedule adjustment part of 1st Embodiment. It is a figure for demonstrating the 1st example of the schedule adjustment in 1st Embodiment. It is a figure for demonstrating the 2nd example of the schedule adjustment in 1st Embodiment. It is an example of schematic structure of the multithread processor of 2nd Embodiment. It is a figure showing the example of an adjustment management table. It is a flowchart which shows the operation | movement procedure for every schedule update period of the schedule adjustment part of 2nd Embodiment. It is a flowchart which shows the operation | movement procedure for every schedule update period of the schedule adjustment part of 2nd Embodiment. It is a flowchart which shows the operation | movement procedure for every schedule update period of the schedule adjustment part of 2nd Embodiment. It is a figure for demonstrating the example of the schedule adjustment in 2nd Embodiment. (A) And (b) is a figure showing another example of a schedule table.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is an example of a schematic configuration of the multithread processor according to the first embodiment.

  As shown in FIG. 1, the multi-thread processor includes an instruction bus 100, a main storage unit 101, a zeroth instruction buffer 110, a first instruction buffer 111, an instruction fetch unit 145, a selector 120, and a decoder 130. An execution unit 140, a thread scheduler 160, a schedule register 180, a schedule adjustment unit 192, an execution cycle number addition unit 190, an execution cycle number table storage unit 191, a data bus 170, and a main storage unit 102. , 0th register set 150, first register set 151, selector 121, and selector 122.

  The multi-thread processor according to the present embodiment has a multi-thread execution environment including thread 0 and thread 1. In this multi-thread processor, each thread operates with a user authority or an authority other than the user authority every cycle.

  In a multi-thread execution environment, a plurality of threads share a part of hardware for processing. Here, a thread refers to a virtual processing entity that performs processing while partially sharing hardware. In the present embodiment, the 0th instruction buffer 110 and the 0th register set 150 are used in the thread 0, and the first instruction buffer 111 and the first register set 151 are used in the thread 1. Other components in the processor are shared between thread 0 and thread 1.

  For each cycle, which is the minimum unit in which the processor performs basic operations, thread 0 or thread 1 is sequentially selected as an execution thread. Hereinafter, the execution thread refers to a thread that is executing a process. Switching of execution threads is controlled by the thread scheduler 160.

  The instruction bus 100 is a bus through which instruction data is transmitted between connected circuits. The data bus 170 is a bus through which data is transmitted between connected circuits.

  The main storage unit 101 is connected to the instruction bus 100. The main storage unit 101 holds a program A, a program B, an OS_A used by the program A, an OS_B used by the program B, and a hypervisor that is software for protecting and arbitrating between the OS_A and the OS_B. . The main storage unit 101 is, for example, an FD (Floppy Disk), an HDD (Hard Disk Drive), a ROM (Read Only Memory), a RAM (Random Access Memory), a CD (Compact Disk), a DVD (Digital Versatile Disk), or the like. .

The thread 0 executes the user program A, OS_A, or hypervisor.
The thread 1 executes a user program B, OS_B, or a hypervisor.

  When the thread 0 executes the user program A, the execution unit 140 sets “user authority” as the authority information of the thread 0 in the 0th register set 150, and the thread 0 operates with “user authority”. When the thread 0 executes the function (service) of OS_A, the execution unit 140 sets “supervisor authority” as the authority information of the thread 0 in the 0th register set 150, and the thread 0 operates with “supervisor authority”. When the thread 0 executes the hypervisor, the execution unit 140 sets “hypervisor authority” as authority information of the thread 0 in the 0th register set 150, and the thread 0 operates with “hypervisor authority”.

  Similarly, when the thread 1 executes the user program B, the execution unit 140 sets “user authority” as the authority information of the thread 1 in the first register set 151, and the thread 1 operates with “user authority”. To do. When the thread 1 executes the function (service) of OS_B, the execution unit 140 sets “supervisor authority” as the authority information of the thread 1 in the first register set 151, and the thread 1 operates with “supervisor authority”. When the thread 1 executes the hypervisor, the execution unit 140 sets “hypervisor authority” as the authority information of the thread 1 in the first register set 151, and the thread 1 operates with “hypervisor authority”.

  The main storage unit 102 is connected to the data bus 170. The main storage unit 102 holds data used by the programs A and B. The main storage unit 102 is, for example, an FD, HDD, RAM, or the like. The main storage unit 101 and the main storage unit 102 may be the same main storage unit. Further, there may be a main storage unit 101 and a main storage unit 102 for program A and program B, respectively.

  The 0th instruction buffer 110 and the first instruction buffer 111 are each connected to the instruction bus 100. The instruction bus 100 is connected to the main storage unit 101.

  The instruction fetch unit 145 has a program counter for the 0th instruction buffer 110 and a program counter for the first instruction buffer 111. The execution unit 140 outputs the address of the program counter of the 0th instruction buffer 110 to the instruction bus 100 and reads the instructions of the program A from the main storage unit 101 to the 0th instruction buffer 110 one by one. The instruction fetch unit 145 outputs the address of the program counter of the first instruction buffer 111 to the instruction bus 100 and reads the instructions of the program B from the main storage unit 101 to the first instruction buffer 111 one by one.

  The 0th instruction buffer 110 and the first instruction buffer 111 are connected to the selector 120. The selector 120 selects one instruction buffer out of the 0th instruction buffer 110 and the first instruction buffer 111 and connects the selected instruction buffer to the decoder 130. The instruction buffer selected by the selector 120 is controlled by the thread scheduler 160.

  The decoder 130 decodes the instruction in the 0th instruction buffer 110 or the first instruction buffer 111 output from the selector 120 and sends the decoding result to the execution unit 140.

  The zeroth register set 150 includes a plurality of general-purpose registers, system registers (including authority information), and the like. The first register set 151 includes a plurality of general-purpose registers, system registers (including authority information), and the like.

  The selector 121 selects the 0th register set 150 or the first register set 151 and sends the data of the selected register set to the execution unit 140. The selector 122 selects the 0th register set 150 or the first register set 151 and sends data representing the execution result by the execution unit 140 to the selected register set.

  The execution unit 140 executes the decoded instruction sent from the decoder 130. The execution unit 140 performs an operation on the data stored in the 0th register set 150 or the first register set 151 according to the type of operation. The contents of the operation are addition, multiplication, division, load, store, branch, or the like, and the execution unit 140 includes a circuit corresponding to each operation. In the case of load (or store), an address is output from the execution unit 140 to the data bus 170 and data is read (or written) from the main storage unit 102. The read data is stored in the 0th register set 150 or the first register set 151. The register set used by the execution unit 140 is selected by the selectors 121 and 122. The selectors 121 and 122 are controlled by the thread scheduler 160.

  The schedule register 180 stores a schedule table 200 as shown in FIG. Each entry in the schedule table 200 is assigned a number and a thread number to be executed. The schedule table 200 has 15 entries, and defines threads to be executed for 15 cycles.

  The schedule table 200 includes a core schedule table 201 including the 0th to 9th entries and a compensation schedule table 202 including the 10th to 14th entries.

  The core schedule table 201 defines threads to be executed during the core period. The core schedule table 201 is set by an OS or a hypervisor other than the schedule adjustment unit 192. For example, when the execution unit 140 executes a hypervisor that determines the execution order and execution ratio of the thread 0 and the thread 1, the thread number of each entry in the core schedule table 201 is set after executing the 14th entry thread. .

  The compensation schedule table 202 defines threads to be executed during the compensation period. The compensation schedule table 202 is set by the schedule adjustment unit 192 for each schedule update period. In the present embodiment, the schedule update period is 15 cycles.

  The thread scheduler 160 reads one entry of the schedule table 200 every cycle. The thread scheduler 160 reads the entries in order from the entry with the number 0, and when reading the last entry, reads the entries in the order from the entry with the number 0 again (denoted as circulating).

  The thread scheduler 160 switches and executes each thread for each cycle in the order set in the schedule register 180. Thereby, although it is physically one processor, it behaves like having a plurality of virtual processors. The “cycle” here may be one instruction, one group of instructions, or a fixed time.

  When the thread number set in the read entry is “0”, the thread scheduler 160 causes the selector 120 to select the instruction output from the zeroth instruction buffer 110 and causes the selector 121 to select from the zeroth register set 150. Data reading is selected, and the selector 122 is selected to write data to the zeroth register set 150.

  When the thread number set in the read entry is “1”, the thread scheduler 160 causes the selector 120 to select the output of the instruction from the first instruction buffer 111 and causes the selector 121 to select from the first register set 151. Data reading is selected, and the selector 122 is selected to write data to the first register set 151.

  If a thread number that does not exist in the read entry is set, the thread scheduler 160 does not cause the selector 120 to select any instruction from the 0th instruction buffer 110 and the first instruction buffer 111, No instruction is executed (NOP (no operation) instruction is executed).

  The execution cycle number table storage unit 191 has an execution cycle number table 300 as shown in FIG. A column 301 of the execution cycle number table 300 indicates the authority of the thread according to the present embodiment. The thread 0 and the thread 1 of the present embodiment have “hypervisor authority”, “supervisor authority”, or “user authority”. As illustrated in FIG. 3, the column 302 of the execution cycle number table 300 is a column that stores the number of execution cycles for the thread 0. The column 303 of the execution cycle number table 300 is a column that stores the number of execution cycles for the thread 1. A row 311 of the execution cycle number table 300 is a row for storing the number of execution cycles of the user authority of the thread 0 and the thread 1. The row 312 of the execution cycle number table 300 is a row for storing the number of execution cycles of the supervisor authority of the thread 0 and the thread 1. The row 313 of the execution cycle number table 300 is a row for storing the number of execution cycles of the hypervisor authority of the thread 0 and thread 1.

  The execution cycle number adding unit 190 cooperates with the thread scheduler 160 to record the number of execution cycles of the hypervisor executed in each thread in the execution cycle number table storage unit 191.

(Operation of the execution cycle number adding unit 190)
FIG. 4 is a flowchart showing an operation procedure in each cycle of the execution cycle number adding unit 190. In the initial state, the number of execution cycles stored in the execution cycle number table storage unit 191 is all “0”.

  The execution cycle number adding unit 190 acquires the thread number being executed from the thread scheduler 160 (step S100).

  Next, when the executing thread is the thread 0 (YES in step S101), the execution cycle number adding unit 190 acquires the authority information of the thread 0 from the 0th register set 150 (step S102).

  Next, the execution cycle number adding unit 190 adds “1” to the execution cycle number of the authority acquired by the thread 0 in the execution cycle number table 300 stored in the execution cycle number table storage unit 191. For example, when the acquired authority is a hypervisor authority, the execution cycle number adding unit 190 adds “1” to the execution cycle number recorded in the row 313 of the column 302 of the execution cycle number table 300 (step S103). ).

  Next, when the executing thread is not thread 0 (NO in step S101), the execution cycle number adding unit 190 acquires the authority information of the thread 1 from the first register set 151 (step S104).

  Next, the execution cycle number adding unit 190 adds “1” to the execution cycle number of the authority acquired by the thread 1 in the execution cycle number table 300 stored in the execution cycle number table storage unit 191. For example, when the acquired authority is a hypervisor authority, the execution cycle number adding unit 190 adds “1” to the execution cycle number recorded in the row 313 of the column 303 of the execution cycle number table 300 (step S105). ).

(Operation of schedule adjustment unit 192)
The schedule adjustment unit 192 changes the compensation schedule table 202 of the schedule table 200 for each schedule update period based on the number of execution cycles of hypervisor authority for each thread in the execution cycle number table 300 in cooperation with the thread scheduler 160. To do. As a result, the schedule adjustment unit 192 performs adjustment so that a thread that operates with a user authority such as a hypervisor authority is supplementarily executed in a later compensation period.

  FIG. 5 is a flowchart illustrating an operation procedure for each schedule update period of the schedule adjustment unit 192 according to the first embodiment.

  First, the schedule adjustment unit 192 acquires the execution cycle number n0 of the hypervisor authority of the thread 0 from the execution cycle number table storage unit 191. Specifically, the schedule adjustment unit 192 acquires the execution cycle number n0 recorded in the column 302 and the row 313 of the execution cycle number table 300 (step S200).

  Next, the schedule adjustment unit 192 acquires the execution cycle number n1 of the hypervisor authority of the thread 1 from the execution cycle number table storage unit 191. Specifically, the schedule adjustment unit 192 acquires the number of execution cycles n1 recorded in the column 303 and the row 313 of the execution cycle number table 300 (step S201).

  Next, the schedule adjustment unit 192 obtains the sum N (= n0 + n1) of the number of execution cycles n0 acquired in step S200 and the number of execution cycles n1 acquired in step S201 (step S202).

  Next, the schedule adjustment unit 192 determines whether the obtained sum N is equal to or less than the number of entries M in the compensation schedule table 202.

  If the result of the determination is equal or less (YES in step S203), the process proceeds to step S204. As a result of the determination, if there are many (NO in step S203), the process proceeds to step S220.

  If YES in step S203, the schedule adjustment unit 192 sets “0” to the n0 execution cycle entries acquired in step S200 starting from the tenth entry in the compensation schedule table 202 (step S204). Further, the schedule adjustment unit 192 sets the execution cycle number of the hypervisor authority of the thread 0 in the execution cycle number table 300 recorded in the execution cycle number table storage unit 191 to zero. Specifically, the schedule adjustment unit 192 sets the number of execution cycles in column 302 and row 313 of the execution cycle number table 300 to 0 (step S205).

  Next, the schedule adjustment unit 192 adds “1” to the n1 execution cycle entries acquired in step S201 starting from the entry immediately after the last entry to which “0” is added in step S204 in the compensation schedule table 202. "Is set (step S206). Further, the schedule adjustment unit 192 sets the execution cycle number of the hypervisor authority of the thread 1 in the execution cycle number table 300 stored in the execution cycle number table storage unit 191 to 0. Specifically, the schedule adjustment unit 192 sets the number of execution cycles in the column 303 and the row 313 of the execution cycle number table 300 to 0 (step S207).

  Next, when there are remaining entries in the supplementary schedule table 202, the schedule adjustment unit 192 starts from the entry immediately after the last entry added with “1” in step S206 as the last entry (fourteenth entry). ) Until "-1" is set (step S208).

  If NO in step S203, the schedule adjustment unit 192 calculates a ratio R (= M / N) between the number of entries M in the supplementary schedule table 202 and the total number N of execution cycles obtained in step S202 (step S202). S220).

  Next, based on the ratio R, the schedule adjustment unit 192 calculates a corrected execution cycle number n0 ′ (= n0 × R) obtained by correcting the execution cycle number n0 of the hypervisor authority of the thread 0. In this calculation, the decimal part is rounded down (step S221).

  Next, the schedule adjustment unit 192 calculates a corrected execution cycle number n1 ′ (= n1 × R) obtained by correcting the execution cycle number n1 of the hypervisor authority of the thread 1 based on the ratio R. In this calculation, the decimal part is rounded down (step S222).

  Next, the schedule adjustment unit 192 sets “0” to the entry of the number of correction execution cycles n0 ′ calculated in step S221 starting from the entry 10 of the compensation schedule table 202 (step S223). Further, the schedule adjustment unit 192 reduces the execution cycle number of the hypervisor authority of the thread 0 in the execution cycle number table 300 stored in the execution cycle number table storage unit 191 by the corrected execution cycle number n0 ′. Specifically, the schedule adjustment unit 192 subtracts the modified execution cycle number n0 ′ from the execution cycle number in the column 302 and row 313 of the execution cycle number table 300, and overwrites it with the subtracted value (step S224).

  Next, the schedule adjustment unit 192 sets the number of correction execution cycles n1 ′ acquired in step S222 as the starting point from the entry immediately after the last entry to which “0” is added in step S223 in the compensation schedule table 202. “1” is set (step S225). Furthermore, the schedule adjustment unit 192 reduces the execution cycle number of the hypervisor authority of the thread 1 in the execution cycle number table 300 stored in the execution cycle number table storage unit 191 by the corrected execution cycle number n1 ′. Specifically, the schedule adjustment unit 192 subtracts the corrected execution cycle number n1 ′ from the execution cycle number in the column 303 and the row 313 of the execution cycle number table 300, and overwrites it with the subtracted value (step S226).

  Next, when there is a remaining entry in the supplementary schedule table 202, that is, the schedule adjustment unit 192, that is, the entry immediately after the last entry added with “1” in step S226 starts as the last entry (entry 14). ) Until "-1" is set (step S227).

(First example of schedule adjustment)
FIG. 6 is a diagram for explaining a first example of schedule adjustment in the first embodiment.

It is assumed that the number of execution cycles n0 of the thread 0 acquired in step S200 is “0”.
The number of execution cycles n1 of the thread 1 acquired in step S201 is “3”.

  In step S202, the sum N is "3". As a result, in step S203, N ≦ M (= 5), and the process proceeds to step S204.

  In step S204, n0 is “0”, and “0” is not set in the compensation schedule table 202.

  In step S205, when n0 is “0”, the number of execution cycles of the hypervisor authority of thread 0 remains “0”.

  In step S206, “1” is set in “3” entries (tenth, eleventh, and twelfth entries) of n1 in the compensation schedule table 202 because n1 is “3”.

  In step S207, n1 is set to “3”, and the number of execution cycles of the hypervisor authority of thread 1 is set to “0”.

  In step S <b> 208, “−1” is set in the thirteenth to fourteenth entries, which are the remaining entries in the compensation schedule table 202.

(Second example of schedule adjustment)
FIG. 7 is a diagram for explaining a second example of schedule adjustment in the first embodiment.

The number of execution cycles n0 of the thread 0 acquired in step S200 is “4”.
The number of execution cycles n1 of the thread 1 acquired in step S201 is “3”.

  In step S202, the sum N is "7". As a result, in step S203, N> M (= 5), and the process proceeds to step S220.

In step S220, R = 5/7.
In step S221, since the integer part of 4 × 5/7 is 2, n0 ′ is “2”.

In step S222, since the integer part of 3 × 5/7 is 2, n1 ′ is “2”.
In step S223, “0” is set in “2” entries (tenth and eleventh entries) of the supplementary schedule table 202 because n0 ′ is “2”.

  In step S224, n0 ′ is set to “2”, and the number of execution cycles of the hypervisor authority of thread 0 is set to “2” which is smaller from “4” to “2”.

  In step S225, n1 'is "2", and "1" is set to "2" entries (twelfth and thirteenth entries) in the supplementary schedule table 202.

  In step S226, n1 ′ is set to “2”, and the number of execution cycles of the hypervisor authority of thread 1 is set to “1” which is smaller by “2” from “3”.

  In step S227, “−1” is set in the fourteenth entry, which is the remaining entry in the compensation schedule table 202.

  As described above, in this embodiment, the number of execution cycles in which the hypervisor operates with the hypervisor authority is recorded for each thread, and each thread has the recorded number of execution cycles of the hyper authority in the compensation period. It will be executed for the corresponding number of cycles.

  As a result, the execution of the number of cycles that the program originally intended to operate is compensated, and the processing time allocated to the program can be maintained.

  In the present embodiment, the thread to be set in the compensation schedule table 202 is determined based on the number of execution cycles of the hypervisor authority for each thread in the execution cycle number table 300. However, the present invention is not limited to this. For example, the execution cycle number of the hyper authority is calculated using the execution cycle number of the user authority and the supervisor authority for each thread in the execution cycle number table 300, and the compensation schedule is calculated based on the calculated execution cycle number of the hyper authority. A thread to be set in the table 202 may be determined.

[Modification of First Embodiment]
In the first embodiment, the thread to be set in the compensation schedule table 202 is determined based on the number of execution cycles of the hypervisor authority for each thread in the execution cycle number table 300. However, the present invention is not limited to this. The thread for setting the supplementary schedule table 202 may be determined based on the number of execution cycles of supervisor authority for each thread in the execution cycle number table 300.

  Further, the thread for setting the compensation schedule table 202 may be determined based on the sum of the number of execution cycles of supervisor authority and the number of execution cycles of hypervisor authority for each thread in the execution cycle number table 300.

[Second Embodiment]
In the first embodiment, the number of operation cycles of the hypervisor is added as the number of threads. In the present embodiment, the number of cycles to be added is further changed according to the priority of the thread and the additional upper limit value.

FIG. 8 is an example of a schematic configuration of the multithread processor according to the second embodiment.
The multi-thread processor of the second embodiment is different from the multi-thread processor of the first embodiment in that the multi-thread processor of the second embodiment has an adjustment management table storage unit 600, and second The schedule adjustment unit 592 of the embodiment is different in function from the schedule adjustment unit 192 of the first embodiment.

The adjustment management table storage unit 600 stores an adjustment management table 593 as shown in FIG.
A column 601 of the adjustment management table 593 indicates the type of data used by the schedule adjustment unit 592. “Priority” is the priority of thread 0. The higher the priority value, the higher the priority (the higher the priority). The “upper limit cycle number” is an upper limit of the number of slots to be allocated when the hypervisor operates in a thread. The reason why the “upper limit cycle number” is set for each thread is that only the high priority threads are set in the supplementary schedule table 202 to prevent the low priority threads from being executed in the supplementary period. Because.

  The column 602 of the adjustment management table 593 is a column for storing the priority for thread 0 and the upper limit cycle number, and the column 603 of the adjustment management table 593 is a column for storing the priority for thread 1 and the upper limit cycle number. .

  The row 611 of the adjustment management table 593 is a row for storing the priorities of the thread 0 and the thread 1. A row 612 of the adjustment management table 593 is a row for storing the upper limit cycle numbers of the thread 0 and the thread 1.

(Operation of schedule adjustment unit 592)
The schedule adjustment unit 592 cooperates with the thread scheduler 160 based on the execution cycle number of the hypervisor authority for each thread in the execution cycle number table 300 and the upper limit cycle number and priority for each thread in the adjustment management table 593. The supplementary schedule table 202 of the schedule table 200 is changed every thread update cycle.

  10 to 12 are flowcharts illustrating an operation procedure for each schedule update period of the schedule adjustment unit 592 according to the second embodiment.

  First, the schedule adjustment unit 592 acquires the execution cycle number n0 of the hypervisor authority of the thread 0 from the execution cycle number table 300 of the execution cycle number table storage unit 191. Specifically, the schedule adjustment unit 592 acquires the execution cycle number n0 stored in the column 302 and the row 313 of the execution cycle number table 300 (step S500).

  Next, the schedule adjustment unit 592 acquires the execution cycle number n1 of the hypervisor authority of the thread 1 from the execution cycle number table 300 of the execution cycle number table storage unit 191. Specifically, the schedule adjustment unit 592 acquires the number of execution cycles n1 stored in the column 303 and the row 313 of the execution cycle number table 300 (Step S501).

  Next, the schedule adjustment unit 592 acquires the upper limit cycle number of the thread 0 from the adjustment management table 593. Specifically, the schedule adjustment unit 592 acquires the upper limit cycle number u0 stored in the column 602 and the row 612 of the adjustment management table 593 (step S502).

  The schedule adjustment unit 592 determines the smaller of the execution cycle number n0 acquired in step S500 and the upper limit cycle number u0 acquired in step S502 as the request cycle number s0 (step S503).

  Next, the schedule adjustment unit 592 acquires the upper limit cycle number of the thread 1 from the adjustment management table 593. Specifically, the schedule adjustment unit 592 acquires the upper limit cycle number u1 stored in the column 603 and the row 612 of the adjustment management table 593 (step S504).

  The schedule adjustment unit 592 determines the smaller of the number of execution cycles n1 acquired in step S501 and the upper limit number of cycles u1 acquired in step S504 as the request cycle number s1 (step S505).

  Next, the schedule adjustment unit 592 obtains the sum S (= s0 + s1) of the request cycle number s0 determined in step S503 and the request cycle number s1 determined in step S505 (step S506).

  Next, the schedule adjustment unit 192 determines whether the obtained total sum S is equal to or less than the number of entries M in the compensation schedule table 202.

  As a result of the determination, if equal or less (YES in step S507), the process proceeds to step S510. As a result of the determination, if there are many (NO in step S507), the process proceeds to step S520.

  If YES in step S507, the schedule adjustment unit 592 sets “0” to the entry of the number of request cycles s0 determined in step S503 starting from the tenth entry of the supplementary schedule table 202 (step S510). Further, the schedule adjustment unit 592 reduces the execution cycle number of the hypervisor authority of the thread 0 in the execution cycle number table 300 stored in the execution cycle number table storage unit 191 by the request cycle number s0. Specifically, the schedule adjustment unit 592 subtracts only the request cycle number s0 from the execution cycle number in the column 302 and row 313 of the execution cycle number table 300, and overwrites it with the subtracted value (step S511).

  Next, the schedule adjustment unit 592 adds “1” to the entry of the request cycle number s1 determined in step S505 starting from the entry immediately after the last entry to which “0” is added in step S510 in the compensation schedule table 202. Is set (step S512). Further, the schedule adjustment unit 592 reduces the execution cycle number of the hypervisor authority of the thread 1 in the execution cycle number table 300 stored in the execution cycle number table storage unit 191 by the request cycle number s1. Specifically, the schedule adjustment unit 592 subtracts only the request cycle number s1 from the execution cycle number in the column 303 and row 313 of the execution cycle number table 300, and overwrites it with the subtracted value (step S513).

  Next, when there is a remaining entry in the compensation schedule table 202, the schedule adjustment unit 592 starts from the entry immediately after the last entry to which “1” is added in step S512 as the last entry (14th entry). "-1" is set up to (entry) (step S514).

  If NO in step S507, the schedule adjustment unit 592 acquires the priority of the thread 0 from the adjustment management table 593. Specifically, the schedule adjustment unit 592 acquires the priority of the thread 0 stored in the column 602 and the row 611 of the adjustment management table 593 (Step S520).

  Next, the schedule adjustment unit 592 acquires the priority of the thread 1 from the adjustment management table 593. Specifically, the schedule adjustment unit 592 acquires the priority of the thread 1 stored in the column 603 and the row 611 of the adjustment management table 593 (step S521).

  The schedule adjustment unit 592 compares the priority of the thread 0 and the priority of the thread 1, and if the priority of the thread 0 is equal to or higher than the priority of the thread 1 (YES in step S522), the process proceeds to step S530. If the priority of thread 0 is lower than the priority of thread 1 (NO in step S522), the process proceeds to step S540.

  In the case of YES in step S522, the schedule adjustment unit 592 sets the smaller of the entry number M and the request cycle number s0 in the compensation schedule table 202 to the request cycle possible number p0 (step S530).

  The schedule adjustment unit 592 sets “0” to the entries for the required number of possible cycles p0 determined in step S530 starting from the tenth entry of the supplementary schedule table 202 (step S531). Further, the schedule adjustment unit 592 reduces the execution cycle number of the hypervisor authority of the thread 0 of the execution cycle number table 300 stored in the execution cycle number table storage unit 191 by the request cycle possible number p0. Specifically, the schedule adjustment unit 592 subtracts only the request cycle possible number p0 from the number of execution cycles in the column 302 and the row 313 of the execution cycle number table 300, and overwrites it with the subtracted value (step S532).

  The schedule adjustment unit 592 determines whether or not there is an unset entry in the compensation schedule table 202 in the current update cycle. If there is an unset entry (YES in step S533), the process proceeds to step S534. If there is no unset entry (NO in step S533), the process ends.

  If YES in step S533, the schedule adjustment unit 592 determines the smaller of the number MU of unset entries and the request cycle number s1 as the request cycle possible number p1 (step S534).

  The schedule adjustment unit 592 sets “1” to the entry of the request cycle possible number p1 determined in step S534 starting from the entry immediately after the last entry to which “0” is added in step S531 of the compensation schedule table 202. Setting is made (step S535). Further, the schedule adjustment unit 592 reduces the execution cycle number of the hypervisor authority of the thread 1 of the execution cycle number table 300 stored in the execution cycle number table storage unit 191 by the request cycle possible number p1. Specifically, the schedule adjustment unit 592 subtracts only the request cycle possible number p1 from the number of execution cycles in the column 303 and row 313 of the execution cycle number table 300, and overwrites it with the subtracted value (step S536).

  Next, when there are remaining entries in the supplementary schedule table 202, the schedule adjustment unit 592 starts from the entry immediately after the last entry to which “1” is added in step S537 as the last entry (14th entry). "-1" is set up to (entry) (step S537).

  In the case of NO in step S522, the schedule adjustment unit 592 determines the smaller of the entry number M and the request cycle number s1 in the compensation schedule table 202 as the request cycle possible number p1 (step S540).

  The schedule adjustment unit 592 sets “1” to the entry of the request cycle possible number p1 determined in step S540 starting from the tenth entry of the compensation schedule table 202 (step S541). Further, the schedule adjustment unit 592 reduces the execution cycle number of the hypervisor authority of the thread 1 of the execution cycle number table 300 stored in the execution cycle number table storage unit 191 by the request cycle possible number p1. Specifically, the schedule adjustment unit 592 subtracts only the request cycle possible number p1 from the execution cycle number in the column 303 and the row 313 of the execution cycle number table 300, and overwrites it with the subtracted value (step S542).

  The schedule adjustment unit 592 determines whether or not there is an unset entry in the compensation schedule table 202 in the current update cycle. If there is an unset entry (YES in step S543), the process proceeds to step S544. If there is no unset entry (NO in step S543), the process ends.

  If YES in step S543, the schedule adjustment unit 592 determines the smaller of the number MU of unset entries and the request cycle number s0 as the request cycle possible number p0 (step S544).

  The schedule adjustment unit 592 sets “0” to the p0 requested cycle possible entries determined in step S544 starting from the entry immediately after the last entry to which “0” is added in step S541 of the supplementary schedule table 202. It sets (step S545). Further, the schedule adjustment unit 592 reduces the execution cycle number of the hypervisor authority of the thread 0 of the execution cycle number table 300 stored in the execution cycle number table storage unit 191 by the request cycle possible number p0. Specifically, the schedule adjustment unit 592 subtracts only the request cycle possible number p0 from the execution cycle number in the column 302 and row 313 of the execution cycle number table 300, and overwrites it with the subtracted value (step S546).

Next, when there are remaining entries in the supplementary schedule table 202, the schedule adjustment unit 592 starts from the entry immediately after the last entry to which “0” is added in step S547 as the last entry (14th entry). "-1" is set up to (entry) (step S547).
(Example of schedule adjustment)
FIG. 13 is a diagram for explaining an example of schedule adjustment in the second embodiment.

The number of execution cycles n0 of the thread 0 acquired in step S500 is “5”.
The number of execution cycles n1 of the thread 1 acquired in step S501 is “2”.

It is assumed that the upper limit cycle number u0 of the thread 0 acquired in step S502 is “4”.
In step S503, since n0> u0, the required cycle number s0 is “4”.

The upper limit cycle number u1 of the thread 1 acquired in step S504 is “2”.
In step S505, since n1 = u1, the required cycle number s1 is “2”.

In step S506, the sum S of s0 and s1 is “6”.
In step S507, S> M (= 5), and the process proceeds to step S520.

The priority of the thread 0 acquired in step S520 is set to “100”.
The priority of the thread 1 acquired in step S521 is set to “40”.

  In step S522, the process proceeds to step S530 depending on the priority of thread 0> priority of thread 1.

In step S530, the required number of possible cycles p0 becomes “4” due to s0 <M.
In step S531, “4” entries (tenth to thirteenth entries) in the compensation schedule table 202 are set to “0”.

  In step S532, the number of execution cycles of the hypervisor authority of thread 0 is set to “1” which is smaller by “4” than “5”.

  In step S533, since there is an unset entry (14th entry), the process proceeds to step S534.

  In step S534, since the number of unset entries MU is “1”, the request cycle possible number p1 becomes “1” because s1> MU.

  In step S535, “1” entries (14th entry) in the compensation schedule table 202 are set to “1”.

  In step S536, the number of execution cycles of the hypervisor authority of thread 1 is set to “1” which is smaller from “2” by “1”.

  In step S537, since there are no remaining entries in the compensation schedule table 202, “−1” is not set.

  As described above, in this embodiment, for each thread, the number of execution cycles in which the hypervisor operates with the hypervisor authority is recorded, and in the compensation period, each thread records the number of execution cycles of the recorded hyper authority, Only the number of cycles corresponding to the priority and the upper limit number of cycles is executed.

As a result, as in the first embodiment, the execution of the number of cycles that the program was originally supposed to operate is compensated for, and the processing time allocated to the program can be maintained. Furthermore, in this embodiment, the deadline of a program with a high priority can be protected by making up for the programs in order of priority of programs operating on threads. Further, in this embodiment, since an upper limit value can be set for the number of threads to be compensated, even a low priority program can be compensated, and the program time constraint cannot be observed (deadline miss). It becomes difficult to occur.
(Modification of the first and second embodiments)
The number of entries in the schedule table 200, the core schedule table 201, and the compensation schedule table 202 is not limited to that shown in FIG. 2, and any number is possible.

  Further, the entries included in the core schedule table 201 and the supplementary schedule table 202 are not limited to those shown in FIG. 2, but may be those shown in FIGS. 14 (a) and 14 (b). .

  As shown in FIG. 14A, the schedule table 230 includes a core schedule table 231 including the fifth to fourteenth entries and a compensation schedule table 232 including the zeroth to fourth entries.

  As shown in FIG. 14B, the schedule table 240 includes a core schedule table 241 including entries 0, 1, 3, 4, 6, 7, 9, 10, 12, 13 and second, second, And a supplementary schedule table 242 including fifth, eighth, eleventh and fourteenth entries.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  100 instruction bus, 101, 102 main storage unit, 110 0th instruction buffer, 111 1st instruction buffer, 120, 121, 122 selector, 130 decoder, 140 execution unit, 145 instruction fetch unit, 150 0th register set, 151 1st 1 register set, 160 thread scheduler, 170 data bus, 180 schedule register, 190 execution cycle number addition unit, 191 execution cycle number table storage unit, 192, 592 schedule adjustment unit, 200, 230, 240 schedule table, 201, 231, 241 Core schedule table, 202, 232, 242 Compensation schedule table, 300 execution cycle number table, 593 adjustment management table, 600 adjustment management table storage unit.

Claims (9)

A multi-thread processor in which each thread operates with user authority or non-user authority every cycle,
A scheduler that switches threads to be executed in units of cycles;
A schedule adjustment unit configured to set a thread to be executed in a second period other than the first period in which a thread to be executed by the operating system or the hypervisor is set;
The schedule adjustment unit is a multi-thread processor that adjusts a thread that operates with an authority other than a user authority to be supplementarily executed in the second period. A first storage unit that stores, as a first authority cycle number, the number of cycles operated with a first authority other than the user authority for each thread;
A second storage unit that stores a schedule that defines threads to be executed for each cycle for a predetermined number of cycles;
The schedule includes a first schedule that defines threads to be executed in the first period, and a second schedule that defines threads to be executed in the second period,
The schedule adjustment unit sets a thread of the second schedule based on the first number of authority cycles for each of the threads stored in the first storage unit for each predetermined number of cycles. Item 4. The multithread processor according to Item 1. An execution cycle number adding unit that increments the first authority cycle number of the thread stored in the first storage unit by one when there is a thread that operates with an authority other than the user authority for each cycle. Prepared,
The schedule adjustment unit subtracts the number of threads set in the second schedule from the first authority cycle number of each thread stored in the first storage unit for each predetermined number of cycles. The multi-thread processor according to claim 2.   When the sum of the first authority cycle numbers of the respective threads stored in the first storage unit is less than or equal to the number of threads that can be set in the second schedule, the schedule adjustment unit sets the second schedule. The multi-thread processor according to claim 3, wherein the number of threads to be set is the first number of authority cycles of each thread.   When the sum of the number of first authority cycles of each thread stored in the first storage unit is larger than the number of threads that can be set in the second schedule, the schedule adjustment unit The ratio of the number of threads that can be set to the sum of the number of the first authority cycles is calculated, and the first authority cycle number of each thread is multiplied by the ratio to calculate the ratio of the first authority cycle number of each thread. 5. The multithread processor according to claim 4, wherein a correction value for one authority cycle number is calculated, and the number of threads set in the second schedule is used as the correction value for the first authority cycle number for each thread. A third storage unit that stores the priority of each thread;
For each of the predetermined number of cycles, the schedule adjustment unit includes the first authority cycle number for each thread stored in the first storage unit and the thread stored in the third storage unit. The multi-thread processor according to claim 2, wherein a thread of the second schedule is set based on the priority. A third storage unit that stores an upper limit value of the number that can be set in the second schedule for each thread;
For each of the predetermined number of cycles, the schedule adjustment unit includes the first authority cycle number for each thread stored in the first storage unit and the thread stored in the third storage unit. The multi-thread processor according to claim 2, wherein a thread of the second schedule is set based on the upper limit value of the settable number.   The multithreaded processor of claim 1, wherein the first authority is a hypervisor authority.   The multithreaded processor of claim 1, wherein the first authority is a supervisor authority.

Images