JP4669229B2 - Reference voltage generation circuit and mute circuit - Google Patents

Description

  The present invention relates to a reference voltage generation circuit that generates a reference voltage for setting an operating point of an analog signal, and a mute circuit using the reference voltage generation circuit. In particular, the present invention relates to a reference voltage generation circuit that generates a reference voltage that smoothly changes when switching between a mute state and a non-mute state, and a mute circuit that uses this reference voltage to reduce the generation of a pop sound. .

  Conventionally, in a mute circuit that processes (inputs / outputs) audio signals as electrical signals, the output signal is grounded when muted, a signal is output with a specified voltage as the operating point when not muted, and the operating point is set when switching between the two states. It is known that the generation of analog output noise (so-called pop noise) can be reduced by gently changing the noise.

  For example, FIG. 1 is a circuit diagram showing a mute circuit introduced as a prior art in FIG. The mute circuit is composed of an analog signal output circuit and a reference voltage generation circuit, and suppresses a noise. The reference voltage generation circuit is composed only of a resistor, a switch and a capacitor.

  FIG. 2 is a timing chart showing how the mute circuit shown in FIG. 1 operates. The voltage change at the operation reference terminal of the analog signal output circuit is determined as an exponential curve having a time constant determined by the resistor and the capacitor, and the output voltage VOUT2 of the analog signal output circuit changes as shown in FIG. When the transition from mute to non-mute and from non-mute to mute, the portion surrounded by the broken line changes suddenly and discontinuously, so that the output VOUT2 is audible when switching between the mute state and the non-mute state. A noise is generated by the component.

  FIG. 3 is a circuit diagram showing a mute circuit proposed in FIG. This mute circuit is composed of a reference voltage generating circuit composed of a P-type MOS transistor, an N-type MOS transistor, a resistor, a switch and a capacitor, and an analog signal output circuit.

  FIG. 4 is a timing chart showing the operation of the mute circuit shown in FIG. The proposed mute circuit has an analog signal output by inserting a P-type MOS transistor and an N-type MOS transistor in the reference voltage generating circuit in order to reduce the noise caused by the conventional mute circuit of FIG. The voltage change of the circuit output VOUT4 is moderated. As a result, the noise of the output VOUT4 at the time of mutual switching between the mute state and the non-mute state in the portion surrounded by the broken line is reduced.

JP 2003-273653 A

  However, the mute circuit proposed in Patent Document 1 makes the slope at the rise or fall of the voltage at the operation reference terminal gentler than that in FIG. 2 before that, and the noise at the output of the analog signal output circuit is Although it has been reduced, there is a portion where the signal change is discontinuous at the beginning of the rise and the fall (immediately after the mode transition), and a slight noise is still generated.

  The present invention has been made in view of such a problem, and an object of the present invention is to operate an analog signal that does not generate a clicking sound when switching between a mute state and a non-mute state by a configuration including a reference voltage generation circuit including a current source. It is an object to provide a reference voltage generation circuit capable of setting a point, and a mute circuit using this reference voltage to reduce the generation of a clicking sound.

  In order to achieve the above object, a reference voltage generation circuit according to the present invention outputs a voltage of a first voltage terminal from an output terminal in a first output mode, and outputs a voltage of a second voltage terminal in the second output mode. And a reference voltage generation circuit having a capacitive element between a third voltage terminal and the output terminal, wherein the reference voltage generation circuit is in a transient state when switching from the second output mode to the first output mode. A first current source for causing a current proportional to a potential difference between the two voltage terminals and the output terminal to flow from the first voltage terminal to the output terminal, or switching from the first output mode to the second output mode. And a second current source for causing a current proportional to a potential difference between the first voltage terminal and the output terminal to flow from the second voltage terminal to the output terminal in a transient state.

In order to achieve the above object, a mute circuit according to the present invention comprises a reference voltage generation circuit having the above-described configuration, wherein a voltage at the second voltage terminal is a ground potential , and a reference voltage generation circuit from the reference voltage generation circuit. A mute circuit including an output voltage as an operation reference voltage, an analog signal output according to the operation reference voltage, or a signal processing means for muting, wherein the signal processing means uses the reference as the operation reference voltage. When a voltage at the first voltage terminal of the voltage generation circuit is input, the analog signal is output with the voltage as an operating point, and a ground potential that is a voltage at the second voltage terminal of the reference voltage generation circuit is used as the operation reference voltage. are input, characterized in that muting said analog signal at the ground potential.

  According to the reference voltage generation circuit and the mute circuit of the present invention, the slope at the time of rising or falling of the output signal at the output terminal can be made more gradual and smooth, so that the mute state and the non-mute state (first output mode) And the second output mode), there is an effect of not generating a clicking sound in the output of the signal processing means.

  Hereinafter, embodiments of the present invention will be described.

  FIG. 5 is a diagram showing a first configuration example that can be said to be the most basic principle configuration of the reference voltage generating circuit according to the present invention. The reference voltage generation circuit shown in FIG. 5 includes a first current source circuit I11 that allows current to flow from the first voltage terminal V11 to the reference voltage output terminal VN1, and a current from the reference voltage output terminal VN1 to the second voltage terminal V12 of the mute potential VM1. And a capacitive element C1 connected between the reference voltage output terminal VN1 and the third voltage terminal V13. The reference voltage generation circuit outputs the reference voltage VO1 from the reference voltage output terminal VN1.

  When the first current source circuit I11 cancels mute and shifts to the non-mute mode, the reference voltage output terminal VN1 and the second voltage terminal V12 are kept until the voltage of the reference voltage output terminal VN1 becomes equal to the voltage of the first voltage terminal V11. A current in a predetermined range proportional to the voltage difference is generated. This current is supplied to the capacitive element C1, and the voltage at the reference voltage output terminal VN1 changes based on the supplied charge amount (that is, the product of the current amount and time) and the capacitance value of the capacitive element C1. The voltage of the first voltage terminal V11 and the reference voltage output terminal VN1 until the voltage of the reference voltage output terminal VN1 becomes equal to the voltage of the second voltage terminal V12 when the second current source circuit I12 shifts from the non-mute to the mute mode. A predetermined range of current proportional to the difference is generated. This current is supplied from the capacitive element C1, and the voltage of the reference voltage output terminal VN1 changes based on the supplied charge amount (that is, the product of the current amount and time) and the capacitance value of the capacitive element C1.

  Here, the third voltage terminal V13 connected to the capacitive element C1 is a fixed voltage, for example, a ground voltage, a voltage at the first voltage terminal V11, or a voltage at the second voltage terminal V12. Can do.

  The reference voltage generating circuit according to the present invention is provided with the first current source circuit I11 and the second current source circuit I12 described above in order to reduce the noise caused by the conventional mute circuit of FIGS. As shown in the timing chart of FIG. 6, the voltage change of the reference voltage VO1 at the time of switching between the mute state and the non-mute state in the portion surrounded by the broken line is made gentle. In the operation example of FIG. 6, the analog signal reference potential VA1 is set to a steady analog operation point, and the mute potential VM1 is set to the ground potential GND.

  At time t0 in FIG. 6, the mute state is switched to the non-mute state. During the period from time t0 to t1, the first current source circuit I11 generates a current proportional to VO1-GND, so that the current gradually increases and the voltage change of the reference voltage VO1 becomes steeper. The voltage rise immediately after the mode switching is moderate and the audible component is suppressed.

  During the period from time t1 to t2, since the current generated by the first current source circuit I11 reaches a predetermined current value that has been determined in advance, the current does not increase further, so the voltage of the reference voltage VO1 has a constant slope. Increase.

  Since the reference voltage VO1 approaches the analog signal reference potential VA1 during the period from the time t2 to the time t3, the current that can be supplied gradually decreases due to the capability limit of the first current source circuit I11, and the voltage increase gradually becomes gradual and smooth. Asymptotically approaching the analog signal reference potential VA1.

  Here, by inserting a resistance element in series with the first current source circuit I11 installed between the first voltage terminal V11 and the reference voltage output terminal VN1, the rate of change of the reference voltage VO1 gradually approaching is increased. It is also possible to adjust. Since the reference voltage VO1 is equal to the analog signal reference potential VA1 in a steady state when not muted, the first current source circuit I11 does not generate current.

  At time t4, the non-mute state is switched to the mute state. During the period from time t4 to time t5, the second current source circuit I12 generates a current proportional to VA-VO1, so that the current gradually increases and the voltage change of the reference voltage VO1 becomes steeper. The voltage drop at the time of mode switching is gradual, and the audible component is suppressed.

  During the period from time t5 to time t6, the current generated by the second current source circuit I12 reaches a predetermined current value, so that the current does not increase further, so the voltage of the reference voltage VO1 has a constant slope. Decrease.

  During the period from time t6 to t7, the reference voltage VO1 approaches the mute potential VM1 (GND), so that the current that can be supplied gradually decreases due to the capability limit of the second current source circuit I12, and the voltage drop gradually becomes gentle. Smoothly approaches the mute potential VM1 (GND). By setting the second voltage terminal V12 to the mute potential VM1, the voltage source is only one for the first voltage terminal V11, and there is an effect that a stable mute potential can be easily obtained.

  Here, by inserting a resistance element in series with the second current source circuit I12 installed between the second voltage terminal V12 and the reference voltage output terminal VN1, the rate of change of the reference voltage VO1 gradually approaching is increased. It is also possible to adjust. Since the reference voltage VO1 is equal to the mute potential VM1 in the steady state at the time of mute, the second current source circuit I12 does not generate current.

  FIG. 7 is a diagram showing a second configuration example of the reference voltage generating circuit according to the present invention. The reference voltage generating circuit shown in FIG. 7 is installed between the first current source circuit I71 for passing a current from the first voltage terminal V71 to the reference voltage output terminal VN7, and between the reference voltage output terminal VN7 and the third voltage terminal V73. It is comprised with the capacitive element C7. This reference voltage generation circuit outputs a reference voltage VO7 from a reference voltage output terminal VN7.

  The first current source circuit I71 in this configuration example is also connected to the reference voltage output terminal VN7 until the voltage of the reference voltage output terminal VN7 becomes equal to the voltage of the first voltage terminal V71 when the mute is released and the mode is changed to the non-mute mode. A current in a predetermined range proportional to the voltage difference of the second voltage terminal V72 is generated. At this time, the voltage change of the reference voltage VO1 is gentle and the audible component is suppressed. At the time of muting, the reference voltage output terminal VN7 and the second voltage terminal V72 are short-circuited, and the voltage of the reference voltage output terminal VN7 and the voltage of the second voltage terminal V72 become equal.

FIG. 8 is a diagram showing a third configuration example of the reference voltage generating circuit according to the present invention.
The reference voltage generating circuit shown in FIG. 8 is connected between the second current source circuit I82 that allows current to flow from the reference voltage output terminal VN8 to the second voltage terminal V82, and between the reference voltage output terminal VN8 and the third voltage terminal V83. It is comprised with the capacitive element C8. The reference voltage generation circuit outputs a reference voltage VO8 from a reference voltage output terminal VN8.

  The second current source circuit I82 has the first voltage terminal V81 and the reference voltage output terminal VN8 until the voltage of the reference voltage output terminal VN8 becomes equal to the voltage of the second voltage terminal V82 when the mute mode is changed from the non-mute mode. A predetermined range of current proportional to the voltage difference is generated. At this time, the voltage change of the reference voltage VO1 is gentle and the audible component is suppressed. When not muted, the reference voltage output terminal VN8 and the first voltage terminal V81 are short-circuited, and the voltage of the reference voltage output terminal VN8 and the voltage of the first voltage terminal V81 become equal.

  FIG. 9 is a diagram showing a first configuration example of the mute circuit according to the present invention.

  The mute circuit shown in FIG. 9 includes the reference voltage generation circuit 90 and the analog signal output circuit 92 of any of the first to third configuration examples. The operation reference terminal of the analog signal output circuit 92 is connected to the reference voltage output terminal of the reference voltage generation circuit 90. With this configuration, since the audible component can be suppressed by gently and smoothly changing the operating point of the analog signal output from the analog signal output circuit 92, the analog signal output circuit 92 at the time of switching between the mute state and the non-mute state Can be reduced.

  In this example, the analog input signal is assumed to be so-called AC coupling in which the DC component is cut. By switching between the mute state and the non-mute state, the voltage at the operation reference terminal moves in the same manner as the reference voltage VO1 in FIG. 6, and the operation points of the analog input signal and the analog output signal also move exactly the same.

  FIG. 10 is a diagram showing a second configuration example of the mute circuit according to the present invention.

The mute circuit shown in FIG. 10 has an analog signal generation circuit 101 that generates a first analog signal whose operation point is a first reference potential, and a voltage supplied from the reference voltage generation circuit 100 according to the present invention to an operation reference terminal. An analog signal output circuit 103 that operates in accordance with the level shift circuit 102 that converts an analog signal having the first reference potential as an operating point into an analog signal having the second reference potential as an operating point. The analog signal generation circuit 101 outputs an analog signal whose operating point is the first reference potential which is the voltage of the first voltage terminal in a steady state when not muted . The analog signal output circuit 103 outputs an analog signal whose operating point is the second reference potential supplied from the reference voltage generation circuit 100 when not muted, and is supplied from the reference voltage generation circuit 100 in a steady state when muted . The ground potential that is the voltage of the second voltage terminal is output.

With the above structure, slowly the analog signal output from the analog signal output circuit 103, and can suppress a smoothly varying is not audible components, the second reference potential level from an analog signal to the operating point of the first reference potential It is possible to reduce the noise caused by the conversion and the output of the analog signal output circuit 103 when switching between the mute state and the non-mute state.

In this example, it is assumed that the first reference potential has reached a predetermined voltage value, and the first analog signal generated from the analog signal generation circuit 101 moves using the first reference potential as an operating point. By switching between the mute state and the non-mute state, the second reference potential moves in the same manner as the reference voltage VO1 in FIG. 6, and the operating point of the second analog signal is exactly the same.
Subsequently, a circuit according to a specific embodiment of the present invention will be described.

  FIG. 11 is a circuit diagram showing a specific example of the first configuration example of the reference voltage generating circuit according to the present invention.

  First, in this example, the third voltage terminal connected to the capacitive element is connected in common with the second voltage terminal, and this common connection terminal is connected to GND. Further, as a voltage of the reference voltage terminal, for example, a constant voltage generated by a band gap generation circuit, a voltage generated by dividing a positive power supply voltage and a GND voltage, or an emitter follower circuit of an operational amplifier or a bipolar transistor. Or a voltage buffered by a source follower circuit of a MOS transistor can be used.

  In the mute state, the switch S11 is off and the switch S12 is on, and the voltage of the reference voltage output terminal VN11 is the mute potential VM11. At this time, the current source I111 in the first current source circuit 111 generates a current of i111 = 2 × e0. When the illustrated elements are formed on the same semiconductor chip, the P-type MOS transistors PM11 and PM12 have the same size, the N-type MOS transistors NM11, NM12, NM13, and NM14 have the same size, and the P-type MOS transistors PM13 and PM14 have the same size. When formed in a size, a current of i112 = i113 = e0 and i114 = i115 = 0 flows.

  By switching from the mute state to the non-mute state, the switch S11 is turned on and the switch S12 is turned off. As the switches S11 and S12 are switched, the voltage at the reference voltage output terminal VN11 rises from the mute potential VM11 toward the analog signal reference potential VA11.

  When the difference (VN11−VM11) between the reference voltage output terminal VN11 and the mute potential VM11 at this time is ΔV1, and the gate conductance of the P-type MOS transistors PM11 and PM12 is gm1, the currents flowing in the P-type MOS transistors PM11 and PM12 are respectively I112 = e0 + gm1 / 2 × ΔV1, i113 = e0−gm1 ÷ 2 × ΔV1. Thereby, a current of i114 = i112−i113 = gm1 × ΔV1 flows, and i115 also flows the same current as i114.

  In addition, by inserting a current source that applies a small constant current in parallel with the P-type MOS transistor PM14 between the first voltage terminal V111 and the switch S11, the operation can be surely started at the beginning of the rising of the reference signal VO11. Is possible.

  Since the current i115 increases as the reference voltage VO11 increases, the voltage at the reference voltage output terminal VN11 gradually changes steeply in the same manner as the reference voltage VO1 during the period from time t0 to time t1 in FIG.

  When the current generated in the first current source circuit 111 reaches a predetermined current value i115 = 2 × e0, since the current does not increase any more, the voltage at the reference voltage output terminal VN11 is as shown in FIG. As with the reference voltage VO1 in the section from time t1 to time t2, it changes with a constant slope.

  Furthermore, since the reference voltage VO11 approaches the analog signal reference potential VA11, the current that can be supplied to the P-type MOS transistor PM14 enters the linear operation region gradually decreases, and the voltage change gradually becomes gentle. The voltage at the reference voltage output terminal VN11 Is asymptotically approaching the analog signal reference potential VA11 in the same manner as the reference voltage VO1 in the period from time t2 to time t3 in FIG.

  Here, by inserting a resistance element in series between the switch S11 and the reference voltage output terminal VN11, it is also possible to adjust the changing speed of the reference voltage VO11 that gradually approaches.

  Since the switch S11 is on and the switch S12 is off and the voltage of the reference voltage output terminal VN11 is equal to the analog signal reference potential VA11 in the steady state when not muted, the first current source circuit 111 does not supply current.

  At this time, the current source I112 in the second current source circuit 112 generates a current of i116 = 2 × e0. When the P-type elements are formed on the same semiconductor chip, if the MOS transistors PM15 and PM16 are formed to the same size and the N-type MOS transistors NM15, NM16, NM17 and NM18 are formed to the same size, i117 = i118 = e0, A current of i119 = 0 flows.

  By switching from the non-mute state to the mute state, the switch S11 is turned off and the switch S12 is turned on. As the switches S11 and S12 are switched, the voltage at the reference voltage output terminal VN11 drops from the analog signal reference potential VA11 toward the mute potential VM11.

  If the difference (VA11−VN11) between the reference voltage output terminal VN11 and the analog signal reference potential VA11 at this time is ΔV2, and the gate conductances of the P-type MOS transistors PM15 and PM16 are gm2, the currents flowing through the P-type MOS transistors PM15 and PM16 Are i117 = e0 + gm2 ÷ 2 × ΔV2, and i118 = e0−gm2 ÷ 2 × ΔV2. Thereby, a current of i119 = i117−i118 = gm2 × ΔV2 flows.

  Further, by inserting a current source that applies a small constant current in parallel with the N-type MOS transistor NM18 between the second voltage terminal V112 and the switch S12, the operation can be surely started at the beginning of the fall of the reference voltage VO11. It becomes possible.

  Since the current i119 increases with the voltage drop of the reference voltage VO11, the voltage at the reference voltage output terminal VN11 gradually changes steeply in the same manner as the reference voltage VO1 in the period from time t4 to t5 in FIG.

  When the current generated in the second current source circuit 112 reaches a predetermined current value i119 = 2 × e0, the current does not increase any more, so the voltage at the reference voltage output terminal VN11 is as shown in FIG. Like the reference voltage VO1 in the section from time t5 to time t6, it changes with a constant slope.

  Further, since the reference voltage VO11 approaches the mute potential VM11, the current that can be supplied to the N-type MOS transistor NM18 enters the linear operation region gradually decreases, and the voltage change gradually decreases. The voltage at the reference voltage output terminal VN11 is as shown in FIG. 6 smoothly approaches the mute potential VM11 in the same manner as the reference voltage VO1 in the interval from time t6 to t7.

  Here, by inserting a resistance element in series between the switch S12 and the reference voltage output terminal VN11, it is also possible to adjust the changing speed of the reference voltage VO11 that gradually approaches.

  In the steady state at the time of mute, the switch S11 is off and the switch S12 is on, and the voltage of the reference voltage output terminal VN11 is equal to the mute potential VM11. Therefore, the second current source circuit 112 does not supply current.

  FIG. 12 is a circuit diagram showing a specific example of the second configuration example of the reference voltage generating circuit according to the present invention.

  First, in this example, the third voltage terminal connected to the capacitive element is connected in common with the second voltage terminal, and this common connection terminal is connected to GND. Further, as a voltage of the reference voltage terminal, for example, a constant voltage generated by a band gap generation circuit, a voltage generated by dividing a positive power supply voltage and a GND voltage, or an emitter follower circuit of an operational amplifier or a bipolar transistor. Or a voltage buffered by a source follower circuit of a MOS transistor can be used.

  In the mute state, the switch S21 is off and the switch S22 is on, and the voltage of the reference voltage output terminal VN12 is the mute potential VM12. At this time, the current source I121 in the first current source circuit 121 generates a current of i121 = 2 × e0. When the illustrated elements are formed on the same semiconductor chip, the P-type MOS transistors PM21 and PM22 have the same size, the N-type MOS transistors NM21, NM22, NM23, and NM24 have the same size, and the P-type MOS transistors PM23 and PM24 have the same size. When formed in a size, a current of i122 = i123 = e0 and i124 = i125 = 0 flows.

  By switching from the mute state to the non-mute state, the switch S21 is turned on and the switch S22 is turned off. As the switches S21 and S22 are switched, the voltage at the reference voltage output terminal VN12 rises from the mute potential VM12 toward the analog signal reference potential VA12.

  If the difference (VN12−VM12) between the reference voltage output terminal VN12 and the mute potential VM12 at this time is ΔV3 and the gate conductances of the P-type MOS transistors PM21 and PM22 are gm3, the currents flowing through the P-type MOS transistors PM21 and PM22 are respectively I122 = e0 + gm3 ÷ 2 × ΔV3, i123 = e0−gm3 ÷ 2 × ΔV3. As a result, a current of i124 = i122−i123 = gm3 × ΔV3 flows, and i125 also flows the same current as i124.

  Further, by inserting a current source that applies a small constant current in parallel with the P-type MOS transistor PM24 between the first voltage terminal V121 and the switch S21, the operation can be surely started at the beginning of the rising of the reference voltage VO12. Is possible.

  Since the current i125 increases as the reference voltage VO12 rises, the voltage at the reference voltage output terminal VN12 gradually changes steeply in the same manner as the reference voltage VO1 during the period from time t0 to t1 in FIG.

  When the current generated in the first current source circuit 121 reaches a predetermined current value i125 = 2 × e0, the current does not increase any more, so the voltage at the reference voltage output terminal VN12 is as shown in FIG. Like the reference voltage VO1 in the section from time t1 to t2, it changes with a constant slope.

  Further, since the reference voltage VO12 approaches the analog signal reference potential VA12, the current that can be supplied to the P-type MOS transistor PM24 enters the linear operation region gradually decreases, and the voltage change gradually becomes gentle. The voltage at the reference voltage output terminal VN12 Is asymptotically approaching the analog signal reference potential VA12 in the same manner as the reference voltage VO1 in the section from time t2 to time t3 in FIG.

  Here, by inserting a resistance element in series between the switch S21 and the reference voltage output terminal VN12, it is also possible to adjust the changing speed of the reference voltage VO12 that gradually approaches.

  In the steady state when not muted, the switch S11 is on and the switch S12 is off, and the voltage at the reference voltage output terminal VN11 is equal to the analog signal reference potential VA11. Therefore, the first current source circuit 121 does not supply current.

  FIG. 13 is a circuit diagram showing a specific example of the third configuration example of the reference voltage generating circuit according to the present invention.

  First, in this example, the third voltage terminal connected to the capacitive element is connected in common with the second voltage terminal, and this common connection terminal is connected to GND. Further, as a voltage of the reference voltage terminal, for example, a constant voltage generated by a band gap generation circuit, a voltage generated by dividing a positive power supply voltage and a GND voltage, or an emitter follower circuit of an operational amplifier or a bipolar transistor. Or a voltage buffered by a source follower circuit of a MOS transistor can be used.

  In the non-muted state, the switch S31 is on and the switch S32 is off, and the voltage of the reference voltage output terminal VN13 is the analog signal reference potential VA13. At this time, the current source I131 in the second current source circuit 132 generates a current of i131 = 2 × e0. When the illustrated elements are formed on the same semiconductor chip, if the P-type MOS transistors PM31 and PM32 are formed in the same size and the N-type MOS transistors NM31, NM32, NM33, and NM34 are formed in the same size, i132 = i133 = e0, A current of i134 = 0 flows.

  By switching from the non-mute state to the mute state, the switch S31 is turned off and the switch S32 is turned on. As the switches S31 and S32 are switched, the voltage at the reference voltage output terminal VN13 drops from the analog signal reference potential VA13 toward the mute potential VM13. If the difference (VA13−VN13) between the reference voltage output terminal VN13 and the analog signal reference potential VA13 at this time is ΔV4, and the gate conductance of the P-type MOS transistors PM31 and PM32 is gm4, the current flowing through the P-type MOS transistors PM31 and PM32 Respectively, i132 = e0 + gm4 ÷ 2 × ΔV4 and i133 = e0−gm4 ÷ 2 × ΔV4. As a result, a current of i134 = i132−i133 = gm4 × ΔV4 flows.

  Further, by inserting a current source that applies a small constant current in parallel with the N-type MOS transistor NM34 between the second voltage terminal V132 and the switch S32, the operation can be surely started at the beginning of the fall of the reference voltage VO13. It becomes possible.

  Since the current i134 increases with the voltage drop of the reference voltage VO13, the voltage at the reference voltage output terminal VN13 gradually changes steeply in the same manner as the reference voltage VO1 in the period from time t4 to t5 in FIG.

  When the current generated in the second current source circuit 132 reaches a predetermined current value i134 = 2 × e0, the current does not increase any more, so the voltage at the reference voltage output terminal VN13 is as shown in FIG. Like the reference voltage VO1 in the section from time t5 to time t6, it changes with a constant slope.

  Furthermore, since the reference voltage VO13 approaches the mute potential VM13, the current that can be supplied to the N-type MOS transistor NM34 enters the linear operation region gradually decreases, and the voltage change gradually decreases. The voltage at the reference voltage output terminal VN13 is as shown in FIG. As in the case of the reference voltage VO1 in the section from time t6 to time t7 in FIG.

  Here, by inserting a resistance element in series between the switch S32 and the reference voltage output terminal VN13, it is also possible to adjust the changing speed of the reference voltage VO13 that gradually approaches.

  In the steady state at the time of mute, the switch S11 is off and the switch S12 is on, and the voltage of the reference voltage output terminal VN11 is equal to the mute potential VM11. Therefore, the second current source circuit 132 does not supply current.

  FIG. 14 is a circuit diagram showing a specific example of the first configuration example of the mute circuit according to the embodiment of the present invention.

  The operation reference terminal of the operational amplifier OP14 is connected to the reference voltage output terminal of the reference voltage generation circuit 140, and the analog input signal assumes so-called AC coupling in which the DC component is cut. By switching between the mute state and the non-mute state, the voltage at the operation reference terminal moves in the same manner as the reference voltage VO1 in FIG. 6, and the operation points of the analog input signal and the analog output signal also move exactly the same.

  With this configuration, the audible component can be suppressed by gently and smoothly changing the analog signal output from the analog signal output circuit 142. Therefore, in the output of the analog signal output circuit 142 when switching between the mute state and the non-mute state The noise can be reduced.

  FIG. 15 is a circuit diagram showing a specific example of the second configuration example of the mute circuit according to the embodiment of the present invention.

  It is assumed that the first reference potential has reached a predetermined voltage value in advance, and the first analog signal generated from the analog signal generation circuit 151 moves using the first reference potential as an operating point. The level shift circuit 152 includes an operational amplifier OP15 and four resistance elements having the same size, and converts an analog signal having the first reference potential as an operating point into an analog signal having the second reference potential as an operating point. By switching between the mute state and the non-mute state, the second reference potential moves in the same way as the reference signal VO1 in FIG. 6, and the operating point of the second analog signal is exactly the same.

  With this configuration, the audible component can be suppressed by gently and smoothly changing the analog signal output from the analog signal output circuit 153, so that the second reference potential is operated from the analog signal having the first reference potential as the operating point. It is possible to reduce the noise at the output of the analog signal output circuit 153 at the time of switching between the mute state and the non-mute state. Here, the analog signal generation circuit 151 can be configured by, for example, a delta-sigma modulator.

  The present invention relates to a reference voltage generation circuit that generates a reference voltage for setting an operating point of an analog signal, and a mute circuit using the reference voltage generation circuit. The reference voltage generation circuit according to the present invention generates a reference voltage that smoothly changes when switching between the mute state and the non-mute state, and the mute circuit according to the present invention uses the above-described reference voltage to enable the mute state and the non-mute state. This is suitable for reducing the generation of a clicking sound at the time of switching.

It is a circuit diagram which shows an example of the conventional mute circuit. 3 is a timing chart showing the operation of the mute circuit in FIG. 1. It is a circuit diagram which shows another example of the conventional mute circuit. 4 is a timing chart showing the operation of the mute circuit in FIG. 3. 1 is a circuit diagram showing a first configuration example of a reference voltage generating circuit according to the present invention. FIG. 6 is a timing chart showing how the reference voltage generating circuit in FIG. 5 operates. It is a circuit diagram which shows the 2nd structural example of the reference voltage generation circuit which concerns on this invention. It is a circuit diagram which shows the 3rd structural example of the reference voltage generation circuit which concerns on this invention. 1 is a circuit diagram showing a first configuration example of a mute circuit according to the present invention. FIG. It is a circuit diagram which shows the 2nd structural example of the mute circuit based on this invention. 1 is a circuit diagram showing an embodiment of a first configuration of a reference voltage generating circuit according to the present invention. FIG. It is a circuit diagram which shows the Example of the 2nd structure of the reference voltage generation circuit which concerns on this invention. It is a circuit diagram which shows the Example of the 3rd structure of the reference voltage generation circuit which concerns on this invention. FIG. 3 is a circuit diagram showing an embodiment of a first configuration of a mute circuit according to the present invention. It is a circuit diagram which shows the Example of the 2nd structure of the mute circuit based on this invention.

Explanation of symbols

90, 100, 140, 150 Reference voltage generation circuit 92, 103, 142, 153 Analog signal output circuit 101, 151 Analog signal generation circuit 102, 152 Level shift circuit 111, 121 First current source circuit 112, 132 Second current source Circuits R21, R22, R41, R42 Resistors SW21, SW22, SW41, SW42, S11, S12, S21, S22, S31, S32 Switch C2, C4 capacitors OP2, OP4, OP14, OP15 operational amplifiers M41, PM11-16, PM21-1 24, PM31, PM32 P-type MOS transistors M42, NM11-15, NM16-18, NM21-24, NM31-34 N-type MOS transistors I111, I112, I121, I131 Current source VS Analog signal reference potential GND Grounding power VIN2, VIN4 analog signal input VOUT2, VOUT4 analog signal output

Claims (5)

The voltage of the first voltage terminal is output from the output terminal in the first output mode, the voltage of the second voltage terminal is output from the output terminal in the second output mode, and a capacitive element is provided between the third voltage terminal and the output terminal. A reference voltage generating circuit comprising:
To flow a current proportional to the potential difference between the second voltage terminal and the output terminal from the first voltage terminal to the output terminal in a transient state when switching from the second output mode to the first output mode. A first current source of
To flow a current proportional to a potential difference between the first voltage terminal and the output terminal from the second voltage terminal to the output terminal in a transient state when switching from the first output mode to the second output mode. A reference voltage generating circuit comprising the second current source. The reference voltage generating circuit according to claim 1,
When the transient state shifts to the steady state of the first output mode or the steady state of the second output mode, the current generated by the first current source or the second current source gradually decreases. The reference voltage generation circuit, wherein the output voltage gradually approaches the voltage at the first voltage terminal or the second voltage terminal. In the reference voltage generation circuit according to claim 1 or 2,
A reference voltage generating circuit, wherein the voltage of the second voltage terminal is a ground potential. 4. A reference voltage generation circuit according to claim 3 , and signal processing means for inputting an output voltage from the reference voltage generation circuit as an operation reference voltage and outputting an analog signal or muting in accordance with the operation reference voltage. A mute circuit,
When the voltage at the first voltage terminal of the reference voltage generation circuit is input as the operation reference voltage, the signal processing means outputs the analog signal using the voltage as an operation point, and generates the reference voltage as the operation reference voltage. When the ground potential is the voltage of the second voltage terminal of the circuit is input mute circuit, characterized by muting said analog signal at the ground potential. 5. The mute circuit according to claim 4, further comprising:
Means for generating an analog signal whose operating point is another operating reference voltage different from the operating reference voltage;
A mute circuit comprising level shift means for converting an operating point of the analog signal to a voltage equal to an output voltage from the reference voltage generation circuit and providing the same as an analog signal input of the signal processing means.

Images