JP4662863B2 - Dissolve video editing device - Google Patents

Description

  The present invention relates to a dissolve video editing apparatus, and more particularly to a dissolve video editing apparatus that can easily edit a dissolve video that gradually shifts a video to another video.

  An editing operation for creating a dissolve video from two videos (first video I1 and second video I2) recorded in the VTR has conventionally been performed as shown in FIG. This was done using a VTR 82, three monitors 83, 84 and 85 and a switcher 86.

  As shown in the block diagram of FIG. 9, the switcher 86 includes a first multiplier 861 that multiplies the first video I1 recorded in the first VTR 81 and the coefficient q, and the coefficient q from “1”. A subtractor 862 for subtracting, a second multiplier 863 for multiplying the second video I2 recorded in the second VTR 82 and the output of the subtractor 862, the output of the first multiplier 861, and the second And a combiner 864 for combining the outputs of the multiplier 863.

  The coefficient q changes as a function of time from “1” to “0” by a fader operation or by a program.

When a dissolve video is created by the above-described conventional system, the first video I2 recorded in the first VTR 81 is cued at the dissolve start position after the second video I2 recorded in the second VTR 82 is cued. Playback of the video I1 is started. When the dissolve start position of the first video I1 is reached, reproduction of the second video I2 is started by the second VTR 82, and the coefficient q is changed from “1” to “0”. That is, in the above system, the dissolve video DI is calculated by [Equation 1].

  The dissolve video DI is rarely completed in one editing operation, and a plurality of dissolve videos DI are produced by changing the dissolve start position, dissolve end position, coefficient q change state, etc. It is common to select an excellent dissolve video DI.

  However, in order to create a plurality of dissolve images DI in the conventional system, it is necessary to repeat the cueing of the second image I2 and the reproduction of the first image I1 and the second image I2, which makes the operation complicated. In addition, it is inevitable that the first video I1 and the second video I2 recorded in the VTR deteriorate.

As the access time and capacity of hard disk recorders have recently increased, so-called nonlinear editing, in which video recorded on a VTR is digitally recorded on the hard disk and edited with the digital video recorded on the hard disk, has become mainstream. (For example, see Patent Document 1).
JP 11-39849 A ([0024] to [0026], FIG. 1)

However, when the non-linear editing apparatus disclosed in Patent Document 1 is applied to dissolve video editing, although the video does not deteriorate even if playback is repeated, a high-performance hard disk with a short access time is used, or a plurality of hard disks are used. not the only but it is necessary to use a hard disk, operation memory of large capacity having a long address length in order to realize the function of the switcher 86 digitally is a problem that required.

  That is, in order to create a dissolve video DI, it is necessary to simultaneously read video frames at the same time. However, since the hard disk cannot access two areas at the same time, two frames are required within one frame period (1/30 second). It was necessary to use a high-performance hard disk with a short access time capable of accessing the area, or to use separate hard disks for the first video I1 and the second video I2.

  Further, when the first video I1, the second video I2, and the dissolve video DI are each a 10-bit digital signal and the coefficient is an 8-bit digital signal, the function of the switcher 86 is digitally realized. For this purpose, an arithmetic memory having an address length of 18 bits and a capacity of 300 megabytes is required.

  The present invention has been made to solve the conventional problems, and an object thereof is to provide a dissolve video editing apparatus capable of easily editing a dissolve video.

  The dissolve video editing apparatus according to the present invention includes at least one randomly accessible video data recording unit in which first video data and second video data are recorded, and a dissolve period read from the video data recording unit. First pixel dividing means for dividing each pixel included in the first video frame constituting the first video data into first upper bits and first lower bits, and the video data recording means Each pixel included in the second video frame synchronized with the first video frame constituting the second video data in the dissolve period read from the second high-order bit and second low-order bit A second pixel dividing unit that divides the data into bits, a first weighting factor that changes from “1” to “0” within the dissolve period, and a first weighting factor from “1”. Weight coefficient generation means for generating the calculated second weight coefficient, and a dissolve upper bit based on the first upper bit, the second upper bit, the first weight coefficient, and the second weight coefficient Dissolving upper bit calculation means for calculating, Dissolving lower bit calculation means for calculating a dissolving lower bit based on the first lower bit, the second lower bit, the first weighting factor and the second weighting factor A dissolve video frame synthesizing unit for synthesizing a dissolve video frame from a dissolve pixel obtained by combining the dissolve upper bit and the dissolve lower bit, and a dissolve video data recording unit for recording the dissolve video frame as dissolve video data over the dissolve period It has the structure containing these.

  With this configuration, the dissolve video can be easily edited.

  In the dissolve video editing apparatus according to the present invention, the dissolve high-order bit calculating unit calculates a first dissolve high-order bit by multiplying the first high-order bit and the first weighting factor to calculate a first dissolve high-order bit. A calculating means; a second dissolve high-order bit calculating means for calculating a second dissolve high-order bit by multiplying the second high-order bit and the second weighting factor; the first dissolve high-order bit; Dissolving upper bit combining means for combining with the second dissolving upper bit to obtain a dissolving upper bit, wherein the dissolving lower bit calculating means multiplies the first lower bit and the first weighting factor. First dissolve lower-order bit calculating means for calculating the first dissolve lower-order bits, the second lower-order bits and the second weighting factor. Second dissolve lower bit calculating means for calculating a second dissolve lower bit, and a dissolve lower bit that combines the first dissolve lower bit and the second dissolve lower bit to form a dissolve lower bit And a coupling means.

  With this configuration, a dissolve video can be generated with a significantly smaller calculation memory capacity than in the prior art.

  According to the present invention, a dissolve video is generated by dividing a pixel into an upper bit and a lower bit to generate a dissolve video, so that the dissolve video can be easily edited with a significantly smaller calculation memory capacity than in the prior art. A video editing apparatus can be provided.

  Embodiments of a dissolve video editing apparatus according to the present invention will be described below with reference to the drawings.

(First embodiment)
As shown in the block diagram of FIG. 1, the dissolve video editing apparatus 1 according to the first embodiment is a randomly accessible video data recording unit in which the first video data ID1 and the second video data ID2 are recorded. The functioning first hard disk (HDD) recorder 111 and second hard disk recorder 112, and the first video data ID1 within the dissolve period DP read from the first hard disk recorder 111 and the second hard disk recorder 112 are First pixel dividing means 121 for dividing each pixel included in the first video frame IF1 constituting the first video frame IF1 into a first upper bit HB1 and a first lower bit LB1, a first hard disk recorder 111, and a second hard disk Within the dissolve period DP read from the recorder 112 2nd pixel division which divides each pixel contained in 2nd video frame IF2 synchronized with 1st video frame IF1 which constitutes 2 video data ID2 into 2nd upper bit HB2 and 2nd lower bit LB2 Means 122 generates a first weighting factor q _{1 that} changes from “1” to “0” within a dissolve period DP, and a second weighting factor q ₂ that is obtained by subtracting the first weighting factor q ₁ from “1”. Weight coefficient generating means 13, and a dissolve high-order bit for calculating a dissolve high-order bit HDB based on the first high-order bit HB1, the second high-order bit HB2, the first weight coefficient q ₁ and the second weight coefficient q ₂ and calculation means 14, the first lower-order bits LB1, second low-order bit LB2, di to calculate a dissolve lower bits LDB based on the first weighting factor q ₁ and the second weighting factor q ₂ A dissolve lower bit calculation means 15, a dissolve video frame synthesizing means 16 for synthesizing a dissolve video frame DIF from a dissolve pixel DB obtained by combining a dissolve upper bit HDB and a dissolve lower bit LDB, and a dissolve video frame DIF over a dissolve period DP. It comprises a dissolve video data recording means 17 for recording as data DID.

Then, dissolve upper bit calculating means 14, as shown in the block diagram of FIG. 2, the calculating the first dissolve upper bit HDB1 by multiplying the first high-order bits HB1 the first weight factor q ₁ 1 dissolve upper bit calculating means 41; a second dissolve upper bit calculating means 42 for calculating a second dissolve upper bit HDB2 by multiplying the second upper bit HB2 by a second weighting factor q ₂ ; Dissolving upper bit combining means 43 that combines the first dissolve upper bit HDB1 and the second dissolve upper bit HDB2 to form the dissolving upper bit HDB is included.

The dissolve lower bit calculation means 15 has the same configuration as the dissolve upper bit calculation means 14, and, as shown in the block diagram of FIG. 2, the first lower bit LB1 and the first weight coefficient q ₁ are obtained. first and dissolve lower bit calculating means 44, the second dissolve lower bits by multiplying the second low-order bit LB2 a second weighting factor q ₂ for calculating a first dissolve lower bit LDB1 by multiplying LDB2 Including a second dissolve lower bit calculating means 45 for calculating the lower dissolve bit LD1 by combining the first dissolve lower bit LD1 and the second dissolve lower bit LD2 into a dissolve lower bit LDB. It has become.

  As shown in the block diagram of FIG. 3, the dissolve video editing apparatus 1 according to the first embodiment includes a first VTR 101 that records the first video I1 and a second VTR 102 that records the second video I2. The first hard disk recorder 111 that converts the first video I1 into digital data and records it as the first video data ID1, and the second hard disk recorder 111 that converts the first video I2 into digital data and records it as the second video data ID2. 2 hard disk recorder 112, personal computer (PC) 3 functioning as a dissolve editor, peripheral device 31 of PC 3, and monitor 32.

  The PC 3 stores in the CPU 300 that executes processing based on the program, the memory 301 that stores the program and the processing result, the first video data ID1 recorded in the first hard disk recorder 111, and the second hard disk recorder 112. A video interface (I / F) 302 that reads the stored second video data ID2, a dissolve video I / F 303 that outputs a dissolve video, and a peripheral device I / F 304 that connects the peripheral device 31 of the PC 3 are included. It has a configuration.

  A first hard disk recorder 111 and a second hard disk recorder 112 are connected to the video I / F 302, and a peripheral device 31 including a display 311, a keyboard 312 and a pointing device 313 is connected to the peripheral device I / F 304. A monitor 32 is connected to the I / F 303.

  Next, the operation of the dissolve video editing apparatus according to the first embodiment will be described with reference to a program installed in the PC 3.

  FIG. 4 is a flowchart of the first dissolve video editing program installed in the PC 4. The CPU 300 first sets the playback times of the first video data ID1 and the second video data ID2 in advance. It is determined whether or not the start time of the dissolve period DP has been reached (step S400). When it is determined that the start time has not been reached, this routine is directly terminated.

  Conversely, when CPU 300 determines in step S400 that the start time has been reached, CPU 300 sets dissolve time DT indicating the time of dissolve period DP to 0 (step S401), and first video from first hard disk recorder 111 is displayed. The video frame IF1 (DT) at the dissolve time DT of the data ID1 is read (step S402), and the video frame IF2 (DT) at the dissolve time DT of the second video data ID2 is read from the second hard disk recorder 112 (step S403). .

  Next, the CPU 300 initializes the pixel number k to “1” (step S404), and sets the pixel P1 (k) of the first video frame IF1 (DT) to the first upper bit HB1 (k) and the first Dividing into lower bits LB1 (k), the pixel P2 (k) of the second video frame IF2 (DT) is divided into second upper bits HB2 (k) and second lower bits LB2 (k) (step) S405).

  Actually, the pixel has three components of red, blue, and green. In this specification, the three components are collectively referred to as P1 (k) or P2 (k).

Next, the CPU 300 combines the first upper bit HB1 (k) and the second upper bit HB2 (k) based on [Equation 2] to form the dissolve upper bit HDB (k) (step S406).

Further, the CPU 300 combines the first lower bit LB1 (k) and the second lower bit LB2 (k) based on [Equation 3] to obtain a dissolve lower bit LDB (k) (step S407).

  Then, the CPU 300 synthesizes the dissolve pixel DB (k) of the dissolve video frame DIF (DT) from the dissolve upper bit HDB (k) and the dissolve lower bit LDB (k) (step S408).

  The CPU 300 determines whether or not the synthesis has been completed for all the pixels of the frame based on whether or not k has reached the maximum value K (step S409), and if k has not reached the maximum value K. If it is determined, k is incremented (step S410), and the processing from step S405 to step S409 is repeated.

  When it is determined that k has reached the maximum value K, the CPU 300 records the dissolve video frame DIF (DT) at the dissolve time DT (step S411), and whether the dissolve time DT has reached the end time of the dissolve period DP. It is determined whether or not (step S412).

If the CPU 300 determines in step S412, that the dissolve time DT has not reached the end time of the dissolve period DP, the CPU 300 advances the dissolve time DT by a predetermined time ΔT (step S413), and uses the first equation using [Equation 4]. The coefficient q ₁ and the second coefficient q ₂ are updated (step S414), and the processing from step S402 to step S412 is repeated.

  When CPU 300 determines in step S412 that DT = DP and the dissolve time DT has reached the end time of the dissolve period DP, this routine is terminated.

  As described above, according to the first embodiment, it is possible to significantly reduce the arithmetic memory capacity to about 32 Kbytes by generating a dissolve video by dividing a pixel into upper bits and lower bits. Become.

(Second Embodiment)
As shown in the block diagram of FIG. 5, the dissolve video editing apparatus 2 according to the second embodiment includes at least one randomly accessible video data in which the first video data ID1 and the second video data ID2 are recorded. A hard disk (HDD) recorder 21 that functions as a recording unit, and a first video frame IF1 that constitutes the first video data ID1 or a second video frame IF2 that constitutes the second video data ID2 are framed from the hard disk recorder 21. Current video frame storage means 22 that alternately reads and stores the current video frame PIF every period, and the current video frame PIF stored in the current video frame storage means 22 before reading the current video frame PIF as the previous video frame BIF. Previous video frame storage means 23 for storing, current video frame A dissolve video frame synthesizing unit 24 for synthesizing the dissolve video frame DIF based on the current video data PIF stored in the video storage unit 22 and the previous video frame BIF stored in the previous video frame storage unit 23; Dissolve video data recording means 25 for recording DIF as dissolve video data DID over the dissolve period DP.

Then, the dissolve video frame synthesizing unit 24 reads the first video frame IF1 from the current video frame storage unit 22 when the current video frame storage unit 22 reads the first video frame IF1, and stores the current video frame storage unit 24. When the means 22 is reading the second video frame IF2, the first video frame reading means 241 that reads the first video frame IF1 from the previous video frame storage means 23 and the current video frame storage means 22 are the second video frame IF2. When the current video frame IF2 is being read, the second video frame IF2 is read from the current video frame storage means 22, and when the current video frame storage means 22 is reading the first video frame IF1, the previous video frame IF2 is read. A second video frame for reading the second video frame IF2 from the storage means 23 A reading means 242, the second weighting factor q ₂ from the first weighting factor q ₁ and "1" obtained by subtracting the first weighting factor q ₁ changes from "1" to the dissolve transition DP to "0" Weight coefficient generation means 243 to be generated, multiplication result of the first video frame IF1 read from the first video frame read means 241 and the first weight coefficient q _1, and second video frame read means 242 It has a configuration which includes a dissolve image frame calculation means 244 for calculating a dissolve image frame DIF by adding the second image frame IF2 read the multiplication result between the second weighting factor q ₂ from.

  The hardware configuration of the second embodiment is such that the first video data ID1 obtained by digitizing the first video I1 captured by the first VTR 101 and the second video I2 captured by the second VTR 102 are digitalized. The hard disk recorder 21 that functions as at least one randomly accessible video data recording unit in which the second video data ID2 is recorded and the PC 3 are configured. The PC 3 is the same as that of the first embodiment. Since there is, explanation is omitted.

  Next, the operation of the dissolve video editing apparatus according to the second embodiment will be described with reference to a program installed in the PC 3.

  FIG. 6 is a flowchart of the second dissolve video editing program installed in the PC 3, and the CPU 300 first sets the playback times of the first video data ID1 and the second video data ID2 respectively. It is determined whether or not the start time of the dissolve period DP has been reached (step S600). When it is determined that the start time has not been reached, this routine is directly terminated.

  Conversely, when it is determined in step S600 that the start time has been reached, the CPU 300 sets a dissolve time DT indicating the time of the dissolve period DP to 0 (step S601), and initializes the switching index M to “1” ( In step S602), the stored contents of the current frame memory functioning as the current video frame storage means 22 are moved to the previous frame memory functioning as the previous video frame storage means 23 (step S603).

  The CPU 300 determines whether or not the switching index M is “1”, that is, whether it is the read timing of the first video data ID1 or the read timing of the second video data ID2 (step S604). When it is determined that the switching index M is “1”, the first video frame IF1 is read and stored in the current frame memory (step S605).

Then, the CPU 300 synthesizes the dissolve video frame DIF from the first video frame IF1 stored in the current frame memory and the second video frame IF2 stored in the previous frame memory based on [Equation 5]. (Step S606).

  Further, the CPU 300 sets the switching index M to “2” (step S607), and proceeds to step S611.

  On the other hand, when the CPU 300 determines in step S604 that the switching index M is “2”, the CPU 300 reads the second video frame IF2 and stores it in the current frame memory (step S608).

  Then, the CPU 300 synthesizes the dissolve video frame DIF from the first video frame IF1 stored in the previous frame memory and the second video frame IF2 stored in the current frame memory based on [Equation 5]. (Step S609).

  Further, the CPU 300 sets the switching index M to “1” (step S610), and proceeds to step S611.

  In step S611, the CPU 300 records the dissolve video frame DIF in the memory 301 (step S611), and determines whether or not the dissolve time DT has reached the end time of the dissolve period DP (step S612).

If the CPU 300 determines in step S612 that the dissolve time DT has not reached the end time of the dissolve period DP, the CPU 300 advances the dissolve time DT by a predetermined time ΔT (step S613), the first coefficient q ₁ and the second coefficient update the coefficients q ₂ (step S614), and repeats the processing of step S603~ step S612.

  When CPU 300 determines in step S612 that DT = DP and the dissolve time DT has reached the end time of the dissolve period DP, this routine is terminated.

  FIG. 7 is a process diagram showing the process of generating a dissolve video in the second embodiment. In the dissolve period DP, the video frame IF1 of the first video data ID1 and the video frame IF2 of the second video data ID2 are shown. Use alternately to generate dissolve video.

  As described above, according to the second embodiment, the hard disk recorder only needs to be able to access one frame of video data for each frame period. Can be generated easily.

  The first embodiment and the second embodiment are combined, and the first video frame and the second video frame are alternately read for each frame period, and the first video frame and the second video frame are read out alternately. It is also possible to generate a dissolve video by decomposing a video frame into upper bits and lower bits.

  As described above, the dissolve video editing apparatus according to the present invention has an effect that the dissolve video can be easily edited with a significantly smaller calculation memory capacity than the conventional one, and is effective as a video editing apparatus or the like. .

1 is a block diagram of a dissolve video editing apparatus according to a first embodiment of the present invention. FIG. 3 is a block diagram of a dissolve upper bit calculation unit and a dissolve lower bit calculation unit of the dissolve video editing apparatus according to the present invention. The block diagram which shows the hardware constitutions of the dissolve video editing apparatus which concerns on this invention. The flowchart of the 1st dissolve image editing program which CPU of the dissolve image editing apparatus which concerns on this invention performs. The block diagram of the dissolve video editing apparatus in the 2nd Embodiment of this invention. The flowchart of the 2nd dissolve video editing program which CPU of the dissolve video editing device concerning this invention performs. The process figure which shows the generation | occurrence | production process of a dissolve image. The figure explaining the edit work which produces the conventional dissolve image | video. The block diagram of the switcher used for the edit work of the conventional dissolve image | video.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Dissolve video editing apparatus 111 1st hard disk (HDD) recorder 112 2nd hard disk (HDD) recorder 121 1st pixel division means 122 2nd pixel division means 13, 243 Weight coefficient generation means 14 Dissolve upper bit calculation means 15 Dissolve lower bit calculation means 16 Dissolve video frame synthesis means 17, 25 Dissolve video data recording means 21 Hard disk (HDD) recorder 22 Current video frame storage means 23 Previous video frame storage means 24 Dissolve video frame synthesis means 244 Dissolve video frame calculation means 41 first dissolve upper bit calculating means 42 second dissolve upper bit calculating means 43 dissolve upper bit combining means 44 first dissolve lower bit calculating means 45 second Zorubu lower bit calculating means 46 dissolve lower bit coupling means

Claims (2)

At least one randomly accessible video data recording means in which the first video data and the second video data are recorded;
Each pixel included in the first video frame constituting the first video data within the dissolve period read from the video data recording means is divided into a first upper bit and a first lower bit. One pixel dividing means;
Each pixel included in the second video frame synchronized with the first video frame constituting the second video data in the dissolve period read from the video data recording means is set to a second upper bit. And a second pixel dividing means for dividing into a second lower bit,
Weighting factor generating means for generating a first weighting factor that changes from “1” to “0” within the dissolve period and a second weighting factor obtained by subtracting the first weighting factor from “1”;
A dissolve high-order bit calculating means for calculating a dissolve high-order bit based on the first high-order bit, the second high-order bit, the first weighting factor, and the second weighting factor;
A dissolve lower bit calculating means for calculating a dissolve lower bit based on the first lower bit, the second lower bit, the first weighting factor, and the second weighting factor;
A dissolve video frame synthesizing unit that synthesizes a dissolve video frame from a dissolve pixel obtained by combining the dissolve upper bits and the dissolve lower bits;
A dissolve video editing apparatus comprising: dissolve video data recording means for recording the dissolve video frame as dissolve video data over the dissolve period. A first dissolve upper bit calculating means for calculating a first dissolve upper bit by multiplying the first upper bit by the first weighting factor;
A second dissolve upper bit calculating means for calculating a second dissolve upper bit by multiplying the second upper bit and the second weighting factor;
A dissolve upper bit combining means for combining the first dissolve upper bit and the second dissolve upper bit into a dissolve upper bit,
The dissolve lower bit calculation means is a first dissolve lower bit calculation means for calculating a first dissolve lower bit by multiplying the first lower bit and the first weighting factor;
A second dissolve lower bit calculating means for calculating a second dissolve lower bit by multiplying the second lower bit and the second weighting factor;
2. The dissolve video editing apparatus according to claim 1, further comprising a dissolve lower bit combining unit that combines the first dissolve lower bit and the second dissolve lower bit to form a dissolve lower bit.

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