JP4660566B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device capable of electrically rewriting data.

  Conventionally, LSIs have been formed by integrating elements in a two-dimensional plane on a silicon substrate. In order to increase the storage capacity of the memory, the size of one element can only be reduced (miniaturized). However, in recent years, the miniaturization has become difficult in terms of cost and technology. For miniaturization, photolithography technology needs to be improved. For example, in the current ArF immersion exposure technology, the rule near 40 nm is the resolution limit, and for further miniaturization, EUV exposure is required. It is necessary to introduce a machine. However, the EUV exposure apparatus is expensive, and it is not realistic when considering the cost. Even if miniaturization is achieved, it is expected that physical limits such as breakdown voltage between elements will be reached unless the drive voltage is scaled. That is, there is a high possibility that operation as a device is difficult.

  In recent years, therefore, many semiconductor memory devices in which memory cells are arranged three-dimensionally have been proposed in order to increase the degree of memory integration (see Patent Documents 1 to 3).

  As one of conventional semiconductor memory devices in which memory cells are arranged three-dimensionally, there is a semiconductor memory device using a transistor having a cylindrical structure (Patent Documents 1 to 3). In a semiconductor memory device using a transistor having a columnar structure, a stacked conductive layer and a pillar-shaped columnar semiconductor that are stacked in multiple layers to be a gate electrode are provided. The columnar semiconductor functions as a channel (body) portion of the transistor. A memory gate insulating layer capable of storing electric charge is provided around the columnar semiconductor. A configuration including these stacked conductive layers, columnar semiconductors, and memory gate insulating layers is called a memory string.

Also in the semiconductor memory device having the memory string, a capacitive element is always required as in the conventional case. The capacitor element is used for boosting the voltage of the semiconductor memory device or as a protection element. In the capacitor element, the occupation area is required to be reduced similarly to the memory cell. However, in the case of a nonvolatile semiconductor memory device, since a high voltage is used for data writing or the like, a large capacity capacitor element is required. That is, the capacitive element used in the conventional nonvolatile semiconductor memory device occupies a larger area than other semiconductor devices.
JP 2007-266143 A US Pat. No. 5,599,724 US Pat. No. 5,707,885

  The present invention provides a nonvolatile semiconductor memory device in which the area occupied by a capacitor element is reduced.

A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series, and a capacitor element region that forms a capacitor element. The memory strings are stacked on a substrate, and a plurality of first conductive layers functioning as control gates of the memory cells, and a plurality of first conductive layers formed between the top and bottom of the plurality of first conductive layers. One interlayer insulating layer, a plurality of first conductive layers and a semiconductor layer formed so as to penetrate through the plurality of first interlayer insulating layers, and formed between the first conductive layer and the semiconductor layer and a charge storage layer insulating film, the capacitor element region includes a plurality of second conductive layers stacked on the substrate were and formed on the first conductive layer and the same layer, the plurality of second conductive layer Formed between the upper and lower sides of A first interlayer insulating layer and a plurality of second interlayer insulating layers formed in the same layer, and one of the two second conductive layers stacked adjacent to each other is connected to a first potential; The other of the two second conductive layers stacked adjacent to each other is connected to a second potential different from the first potential, the two stacked second conductive layers stacked adjacent to each other, and The second interlayer insulating layer between the two second conductive layers constitutes the capacitive element.

  The present invention can provide a nonvolatile semiconductor memory device in which the area occupied by the capacitor element is reduced.

  Hereinafter, an embodiment of a nonvolatile semiconductor memory device according to the present invention will be described with reference to the drawings.

[First Embodiment]
(Configuration of Nonvolatile Semiconductor Memory Device 100 according to First Embodiment)
FIG. 1 is a schematic view of a nonvolatile semiconductor memory device 100 according to the first embodiment of the present invention. As shown in FIG. 1, the nonvolatile semiconductor memory device 100 according to the first embodiment mainly includes a memory transistor region 12, a word line driving circuit 13, a source side selection gate line (SGS) driving circuit 14, and a drain side selection gate. It has a line (SGD) drive circuit 15, a sense amplifier (not shown), and a capacitor element region C. The memory transistor region 12 includes a memory transistor that stores data. The word line drive circuit 13 controls the voltage applied to the word line (first conductive layer) WL. The source side select gate line (SGS) drive circuit 14 controls the voltage applied to the source side select gate line SGS. The drain side select gate line (SGD) drive circuit 15 controls the voltage applied to the drain side select gate line (SGD). The sense amplifier amplifies the potential read from the memory transistor. The capacitive element region C constitutes a capacitive element used for boosting a voltage used for driving the nonvolatile semiconductor memory device 100 or as a protective element. In addition to the above, the nonvolatile semiconductor memory device 100 according to the first embodiment includes a bit line driving circuit that controls a voltage applied to the bit line BL and a source line driving circuit that controls a voltage applied to the source line SL ( (Not shown).

  As shown in FIG. 1, in the nonvolatile semiconductor memory device 100 according to the first embodiment, the memory transistor constituting the memory transistor region 12 is formed by stacking a plurality of semiconductor layers.

  FIG. 2 is a schematic perspective view of a part of the memory transistor region 12 of the nonvolatile semiconductor memory device 100 according to the first embodiment. In the first embodiment, the memory transistor region 12 includes m × n memory strings MS (m and n are natural numbers) including memory transistors (MTr1mn to MTr4mn), a source side selection transistor SSTrmn, and a drain side selection transistor SDTrmn. Have. FIG. 2 shows an example of m = 3 and n = 4.

  The word lines WL1 to WL4 connected to the gates of the memory transistors MTr1mn to MTr4mn of each memory string MS are each formed of the same conductive layer via an interlayer insulating layer (first interlayer insulating layer). It is common. That is, all the gates of the memory transistors MTr1mn of each memory string MS are connected to the word line WL1. Further, all the gates of the memory transistors MTr2mn of each memory string MS are connected to the word line WL2. Further, all the gates of the memory transistors MTr3mn of each memory string MS are connected to the word line WL3. Further, all the gates of the memory transistors MTr4mn of each memory string MS are connected to the word line WL4. In the nonvolatile semiconductor memory device 100 according to the first embodiment, as shown in FIGS. 1 and 2, the word lines WL <b> 1 to WL <b> 4 each extend two-dimensionally in the horizontal direction parallel to the semiconductor substrate Ba. It is formed as follows. Further, the word lines WL1 to WL4 are respectively disposed substantially perpendicular to the memory strings MS. Further, the end portions in the row direction of the word lines WL1 to WL4 are formed in a step shape. Here, the row direction is a direction orthogonal to the vertical direction, and the column direction is a direction orthogonal to the vertical direction and the row direction.

  Each memory string MS has a columnar columnar semiconductor CLmn (in the case of FIG. 2, m = 1 to 3, n = 1) on an n + region (Ba2 described later) formed in the P-well region Ba1 of the semiconductor substrate Ba. To 4). Each columnar semiconductor CLmn is formed in the vertical direction from the semiconductor substrate Ba, and is arranged in a matrix on the surface of the semiconductor substrate Ba and the word lines (WL1 to WL4). That is, the memory strings MS are also arranged in a matrix in a plane perpendicular to the columnar semiconductor CLmn. The columnar semiconductor CLmn may be cylindrical or prismatic. The columnar semiconductor CLmn includes a columnar semiconductor having a stepped shape.

  Further, as shown in FIG. 2, a rectangular plate-shaped drain-side selection gate line SGD that forms a drain-side selection transistor SDTrmn in contact with the columnar semiconductor CLmn via an insulating layer (not shown) is disposed above the memory string MS. (In the case shown in FIG. 2, SGD1 to SGD4) are provided. Each drain-side selection gate line SGD is insulated and separated from each other, and is formed in a line extending in the row direction and repeatedly provided in the column direction, unlike the word lines WL1 to WL4. A columnar semiconductor CLmn is provided so as to penetrate the center in the column direction of the drain-side selection gate line SGD.

  As shown in FIG. 2, a source-side selection gate line SGS that constitutes a source-side selection transistor SSTrmn is provided below the memory string MS so as to be in contact with the columnar semiconductor CLmn via an insulating layer (not shown). Yes. The source side select gate line SGS is formed so as to expand two-dimensionally in the horizontal direction, like the word lines WL1 to WL4. In addition to the structure shown in FIG. 2, the source side select gate line SGS may have a strip shape extending in the row direction and repeatedly provided in the column direction.

  Next, with reference to FIG. 2 and FIG. 3, a circuit configuration constituted by the memory string MS in the first embodiment and its operation will be described. FIG. 3 is a circuit diagram of one memory string MS in the first embodiment.

  As shown in FIGS. 2 and 3, in the first embodiment, the memory string MS includes four memory transistors MTr1mn to MTr4mn, a source side selection transistor SSTrmn, and a drain side selection transistor SDTrmn. The four memory transistors MTr1mn to MTr4mn, the source side select transistor SSTrmn, and the drain side select transistor SDTrmn are connected in series (see FIG. 3). In the memory string MS of the first embodiment, the columnar semiconductor CLmn is formed in the n + region formed in the P− type region (P-well region) Ba1 on the semiconductor substrate Ba.

  A source line SL (n + region formed in the P-well region Ba1 of the semiconductor substrate Ba) is connected to the source of the source side select transistor SSTrmn. A bit line BL is connected to the drain of the drain side select transistor SDTrmn.

  Each memory transistor MTrmn has a columnar semiconductor CLmn, a charge storage layer formed so as to surround the columnar semiconductor CLmn, and a word line WL formed so as to surround the charge storage layer. The word line WL functions as a control gate of the memory transistor MTrmn.

  In the nonvolatile semiconductor memory device 100 having the above configuration, the voltages of the bit lines BL1 to BL3, the drain side selection gate line SGD, the word lines WL1 to WL4, the source side selection gate line SGS, and the source line SL are the bit line drive circuit. (Not shown), controlled by a drain side selection gate line driving circuit 15, a word line driving circuit 13, a source side selection gate line driving circuit 14, and a source line driving circuit (not shown). That is, data is read, written, and erased by controlling the charge in the charge storage layer of a predetermined memory transistor MTrmn.

  Next, the configuration of the capacitive element region C will be described with reference to FIGS. 4 is a partial schematic cross-sectional view of the capacitive element region C, and FIG. 5 is a top view thereof. The capacitive element region C includes capacitive lines (second conductive layers) CpL1 to CpL4 extending in the row and column directions, first and second contact lines CL1 and CL2 connected to the capacitive lines CpL1 to CpL4 and extending upward, and first , First and second wirings L1, L2 connected to the upper ends of the second contact lines CL1, CL2.

  The capacitive lines CpL1 to CpL4 are stacked one above the other with an interlayer insulating layer (second interlayer insulating layer) interposed therebetween. The ends in the row direction of the capacitance lines CpL1 to CpL4 are formed in a stepped shape.

  The first contact line CL1 is connected to the end in the row direction of the second capacitive line CpL2 from the lower layer. The first contact line CL1 is connected to the end in the row direction of the fourth capacitance line CpL4 from the lower layer.

  The second contact line CL2 is connected to the end in the row direction of the first capacitor line CpL1 from the lower layer. The second contact line CL2 is connected to the end of the third capacitor line CpL3 from the lower layer in the row direction.

  The first wiring L1 is connected to the upper end of the first contact line CL1. The first wiring L1 is connected to a predetermined potential. Accordingly, the capacitor line CpL2 and the capacitor line CpL4 are connected to a predetermined potential via the first contact line CL1. Here, the predetermined potential is, for example, 2.5V.

  The second wiring L2 is connected to the upper end of the second contact line CL2. The second wiring L2 is connected to the ground potential. Therefore, the capacitance line CpL1 and the capacitance line CpL3 are connected to the ground potential via the second contact line CL2.

  With the above configuration, the capacitive element Cp1 is configured in which the capacitive line CpL1 and the capacitive line CpL2 are the upper and lower electrodes, and the interlayer insulating layer between the capacitive line CpL1 and the capacitive line CpL2 is a dielectric film. In addition, the capacitive element Cp2 is configured in which the capacitive line CpL2 and the capacitive line CpL3 are the upper and lower electrodes, and the interlayer insulating layer between the capacitive line CpL2 and the capacitive line CpL3 is a dielectric film. In addition, the capacitive element Cp3 is configured in which the capacitive line CpL3 and the capacitive line CpL4 are the upper and lower electrodes, and the interlayer insulating layer between the capacitive line CpL3 and the capacitive line CpL4 is a dielectric film.

(Specific Configuration of Nonvolatile Semiconductor Memory Device 100 According to First Embodiment)
Next, a more specific configuration of the nonvolatile semiconductor memory device 100 will be described with reference to FIGS. 6 is a specific cross-sectional view of the memory transistor region 12 of the nonvolatile semiconductor memory device 100 according to the first embodiment, and FIG. 7 is a partially enlarged view of FIG. FIG. 8 is a specific cross-sectional view of the capacitive element region C of the nonvolatile semiconductor memory device 100 according to the first embodiment.

  First, the memory transistor region 12 will be described. As shown in FIG. 6, the nonvolatile semiconductor memory device 100 (memory strings MS) includes, in the memory transistor region 12, from the lower layer to the upper layer on the semiconductor substrate Ba, the source side select transistor layer 20, the memory transistor layer 30, and A drain-side selection transistor layer 40 and a wiring layer 50 are provided. The source side select transistor layer 20 functions as the source side select transistor SSTrmn. The memory transistor layer 30 functions as the memory transistor MTrmn. The drain side select transistor layer 40 functions as the drain side select transistor SDTrmn.

  A p-type region (p-well region) Ba1 is formed on the semiconductor substrate Ba. An n + region (source line region) Ba2 is formed on the P− type region Ba1.

  The source side select transistor layer 20 includes a source side first insulating layer 21, a source side conductive layer 22, a source side second insulating layer 23, and a source side isolation insulating layer 24, which are sequentially stacked on the semiconductor substrate Ba.

The source-side first insulating layer 21, the source-side conductive layer 22, the source-side second insulating layer 23, and the source-side isolation / insulation layer 24 have a memory so as to expand two-dimensionally in a horizontal direction parallel to the semiconductor substrate Ba It is formed in the transistor region 12. The source-side first insulating layer 21, the source-side conductive layer 22, the source-side second insulating layer 23, and the source-side isolation / insulating layer 24 are divided into predetermined regions (erase units) in the memory transistor region 12, Sidewall insulating layers 25 are formed at the ends in the row direction and the column direction. An insulating layer 26 is formed from the semiconductor substrate Ba to the upper surface of the source-side isolation / insulation layer 24. −
The source side first insulating layer 21 and the source side second insulating layer 23 are made of silicon oxide (SiO ₂ ). The source side conductive layer 22 is composed of P + type polysilicon (p-Si). The source-side isolation / insulation layer 24 is composed of silicon nitride (SiN).

  A source-side hole 27 is formed so as to penetrate the source-side isolation / insulation layer 24, the source-side second insulation layer 23, the source-side conductive layer 22, and the source-side first insulation layer 21. On the side wall facing the source side hole 27, a source side gate insulating layer 28 and a source side columnar semiconductor layer 29 are sequentially provided.

The source side gate insulating layer 28 is formed of silicon oxide (SiO ₂ ). The source side columnar semiconductor layer 29 is formed of polysilicon (p-Si). Further, the source side columnar semiconductor layer 29 may be composed of N + type polysilicon at the upper part thereof.

  In the configuration of the source side select transistor 20, in other words, the configuration of the source side conductive layer 22 is formed so as to sandwich the source side gate insulating layer 28 together with the source side columnar semiconductor layer 29. Yes.

  In the source side select transistor layer 20, the source side conductive layer 22 functions as the source side select gate line SGS. Further, the source side conductive layer 22 functions as a control gate of the source side select transistor SSTrmn.

  The memory transistor layer 30 includes first to fifth inter-wordline insulating layers (first interlayer insulating layers) 31a to 31e provided above the source-side isolation insulating layer 24 and above the insulating layer 26, and first to first The first to fourth word line conductive layers 32a to 32d (first conductive layer) provided above and below the five word line insulating layers 31a to 31e and the fifth inter word line insulating layer 31e are sequentially stacked. A memory isolation / insulation layer 33 a and a memory protection insulation layer 33 are provided.

  The first to fifth inter-word line insulating layers 31a to 31e, the first to fourth word line conductive layers 32a to 32d, and the memory isolation insulating layer 33a are two-dimensionally expanded in the row direction and the column direction. It is formed and is stepped at the end in the row direction. The memory protection insulating layer 33 includes first to fifth inter-word line insulating layers 31a to 31e, first to fourth word line conductive layers 32a to 32d, and end portions in the row direction and column direction of the memory isolation insulating layer 33a. It is formed so as to cover the end. Further, in the memory transistor layer 30, from the upper portion of the memory protection insulating layer 33 formed on the upper surface of the first inter-wordline insulating layer 31a to the upper portion of the memory protection insulating layer 33 formed on the upper surface of the memory isolation insulating layer 33a. An insulating layer 34 is formed.

The first to fifth inter-wordline insulating layers 31a to 31e are composed of silicon oxide (SiO ₂ ). The first to fourth word line conductive layers 32a to 32d are composed of P + type polysilicon (p-Si). The memory isolation / insulation layer 33a and the memory protection insulation layer 33 are made of silicon nitride (SiN).

  In the memory transistor layer 30, the memory hole 35 penetrates the memory isolation / insulation layer 33a, the first to fifth inter-wordline insulating layers 31a to 31e, and the first to fourth wordline conductive layers 32a to 32d. Is formed. The memory hole 35 is provided at a position aligned with the source side hole 27. A memory gate insulating layer 36 and a memory columnar semiconductor layer 37 are sequentially provided on the side wall in the memory side hole 35.

  The memory gate insulating layer 36 is configured as shown in FIG. As shown in FIG. 7, the memory gate insulating layer 36 includes a tunnel insulating layer 36a, a charge storage layer 36b for storing charges, and a block insulating layer 36c sequentially from the side wall of the columnar semiconductor layer 37.

The tunnel insulating layer 36a and the block insulating layer 36c are formed of silicon oxide (SiO ₂ ). The charge storage layer 36b is formed of silicon nitride (SiN). The memory columnar semiconductor 37 is made of polysilicon (p-Si). Further, the memory columnar semiconductor layer 37 may be composed of N + type polysilicon at the upper part thereof.

  In other words, in the memory transistor 30, in other words, the first to fourth word line conductive layers 32 a to 32 d are configured such that the first to fourth word line conductive layers 32 a to 32 d include the tunnel insulating layer 36 a together with the memory columnar semiconductor layer 37. The charge storage layer 36b and the block insulating layer 36c are formed therebetween.

  In the memory transistor layer 30, the first to fourth word line conductive layers 32a to 32d function as the word lines WL1 to WL4. The first to fourth word line conductive layers 32a to 32d function as control gates of the memory transistor MTrmn.

  The drain side select transistor layer 40 includes a drain side first insulating layer 41, a drain side conductive layer 42, a drain side second insulating layer 43, and a drain side isolation insulating layer 44 that are sequentially stacked on the memory protection insulating layer 33. .

  The drain-side first insulating layer 41, the drain-side conductive layer 42, the drain-side second insulating layer 43, and the drain-side isolation insulating layer 44 are provided at positions aligned with the upper portion of the memory columnar semiconductor layer 37 and extend in the row direction. It is formed in a line shape repeatedly provided in the column direction. In the drain side select transistor layer 40, an insulating layer 45 is formed from the upper surface of the insulating layer 34 to a predetermined height above the drain side isolation insulating layer 44.

The drain side first insulating layer 41 and the drain side second insulating layer 43 are formed of silicon oxide (SiO ₂ ). The drain side conductive layer 42 is formed of P + type polysilicon (p-Si). The drain-side isolation / insulation layer 44 is formed of silicon nitride (SiN).

  Further, in the drain side select transistor layer 40, the drain side isolation insulating layer 44, the drain side second insulating layer 43, the drain side conductive layer 42, the drain side first insulating layer 41, and the memory protection insulating layer 33 are penetrated. A drain side hole 46 is formed. The drain side hole 46 is provided at a position aligned with the memory hole 35. A drain side gate insulating layer 47 and a drain side columnar semiconductor layer 48 are sequentially provided on the side wall facing the drain side hole 46.

The drain side gate insulating layer 47 is formed of silicon oxide (SiO ₂ ). The drain side columnar semiconductor layer 48 is formed of polysilicon (p-Si). The upper part of the drain side columnar semiconductor layer 48 is made of n + type polysilicon.

  In the configuration of the drain side select transistor 40, in other words, the configuration of the drain side conductive layer 42 is formed so as to sandwich the drain side gate insulating layer 47 together with the drain side columnar semiconductor layer 48. Yes.

  In the drain side select transistor 40, the drain side conductive layer 42 functions as the drain side select gate line SGD. Further, the drain side conductive layer 42 functions as a control gate of the drain side select transistor SDTrmn.

  Plug holes 61 a to 61 h are formed in the source side select transistor layer 20, the memory transistor layer 30, and the drain side select transistor layer 40.

  Plug hole 61a is formed to reach n + region (source line region) Ba2. The plug hole 61 b is formed so as to reach the upper surface of the source side conductive layer 22. Plug holes 61c to 61f are formed so as to reach the upper surfaces of first to fourth word line conductive layers 32a to 32d. The plug hole 61g is formed so as to reach the upper surface of the drain side conductive layer. The plug hole 61 h is formed so as to reach the drain side columnar semiconductor layer 48.

  A barrier metal layer 62 and a plug conductive layer 63 are sequentially formed on the side walls facing the plug holes 61a to 61h. The barrier metal layer 62 is composed of titanium-titanium nitride (Ti-TiN). The plug conductive layer 63 is made of tungsten (W).

The wiring layer 50 includes wiring first to fourth insulating layers 51 to 54 sequentially stacked on the upper surface of the insulating layer 45. The wiring first insulating layer 51 and the wiring fourth insulating layer 54 are made of silicon nitride (SiN). The wiring second insulating layer 52 and the wiring third insulating layer 53 are made of silicon oxide (SiO ₂ ).

  Further, the wiring layer 50 has a wiring groove 56a. The wiring groove 56 a is formed so as to penetrate the wiring first insulating layer 51 and the wiring second insulating layer 52. The wiring groove 56a is provided at a position aligned with the plug holes 61a to 61h.

  A barrier metal layer 56b and a wiring conductive layer 56c are sequentially formed on the side wall facing the wiring groove 56a. The barrier metal layer 56b is composed of titanium-titanium nitride (Ti-TiN). The wiring conductive layer 56c is made of tungsten (W).

  Next, the capacitive element region C will be described. As shown in FIG. 8, in the capacitive element region C, the nonvolatile semiconductor memory device 100 includes a first insulating layer 81, a capacitive element layer 70, and second to sixth insulating layers on the semiconductor substrate Ba from the lower layer to the upper layer. It has layers 82-86. The capacitive element layer 70 constitutes capacitive elements Cp1 to Cp3.

The first insulating layer 81 is composed of silicon oxide (SiO ₂ ). The first insulating layer 81 is formed up to the upper surface of the source-side isolation / insulation layer 24 in the memory transistor region 12.

  The capacitive element layer 70 includes first to fifth capacitive element insulating layers (first interlayer insulating layers) 71a to 71e and first to fourth capacitive element conductive layers (first conductive layers) 72a to 72d that are alternately stacked. Have

  The second capacitor element insulating layer 71b and the first capacitor element conductive layer 72a are formed with their end portions in the row direction aligned. The third capacitor element insulating layer 71c and the second capacitor element conductive layer 72b are formed with their end portions in the row direction aligned. The fourth capacitor element insulating layer 71d and the third capacitor element conductive layer 72c are formed with their end portions in the row direction aligned. The fifth capacitor element insulating layer 71e and the fourth capacitor element conductive layer 72d are formed with their end portions in the row direction aligned. The row direction end portions of the second to fifth capacitor element insulating layers 71b to 71e and the row direction end portions of the first to fourth capacitor element conductive layers 72a to 72d are formed in a step shape.

The first to fifth capacitor element insulating layers 71a to 71e are made of silicon oxide (SiO ₂ ). The first to fourth capacitor element conductive layers 72a to 72d are made of polysilicon (p-Si).

  The first to fifth capacitor element insulating layers 71a to 71e are formed in the same layer as the first to fifth inter-wordline insulating layers 31a to 31e. The first to fourth capacitor element conductive layers 72a to 72d are formed in the same layer as the first to fourth word line conductive layers 32a to 32d.

  The second insulating layer 82 covers the capacitive element layer 70 and is formed up to the upper surface of the insulating layer 45. The third insulating layer 83 is formed from the second insulating layer 82 to the upper surface of the wiring first insulating layer 51. The fourth insulating layer 84 is formed from the third insulating layer 83 to the upper surface of the wiring second insulating layer 52. The fifth insulating layer 85 is formed from the fourth insulating layer 84 to the upper surface of the wiring third insulating layer 53. The sixth insulating layer 86 is formed from the fifth insulating layer 85 to the upper surface of the wiring fourth insulating layer 54.

The second, fourth, and fifth insulating layers 82, 84, and 85 are made of silicon oxide (SiO ₂ ). The third and sixth insulating layers 83 and 86 are made of silicon nitride (SiN).

  Contact holes 91 a to 91 d are formed in the capacitor element layer 70 and the second insulating layer 82. The contact hole 91a is formed to reach the second capacitor element conductive layer 72b. The contact hole 91b is formed so as to reach the fourth capacitor element conductive layer 72d. The contact hole 91c is formed so as to reach the first capacitor element conductive layer 72a. The contact hole 91d is formed so as to reach the third capacitor element conductive layer 72c.

  Contact conductive layers 92 are formed in the contact holes 91a to 91d. The contact conductive layer 92 is composed of titanium-titanium nitride (Ti-TiN) and tungsten (W).

  In the second and third insulating layers 82 and 83, a first wiring groove 94a and a second wiring groove 94b are formed. The first wiring groove 94a is formed above the contact holes 91a and 91b. The second wiring groove 94b is formed above the contact holes 91c and 91d.

  A first wiring conductive layer 95a and a second wiring conductive layer 95b are formed in the first wiring groove 94a and the second wiring groove 94b. The first wiring conductive layer 95a and the second wiring conductive layer 95b are composed of titanium-titanium nitride (Ti-TiN) and tungsten (W).

  The first wiring conductive layer 95a is connected to a predetermined potential. The second wiring conductive layer 95b is connected to the ground potential. Here, the predetermined potential is, for example, 2.5V. Accordingly, the first capacitor element conductive layer 72a and the third capacitor element conductive layer 72c are connected to the ground potential, and the second capacitor element conductive layer 72b and the fourth capacitor element conductive layer 72d are connected to the predetermined potential. Yes.

  With the above configuration, a capacitive element is configured in which the first capacitive element conductive layer 72a and the second capacitive element insulating layer 71b are upper and lower electrodes and the second capacitive element conductive layer 72b is a dielectric film. In addition, a capacitive element is configured in which the second capacitive element conductive layer 72b and the third capacitive element insulating layer 71c are upper and lower electrodes, and the fourth capacitive element conductive layer 72c is a dielectric film. Further, a capacitive element is configured in which the third capacitive element conductive layer 72c and the second capacitive element insulating layer 71d are upper and lower electrodes, and the fourth capacitive element conductive layer 72d is a dielectric film.

  That is, the first to fourth capacitive element conductive layers 72a to 72d function as the capacitive lines CpL1 to CpL4. The first to fifth capacitor element insulating layers 71a to 71e function as interlayer insulating layers between the capacitor lines CpL1 to CpL4. Contact conductive layer 92 in contact holes 91a and 91b functions as first contact line CL1. The contact conductive layer 92 in the contact holes 91c and 91d functions as the second contact line CL2. The first wiring conductive layer 95a functions as the first wiring L1. The second wiring conductive layer 95b functions as the second wiring L2.

(Effect of Nonvolatile Semiconductor Memory Device 100 According to First Embodiment)
Next, effects of the nonvolatile semiconductor memory device 100 according to the first embodiment will be described. The nonvolatile semiconductor memory device 100 according to the first embodiment can be highly integrated as shown in the stacked structure. In addition, as described in the above manufacturing process, the nonvolatile semiconductor memory device 100 includes each layer that becomes the memory transistor MTrmn, each source-side selection transistor SSTrmn, and each layer that becomes the drain-side selection transistor layer SDTrmn regardless of the number of stacked layers. It can be manufactured with a predetermined number of lithography steps. That is, the nonvolatile semiconductor memory device 100 can be manufactured at a low cost.

  In addition, the nonvolatile semiconductor memory device 100 according to the first embodiment of the present invention has a capacitive element region C. The capacitive element region C includes the laminated first to fifth capacitive element insulating layers 71a to 71e (word lines WL1 to WL4) and the first to fourth capacitive element conductive layers 72a to 72d. Cp1 to Cp3 are configured. Therefore, the nonvolatile semiconductor memory device 100 according to the first embodiment can reduce the occupation area of the capacitive elements Cp1 to Cp3.

  The first to fifth capacitor element insulating layers 71a to 71e are formed in the same layer as the first to fifth inter-wordline insulating layers 31a to 31e. The first to fourth capacitor element conductive layers 72a to 72d are formed in the same layer as the first to fourth word line conductive layers 32a to 32d. Therefore, the capacitive elements Cp1 to Cp4 can be formed in substantially the same process as the memory transistor MTrmn. That is, the nonvolatile semiconductor memory device 100 according to the first embodiment can improve the yield.

[Second Embodiment]
(Configuration of Nonvolatile Semiconductor Memory Device According to Second Embodiment)
Next, the configuration of the nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a partial schematic cross-sectional view of the capacitive element region Ca of the nonvolatile semiconductor memory device according to the second embodiment, and FIG. 10 is a top view thereof. Note that in the second embodiment, identical symbols are assigned to configurations similar to those in the first embodiment and descriptions thereof are omitted.

  As shown in FIGS. 9 and 10, the nonvolatile semiconductor memory device according to the second embodiment has a capacitive element region Ca different from that of the first embodiment. In the capacitive element region Ca, the configurations of the first contact line CL1 'and the second contact line CL2' are different from those of the first embodiment.

  The first contact line CL1 'is connected to the second capacitive line CpL2 from the lower layer. The first contact line CL1 'is connected to the third capacitor line CpL3 from the lower layer. These first contact lines CL1 'are connected to the first wiring L1. Accordingly, the capacitor line CpL2 and the capacitor line CpL3 are connected to a predetermined potential via the first contact line CL1 '.

  The second contact line CL2 'is connected to the first capacitor line CpL1 from the lower layer. The second contact line CL2 'is connected to the fourth capacitive line CpL4 from the lower layer. These second contact lines CL2 'are connected to the second wiring L2. Accordingly, the capacitor line CpL1 and the capacitor line CpL4 are connected to the ground potential via the second contact line CL2 '.

  With the above configuration, the capacitive element Cp4 is configured in which the capacitive line CpL1 and the capacitive line CpL2 are the upper and lower electrodes, and the interlayer insulating layer between the capacitive line CpL1 and the capacitive line CpL2 is a dielectric film. In addition, a capacitive element Cp5 is configured in which the capacitive line CpL3 and the capacitive line CpL4 are the upper and lower electrodes, and the interlayer insulating layer between the capacitive line CpL3 and the capacitive line CpL4 is a dielectric film.

(Effects of Nonvolatile Semiconductor Memory Device According to Second Embodiment)
Next, effects of the nonvolatile semiconductor memory device according to the second embodiment will be described. From the above configuration, the nonvolatile semiconductor memory device according to the second embodiment has the same effects as those of the first embodiment.

[Third Embodiment]
(Configuration of Nonvolatile Semiconductor Memory Device According to Third Embodiment)
Next, the configuration of the nonvolatile semiconductor memory device according to the third embodiment of the present invention will be described with reference to FIGS. FIG. 11 is a schematic top view of the nonvolatile semiconductor memory device according to the third embodiment. 12 is a cross-sectional view taken along the line II ′ of FIG. 11, and FIG. 13 is a cross-sectional view taken along the line II-II ′ of FIG. Note that in the third embodiment, identical symbols are assigned to configurations similar to those in the first and second embodiments and descriptions thereof are omitted.

  As shown in FIG. 11, the nonvolatile semiconductor memory device according to the third embodiment includes a memory transistor region 12a having a plurality of memory strings MSa and a capacitor element region Cb having a capacitor element. In the memory transistor region 12a, the memory strings MSa are repeatedly provided with a predetermined pitch in the column direction so as to sandwich the insulating layer. The capacitive element region Cb is provided so that both ends in the column direction and the row direction are sandwiched between insulating layers.

  As shown in FIG. 12, a pair of first stacked portions 110A and 110B are formed on the semiconductor substrate 300 in the memory transistor region 12a. A second stacked unit 120A and a third stacked unit 130A are stacked on the first stacked unit 110A. Similarly, the second stacked unit 120B and the third stacked unit 130B are stacked on the first stacked unit 110B. The first stacked unit 110A (second stacked unit 120A and third stacked unit 130A) and the first stacked unit 110B (second stacked unit 120B and third stacked unit 130B) are separated by a predetermined length in the row direction. Is formed. The outer periphery of the first stacked unit 110A (second stacked unit 120A, third stacked unit 130A) and the first stacked unit 110B (second stacked unit 120B, third stacked unit 130B) includes an insulating layer 140, an insulating layer 150, And an insulating layer 151 is deposited.

  110 A of 1st laminated parts are the 1st-4th word line conductive layers 111a-111d (1st conductive layer) and the 1st-4th word line insulating layers 112a-112d (1st interlayer insulating layer) from a lower layer. Are alternately stacked.

  The first stacked unit 110B includes, from the bottom, the fifth to eighth word line conductive layers (first conductive layers) 111e to 111h and the fifth to eighth word line insulating layers (first interlayer insulating layers) 112e to 112h. Are alternately stacked.

  Each of the first to eighth word line conductive layers 111a to 111h functions in the same manner as the word line WL described above. Each of the first to eighth word line conductive layers 111a to 111h functions in the same manner as the control gate of each memory transistor MTrmn described above.

  Each of the first to eighth word line conductive layers 111a to 111h is made of polysilicon (p-Si). The first to fourth word line conductive layers 111a to 111d and the fifth to eighth word line conductive layers 111e to 111h are provided at the end of the row direction opposite to the opposite side of the first stacked portions 110A and 110B. And a silicide layer 111A.

The first to eighth inter-wordline insulating layers 112a to 112h are composed of silicon oxide (SiO ₂ ).

  Each of the first stacked portions 110A and 110B has a block insulating layer 113, a charge storage layer 114, a tunnel insulating layer 115, N− on the side surface where the first stacked portions 110A and 110B face each other with the insulating layer 140 therebetween. A type semiconductor layer 116 is included.

The block insulating layer 113 is formed in contact with the side walls of the first to eighth word line conductive layers 111a to 111h and the first to eighth inter-word line insulating layers 112a to 112h. The block insulating layer 113 is composed of silicon oxide (SiO ₂ ). The charge storage layer 114 is provided in contact with the block insulating layer 113 and is formed so as to store charges. The charge storage layer 114 is composed of silicon nitride (SiN). The tunnel insulating layer 115 is provided in contact with the charge storage layer 114. The tunnel insulating layer 115 is made of silicon oxide (SiO ₂ ).

  The N − type semiconductor layer 116 has a U-shaped cross-sectional shape in the I-I ′ direction. The N − -type semiconductor layer 116 connects the side portions 116 a and 116 a provided in contact with each tunnel insulating layer 115 and extending in the stacking direction (pillar shape) and the bottoms of the pair of side portions 116 a and 116 a. The bottom portion 116b is formed as described above. Note that the N − type semiconductor layer 116 is formed of a semiconductor layer into which a low concentration N − type impurity is introduced.

  The second stacked unit 120A includes a drain-side first insulating layer 121a, a drain-side conductive layer 122a, and a drain-side second insulating layer 123a that are sequentially stacked on the first stacked unit 110A (fourth word line conductive layer 111d). Have. The drain side conductive layer 122a functions in the same manner as the drain side select gate line SGD described above. The drain side conductive layer 122a functions in the same manner as the control gate of the drain side select transistor SDT described above.

The drain side first insulating layer 121a and the drain side second insulating layer 123a are made of silicon oxide (SiO ₂ ). The drain side conductive layer 122a is made of polysilicon (p-Si). The drain-side conductive layer 122a has a silicide layer 122A at the end opposite to the opposite side of the second stacked portions 120A and 120B in the row direction.

  The second stacked unit 120B includes a source-side first insulating layer 121b, a source-side conductive layer 122b, and a source-side second insulating layer 123b that are sequentially stacked on the first stacked unit 110B (eighth word line conductive layer 111h). Have. The source side conductive layer 122b functions in the same manner as the source side select gate line SGS described above. The source side conductive layer 122b functions similarly to the control gate of the source side select transistor SST described above.

The source side first insulating layer 121b and the source side second insulating layer 122b are made of silicon oxide (SiO ₂ ). The source side conductive layer 122b is composed of polysilicon (p-Si). The source-side conductive layer 122b has a silicide layer 122A at the end opposite to the opposite side of the second stacked portions 120A and 120B in the row direction.

  Each of the second stacked portions 120A and 120B has a gate insulating layer 124, a P− type semiconductor layer 125, and an N + type semiconductor on the side surface where the drain side conductive layer 122a and the source side conductive layer 122b face each other with the insulating layer 140 interposed therebetween. It has a layer 126.

  The gate insulating layer 124 is provided in contact with the side wall of the drain side conductive layer 122a, the side wall of the drain side second insulating layer 123a, the side wall of the source side conductive layer 122b, and the side wall of the source side second insulating layer 123b. The P − type semiconductor layer 125 is provided in the same layer as the drain side conductive layer 122a and the source side conductive layer 122b in the stacking direction. The P − type semiconductor layer 125 is provided in contact with the side surface of the gate insulating layer 124 and the upper surface of the N − type semiconductor layer 116. The P− type semiconductor layer 125 is a semiconductor layer into which a low concentration P− type impurity is introduced. The N + type semiconductor layer 126 is provided in contact with the side surface of the gate insulating layer 124 and the upper surface of the P− type semiconductor layer 125.

  Each of the third stacked units 130A and 130B includes a contact layer 131 formed on the drain side second insulating layer 123a and on the source side second insulating layer 123b.

  One end of the contact layer 131 is formed in contact with the upper part of the N + type semiconductor layer 126. The contact layer 131 is formed in a rectangular plate shape whose longitudinal direction is the row direction. The contact layer 131 is composed of a silicide layer.

  Furthermore, the third stacked unit 130 </ b> A includes a contact plug layer 132 provided on the upper surface of the contact layer 131 and a wiring layer 133 provided on the upper surface of the contact plug layer 132.

  The wiring layer 133 is formed so as to straddle and contact the upper surface of the contact plug layer 132 in the plurality of second stacked portions 120A. The wiring layer 133 functions in the same manner as the bit line BL described above.

  The third stacked unit 130 </ b> B includes a wiring layer 134 provided on the upper surface of the contact layer 131. The wiring layer 134 is formed on the upper surface of the contact layer 131. The wiring layer 134 is formed so as to straddle and contact the upper surface of the contact layer 131 in the plurality of second stacked portions 120B arranged in the column direction. The wiring layer 134 functions in the same manner as the source line SL described above. An insulating layer 135 is formed between the bottom surface of the wiring layer 133 and the insulating layers 140 and 150.

  As shown in FIG. 13, in the capacitive element region Cb, the capacitive element layer 210, the first insulating layer 240, the first and second wiring conductive layers 231a and 231b, and the second insulating layer are sequentially formed on the semiconductor substrate 300. 260 is formed. An insulating layer 250 and an insulating layer 251 are deposited on the outer periphery of the capacitor element layer 210, the first insulating layer 240, the first and second wiring conductive layers 231 a and 231 b, and the second insulating layer 260.

  The capacitive element layer 210 includes first to fourth capacitive element insulating layers (second interlayer insulating layers) 211a to 211d and first to fourth capacitive element conductive layers 212a to 212d (stacked alternately on the semiconductor substrate 300). Second conductive layer). The end of the first capacitor element insulating layer 211a in the row direction is formed to be aligned with the end of the first capacitor element conductive layer 212a in the row direction. The end of the second capacitor element insulating layer 211b in the row direction is formed to be aligned with the end of the second capacitor element conductive layer 212b in the row direction. The end of the third capacitor element insulating layer 211c in the row direction is formed to be aligned with the end of the third capacitor element conductive layer 212c in the row direction. The end of the fourth capacitor element insulating layer 211d in the row direction is formed to be aligned with the end of the fourth capacitor element conductive layer 212d in the row direction. The end portions in the row direction of the first to fourth capacitor element insulating layers 211a to 211d and the first to fourth capacitor element conductive layers 212a to 212d are formed in a step shape.

  The first capacitor element insulating layer 211a is formed in the same layer as the first and fifth inter-wordline insulating layers 112a and 112e. The second capacitor element insulating layer 211b is formed in the same layer as the second and sixth inter-wordline insulating layers 112b and 112f. The third capacitor element insulating layer 211c is formed in the same layer as the third and seventh inter-wordline insulating layers 112c and 112g. The fourth capacitor element insulating layer 211d is formed in the same layer as the fourth and eighth inter-wordline insulating layers 112d and 112h.

  The first capacitor element conductive layer 212a is formed in the same layer as the first and fifth word line conductive layers 111a and 111e. The second capacitor element conductive layer 212b is formed in the same layer as the second and sixth word lines 111b and 111f. The third capacitor element conductive layer 212c is formed in the same layer as the third and seventh word line conductive layers 111c and 111g. The fourth capacitor element conductive layer 212d is formed in the same layer as the fourth and eighth word line conductive layers 111d and 111h.

The first to fourth capacitor element insulating layers 211a to 211d are made of silicon oxide (SiO ₂ ). The first to fourth capacitor element conductive layers 212a to 212d are made of polysilicon (p-Si).

  The first insulating layer 240 is formed so as to cover the first to fourth capacitor element insulating layers 211a to 211d and the first to fourth capacitor element conductive layers 212a to 212d. The first insulating layer 240 is formed to the same height as the upper portion of the insulating layer 140.

  The first and second wiring conductive layers 231a and 231b are formed in the same layer as the contact layer 131. The second insulating layer 260 is formed to the same height as the upper surface of the insulating layer 135. The first and second wiring conductive layers 231a and 231b are composed of titanium-titanium nitride (Ti-TiN) and tungsten (W).

  Contact holes 221 a to 221 d are formed in the capacitor element layer 210 and the first insulating layer 240. The contact hole 221a is formed to reach the second capacitor element conductive layer 212b. The contact hole 221b is formed so as to reach the fourth capacitor element conductive layer 212d. The contact hole 221c is formed so as to reach the first capacitor element conductive layer 212a. The contact hole 221d is formed so as to reach the third capacitor element conductive layer 212c.

  A contact conductive layer 222 is formed in the contact holes 221a to 221d. The contact conductive layer 222 is composed of titanium-titanium nitride (Ti-TiN) and tungsten (W).

  A first wiring conductive layer 231a is provided above the contact holes 221a and 221b. A second wiring conductive layer 231b is provided above the contact holes 221c and 221d.

  The first wiring conductive layer 231a is connected to a predetermined potential. The second wiring conductive layer 231b is connected to the ground potential. Accordingly, the first capacitor element conductive layer 212a and the third capacitor element conductive layer 212c are connected to the ground potential, and the second capacitor element conductive layer 212b and the fourth capacitor element conductive layer 212d are connected to the predetermined potential. Yes.

  With the above configuration, a capacitor element in which the first capacitor element conductive layer 212a and the second capacitor element insulating layer 211b are upper and lower electrodes and the second capacitor element conductive layer 212b is a dielectric film is configured. In addition, a capacitor element in which the second capacitor element conductive layer 212b and the third capacitor element insulating layer 211c are used as upper and lower electrodes and the fourth capacitor element conductive layer 212c is used as a dielectric film is configured. In addition, a capacitive element in which the third capacitive element conductive layer 212c and the second capacitive element insulating layer 211d are used as upper and lower electrodes and the fourth capacitive element conductive layer 212d is a dielectric film is configured.

  That is, the first to fourth capacitor element conductive layers 212a to 212d function in the same manner as the capacitor lines CpL1 to CpL4 described above. The first to fourth capacitor element insulating layers 211a to 211d function in the same manner as the interlayer insulating layer between the capacitor lines CpL1 to CpL4 described above. The contact conductive layer 222 in the contact holes 221a and 221b functions in the same manner as the first contact line CL1 described above. The contact conductive layer 222 in the contact holes 221c and 221d functions in the same manner as the second contact line CL2 described above. The first wiring conductive layer 231a functions in the same manner as the first wiring L1 described above. The second wiring conductive layer 231b functions in the same manner as the second wiring L2 described above.

(Effects of Nonvolatile Semiconductor Memory Device According to Third Embodiment)
Next, effects of the nonvolatile semiconductor memory device according to the third embodiment of the invention will be described. The nonvolatile semiconductor memory device according to the third embodiment has the same effects as those of the first and second embodiments.

[Other embodiments]
Although one embodiment of the nonvolatile semiconductor memory device has been described above, the present invention is not limited to the above-described embodiment, and various modifications, additions, substitutions, and the like can be made without departing from the spirit of the invention. Is possible. For example, in the nonvolatile semiconductor memory device according to the third embodiment, the first to fourth capacitor element conductive layers 212a to 212d and the first and second wiring conductive layers 231a and 231b are as in the configuration of the second embodiment. It may be connected.

  Further, the number of stacked word lines WL (word line conductive layers) and capacitor lines Cp (capacitive element conductive layers) is not limited to the number of stacked layers in the embodiment, and may be a multilayer.

  In the first embodiment, the (n + 1) th (n is a natural number greater than or equal to 0) word lines WL1 to WL4 (first to fourth word line conductive layers 32a to 32d) from the lower layer are connected to the ground potential, and from the lower layer The (n + 2) th word lines WL1 to WL4 are connected to a predetermined potential. However, the present invention is not limited to the above-described configuration, and the (n + 1) th WL1 to WL4 from the lower layer may be connected to a predetermined potential, and the (n + 2) WL1 to WL4 from the lower layer may be connected to the ground potential.

  In the second embodiment, the 3n + 1th (n is a natural number of 0 or more) WL1 to WL4 from the lower layer is connected to the ground potential, and the 3n + 2th and 3n + 3th WL1 to WL4 from the lower layer are connected to the predetermined potential. It has a configuration. However, the present invention is not limited to the above configuration, and the 3n + 1 WL1 to WL4 from the lower layer are connected to a predetermined potential, and the 3n + 2 and 3n + 3 WL1 to WL4 from the lower layer are connected to the ground potential. Good.

1 is a schematic configuration diagram of a nonvolatile semiconductor memory device 100 according to a first embodiment of the present invention. 1 is a partial schematic perspective view of a memory transistor region 12 of a nonvolatile semiconductor memory device 100 according to a first embodiment of the present invention. FIG. 3 is a circuit diagram of one memory string MS in the first embodiment of the present invention. 2 is a partial schematic cross-sectional view of a capacitive element region C of the nonvolatile semiconductor memory device 100 in the first embodiment. FIG. 2 is a partial schematic top view of a capacitive element region C of the nonvolatile semiconductor memory device 100 in the first embodiment. FIG. 3 is a specific cross-sectional view of a memory transistor region 12 of the nonvolatile semiconductor memory device 100 according to the first embodiment. FIG. FIG. 7 is a partially enlarged view of FIG. 6. 3 is a specific cross-sectional view of a capacitive element region C of the nonvolatile semiconductor memory device 100 according to the first embodiment. FIG. FIG. 6 is a partial schematic cross-sectional view of a capacitive element region Ca of a nonvolatile semiconductor memory device in a second embodiment. It is a partial schematic top view of the capacitive element region Ca of the nonvolatile semiconductor memory device in the second embodiment. It is a top view of the nonvolatile semiconductor memory device in the third embodiment. FIG. 10 is a specific cross-sectional view of a memory transistor region 12a of a nonvolatile semiconductor memory device in a third embodiment. FIG. 6 is a specific cross-sectional view of a capacitive element region Cb of a nonvolatile semiconductor memory device according to a third embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Nonvolatile semiconductor memory device 12, 12a ... Memory transistor area | region, 13 ... Word line drive circuit, 14 ... Source side selection gate line drive circuit, 15 ... Drain side selection gate line drive circuit, 16 ... Sense amplifier, 20 ... Source side select transistor layer, 30 ... memory transistor layer, 40 ... drain side select transistor layer, 50 ... wiring layer, 110A, 110B ... first stacked portion, 120A, 120B ... second stacked portion, 130A, 130B ... third stacked Part, Ba, 300 ... semiconductor substrate, CLmn ... columnar semiconductor, MTr1-MTr4 ... memory transistor, SSTrmn ... source side select transistor, SDTrmn ... drain side select transistor, C, Ca, Cb ... capacitive element region.

Claims (5)

A nonvolatile semiconductor memory device comprising a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series, and a capacitor element region constituting a capacitor element,
The memory strings are
A plurality of first conductive layers stacked on a substrate and functioning as control gates of the memory cells ;
A plurality of first interlayer insulating layers formed between the top and bottom of the plurality of first conductive layers;
A semiconductor layer formed so as to penetrate through the plurality of first conductive layers and the plurality of first interlayer insulating layers;
A charge storage layer and an insulating film formed between the first conductive layer and the semiconductor layer;
The capacitive element region is
A plurality of second conductive layers stacked on the substrate and formed in the same layer as the first conductive layer;
A plurality of second interlayer insulating layers formed between upper and lower sides of the plurality of second conductive layers and formed in the same layer as the first interlayer insulating layer;
One of the two second conductive layers stacked adjacent to each other is connected to the first potential,
The other of the two second conductive layers stacked adjacent to each other is connected to a second potential different from the first potential,
The non-volatile semiconductor memory device, wherein the adjacent two stacked second conductive layers and the second interlayer insulating layer between the second conductive layers constitute the capacitive element. . A contact layer connected to an end of the second conductive layer and extending in the stacking direction;
The end portions of the plurality of first conductive layers and the end portions of the plurality of second conductive layers are formed stepwise.
The nonvolatile semiconductor memory device according to claim 1, wherein the contact layer is connected to the first potential or the second potential. The n + 1th (n is a natural number of 0 or more) second conductive layer from the lower layer is connected to the first potential,
The nonvolatile semiconductor memory device according to claim 1, wherein the second conductive layer n + 2 from the lower layer is connected to the second potential. The second conductive layer 3n + 1 from the lower layer (n is a natural number of 0 or more) is connected to the first potential,
3. The nonvolatile semiconductor memory device according to claim 1, wherein the second conductive layer of 3n + 2 and 3n + 3 from the lower layer is connected to the second potential. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor layer is formed in a columnar shape or a U-shape.

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