JP4660324B2 - FBC memory device - Google Patents

Description

  The present invention relates to a volatile semiconductor memory device.

  An FBC (Floating Body Cell) is a semiconductor memory device capable of performing a memory operation by accumulating holes in a floating body (floating body) semiconductor layer formed in a MOS (Metal Oxide Semiconductor) transistor (for example, Patent Document 1). reference.). A conventional DRAM (Dynamic Random Access Memory) cell is composed of one transistor and one capacitor, whereas an FBC can perform memory operation with only a transistor without a capacitor structure. Therefore, it is expected as a highly integrated memory device.

  An FBC formed on an SOI (Silicon On Insulator) substrate can reduce the diffusion layer capacitance due to the presence of an insulating film below the source diffusion layer and the drain diffusion layer. A structure is adopted that minimizes the capacitance between the floating p-type semiconductor layers.

On the other hand, when the FBC is formed on the bulk silicon substrate, a floating p-type semiconductor layer is formed on the n-type buried layer, and holes are accumulated in the p-type semiconductor layer. However, compared with the case where the FBC is formed on the SOI substrate, the capacitance between the source and drain diffusion layers and the p-type semiconductor layer increases in the FBC on the bulk silicon substrate. For this reason, there is a problem that the difference between the threshold values of the first data state “1” and the second data state “0” is small and the signal amount is small.
JP 2003-68877 A

  The present invention provides a memory device that can increase a difference between thresholds of a first data state “1” and a second data state “0” in the FBC.

  In one embodiment of the present invention, a substrate, a MOS transistor formed on the substrate, a gate electrode of the MOS transistor is connected to a word line, a drain diffusion layer is connected to a bit line, and a source diffusion layer is connected to a fixed potential line. A floating body that is electrically isolated from the other and can accumulate holes in the substrate, and an electric capacity between the drain diffusion layer and the floating body is between the source diffusion layer and the floating body. It is characterized by being less than the electric capacity.

  According to the present invention, in the FBC, a memory device having a large signal amount can be provided by widening the difference between the threshold values of the first data state “1” and the second data state “0”.

  Examples according to the present invention will be described below.

  A first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a cross-sectional view along the bit line showing the structure of the FBC device according to the first embodiment. The FBC is composed of an n-channel MOS transistor on the silicon substrate 10. An n-type semiconductor layer 20 containing, for example, about 1 × 10 ¹⁸ cm ^{−3 of} phosphorus in the substrate 10 and a p-type semiconductor layer 30 containing, for example, about 3 × 10 ¹⁷ cm ⁻³ to about 1 × 10 ¹⁸ cm ^{−3 of} boron are provided thereon. The p-type semiconductor layer 30 has a floating structure that is electrically insulated from adjacent elements by an element isolation region 90. A gate electrode 50 is formed on the substrate 10 via a gate insulating film 40, and gate sidewalls 60 are formed on both side walls of the gate electrode 50. Further, an n ⁺ -type source diffusion layer 70 and a drain diffusion layer 80 containing approximately 3 × 10 ²⁰ cm ^{−3 of} electrically activated phosphorus are formed in the substrate 10. The source diffusion layer 70 and the drain diffusion layer 80 are formed to such a depth that the bottom of the diffusion layer remains in the region of the p-type semiconductor layer 30 and does not reach the n-type semiconductor layer 20.

  Here, a MOS transistor including the gate insulating film 40, the gate electrode 50, the source diffusion layer 70, and the drain diffusion layer 80 sandwiched between adjacent element isolation regions 90 is defined as one memory cell region 100.

  As shown in FIG. 1, the center line 100 b of the gate electrode 50 in the cross-sectional view is formed at an asymmetric position closer to the drain diffusion layer 80 side than the cell center line 100 a corresponding to the center of the memory cell region 100. As a result, the distance between the gate electrode and the drain diffusion layer end is shorter than the distance between the gate electrode and the source diffusion layer end.

  FIG. 2A is a plan view of the memory cell array according to the first embodiment. In the case of configuring a memory cell array in which FBCs are arranged in a matrix, the gate electrode 50 is continuously formed in one direction, which becomes the word line 50a. The source diffusion layer is connected to the source line 70a, which is a fixed potential line, and is continuously formed in the same direction as the word line 50a. Since this source line 70a is shared by the word lines 50a of two adjacent cells, one source line 70a is formed for two word lines 50a. The bit line 80a is shared with the drain diffusion layer 80 of two adjacent transistors, and is continuously formed in a direction crossing the word line 50a. Bit line 80a is connected to the drain diffusion layer. The transistor is covered with an interlayer insulating film, and a bit line contact 80b electrically connected to the drain diffusion layer is formed thereon. The unit cells 140a patterned in a lattice pattern by the word lines 50a, the source lines 70a, and the bit lines 80a are separated by an insulating region 110.

  For comparison, FIG. 2B shows a plan view when the conventional gate electrode 50 is on the cell center line 100a. Comparing the unit cell 140a of the present invention with the unit cell 140b having a structure symmetrical to the conventional cell center line 100a, this embodiment has the same area as the conventional unit cell. Here, the area of the unit cell 140a does not have to be the same as that of the unit cell 140b in the case of being symmetric with respect to the cell center line, but in this embodiment, a structure symmetric with respect to the cell center line 100a and the gate electrode from the cell center line 100a. When comparing the case where 50 is displaced in the direction of the drain diffusion layer 80, it should be noted that the comparison is made under the same conditions for the area of each unit cell (140a, 140b).

  FIG. 3A shows a cross-sectional shape of the semiconductor memory device according to this embodiment, and particularly shows the concentration distribution of the source diffusion layer 70 and the drain diffusion layer 80. Since the center position of the gate electrode 50 is displaced Δ from the cell center line 100a toward the drain diffusion layer 80, the distance from the center of the gate electrode to the end of the source diffusion layer is increased, and the distance to the end of the drain diffusion layer is decreased. ing. As a result, the dose of the impurity injected into the drain diffusion layer 80 is smaller than the dose of the impurity injected into the source diffusion layer 70, and the concentration distribution is asymmetric with respect to the cell center line 100a. Recognize. For comparison, FIG. 3B shows a symmetric structure with respect to the conventional cell center line 100a.

ここで、図４では説明をわかりやすくするために表１とは異なるバイアス条件を用いていることに留意すべきである。ここで、第一のデータ状態“１”および第二のデータ状態“０”について、フローティングボディにホールが注入されたデータ状態を“１”と定義し、フローティングボディのホールが放出されたデータ状態を“０”と定義する。本実施例では、選択セルに“１”書き込み→“１”記憶保持→“１”読み出しを行い、それに続いて“０”書き込み→“０”記憶保持→“０”読み出しの順に動作させる場合について、順次説明する。動作はこの順序に限定されるものではない。 Next, FIG. 4 shows operation waveforms in the selected cell for writing and reading in this embodiment. Table 1 shows the bias conditions used in the calculation in this example.

Here, it should be noted that a bias condition different from that in Table 1 is used in FIG. 4 for easy understanding. Here, for the first data state “1” and the second data state “0”, the data state in which holes are injected into the floating body is defined as “1”, and the data state in which holes in the floating body are released Is defined as “0”. In the present embodiment, “1” write → “1” memory hold → “1” read is performed on the selected cell, and then “0” write → “0” memory hold → “0” read is operated in this order. These will be described sequentially. The operation is not limited to this order.

FIG. 4 shows the word line voltage V _WL , the bit line voltage V _BL , and the body voltage V _B at the same time. However, FIG. 4 and Table 1 are examples of operating voltages in the first embodiment, and there is no need to use these voltages. The length of the time axis in the graph is schematic and does not limit the relative operation time.

First, to write “1” to the selected cell, the word line voltage V _WL is applied to about 1.5 V at time t ₁ , and then the bit line voltage V _BL is applied to about 2.2 V at time t _2. To do. Impact ionization occurs at the gate end of the drain diffusion layer 80, excess holes are injected and held in the floating body region, and "1" is written.

Next, in order to store and hold “1”, the word line voltage V _WL is applied to about −2 V at time t ₃ , and the bit line voltage V _{BL is set} to about 0 V at time t ₄ . As a result, “1” is stored at time t ₄ .

Next, in order to perform “1” reading, the bit line voltage V _{BL is set} to about 0.2 V at time t ₅ while the word line voltage V _WL is held at about −2.0 V. Then, “1” is read by sweeping the word line voltage V _WL .

To do "0" is written to the selected cell subsequently, the word line voltage _{V WL} selected at the time _{t 11} and applied to approximately 1.5V, followed by time _{t 12} to the bit line voltage _{V BL} about -1. Set to 1V. The junction with the drain diffusion layer becomes a forward bias, holes in the bulk region 30 are emitted, and “0” is written.

Next, in order to store and hold “0”, the word line voltage V _WL selected at time t ₁₃ is applied to about −2 V, and the selected bit line voltage V _{BL is set} to about 0 V at time t ₁₄ . As a result the time _{t 14} "0" is stored.

Finally, in order to perform “0” reading, the selected bit line voltage V _BL is applied to about 0.2 V at time t ₁₅ while the selected word line voltage V _WL is held at about −2 · 0 V. When the word line voltage V _WL is swept, “0” is read out. As described above, a series of operations from “1” writing to “0” reading can be performed.

Here, the amount of change in the body voltage V _B at the time of reading in Embodiment 1 will be described in more detail with reference to FIG. 5 (a) is "1" indicating body voltage _{V B} at "1" memory retention and "1" when read after writing, that is, the body voltage _{V B} at time _{t 5} from time _{t 3} in FIG. FIG. 5 (b) shows a "0" after writing "0" body voltage _{V B} during storage hold and "0" is read, i.e. body voltage _{V B} at time ₁₅ from the time ₁₃ in FIG. 4. “With displacement” in FIGS. 5A and 5B shows the body voltage V _B when the gate electrode 50 has an asymmetric structure in which the gate electrode 50 is displaced by about 0.05 μm from the center line 100a to the drain diffusion layer 80 side. “No displacement” shows the body potential V _B in the case of a structure symmetrical to the conventional cell center line 100a for comparison.

In FIG. 5 (a), "displacement there" whichever is lowered as compared to the "no displacement" body potential V _B is suppressed. That is, “with displacement” means that the threshold value at the time of reading “1” becomes shallow. On the other hand, in FIG. 5B, “with displacement” suppresses the increase in body potential V _B compared with “without displacement”. That is, “with displacement” means that the threshold value at the time of reading “0” becomes deeper. As a result, in “with displacement”, the threshold value at the time of reading “1” becomes shallower, the threshold value at the time of reading “0” becomes deeper, and the difference in threshold values can be increased. That is, there is an effect that the difference between the two data states is increased and the signal amount is increased.

  FIG. 6 shows the relationship of the signal amount with respect to the displacement amount of the gate electrode 50 from the cell center line 100a toward the drain diffusion layer. When the gate center line is aligned with the cell center line 100a (when displacement is 0), the signal amount is about 0.19 V. When the gate center line is displaced by 0.05 μm, the signal amount is about It becomes 0.25V, and is rising 0.06V. This means that the signal amount has increased by about 32% compared to the case without displacement. Further, FIG. 6 shows that in order to increase the signal amount by about 10%, the displacement amount of the gate electrode corresponds to about 0.02 μm.

FIG. 7 shows a signal amount with respect to a ratio (C _db / C _sb ) of the capacitance C _db between the drain diffusion layer 80 and the body to the capacitance C _sb between the source diffusion layer 70 and the body. The signal amount increases depending on the amount of change in C _db / C _sb . For example, it can be seen from FIG. 7 that when C _db / C _{sb is set} to about 0.93, the signal amount increases by about 10% compared to when C _db / C _sb is 1.

As described above, in this embodiment, when the area of the unit cell 140 is constant, the gate electrode 50 is displaced from the cell center line 100a toward the drain diffusion layer 80, and the structure is asymmetric with respect to the cell center line 100a. In other words, by reducing the C _db / C _sb ratio, the signal amount can be increased. Further, there is an effect that the signal amount is increased as the displacement amount of the gate electrode is increased.

  In the first embodiment, as a method of shortening the distance between the word line and the source diffusion layer end, a word line having a linear structure has been described. However, any structure having a similar distance relationship may be used. It doesn't matter. For example, the structure of the word line may be a non-linear structure called a wiggle structure. FIG. 8 shows a plan view as an example of the wiggle structure. In a region where the word line overlaps with the bit line, the word line is close to the drain diffusion layer, and in a region where the word line does not overlap with the bit line, the word line is formed on the cell center line. Moreover, you may combine a wiggle structure and a linear structure suitably.

  A second embodiment of the present invention will be described with reference to FIGS. 9 and 10.

In the first embodiment, the C _db / C _sb ratio is reduced by using an asymmetric structure in which the center position of the word line is displaced to the drain diffusion layer side, but in the second embodiment, the concentration of the drain diffusion layer and the source diffusion layer is changed. The difference from the first embodiment is that the C _db / C _sb ratio is reduced by making it asymmetric.

FIG. 9 is a sectional view showing the structure of the semiconductor memory device according to the second embodiment in the direction along the bit line. The cross-sectional structure of Example 2 is characterized in that the source diffusion layer has a higher impurity concentration than the drain diffusion layer. As a method of manufacturing the FBC having such a feature, for example, as shown in FIG. 9, impurity ions are implanted at an angle with respect to the substrate when forming the source / drain diffusion layers, thereby being shaded by the gate electrode. It is possible to use an asymmetric ion implantation method in which the impurity concentration in the drain diffusion layer region is intentionally made thinner than the impurity concentration in the source diffusion layer. By using this method, C _db / C _sb can be reduced, and the signal amount can be increased corresponding to the amount of change in C _db / C _sb . That is, it is possible to obtain the same effect as in the first embodiment.

FIG. 10 is a plan view of the memory cell array according to the second embodiment. The second embodiment also has the effect of reducing C _db / C _sb as in the first embodiment. However, it should be noted that the unit cell 140c of the second embodiment has a different area from the unit cell 140b in the case of a structure symmetrical to the cell center line 100a.

  Although FIGS. 9 and 10 show the case where the gate electrode position is equal to the cell center line 100a, the gate position may be displaced by appropriately combining with the method of the first embodiment.

  The present invention is not limited to the above configuration, and various modifications are possible.

1 is a cross-sectional view illustrating a structure of a semiconductor memory device according to a first embodiment. FIG. 3 is a plan view showing the layout of the semiconductor memory device according to the first embodiment. FIG. 3 is a cross-sectional view showing the impurity concentration distribution of the semiconductor memory device according to the first embodiment. FIG. 3 is a diagram illustrating operation waveforms of the semiconductor memory device according to the first embodiment. FIG. 3 is a diagram illustrating a body potential change amount of the semiconductor memory device according to the first embodiment. FIG. 6 is a diagram illustrating a signal intensity change amount with respect to a gate displacement amount of the semiconductor memory device according to the first embodiment. FIG. 3 is a diagram illustrating drain-body capacitance and source-body capacitance ratio (C _db / C _sb ) with respect to signal intensity of the semiconductor memory device according to the first embodiment. FIG. 3 is a plan view showing the layout of the semiconductor memory device according to the first embodiment. FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor memory device according to a second embodiment. FIG. 6 is a plan view showing a layout of a semiconductor memory device according to a second embodiment.

Explanation of symbols

10 substrate 20 n-type semiconductor layer 30 p-type semiconductor layer 40 gate insulating film 50 gate electrode 50a word line 60 gate sidewall 70 source diffusion layer 70a source line 80 drain diffusion layer 80a bit line 80b bit line contact 90 element isolation region 100 memory cell Region 100a Cell center line 100b Gate center line 110 Insulating regions 140a to 140c Unit cells t _{1 to} t ₅ t _{11 to} t ₁₅ Time V _BL bit line voltage V _WL Word line voltage V _B Body voltage Δ Displacement C _sb Source-body Capacitance C _db drain-body capacitance

Claims (4)

A substrate,
A MOS transistor formed on the substrate;
The gate electrode of the MOS transistor is connected to the word line, the drain diffusion layer is connected to the bit line, and the source diffusion layer is connected to the fixed potential line.
A floating body that is electrically isolated from the other and can accumulate holes in the substrate;
A semiconductor memory device, wherein an electric capacity between the drain diffusion layer and the floating body is less than an electric capacity between the source diffusion layer and the floating body. The MOS transistor is an n-channel MOS transistor, the floating body is p-type, and the p-type floating body is provided on an n-type semiconductor layer provided in the substrate. 2. The semiconductor memory device according to 1.   The MOS transistor is formed between two element isolation regions adjacent to each other, and the gate electrode of the MOS transistor in a cross section parallel to the bit line is more than the center position between the two adjacent element isolation regions. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a MOS transistor structure formed at a position close to the diffusion layer side.   2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a MOS transistor structure in which an impurity concentration of the drain diffusion layer is made thinner than an impurity concentration of the source diffusion layer.

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