JP2002343885A - Semiconductor memory device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device realizing dynamic memory by the memory cell of simple transistor structure. SOLUTION: A 1-bit memory cell MC consists of a single MISFET having the channel body of floating, and the MISFET dynamically stores a first data state where a channel body is set to be a first potential and a second data state where the channel body is set to be a second potential. The MISFET has the laminated structure of a p-type layer 12 becoming the channel body, an n-type layer 11 in contact with its bottom surface to be depleted by built-in potential, and a p-type layer (substrate) 10 in contact with its bottom surface. A gate electrode 14 is formed on the upper surface of a p-form layer 12 through a gate insulation film 13, and a drain and source diffusion areas 15 and 16 are formed in the depth to the n-type layer 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device for dynamically storing data using a channel body of a MISFET as a storage node, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a conventional DRAM, a memory cell is constituted by a MISFET and a capacitor. The miniaturization of DRAM has been greatly advanced by adopting a trench capacitor structure or a stacked capacitor structure. At present, the size (cell size) of a unit memory cell is determined by
As a result, the area is reduced to an area of 2F × 4F = 8F ² . That is, the minimum processing dimension F decreases with the generation,
When the cell size is generally αF ² , the coefficient α also decreases with the generation, and α = 8 is now realized when F = 0.18 μm.

[0003] In order to secure the same trend in cell size or chip size as in the past, F <0.
At 18 μm, α <8, and at F <0.13 μm, α
It is required to satisfy <6, and how to form the cell size in a small area together with the fine processing is a major issue. Therefore, various proposals have been made to make the memory cell of one transistor / one capacitor to have a size of 6F ² or 4F ² . However, there are technical difficulties such as the need to make the transistors vertical, problems such as increased electrical interference between adjacent memory cells, and difficulties in manufacturing techniques such as processing and film formation. Absent.

On the other hand, without using a capacitor, the channel body of one MISFET is used as a storage node.
A semiconductor memory forming a 1-bit memory cell has been proposed in 1979 (PKChatterjee, e).
t.al., "Circuit Optimizationof the taper isolated d
dynamic gain RAM cell for VLSI memories, "ISSCC Tec
h. Dig. pp.22-23, Feb. 1979). The MISFET structure has a p-type channel body separated from a substrate by an n-type buried layer on a p-type substrate. The principle of the storage operation is to control the height of the barrier to holes in the n-type buried layer by capacitive coupling from the gate electrode, and to control the injection and emission of holes from the substrate to the channel body.

That is, at the time of data writing, the potential of the n-type buried layer is lowered by capacitive coupling from the gate, and holes are injected from the substrate into the channel body. Therefore, the hole accumulation state and the hole emission state of the channel body are stored as binary data. In the data holding state, the potential of the n-type buried layer is raised by capacitive coupling from the gate to prevent holes in the channel body from being released.

In this method, in order to control the potential of the n-type buried layer from the gate, the n-type buried layer must not be depleted, and the existence of electrons as majority carriers is indispensable. Therefore, the n-type drain and source diffusion layers are short-circuited by the n-type buried layer. If the channel length is as large as several μm, the effect of the short-circuit resistance due to the n-type buried layer can be made relatively small as compared with the resistance change due to the channel on / off, as in the present case. When the present invention is applied to a MISFET having a sub-μm channel length, the short-circuit resistance between the source and the drain due to the n-type buried layer cannot be neglected and becomes inoperable.

[0007]

Various other methods have been proposed for forming a 1-bit memory cell with one MISFET. However, there are disadvantages such as a complicated transistor structure and complicated control. was there.

It is an object of the present invention to provide a semiconductor memory device capable of dynamic storage by a memory cell having a simple transistor structure, and a method of manufacturing the same.

[0009]

In a semiconductor memory device according to the present invention, a 1-bit memory cell is constituted by one MISFET having a floating channel body, and the MISFET sets the channel body to a first potential. The first data state and the second potential set to the second potential.
And dynamically memorize the data state,
The MISFET includes a first conductive type first semiconductor layer serving as a channel body, a second conductive type second semiconductor layer in contact with a bottom surface of the first semiconductor layer and being depleted by a built-in potential. A third semiconductor layer of a first conductivity type in contact with a bottom surface of the second semiconductor layer; a gate electrode formed on a top surface of the first semiconductor layer via a gate insulating film; And a source and drain diffusion layer formed to a depth reaching the second semiconductor layer from the upper surface.

Specifically, in the present invention, the first data state is written by causing the MIS transistor to perform pentode operation to cause impact ionization near the drain junction, and the second data state is written by the first gate. The data is written by applying a forward bias between the drain and the semiconductor layer to which a predetermined potential is applied by capacitive coupling from the semiconductor device. Therefore, data writing and reading are performed while the source of the MISFET remains at a fixed potential such as the ground potential. Alternatively, as a method of writing the first data state, a gate-induced drain leak (GID
L: Gate-Induced Drain Leak
age) Current can also be used.

According to the present invention, one memory cell includes:
It is formed by a simple MISFET. MISFET
Has a pnp (or npn) structure below the gate electrode,
The intermediate layer has a channel body that becomes floating by being depleted by a built-in potential. The MISFET stores data depending on the potential state of its channel body, but can use the reverse bias and the forward bias of the drain junction with the source fixed, regardless of the carrier injection from the substrate for data writing. . Therefore, reading and writing are controlled only by controlling the bit line connected to the drain and the word line connected to the gate.
Rewriting and refreshing can be controlled. Unlike the conventional method using carrier injection and emission from the substrate to the channel body, data can be rewritten in arbitrary bit units.

Preferably, in the present invention, an auxiliary gate electrode surrounded by an insulating film is embedded in the second semiconductor layer immediately below the gate electrode. It is assumed that the auxiliary gate electrode is buried between the source and drain diffusion layers such that pn junctions of the first semiconductor layer and the second semiconductor layer remain on both sides. The lower end of the auxiliary gate electrode may be located in the second semiconductor layer or may have a depth reaching the third semiconductor layer.

According to the present invention, there is also provided a method of manufacturing a semiconductor memory device as described above, wherein an impurity is introduced into a surface portion of a semiconductor substrate of a first conductivity type to form a first semiconductor of a first conductivity type serving as a channel body. Forming a layer, and performing ion implantation of an impurity immediately below the first semiconductor layer of the semiconductor substrate to form a second semiconductor layer of a second conductivity type that is depleted by a built-in potential; Forming a gate electrode on the surface of the first semiconductor layer of the semiconductor substrate with a gate insulating film interposed therebetween; and ion-implanting impurities into the semiconductor substrate to form a gate electrode at a depth reaching the second semiconductor layer. Forming source and drain diffusion layers of two conductivity type.

The present invention further provides a method of manufacturing a semiconductor memory device as described above, wherein a step of forming a trench in a semiconductor substrate of a first conductivity type and a step of forming an insulating film on an inner wall of the trench are performed. Burying the auxiliary gate electrode to an intermediate depth, forming a first gate insulating film on the upper surface of the auxiliary gate electrode, and then performing heat treatment in hydrogen gas with the side walls of the trench exposed. Covering the upper portion of the trench with a flow of the semiconductor substrate material, introducing an impurity into a surface portion of the semiconductor substrate to form a first semiconductor layer of a first conductivity type serving as a channel body; Forming a second semiconductor layer of the second conductivity type that is depleted by a built-in potential by ion-implanting impurities directly below the first semiconductor layer of the semiconductor substrate; Forming a gate electrode on the surface of the first semiconductor layer covering the trench via a second gate insulating film, and performing ion implantation of impurities into the semiconductor substrate to reach a depth reaching the second semiconductor layer. Forming a second conductivity type source and drain diffusion layer.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. [Embodiment 1] FIG. 1 is a block diagram showing a D according to a basic embodiment.
2 shows the structure of a RAM cell. The memory cell MC has n
It is composed of a channel MISFET. It has a structure in which an n-type layer 11 and a p-type layer 12 are stacked on a p-type silicon substrate 10, and a gate electrode 14 is formed thereon with a p-type layer 12 as a channel body via a gate insulating film 13. ing. N-type drain and source diffusion layers 15 and 16 are formed so as to be self-aligned with the gate electrode 14.

The p-type layer 12, the n-type layer 11, and the p-type substrate 10
The impurity concentration and the thickness are adjusted so that the n-type layer 11 is completely depleted by the built-in potential. Specifically, in order to form this structure only by ion implantation, the p-type silicon substrate 10 must have a relatively low concentration, and a p-type impurity such as boron is ion-implanted into the surface of the silicon substrate 10 to form a channel body. The p-type layer 12 having an appropriate concentration to obtain a proper threshold value is formed. Further, an n-type impurity such as arsenic is ion-implanted immediately below the p-type layer 12 to form an n-type layer 11. It does not matter before or after these ion implantation steps.

Then, by optimally setting the impurity concentration of the p-type layer 12 and the n-type layer 11 and the thickness of the n-type layer 11,
The n-type layer 11 is completely depleted by the built-in potential. Drain and source diffusion layers 15, 16
Is formed to a depth reaching the n-type layer 11 from the surface. At this time, n under the source / drain diffusion layers 15 and 16
The portion of the mold layer 11 forms a pn junction only with the substrate 10, but it is preferable that this portion is also depleted by a built-in potential with the substrate 10. In the channel width direction (that is, in the direction perpendicular to the plane of the drawing), assuming that the isolation from the adjacent cell is performed by the element isolation insulating film, the p-type layer 12 becomes the depleted n-type layer 12, the drain and the source. The diffusion layers 15 and 16 and the element isolation insulating film enter a floating state electrically separated from the others.

When memory cells MC are arranged in a matrix, gate electrode 14 is connected to word line WL, source diffusion layer 16 is connected to fixed potential line SL (ground potential line), and drain diffusion layer 15 is connected to bit line BL. Connected to.
FIG. 2 shows an equivalent circuit of a unit cell of the cell array configured as described above.

D composed of this n-channel MISFET
The operation principle of the RAM cell utilizes the potential control of the floating channel body (p-type layer 12 separated from the others). That is, a large current flows from the drain diffusion layer 15 by operating the MISFET in the pentode region,
When impact ionization occurs near the drain junction, the channel body can be set to the first potential state in which holes serving as majority carriers are held. This state is, for example, data “1”. Drain diffusion layer 15 and p-type layer 1
The second potential state in which the p-type layer 12 has a lower potential is set to data “0” by forward-biasing the pn junction between the two to release holes in the p-type layer 12. During this time, the source diffusion layer 16 is kept at a fixed potential, for example, a ground potential.

The data "0" and "1" are stored as a difference between the potentials of the channel bodies, and thus as a difference between the threshold voltages of the MISFETs. That is, the threshold voltage Vth1 of the data “1” state where the potential of the body is high due to the accumulation of holes
Is lower than the threshold voltage Vth0 in the data “0” state. A negative bias voltage is applied to the word lines in order to maintain a "1" data state in which holes serving as majority carriers are accumulated in the body. This data holding state does not change even if a read operation is performed, unless a reverse data write operation (erase) is performed. That is, a one-transistor / one-capacitor DRAM utilizing charge storage of a capacitor.
Unlike this, nondestructive reading is possible.

Several data reading methods are conceivable. Word line potential VWL and channel body potential VB
Is as shown in FIG. 3 in relation to data "0" and "1". Therefore, for example, in the first method of reading data, a read potential that is intermediate between the threshold voltages Vth0 and Vth1 of the data “0” and “1” is applied to the word line WL. No current flows,
The fact that a current flows in a memory cell of "1" data is used. Specifically, for example, the bit line BL is set to a predetermined potential V
BL is precharged, and then the word line WL is driven. As a result, in the case of "0" data, the bit line precharge potential VBL does not change, and in the case of "1" data, the precharge potential VBL decreases.

In the second read mode, a current is supplied to the bit line BL after the word line WL is started,
The fact that the rising speed of the bit line potential varies depending on the degree of conduction of “0” and “1” is used. Briefly, the bit line BL is precharged to 0 V, the word line WL is started, and the bit line current is supplied. At this time, data difference can be determined by detecting a difference in potential rise of the bit line by using a dummy cell.

In the present invention, in order to selectively write "0" data, that is, holes are formed only from the body of the memory cell selected by the potential of the word line WL and bit line BL selected in the memory cell array. In order to emit the light, the capacitive coupling between the word line WL and the body becomes essentially. In the state where holes are accumulated in the body by data "1", the word line is sufficiently biased in the negative direction, and the gate-substrate capacitance of the memory cell becomes the gate oxide film capacitance (that is, a depletion layer is formed on the surface). (It is not formed).

As described above, according to this embodiment.
A DRAM cell is constituted by a MISFET having a simple structure. The buried n-type layer 11 is depleted with a built-in potential without the need to control the potential for carrier injection from the substrate as in the method described in the related art. Therefore, even in the case of a short-channel MISFET, the short-circuit resistance of the source and the drain due to the n-type layer 11 does not matter, and miniaturization is possible. Also, if the portion of the n-type layer 11 immediately below the drain and source diffusion layers 15 and 16 is also depleted, the junction capacitance of the drain and source diffusion layers 15 and 16 becomes small, similar to the case where an SOI substrate is used. And the characteristics are improved.

[Embodiment 2] FIG. 4 shows a cell array according to a more specific embodiment of the present invention.
The sectional structure of a bit is shown. However, parts corresponding to those in FIG. 1 are denoted by the same reference numerals as in FIG. In the p-type silicon substrate 10, for example, a range of two bits (two MISFETs) is partitioned as an island-shaped element formation region by the element isolation insulating film 21. As described in the first embodiment, n-type layer 11 is formed in substrate 10 by ion implantation, and p-type layer 12 serving as a channel body is formed thereon. The conditions for depleting n-type layer 11 are also the same as in the first embodiment.

The gate electrode 14 is continuously patterned in a direction perpendicular to the plane of the drawing, with the top and side surfaces being covered by the silicon nitride film 22, to form word lines. The drain diffusion layer 15 and the source diffusion layer 16 are
Concentration (n ⁺ ) diffusion layers 15a, 16a
And extension regions 15b and 16b having a lower concentration and shallower (not reaching the n-type layer 11). Specifically, the extension area 15
b and 16b are formed by performing ion implantation before forming a silicon nitride film on the side surface of the gate electrode 14, and the high-concentration diffusion layers 15a and 16a are formed after forming a silicon nitride film on the side surface of the gate electrode 14. It is formed by performing implantation.

In this example, the source diffusion layer 16 has two M
Shared by ISFET. For example, the source diffusion layer 16 may be formed continuously in a direction perpendicular to the plane of the drawing and may be used as a fixed potential line, or a fixed potential line may be separately provided above and connected thereto. . The substrate on which the elements are formed is covered with an interlayer insulating film 23, and a bit line 24 is provided thereon. The bit line 24 is connected to the drain diffusion layer 15 via a contact hole formed in the interlayer insulating film 23.

[Embodiment 3] DRA described so far
An important point of the M cell is how much the threshold voltage difference between data “0” and “1” can be increased in terms of the operation principle. As is clear from the above-described operation principle, data writing and holding characteristics are determined by controlling the body potential by capacitive coupling from the gate. However, since the threshold voltage is applied to the body potential with a substantially square root, ,
It is not easy to realize a large threshold voltage difference between “0” and “1” data. In addition, in the above-described write operation, the memory cell of "0" write operates as a triode, and when a channel is formed, the gate electrode and the body are not capacitively coupled, and the body potential cannot be controlled.

Therefore, in the present invention, it is preferable that, apart from the main gate electrode used for channel formation, the MIS
An auxiliary gate electrode for controlling the body potential is provided by capacitively coupling to the channel body of the FET. 5 and 6
Shows the cell structure of such an embodiment in correspondence with FIG.

As shown, an auxiliary gate electrode 31 is buried in the p-type layer 12 immediately below the gate electrode 14.
The periphery of the auxiliary gate electrode 31 is surrounded by an insulating film 32. The width (width in the bit line direction) of the auxiliary gate electrode 31 is
It is smaller than that of the main gate electrode 14 and a pn junction between the p-type layer 12 and the n-type layer 11 remains on both sides thereof. As a result, the n-type layer 11 is depleted by the built-in potential between the n-type layer 11 and the p-type layer 12.

The upper end of the auxiliary gate electrode 31 is
, And the potential can be controlled by capacitive coupling with respect to the p-type layer 12. The insulating film 32 (gate insulating film) where the auxiliary gate electrode 31 faces the p-type layer 12 may have the same thickness as the gate insulating film 13 on the main gate electrode 14 side. The thickness of the insulating film 32 on the 31 side is determined so as to optimize the magnitude of capacitive coupling to the p-type layer 12. Therefore, for example, it is made thicker than the gate insulating film 13 on the main gate electrode 14 side.

In FIG. 5, the bottom surface of the auxiliary gate electrode 31 has a depth reaching the p-type substrate 10, and in FIG. 6, the bottom surface of the auxiliary gate electrode 31 is located in the n-type layer 11. ing. 5, the auxiliary gate electrode 31 can be operated without deteriorating the separation characteristics of the p-type layer 12 by the n-type buried layer 11. In the structure shown in FIG. 6, the n-type buried layer 11 is divided by the auxiliary gate electrode 31, so that the drain-source separation characteristics are improved.

The auxiliary gate electrode 31 can be formed continuously, for example, as an auxiliary word line parallel to the word line formed by the main gate electrode 14. The auxiliary gate electrode 31 is driven, for example, in synchronization with the gate electrode 14. As a result, reliable writing can be performed, and the difference between the threshold voltages of “0” and “1” data can be increased. Alternatively, the auxiliary gate electrode 31 is set to a fixed potential lower than the source potential, for example, so that the
By keeping the 1 side in the majority carrier accumulation state, the difference between the "0" and "1" data threshold voltages can be similarly increased.

More specifically, when the word line WL is set to a negative potential to hold “1” data, a negative potential is also applied to the pair of auxiliary word lines to hold the “1” data. The state can be kept good. Word line W
When writing data by increasing the potential of L,
By raising the auxiliary word line, the channel body potential can be raised by capacitive coupling, and reliable data writing can be performed. In the case of writing “0” data, even if a channel is formed on the word line WL side,
Since the channel body potential can be increased by the auxiliary word line, reliable "0" data writing can be performed.
As described above, "0" and "1" data having a large threshold voltage difference can be stored.

In addition, data is held by giving a negative potential to unselected word lines WL. At this time, the auxiliary body lines forming a pair are also set to the negative potential, so that the channel body potential is controlled to be low. When "0" data is written in another memory cell along the same bit line, data destruction in an unselected cell holding "1" data is also reliably prevented.

[Fourth Embodiment] Next, taking the cell structure of FIG. 5 as an example, a specific manufacturing process thereof will be described with reference to FIGS. 7A to 7F. As shown in FIG. 7A, a mask (not shown) such as a silicon oxide film pad is formed on the p-type silicon substrate 10.
Is formed, and the p-type silicon substrate 10 is etched by RIE to form a trench 41 for embedding an auxiliary gate. Subsequently, after an insulating film 32a is formed on the side wall of the trench 41, polycrystalline silicon is deposited, etched back, and the auxiliary gate electrode 31 is buried halfway through the trench. Instead of polycrystalline silicon, another conductor layer such as a high melting point metal can be used.

Thereafter, an insulating film 32b to be a gate insulating film is formed on the upper surface of the buried auxiliary gate electrode 31. This insulating film 32a is formed by, for example, low-temperature wet oxidation or HDP-
It is formed thicker than the surrounding insulating film 32a by CVD or the like. Then, after removing the thin insulating film on the trench side wall above the auxiliary gate electrode 31, a heat treatment is performed in a hydrogen atmosphere at 800 ° C. to 1000 ° C. As a result, silicon flows from the upper side wall of the trench 41, and as shown in FIG. 7D, the upper portion of the trench 41 is covered with the same p-type single-crystal silicon layer 42 as the substrate 10, and the entire surface is flattened. Obtainable.

Such a technique of covering the upper part of the groove by a hydrogen heat treatment has been previously proposed by the present applicant as a technique for confining a cavity inside a silicon substrate (Japanese Patent Laid-Open No. 2000-2000).
-12858). However, a similar structure can be obtained by closing the upper part of the trench 41 by crystal growth in the lateral direction from the side wall of the trench 41 by using the epitaxial growth technique.

Thereafter, STI (Shallow Tre)
After an element isolation insulating film (not shown) is formed by an nch isolation (nch isolation) technique, arsenic (or phosphorus) is ion-implanted into the substrate 10 as shown in FIG.
The mold layer 11 is buried. Substrate 1 by n-type layer 11
The upper p-type layer 12 separated from 0 (particularly, the portion of the p-type layer 42 covering the upper part of the trench 41) is used as a channel body. In order to obtain the impurity concentration, boron ions are implanted into the p-type layer 12 to adjust the impurity concentration. Thus, the impurity concentration distribution becomes as shown in FIG. In order to form the n-type layer 11 with a relatively low dose, the p-type silicon substrate 10 preferably has a low concentration. Then, the n-type layer 10 can be depleted with a built-in potential by implanting boron ions into the upper portion of the n-type layer 11 and setting the channel body to a necessary p-type concentration.

Thereafter, as shown in FIG. 7F, the MISFE
Form T. Specifically, a gate insulating film 13 is formed,
A gate electrode material and a silicon nitride film 22a are laminated thereon, and these laminated films are patterned to form a gate electrode 14a.
To form In this state, ion implantation is performed to form the drain and source n ⁺ -type layers 15a and 16a. Further, a silicon nitride film 22b covering the side wall of the gate electrode 14 is formed.
b, 16b are formed. After this, the process diagram is not shown,
An interlayer insulating film is deposited, contact holes are formed, and bit lines are formed.

Although the manufacturing process of the DRAM cell provided with the buried auxiliary gate electrode 31 has been described above, even in the case of the cell structure without the auxiliary gate electrode shown in FIG. The same steps can be applied.

[Fifth Embodiment] FIGS. 4 to 6 show a structure in which elements are separated in units of 2 bits in the bit line direction. However, not only the source diffusion layer but also the drain diffusion layer are shared by adjacent cells. In this case, element isolation in the bit line direction is not required. In this case, the unit cell area of the cell array can be made smaller.

FIG. 9 is a layout of the cell array of such an embodiment, and FIGS. 10A and 10B are cross-sectional views taken along the lines AA 'and BB' of FIG. The MISFET structure is basically the same as the structure of FIG. 4 without the auxiliary gate electrode. However, the drain and source diffusion layers 15,
Reference numeral 16 denotes a single layer. The element isolation insulating film 21 is formed as shown in FIG.
As shown in (1), the minimum processing dimension is F, and it is embedded in a matrix arrangement in a rectangular pattern having a size of 1F × 3F. Then, the gate electrode 14 is patterned so as to be continuous across both ends of each rectangular element isolation insulating film to form a word line W having a line / space of 1F / 1F.
L is formed.

If the drain and source diffusion layers 15 and 16 are formed by ion implantation after forming the word line WL in this manner, the source diffusion layer 16 becomes a common source line SL in parallel with the word line WL. And shared by adjacent cells in the bit line direction. The drain diffusion layer 15 is formed so as to be separated from an adjacent cell in the word line WL direction by the element isolation insulating film 21 and to be shared by the adjacent cell in the bit line BL direction. The drawing shows a case where the bit line 24 is also formed with a line / space of 1F / 1F. Further, as shown in FIG. 10A, a contact plug 51 is buried in the bit line contact hole.

With such a cell array configuration, the unit cell area is 4F ² as shown by the broken line in FIG.
A high-density DRAM cell array can be obtained. FIG. 11 shows an equivalent circuit of the cell array.

The present invention is not limited to the above embodiment.
For example, FIG. 12 shows an example in which a wiring 25 for commonly connecting the source diffusion layers 16 is formed based on the structure of FIG. The same structure can be applied to the cells shown in FIGS. In the above embodiment, the n-channel MISFET is used.
An ISFET can also be used. In the embodiment, as a method of obtaining a floating channel body, a pnp structure is formed by ion implantation.
A similar structure can be obtained using epitaxial growth.

[0047]

As described above, according to the present invention, a highly integrated semiconductor memory in which a MISFET having a simple structure is used as a memory cell and data is dynamically stored according to the potential state of its channel body. A device can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a DRAM cell according to an embodiment of the present invention;

FIG. 2 is an equivalent circuit of the DRAM cell.

FIG. 3 is a characteristic diagram for explaining a memory operation of the DRAM cell.

FIG. 4 is a sectional view showing a structure of a DRAM cell according to another embodiment.

FIG. 5 is a sectional view showing a structure of a DRAM cell according to another embodiment.

FIG. 6 is a sectional view showing a structure of a DRAM cell according to another embodiment.

FIG. 7A is a cross-sectional view showing a step of forming a trench for embedding an auxiliary gate electrode in a manufacturing step of the embodiment;

FIG. 7B is a sectional view showing an auxiliary gate electrode embedding step in the same manufacturing step.

FIG. 7C is a cross-sectional view showing the step of forming the gate insulating film of the auxiliary gate in the same manufacturing process.

FIG. 7D is a cross-sectional view showing a trench filling step in the manufacturing process.

FIG. 7E is a sectional view showing an n-type layer ion implantation step in the same manufacturing step.

FIG. 7F is a sectional view showing the MISFET forming step in the same manufacturing step.

FIG. 8 is a diagram showing an impurity concentration distribution of a channel body region in the same manufacturing process.

FIG. 9 is a diagram showing a layout of a DRAM cell array according to another embodiment.

10A is a sectional view taken along line A-A 'of FIG.

FIG. 10B is a sectional view taken along line B-B 'of FIG.

FIG. 11 is an equivalent circuit of the DRAM cell array.

FIG. 12 is a diagram showing a structure of a DRAM cell according to another embodiment.

[Explanation of symbols]

Reference Signs List 10: p-type silicon substrate, 11: n-type layer, 12: p-type layer (channel body), 13: gate insulating film, 14: gate electrode, 15 (15a, 15b): drain diffusion layer, 1
6 (16a, 16b): source diffusion layer, 21: element isolation insulating film, 22: silicon nitride film, 23: interlayer insulating film, 2
4 ... bit line, 31 ... auxiliary gate electrode, 32 ... insulating film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Kazumasa Sunouchi 8, Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Takashi Osawa 1 Address F-term in Toshiba Microelectronics Center Co., Ltd. (reference) 5F083 AD01 AD10 AD69 GA09 JA39 KA01 MA06 MA20 PR25 PR33 PR36

Claims (8)

[Claims] 1. A 1-bit memory cell includes one MISFET having a floating channel body, wherein the MISFET has a first data state in which the channel body is set to a first potential and a second data state in which the channel body is set to a second potential. The MISFET dynamically stores a second data state, wherein the MISFET is depleted by a built-in potential in contact with a first semiconductor layer of a first conductivity type serving as a channel body and a bottom surface of the first semiconductor layer. A second conductive type second semiconductor layer, a first conductive type third semiconductor layer in contact with the bottom surface of the second semiconductor layer, and a gate insulating film on an upper surface of the first semiconductor layer. And a source and drain diffusion layer formed at a depth reaching the second semiconductor layer from the upper surface of the first semiconductor layer. Semiconductor memory device that. 2. The method according to claim 1, wherein the first data state is the MISFE.
The write operation is performed by causing T to operate as a pentode to cause impact ionization near the drain junction. The second data state is defined by a channel body provided with a predetermined potential by the capacitive coupling from the first gate electrode and a drain diffusion. 2. The semiconductor memory device according to claim 1, wherein data is written by applying a forward bias between the layers. 3. The semiconductor memory device according to claim 1, wherein an auxiliary gate electrode surrounded by an insulating film is buried in said second semiconductor layer immediately below said gate electrode. 4. The auxiliary gate electrode is buried between the source and drain diffusion layers such that a pn junction between the first semiconductor layer and the second semiconductor layer remains on both sides. Item 4. The semiconductor memory device according to item 3. 5. The auxiliary gate electrode has a lower end formed in the second gate electrode.
4. The semiconductor memory device according to claim 3, wherein said semiconductor memory device is embedded so as to be located in said semiconductor layer. 6. The lower end of the auxiliary gate electrode is the third gate electrode.
4. The semiconductor memory device according to claim 3, wherein said semiconductor memory device is embedded so as to reach said semiconductor layer. 7. A 1-bit memory cell includes one MISFET having a floating channel body, wherein the MISFET has a first data state in which the channel body is set to a first potential and a second data state in which the channel body is set to a second potential. A method of manufacturing a semiconductor memory device for dynamically storing a second data state, comprising: introducing an impurity into a surface portion of a semiconductor substrate of a first conductivity type;
Forming a first semiconductor layer of a first conductivity type serving as a channel body; and ion-implanting impurities directly below the first semiconductor layer of the semiconductor substrate to deplete the semiconductor substrate with a built-in potential. Forming a second semiconductor layer of a mold type; forming a gate electrode on a surface of the first semiconductor layer of the semiconductor substrate via a gate insulating film; and performing ion implantation of impurities into the semiconductor substrate. Forming a source and drain diffusion layer of the second conductivity type at a depth reaching the second semiconductor layer. 8. A 1-bit memory cell includes one MISFET having a floating channel body, wherein the MISFET has a first data state in which the channel body is set to a first potential and a second data state in which the channel body is set to a second potential. A method of manufacturing a semiconductor memory device for dynamically storing a second data state, comprising: forming a trench in a semiconductor substrate of a first conductivity type; forming an insulating film on an inner wall of the trench; Burying the auxiliary gate electrode to an intermediate depth, and forming a first gate insulating film on the upper surface of the auxiliary gate electrode, and then performing a heat treatment in hydrogen gas while exposing the side walls of the trench, Covering the upper portion of the trench with a flow of the semiconductor substrate material; introducing an impurity into a surface portion of the semiconductor substrate to form a channel body; Forming a first semiconductor layer of the first conductivity type, and ion-implanting impurities immediately below the first semiconductor layer of the semiconductor substrate to deplete the semiconductor substrate with a built-in potential. 3) forming a semiconductor layer, forming a gate electrode on a surface of the first semiconductor layer covering the trench via a second gate insulating film, and performing ion implantation of impurities into the semiconductor substrate. Forming a source and drain diffusion layer of the second conductivity type at a depth reaching the second semiconductor layer.