JP4658914B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a chip size package (CSP) structure having substantially the same outer dimensions as a semiconductor chip and a manufacturing method thereof .

Patent Document 1 below discloses a semiconductor device of a wafer level chip size package (W-CSP) as one form of a chip size package (CSP) having substantially the same outer dimensions as the semiconductor chip. In this semiconductor device, a high-frequency circuit region is formed in the central portion of the semiconductor substrate, a low-frequency circuit region is formed in the peripheral portion of the high-frequency circuit region, and is provided above the electrodes of the high-frequency circuit region and the low-frequency circuit region. The external terminals are connected by rewiring. As a result, rewiring, conductor posts (columnar electrodes) and external terminals are not arranged above the high-frequency circuit. Therefore, electromagnetic coupling generated between the high-frequency circuit and rewiring, or characteristics of the high-frequency circuit due to parasitic components Variation is suppressed.
Japanese Patent No. 3616605

  In general, a W-CSP semiconductor device is formed by an LSI formation process and a package (W-CSP) process. The LSI forming process includes a process from forming a desired circuit on a semiconductor substrate to forming a metal wiring (conductive layer) and a passivation film as a protective film. The packaging process includes processes up to forming rewiring, sealing resin, and solder as external terminals. In the semiconductor device, since the LSI is designed so that desired circuit characteristics can be obtained in the LSI formation process, it is desirable that the rewiring generated in the subsequent packaging process is minimal. This is because the circuit characteristics of the LSI optimized in the LSI formation process fluctuate in the subsequent packaging process due to parasitic components (for example, inductance components) of the rewiring.

  In view of this viewpoint, the semiconductor device disclosed in Patent Document 1 is an LSI that is optimally designed in an LSI formation process by rewiring that extends from the central portion of the semiconductor substrate toward the peripheral portion in plan view. The structure of the circuit is easy to change. In addition, since the pitch of the electrode pads in the high frequency circuit area and the pitch of the external terminals electrically connected to the electrode pads are different in plan view, the rewiring path is not constant, and the circuit characteristics due to rewiring It is generally difficult to compensate for variations in LSI design.

Therefore, there has been a demand for a W-CSP semiconductor device and a method for manufacturing the same , in which fluctuations in characteristics of the high-frequency circuit are suppressed and rewiring is minimized.

A semiconductor device according to the present invention is located in a first region where a high-frequency circuit is formed, and around the first region, and includes a low-frequency circuit, a plurality of first electrode pads for the high-frequency circuit, and a low-frequency circuit. And a semiconductor substrate having a main surface including a second region formed with a plurality of second electrode pads. The semiconductor device further includes an insulating film, a sealing resin, a plurality of first external terminals, a plurality of second external terminals, and a conductive layer. The insulating film is formed on the main surface. The sealing resin covers the insulating film. The plurality of first external terminals are formed immediately above the plurality of first electrode pads, protrude from the surface of the sealing resin, and are electrically connected to the plurality of first electrode pads. The plurality of second external terminals are formed immediately above the plurality of second electrode pads, protrude from the surface of the sealing resin, and are electrically connected to the plurality of second electrode pads. The conductive layer is formed on the main surface of the semiconductor substrate while being covered with an insulating film, and electrically connects the high-frequency circuit and the first electrode pad.

  In the semiconductor device of the present invention, the high frequency circuit is disposed in the central region of the semiconductor substrate, and the low frequency circuit is disposed in the peripheral region surrounding the central region. A first external terminal for the high-frequency circuit (first region) is disposed outside the first region. Therefore, a conductor or a second external terminal (hereinafter referred to as a conductor) for transmitting a signal of the high-frequency circuit is not disposed above the high-frequency circuit formed in the first region. Thereby, the characteristic fluctuation | variation of the high frequency circuit resulting from parasitic components, such as this conductor thing, can be suppressed.

In the semiconductor device of the present invention, the first external terminal and the second external terminal are formed immediately above the first electrode pad and the second electrode pad, respectively. In other words, since the electrode pad and the corresponding external terminal are located at the same position when the semiconductor device is viewed in a plan view, the rewiring is minimized and the parasitic component accompanying the rewiring is very small.
In addition, a method for manufacturing a semiconductor device of the present invention includes:
Preparing a semiconductor substrate having a main surface including a first region and a second region around the first region;
Forming a high frequency circuit in the first region;
Forming a low frequency circuit, a plurality of first electrode pads for the high frequency circuit, and a second electrode pad for the low frequency circuit in the second region;
Forming a conductive layer on the main surface of the semiconductor substrate for electrically connecting the high-frequency circuit and the first electrode pad from the first region to the second region;
Forming an insulating film on the main surface of the semiconductor substrate so as to cover the conductive layer and the first and second regions;
Forming a sealing resin covering the insulating film;
Forming a plurality of first external terminals protruding from the surface of the sealing resin so as to be located immediately above the plurality of first electrode pads and electrically connected to the plurality of first electrode pads;
Forming a plurality of second external terminals that protrude from the surface of the sealing resin so as to be positioned directly above the plurality of second electrode pads and are electrically connected to the plurality of second electrode pads; It has.

According to the onset bright, suppress characteristic variation of the high frequency circuit, and a rewiring becomes possible to minimize.

Hereinafter, embodiments of the semiconductor device of the present invention will be described with reference to FIGS.
1 and 2 are diagrams showing the structure of the semiconductor device according to the first embodiment of the present invention. FIG. 1 is a plan view showing a state before sealing with a sealing resin. FIG. 2 is a schematic cross-sectional view taken along line AA in FIG.

  The semiconductor device of the present invention has a semiconductor substrate 101. The semiconductor substrate 101 has a high-frequency circuit region 502 (first region) in which mainly high-frequency circuits are formed and a low-frequency circuit region 501 (second region) in which mainly low-frequency circuits are formed. The high frequency circuit region 502 is a central region of the semiconductor substrate 101, and the low frequency circuit region 501 is a peripheral region of the semiconductor substrate 101 surrounding the central region.

  A high-frequency circuit is a circuit that processes a signal having a relatively high frequency or generates a signal having a relatively high frequency. Examples of the high-frequency circuit include a voltage controlled oscillator (VCO) and a radio signal. There is an RF circuit that performs the above process.

  The low frequency circuit is a circuit that processes a signal having a relatively low frequency or a circuit that generates a signal having a relatively low frequency.

In this specification, the high frequency means a frequency relatively high with respect to the low frequency, and the low frequency means a frequency relatively low with respect to the high frequency.
In the present specification, the high frequency is a range in which characteristics are greatly changed by electromagnetic coupling or by generation of a parasitic component (parasitic inductor or parasitic capacitor), taking the inductor element described above as an example. Means frequency. On the other hand, the low frequency in this specification is a range in which the characteristics do not change so much even if electromagnetic coupling occurs or parasitic components occur, taking the inductor element described above as an example. Means the frequency. Specifically, the high frequency is assumed to be a band of 300 MHz or higher or a radio frequency, but for the purpose described above, it is not particularly limited to these numbers. On the other hand, specifically, the low frequency is assumed to be a band or audio frequency lower than the above high frequency band, but is not particularly limited to this number or the like for the purpose described above.

  The low frequency circuit region 501 on the surface of the semiconductor substrate 101 includes a low frequency circuit, a plurality of electrode pads 103 (second electrode pads) connected to the low frequency circuit, and a plurality of electrode pads connected to the high frequency circuit. 104 (first electrode pad) is formed. The electrode pads 103 and 104 are made of a material containing aluminum or a material containing gold. As shown in FIGS. 1 and 2, the electrode pad 104 is disposed closer to the center of the semiconductor substrate 101 than the electrode pad 103.

  An insulating layer 301 made of silicon oxide or the like is formed on the semiconductor substrate 101 excluding a part of the surface of the electrode pad 103. A protective film 303 made of polyimide or the like is formed on the insulating layer 301. In this structure, a part of the electrode pad 103 is exposed in the opening patterned by the insulating layer 301 and the protective film 303.

A via 601 is formed immediately above the electrode pad 103. A conductor post 403 is formed immediately above the via 601 by laminating copper, for example. It can be considered that the via 601 in the semiconductor device of this embodiment generally corresponds to a rewiring formed in the packaging process of the W-CSP semiconductor device. In this specification, the rewiring is an LSI in a plan view. It means a redistribution layer (RDL) provided in a later packaging process for the purpose of absorbing (redistributing) the difference between the electrode pad position on the formation surface and the external terminal position. The via 601 is formed by the same process as the rewiring in the packaging process. However, as shown in FIGS. 1 and 2, the via 601 is between the electrode pad 103 and the external terminal 203 (second external terminal) in a plan view. No offset is generated.

  As described above, a high-frequency circuit is formed in the high-frequency circuit region 502 on the surface of the semiconductor substrate 101. A metal wiring 205 (conductive layer of the present invention) is connected from the MOS transistor (not shown) forming the high-frequency circuit toward the electrode pad 104. The metal wiring 205 is formed as a conductive layer (wiring thickness: around 1 μm) of aluminum or the like by patterning in an LSI formation step (described later). The metal wiring 205 is not necessarily the uppermost layer wiring when a plurality of wiring layers are formed in the LSI forming process. By this metal wiring 205, the high frequency circuit in the high frequency circuit region 502 and the electrode pad 104 are electrically connected.

  In this specification, the metal wiring means a conductive layer provided in a subsequent process (wiring process) of the LSI forming process, and is different from the rewiring formed in the packaging process.

  An insulating layer 301 made of silicon oxide or the like is formed on the semiconductor substrate 101 excluding a part of the surface of the electrode pad 104. A protective film 303 made of polyimide or the like is formed on the insulating layer 301. In this structure, a part of the electrode pad 104 is exposed by the opening patterned by the insulating layer 301 and the protective film 303.

  A via 601 is formed immediately above the electrode pad 104. A conductor post 404 is formed immediately above the via 601 by laminating copper, for example.

  The sealing resin 701 is a sealing material (for example, epoxy resin or phenol resin) that covers the protective film 303, the via 601, and the conductor posts 403 and 404 and is formed at substantially the same height as the conductor posts 403 and 404. Has been. The surface of the sealing resin 701 is flattened by, for example, a grinder and processed so that the conductor posts 403 and 404 are exposed.

  An external terminal 203 is formed on the exposed upper surface of the conductor post 403. Similarly, external terminals 204 (first external terminals) are formed on the exposed upper surfaces of the conductor posts 404. The external terminals 203 and 204 are spherical electrodes (solder balls) formed by, for example, a ball mount method. As shown in FIG. 1, in the structure of the present embodiment, two rows of external terminals 203 and 204 are regularly arranged at substantially intervals.

  In the semiconductor device of this embodiment, the external terminal 204 that is electrically connected to the high frequency circuit is disposed above the low frequency circuit region 501 disposed outside the high frequency circuit region 502. That is, the external terminal 204 for the high frequency circuit is formed so as to be offset from the high frequency circuit (high frequency circuit region 502) by the metal wiring 205 when viewed in a plan view as shown in FIG. The reason why the metal wiring 205 is formed in this manner is that there are restrictions on the layout of the semiconductor device. That is, in general, in a semiconductor device, the pitch between adjacent external terminals needs to be about 0.3 mm or more from the viewpoint of substrate mounting, whereas the pitch of metal wiring drawn from a transistor in a high-frequency circuit. Is usually 0.1 mm or less, so it is necessary to absorb the difference between the two pitches. In the semiconductor device of this embodiment, this inter-pitch absorption is realized by the metal wiring 205 instead of the rewiring.

  The characteristics of the structure of the semiconductor device of this embodiment are as follows.

(1)
In the present embodiment, the external terminal 203 that is electrically connected to the low frequency circuit is disposed immediately above the electrode pad 103 for the low frequency circuit. That is, no rewiring is performed from the electrode pad 103 toward the external terminal 203 so as to be offset in a plan view. Therefore, the parasitic component from the electrode pad 103 to the external terminal 203 is very small.

(2)
In the semiconductor device of this embodiment, the high frequency circuit is arranged in the central region (high frequency circuit region 502) of the semiconductor substrate 101, and the low frequency circuit is arranged in the peripheral region (low frequency circuit region 501) surrounding this central region. . An external terminal 204 for the high frequency circuit is arranged outside the high frequency circuit region 502. The metal wiring 205 connected to the high frequency circuit is formed so that the external terminal 204 for the high frequency circuit is located outside the high frequency circuit region 502.
That is, in the semiconductor device of the present embodiment, the conductor post 404 and the external terminal 204 are not disposed directly above (above) the high-frequency circuit formed in the high-frequency circuit region 502, and the high-frequency circuit includes the conductor post 404 and the external terminal 204. And separated.

Due to the features of (1) and (2) above, in the semiconductor device of this embodiment, electromagnetic coupling generated between the high frequency circuit and the conductor post 404 and the external terminal 204 or the parasitic of the conductor post 404 and the external terminal 204 is achieved. Variations in the characteristics of the high-frequency circuit due to the components can be suppressed.
If the connection is made from the high frequency circuit region 502 to the electrode pad 104 by rewiring (formed with copper, for example) in the packaging process (described later), the wiring thickness of the rewiring is about 10 μm. In the case where such a thick wiring exists on the high-frequency circuit, there is a possibility that characteristic variation may occur due to electrical coupling between the rewiring and the high-frequency circuit. In contrast, in the semiconductor device of the present embodiment, the high frequency signal is transmitted not by rewiring but by the metal wiring 205 (thickness: about 1 μm conductive layer) manufactured in the LSI formation process (described later). The coupling with the high frequency circuit is small, and the characteristic fluctuation can be suppressed.

  Next, in order to disclose further technical effects of the semiconductor device of this embodiment, reference will be made to the manufacturing process of this semiconductor device.

  Generally, a W-CSP semiconductor device is sealed in a wafer state and separated into individual pieces. The process in the wafer state is roughly divided into an LSI formation process and a package process (W-CSP process). The LSI formation process includes forming a high-frequency circuit and a low-frequency circuit (MOS transistor) of this embodiment (an LSI pre-process), and forming an interlayer insulating film with a metal wiring (conductive layer) on the electrode pad. A process (post-LSI process) until a passivation film (not shown in FIG. 2) is formed thereon as an insulating film for wiring protection is included.

  In the semiconductor device of this embodiment shown in FIG. 2, in the LSI formation process, the semiconductor substrate 101 is prepared, a low frequency circuit is formed in the low frequency circuit region 501 of the semiconductor substrate 101, and the high frequency circuit region of the semiconductor substrate 101 is formed. A high frequency circuit is formed at 502. On the low-frequency circuit region 501, electrode pads 103 and 104 are formed by a known technique. Further, a metal wiring 205 (conductive layer) for electrically connecting the high frequency circuit and the electrode pad 104 is formed by a known technique. In the LSI formation process so far, the electrical characteristics of the semiconductor device are optimized. In other words, in the LSI formation process, the semiconductor device is formed to have a design median value of electrical characteristics.

  The packaging process of the W-CSP semiconductor device is generally a process after the formation of the rewiring. In the semiconductor device of this embodiment, the forming process of each of the insulating layer 301, the protective film 303, the via 601 corresponding to the rewiring, the conductor posts 403 and 404, the sealing resin 701, and the external terminals 203 and 204 is included in the packaging process. It is. For example, a conventional technique disclosed in Japanese Patent Application Laid-Open No. 2006-302933 can be applied to the forming conditions of each forming step.

  As described above, the semiconductor device is manufactured so that the electrical characteristics are optimized in the LSI formation process. Therefore, if many parasitic components are added in the packaging process, the desired electrical characteristics can be obtained. (Or electrical characteristics vary), or a complicated design process of designing the LSI formation process so that the additional parasitic component is taken into consideration is required. In order to eliminate such considerations, it is desirable to minimize rewiring having parasitic components. In the semiconductor device of the present embodiment, the via 601 corresponding to rewiring is disposed only immediately above the electrode pads 103 and 104 and does not cause an offset in plan view, so that the parasitic component is minimized. Therefore, in the semiconductor device of this embodiment, the electrical characteristics once optimized in the LSI formation process are not easily affected by the packaging process after the LSI formation process.

  As described above, according to the W-CSP semiconductor device of the present embodiment, the variation in electrical characteristics associated with the packaging process can be minimized by suppressing the characteristic variation of the high-frequency circuit and minimizing the rewiring. Can be

<Modification>
Next, a modified example of the semiconductor device of the present embodiment will be described.

<Modification 1>
In the above-described embodiments, the semiconductor device in which the rewiring in the packaging process is minimized has been described. However, the partial rewiring, that is, the rewiring that causes an offset in a plan view is performed. It may be preferable. For example, when the electrode pads 103 and 104 are set to the power supply potential or the ground potential, they are set to the power supply potential or the ground potential rather than providing the via 601 individually for each electrode pad as in the above embodiment. It is preferable to connect the electrode pads to be connected to the external terminal by rewiring. Since the rewiring is formed wide by being integrated (shared) by rewiring, the parasitic components (resistance, inductance, etc.) of the wiring are reduced, and for example, power supply noise can be reduced.

<Modification 2>
Further, the basic concept described in the above-described embodiments can also be applied to a W-CSP semiconductor device having another structure. For example, FIG. 3 is a cross-sectional view of a W-CSP semiconductor device having a structure different from the structure shown in FIG. Note that the front view of the semiconductor device shown in FIG. 3 is the same as FIG. In FIG. 3, the same parts as those in the cross-sectional view shown in FIG.

Compared with the semiconductor device shown in FIG. 2, the semiconductor device shown in FIG. 3 has no conductor posts 403 and 404 and has a two-layer structure of insulating layers 801 and 803 without the sealing resin 701. Different. The insulating layers 801 and 803 are made of a polyimide-based or phenol-based resin, and the insulating layer 803 is provided in order to ensure moisture resistance reliability like the sealing resin 701.
The semiconductor device shown in FIG. 3 is the same as the semiconductor device shown in FIG. 2 in that the metal wiring 205 is provided in the wiring process of the LSI forming process. On the other hand, in the semiconductor device shown in FIG. 3, since the conductor post is not formed, the parasitic component of the conductor post is reduced as compared with that shown in FIG. Therefore, characteristic fluctuations of the high frequency circuit can be further suppressed.

<Modification 3>
As shown in FIG. 1, in the above-described embodiment, the case where the high-frequency circuit region 502 is formed in the central region of the semiconductor substrate has been described. However, the present invention is not limited to this. As shown in FIG. 4, the high-frequency circuit region 502 may be formed in the peripheral region of the semiconductor substrate. In the semiconductor device of the present invention, since rewiring is minimized regardless of the position of the high frequency circuit on the substrate, the high frequency circuit region 502 is formed on the semiconductor substrate as long as desired electrical characteristics are ensured in the LSI formation process. Even if it is not formed in the central region, the characteristic fluctuation of the high-frequency circuit is suppressed.

  The embodiment of the present invention has been described in detail above, but the specific structure is not limited to the present embodiment, and the design can be changed without departing from the gist of the present invention and applied to other structures. Etc. are also included.

It is a top view of the semiconductor device of a 1st embodiment, and shows the state before being sealed with sealing resin. It is sectional drawing about AA of FIG. It is sectional drawing of the semiconductor device which concerns on the modification of 1st Embodiment. It is a top view of the semiconductor device which concerns on the modification of 1st Embodiment, Comprising: The state before sealing with sealing resin is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Semiconductor substrate 103, 104 ... Electrode pad 203, 204 ... External terminal 301 ... Insulating layer 303 ... Protective film 403, 404 ... Conductor post 501 ... Low frequency circuit area 502 ... High frequency circuit area 601 ... Via 701 ... Sealing resin

Claims (8)

A first region in which a high-frequency circuit is formed; and a low-frequency circuit, a plurality of first electrode pads for the high-frequency circuit, and a plurality of for the low-frequency circuit. A semiconductor substrate having a main surface including a second region in which a second electrode pad is formed;
An insulating film formed on the main surface;
A sealing resin covering the insulating film;
Is formed directly on the plurality of first electrode pads, and a plurality of first external terminal protrudes is electrically connected to the plurality of first electrode pads from the surface of the sealing resin,
Is formed directly on the plurality of second electrode pads, and a plurality of second external terminal protrudes is electrically connected to the plurality of second electrode pads from the surface of the sealing resin,
A conductive layer formed on the main surface of the semiconductor substrate while being covered with the insulating film, and electrically connecting the high-frequency circuit and the first electrode pad;
A semiconductor device comprising:   Of the plurality of first electrode pads and the plurality of second electrode pads, electrode pads connected to a power supply potential or a ground potential are respectively connected to a single rewiring formed on the insulating film. The semiconductor device according to claim 1. The semiconductor device according to claim 1, wherein the insulating film is made of silicon oxide. The semiconductor device according to claim 1, wherein a protective film made of polyimide is formed between the insulating film and the sealing resin. Preparing a semiconductor substrate having a main surface including a first region and a second region around the first region;
  Forming a high frequency circuit in the first region;
  Forming a low frequency circuit, a plurality of first electrode pads for the high frequency circuit, and a second electrode pad for the low frequency circuit in the second region;
  Forming a conductive layer on the main surface of the semiconductor substrate for electrically connecting the high-frequency circuit and the first electrode pad from the first region to the second region;
  Forming an insulating film on the main surface of the semiconductor substrate so as to cover the conductive layer and the first and second regions;
  Forming a sealing resin covering the insulating film;
  Forming a plurality of first external terminals protruding from the surface of the sealing resin so as to be located immediately above the plurality of first electrode pads and electrically connected to the plurality of first electrode pads;
  Forming a plurality of second external terminals that protrude from the surface of the sealing resin so as to be positioned directly above the plurality of second electrode pads and are electrically connected to the plurality of second electrode pads;
  A method for manufacturing a semiconductor device comprising: Forming a single rewiring on the insulating film to which an electrode pad connected to a power supply potential or a ground potential among the plurality of first electrode pads and the plurality of second electrode pads is connected. Item 6. A method for manufacturing a semiconductor device according to Item 5. The method for manufacturing a semiconductor device according to claim 5, wherein the insulating film is made of silicon oxide. Forming a protective film made of polyimide on the insulating film;
  The method for manufacturing a semiconductor device according to claim 5, wherein the sealing resin is formed on the protective film.

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