JP4653869B2 - Delay clock generation apparatus and semiconductor test apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a delay clock generation apparatus that generates a delay clock having a predetermined delay amount, and in particular, the present invention generates a pulse having a leading edge or a trailing edge of a reference clock as a rising timing in accordance with the delay amount to be generated. The present invention relates to a delay clock generator. The present invention also relates to a semiconductor test apparatus including the delay clock generation apparatus.
[0002]
[Prior art]
FIG. 1 shows a conventional timing generator 28. The timing generator 28 includes the delayed clock generator 10 and the reference clock generator 22. The delay clock generation device 10 includes a period delay unit 12, an AND circuit 14, a high resolution delay unit 16, a timing memory 18, and a linearization memory 20. The high resolution delay unit 16 may be, for example, a variable delay circuit that generates a plurality of delay amounts by a combination of a plurality of delay elements.
[0003]
The timing memory 18 stores data of a predetermined delay amount included in the delay clock generated by the delay clock generation device 10 by dividing the data into a delay amount that is an integral multiple of the reference clock period and a delay amount that is less than the reference clock period. is doing. When the timing memory 18 inputs a timing set signal designating that a predetermined delay amount stored in the timing memory 18 is set in the periodic delay unit 12 and the linearize memory 20, the timing memory 18 periodically delays the data having an integral multiple of the delay amount. The data is output to the unit 12, and data with a delay amount less than the period is output to the linearize memory 20.
[0004]
The linearize memory 20 outputs delay path data for setting a combination of delay elements that generate a delay amount less than a period to the high resolution delay unit 16.
[0005]
The period delay unit 12 counts the number of pulses of the reference clock supplied from the reference clock generation unit 22 when receiving a delay clock generation start signal designating generation of a delay clock having a predetermined delay amount. When the number of pulses of the reference clock counted by the period delay unit 12 and the data of the integral multiple of the delay amount match, the AND circuit 14 generates one pulse synchronized with the reference clock.
[0006]
The high resolution delay unit 16 further delays the pulse supplied from the AND circuit 14 by a combination of delay elements set by the delay path data supplied from the linearize memory 20 to generate a delay clock having a predetermined delay amount. Generate.
[0007]
FIG. 2 is a timing chart of the conventional timing generator 28 described with reference to FIG. A timing set signal is supplied in synchronization with the delayed clock generation start signal. For example, when generating a delay clock having a delay amount of 13 ns and 11 ns, the timing set signal TS1 specifies that a delay clock having a delay amount of 13 ns is generated, and the timing set signal TS2 indicates a delay amount of 11 ns. Specifies to generate a delay clock having. In the example of the timing chart of FIG. 2, the period of the reference clock is 4 ns.
[0008]
When the timing set signal TS1 is supplied, the period delay unit 12 counts the reference clock three times, and then outputs an enable signal (logical value “1”) to the AND circuit 14 (point A). The AND circuit 14 outputs a pulse having a delay amount of 12 ns based on the enable signal from the period delay unit 12 and the reference clock (point B). The high resolution delay unit 16 further delays the pulse supplied from the AND circuit 14 by 1 ns and outputs it.
[0009]
When the timing set signal TS2 is supplied, the period delay unit 12 counts the reference clock twice and then outputs an enable signal (logical value “1”). The AND circuit 14 outputs a pulse having a delay amount of 8 ns based on the enable signal from the period delay unit 12 and the reference clock (point B). The high resolution delay unit 16 outputs the pulse supplied from the AND circuit 14 with a delay of 3 ns.
[0010]
[Problems to be solved by the invention]
The conventional timing generator shown in FIG. 1 generates a delay amount less than the period of the reference clock by the high resolution delay unit 16. The high resolution delay unit 16 that generates a delay amount by a combination of a plurality of delay elements generates heat according to the generated delay amount. The amount of heat generation increases in proportion to the amount of delay generated. The high resolution delay unit 16 generates an error in the generated delay amount due to the influence of heat generation. Further, since the influence of power supply noise is also proportional to the delay amount, the error in the delay amount increases as a large delay amount is generated. Furthermore, as the delay amount increases, the power supply noise generated by the high resolution delay unit 16 also increases.
[0011]
Therefore, an object of the present invention is to provide a delay clock generation device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.
[0012]
[Means for Solving the Problems]
In order to solve the above-described problem, a first aspect of the present invention is a delay clock generation device that generates a delay clock having a predetermined delay amount, which is an integral multiple of a reference clock cycle shorter than the predetermined delay amount. A difference between a cyclic delay unit that generates a delay amount, a half-cycle delay unit that generates a half-cycle delay amount of a reference clock, a sum of delay amounts generated by the cyclic delay unit and the half-cycle delay unit, and a predetermined delay amount And a high-resolution delay unit that adds the delay amount to the delay amount generated by the period delay unit and the half-cycle delay unit.
[0013]
In one aspect of the first form, the half-cycle delay unit inputs a signal having a delay amount generated by the cycle delay unit, and receives a signal input at the timing of either the leading edge or the trailing edge of the reference clock. You may supply to a high-resolution delay part.
[0014]
In another aspect of the first aspect, when the period delay unit generates an integer multiple of the delay amount with reference to either the leading edge or the trailing edge of the reference clock, the half period delay unit A pulse having the other leading edge or trailing edge as a rising timing may be generated. The half-cycle delay unit may include a logic gate that generates a pulse whose rising timing is the trailing edge of the reference clock. In addition, it further includes a logic gate that generates a pulse having a delay amount generated by the period delay unit based on the reference clock, and the half cycle delay unit adjusts the pulse width of the pulse generated by the logic gate to a predetermined pulse width. And a pulse width adjusting unit that performs the same.
[0015]
Further, the pulse width adjustment unit may include a delay element that generates a delay amount corresponding to a predetermined pulse width. A first storage unit that stores data for setting an integral multiple delay amount in the period delay unit; a second storage unit that stores data for setting a half cycle delay amount of the reference clock in the half cycle delay unit; The delay amount obtained by excluding the delay amount set by the data stored in the first storage unit from the predetermined delay amount and the delay amount set by the data stored in the second storage unit is set in the high resolution delay unit. And a third storage unit for storing data to be stored. The period delay unit may include a counter that counts the number of pulses of the reference clock and a logic gate that determines whether or not the number of pulses is equal to data stored in the first storage unit.
[0016]
Also, a linearized memory that stores a delay path in a high-resolution delay unit that generates a delay amount set by data stored in the third storage unit, and a linearized memory storage control unit that stores the delay path in the linearized memory The linearized memory storage control unit is supplied from the measurement pulse generation unit that generates the measurement pulse having a predetermined pulse width, the pulse input unit that inputs the measurement pulse, and the pulse input unit. A pulse shaping unit that inverts the measurement pulse and supplies it to at least one of the period delay unit and the half-cycle delay unit, and the pulse shaping unit supplies at least one of the period delay unit and the half-cycle delay unit for a predetermined time interval Based on the counter unit that counts the number of measured pulses and the number of measurement pulses counted by the counter unit, the delay amount of the delay path is measured. It may have a delay amount measuring section for storing in association with each delay path and the measured delay in the linearization memory.
[0017]
In addition, a half-cycle delay detection unit that specifies whether to invert the measurement pulse may be further provided in the pulse generation unit based on whether or not a half-cycle delay amount is generated. Further, when measuring the delay amount generated at the timing of the leading edge of the reference clock, the half-cycle delay detection unit may instruct the pulse generation unit to invert the measurement pulse. The pulse shaping unit may have a logic gate for inverting the measurement pulse. The delay amount measurement unit stores the amount of deviation between the phase generated by inverting the measurement pulse and the phase generated by not inverting the measurement pulse in the linearize memory in addition to the delay amount of the delay path. May be.
[0018]
According to a second aspect of the present invention, in a semiconductor test apparatus for testing a semiconductor device, a period delay unit that generates a delay amount that is an integer multiple of a reference clock period shorter than a predetermined delay amount, and a half-cycle delay of the reference clock A delay generated by the period delay unit and the half cycle delay unit, and a delay amount of a difference between the sum of the delay amounts generated by the period delay unit and the half cycle delay unit and a predetermined delay amount. A timing generator that generates a delay clock having a predetermined delay amount, a pattern generator that generates a test pattern to be input to a semiconductor device, a delay clock and a test pattern Based on the waveform shaper that outputs a shaped test pattern that is shaped to be applied to a semiconductor device, and the device connection that inputs the shaped test pattern to the semiconductor device. A comparator for determining the quality of the semiconductor device by comparing the output signal output from the semiconductor device to which the shaping test pattern is input and the expected value to be output from the semiconductor device output from the pattern generator; A semiconductor test apparatus is provided.
[0019]
The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the claimed invention, and all combinations of features described in the embodiments are the solution of the invention. It is not always essential to the means.
[0021]
FIG. 3 is a block diagram illustrating one embodiment of a semiconductor test apparatus. The semiconductor test apparatus includes a pattern generator 24, a delay signal generation apparatus 30, a device contact portion 32, and a comparator 34. The delay signal generation device 30 includes a waveform shaper 26 and a timing generator 28.
[0022]
The device under test 36 is attached so as to be in electrical contact with the device contact portion 32. The pattern generator 24 generates pattern data that is a test pattern to be input to the device under test 36 and expected value data to be output from the device under test 36 that has received the pattern data. The pattern generator 24 outputs the pattern data to the waveform shaper 26 and outputs the expected value data to the comparator 34. In addition, the pattern generator 24 generates data necessary for generating a delay clock having a predetermined delay amount according to the operation characteristics of the device under test 36, and the period delay unit 12 (not shown) and the linearized memory 20 (not shown). ) Is output to the timing generator 28.
[0023]
The timing generator 28 generates a delay clock having a delay amount specified by the timing set signal and outputs it to the waveform shaper 26.
[0024]
The waveform shaper 26 shapes the pattern data based on the delay clock supplied from the timing generator 28, and outputs the shaped pattern data corresponding to the operating characteristics of the device under test 36 to the device contact unit 32. The device under test 36 outputs an output value for the shaping pattern data to the comparator 34 via the device contact portion 32. The comparator 34 compares the output value with the expected value data supplied from the pattern generator 24 to determine pass / fail of the device under test 36.
[0025]
FIG. 4 is a block diagram illustrating one embodiment of the timing generator 28. The timing generator 28 includes a reference clock generator 22 and a delay clock generator 10. The delay clock generation device 10 includes a cycle delay unit 12, a half cycle delay unit 40, a high resolution delay unit 16, a timing memory 18, and a linearize memory 20. The timing memory 18 includes a first storage unit 18a, a second storage unit 18b, and a third storage unit 18c. The high resolution delay unit 16 may be, for example, a variable delay circuit that includes a plurality of delay elements and generates a plurality of delay amounts by a combination of delay elements.
[0026]
The timing memory 18 stores data of a predetermined delay amount generated by the delay clock generation device 10 in the first storage unit 18a, the second storage unit 18b, and the third storage unit 18c. The first storage unit 18a stores data for setting a delay amount, which is an integral multiple of the reference clock cycle shorter than a predetermined delay amount, in the period delay unit 12. The second storage unit 18b stores data for setting the half cycle delay amount of the reference clock in the half cycle delay unit 40. The third storage unit 18c is obtained by excluding a delay amount set by data stored in the first storage unit and a delay amount set by data stored in the second storage unit from a predetermined delay amount. Is stored in the high resolution delay unit 16.
[0027]
When the timing memory 18 receives the timing set signal, the timing memory 18 converts the data stored in the first storage unit 18a, the second storage unit 18b, and the third storage unit 18c to the period delay unit 12, the half cycle delay unit 40, and the linearized memory, respectively. 20 is output.
[0028]
When the delay clock generation start signal is input, the period delay unit 12 counts the number of reference clock pulses supplied from the reference clock generation unit 22. The cycle delay unit 12 outputs a match signal indicating a match to the half cycle delay unit 40 when the count value of the reference clock matches the data set by the first storage unit 18a. When the coincidence signal is supplied from the cycle delay unit 12, the half cycle delay unit 40 delays the half cycle of the reference clock to the delay amount generated by the cycle delay unit 12 based on the data stored in the second storage unit 18b. Set whether to add quantity. For example, the half-cycle delay unit 40 may generate a pulse at the timing of either the leading edge or the trailing edge of the reference clock. The data stored in the second storage unit 18b is data specifying that a delay amount of a half cycle of the reference clock is added, and the cycle delay unit 12 is based on either the leading edge or the trailing edge of the reference clock. When generating a delay amount that is an integral multiple of the clock period, the half-cycle delay unit 40 may generate a pulse having the other edge of the leading edge or the trailing edge of the reference clock as a rising timing.
[0029]
The high resolution delay unit 16 further delays the pulse supplied from the half-cycle delay unit 40 by a combination of delay elements set by the delay path data supplied from the linearize memory 20 and has a predetermined delay amount. Generate a clock.
[0030]
FIG. 5 is a block diagram showing a detailed configuration of the timing generator 28 described with reference to FIG. 5 with the same reference numerals as those in FIG. 4 perform the same or similar functions and operations as the corresponding components in FIG. The timing generator 28 includes a reference clock generator 22 and a delay clock generator 10. The delay clock generation device 10 includes a cycle delay unit 12, a half cycle delay unit 40, a high resolution delay unit 16, a first storage unit 18a, a second storage unit 18b, a third storage unit 18c, and a linearized memory 20. The period delay unit 12 includes a counter 62, an ENOR circuit (54a, 54b... 54i), and an AND circuit 56a. The half-cycle delay unit 40 includes AND circuits (56b, 56c, 56d, and 56e), flip-flops 58a and 58b, and an OR circuit 60.
[0031]
The reference clock generator 22 shown in FIG. 5 generates a reference clock having a period of 4 ns. For example, when generating a delay clock having a delay amount of 11 ns, the first storage unit 18a stores data (000000010) for setting the delay amount of 8 ns in the periodic delay unit 12 as 9-bit data. The second storage unit 18b stores data (logical value “1”) for setting a half cycle (2 ns) delay amount of the reference clock in the half cycle delay unit 40 as 1-bit data. The third storage unit 18c stores, as 7-bit data, data (1000000) for setting the 1 ns delay amount obtained by removing the 8 ns and 2 ns delay amounts from the 11 ns delay amount in the high resolution delay unit 16.
[0032]
When the counter 62 receives the delayed clock generation start signal, the counter 62 starts counting the reference clock. The counter 62 counts the reference clock at the rising edge of the pulse and outputs it as 9-bit data. In another embodiment, the counter 62 may count the reference clock at the falling edge of the pulse. The ENOR circuit 54a outputs a logical value “1” when the least significant bit of the count value output from the counter 62 and the least significant bit of the data stored in the first storage unit 18a have the same logical value. . Similarly to the ENOR circuit 54a, the ENOR circuits 54b to 54i output a logical value “1” when the corresponding bits are the same. The AND circuit 56a outputs a logical value “1” when all the output values of the ENOR circuits (54a to 54i) are the logical value “1”. Therefore, when the data stored in the first storage unit 18a is 000000010 (data for setting a delay amount of 8 ns), the cycle delay unit 12 indicates that the count value is 000000010 (counting the reference clock pulse twice). The logic value “1” is output to the half-cycle delay unit 40.
[0033]
If the count value is equal to the data stored in the first storage unit 18a, if the data stored in the second storage unit 18b is the logical value “0”, the logical value “1” is output from the AND circuit 56b. Is output. The flip-flop 58a holds the output value (logical value “1”) from the AND circuit 56b at the falling timing of the reference clock. The AND circuit 56 d generates a pulse having the leading edge of the reference clock as a rising timing, and outputs the pulse to the high resolution delay unit 16 via the OR circuit 60.
[0034]
If the count value is equal to the data stored in the first storage unit 18a, if the data stored in the second storage unit 18b is the logical value “1”, the logical value “1” is output from the AND circuit 56c. Is output. The flip-flop 58b holds the output value (logical value “1”) from the AND circuit 56c at the rising timing of the reference clock. The AND circuit 56e generates a pulse having the rising edge as the trailing edge of the reference clock, and outputs the pulse to the high resolution delay unit 16 via the OR circuit 60.
[0035]
In another embodiment, if the counter 62 counts the number of pulses at the falling edge of the pulse and adds a half-cycle delay amount of the reference clock, the half-cycle delay unit 40 rises the leading edge of the reference clock. A pulse with timing may be generated. If the delay amount of the half cycle of the reference clock is not added, the half cycle delay unit 40 may generate a pulse having the rising edge as the trailing edge of the reference clock.
[0036]
The high resolution delay unit 16 further delays the pulse supplied from the half-cycle delay unit 40 by a combination of delay elements set by the delay path data supplied from the linearize memory 20 and has a predetermined delay amount. Generate a delayed clock.
[0037]
FIG. 23 is a functional block diagram of another embodiment of the timing generator 28 described with reference to FIG. 23, the same reference numerals as those in FIG. 5 denote the same or similar functions and configurations as the corresponding configurations in FIG. In FIG. 23, the linearize memory 20 stores data for setting a half-cycle delay amount of the reference clock in the half-cycle delay unit 40.
[0038]
The linearize memory 20 outputs to the half cycle delay unit 40 a signal designating generation of a delay amount of a half cycle of the reference clock. For example, the linearized memory 20 stores data (logical value “1”) for setting a half-cycle delay amount of the reference clock in the most significant bit. Since the linearize memory 20 stores data for setting the delay amount of the half cycle of the reference clock, it can be specified that the delay amount of the half cycle of the reference clock is generated.
[0039]
FIG. 6 shows a timing chart of the timing generator 28 described with reference to FIG. A timing set signal is supplied in synchronization with the delayed clock generation signal. For example, when generating a delay clock having a delay amount of 13 ns and 11 ns, the timing set signal TS1 specifies that a delay clock having a delay amount of 13 ns is generated, and the timing set signal TS2 indicates a delay amount of 11 ns. Specifies to generate a delay clock having.
[0040]
When the timing set signal TS1 is supplied, after the period delay unit 12 counts the reference clock three times, the point A1 in FIG. 5 is enabled (logical value “1”). The AND circuit 56d generates a pulse having a delay amount of 12 ns with the leading edge of the reference clock as a rising timing (point B1). The high resolution delay unit 16 further delays the pulse supplied from the OR circuit 60 by 1 ns to generate a delay clock having a delay amount of 13 ns.
[0041]
When the timing set signal TS2 is supplied, after the period delay unit 12 counts the reference clock three times, the point A2 in FIG. 5 is enabled (logical value “1”). The AND circuit 56e generates a pulse having a delay amount of 10 ns with the trailing edge of the reference clock as the rising timing (point B2). The high resolution delay unit 16 further delays the pulse supplied from the OR circuit 60 by 1 ns to generate a delay clock having a delay amount of 11 ns. Therefore, in the present embodiment, the high resolution delay unit 16 may generate a delay amount less than a half cycle of the reference clock.
[0042]
However, in reality, the delay amount actually generated by the delay element is designed according to variations in the quality of the delay element included in the high-resolution delay unit 16, temperature conditions, voltage conditions, and the like when the delay element is used. There may be an error between the delay amount. Therefore, it is preferable that the high resolution delay unit 16 can generate a delay amount larger than the time obtained by subtracting the pulse width of the reference clock from the cycle of the reference clock in consideration of the variation in the quality of the delay elements. For example, when the period of the reference clock is 4000 ps and the pulse width of the reference clock is 2000 ps, the high resolution delay unit 16 preferably generates a delay amount of about 0 ps to 2500 ps.
[0043]
When the half cycle of the reference clock is 2000 ps and the high resolution delay unit 16 can generate a delay amount of 0 ps to 2500 ps, the delay clock generator 10 can generate a delay amount of 0 to 2500 ps by the high resolution delay unit 16. Further, the delay clock generation device 10 can generate a delay amount of 2000 ps to 4500 ps by delaying the pulse generated at the timing of the trailing edge of the reference clock by the high resolution delay unit 16.
[0044]
The delay clock generation device 10 delays a pulse generated at the timing of the trailing edge of the reference clock by the high resolution delay unit 16 using the first generation method of generating a delay amount of 2000 ps to 2500 ps by the high resolution delay unit 16. It can produce | generate by two methods of the 2nd production | generation method to produce | generate.
[0045]
For example, when generating a delay amount of 2010 ps, the delay clock generator 10 generates a pulse generated at the timing of the trailing edge of the reference clock and the first generation method of generating a delay amount of 2010 ps by the high resolution delay unit 16. It can be generated by any one of the second generation methods that generate a delay amount of 2010 ps with a delay of 10 ps by the high resolution delay unit 16.
[0046]
FIG. 7 shows a timing chart when a delay amount of 2000 ps to 2500 ps is generated by the second generation method in the first cycle of the reference clock and is generated by the first generation method in the second cycle of the reference clock. In the first cycle, when a delay amount of 2000 ps to 2500 ps is generated by the second generation method, a pulse is generated at the timing of the trailing edge of the reference clock (point B2 in FIG. 5). In the second cycle, when a delay amount of 2000 ps to 2500 ps is generated by the first generation method, a pulse is generated at the timing of the leading edge of the reference clock (point B1 in FIG. 5). Therefore, the pulses overlap at point B3 in FIG. It is necessary to set a delay generation method so that pulses do not overlap at point B3.
[0047]
FIG. 8 is a diagram illustrating the relationship between the delay amount and the data for setting the delay amount by the first generation method and the second generation method described with reference to FIG. The delay clock generation device 10 can generate a delay amount of 0 ps to 2000 ps by the first generation method, and can generate a delay amount of 2000 ps to 4500 ps by the second generation method. In FIG. 8, the delay amount of 2000 ps to 2500 ps can be generated by any one of the first generation method and the second generation method. It is necessary to set a method for generating the delay amount of the overlapping portion so that the pulses do not overlap at the point B3 described with reference to FIG. In the present embodiment, the delay amount of the overlapping portion is generated by the first generation method so that the pulses do not overlap. Therefore, in the overlapping portion, the logical value “0” is stored in the second storage unit 18b, and data less than the cycle of the reference clock is stored in the third storage unit 18c. In another embodiment, the delay amount of the overlapping portion may be generated by the second generation method.
[0048]
FIG. 9 is a block diagram illustrating another embodiment of the timing generator 28. The timing generator 28 includes a reference clock generator 22 and a delay clock generator 10. The delay clock generation device 10 includes a cycle delay unit 12, an AND circuit 42, a half cycle delay unit 40, a high resolution delay unit 16, a timing memory 18, and a linearization memory 20. The half cycle delay unit 40 includes a pulse width adjustment unit 44. The timing memory 18 includes a first storage unit 18a, a second storage unit 18b, and a third storage unit 18c. 9, the same reference numerals as those in FIG. 4 denote the same or similar functions and operations as the corresponding structures in FIG.
[0049]
When the timing memory 18 receives the timing set signal, the timing memory 18 converts the data stored in the first storage unit 18a, the second storage unit 18b, and the third storage unit 18c to the period delay unit 12, the half cycle delay unit 40, and the linearized memory, respectively. 20 is output. For example, when a delay clock having a reference clock period of 4 ns and a delay amount of 11 ns is generated, the first storage unit 18 a stores data for setting a delay amount of 8 ns in the period delay unit 12. The second storage unit 18b stores data for setting the delay amount of the half cycle (2 ns) of the reference clock in the half cycle delay unit 40. The third storage unit 18c stores data for setting the 1 ns delay amount obtained by removing the 8 ns and 2 ns delay amounts from the 11 ns delay amount in the high resolution delay unit 16.
[0050]
When the delay clock generation start signal is input, the period delay unit 12 counts the number of reference clock pulses supplied from the reference clock generation unit 22. When the number of pulses of the reference clock counted by the period delay unit 12 matches the data set by the first storage unit 18a, the AND circuit 42 generates one pulse based on the reference clock. For example, if the cycle of the reference clock is 4 ns and the first storage unit 18a stores data for setting the delay amount of 8 ns in the cycle delay unit 12, the cycle delay unit 12 counts the reference clock pulse twice. The AND circuit 42 generates one pulse.
[0051]
The pulse width adjusting unit 44 included in the half cycle delay unit 40 is provided to set the pulse width of the pulse generated by the half cycle delay unit 40 to a predetermined pulse width. The half-cycle delay unit 40 generates a pulse having a predetermined pulse width based on the data stored in the second storage unit 18b, with the timing of the leading edge or trailing edge of the pulse supplied from the AND circuit 42 as the rising timing. To do. For example, when the second storage unit 18b stores data for setting the half-cycle delay amount of the reference clock in the half-cycle delay unit 40, a pulse whose rising edge is the trailing edge of the pulse supplied from the AND circuit 42 Is generated.
[0052]
The high resolution delay unit 16 further delays the pulse supplied from the half-cycle delay unit 40 by a combination of delay elements set by the delay path data supplied from the linearize memory 20 and has a predetermined delay amount. Generate a clock.
[0053]
FIG. 10 is a block diagram showing a detailed configuration of the half-cycle delay unit 40. When the data stored in the second storage unit 18b is a logical value “1”, the AND circuit 48 is enabled. The pulse width adjustment unit 44 delays the pulse supplied from the AND circuit 42 by a predetermined pulse width pwd. For example, the pulse width adjustment unit 44 may be a delay element that delays the input signal by a predetermined pulse width pwd. The AND circuit 48 calculates the logical product of the pulse supplied from the AND circuit 42 and the pulse delayed by the pulse width adjustment unit 44, and has a predetermined pulse width with the trailing edge of the pulse supplied from the AND circuit 42 as the rising timing. Generate a pulse with pwd.
[0054]
Second storage unit 18 b When the data stored in is a logical value “0”, the AND circuit 50 is enabled. The pulse width adjustment unit 44 delays the pulse supplied from the AND circuit 42 by a predetermined pulse width pwd. The AND circuit 50 calculates a logical product of the pulse supplied from the AND circuit 42 and the pulse delayed by the pulse width adjustment unit 44, and has a predetermined pulse width with the leading edge of the pulse supplied from the AND circuit 42 as a rising timing. Generate a pulse with pwd. The OR circuit 52 outputs the pulse generated by either the AND circuit 48 or the AND circuit 50 to the high resolution delay unit 16.
[0055]
FIG. 11 is a timing chart of the half-cycle delay unit 40 described with reference to FIG. When the data stored in the second storage unit 18b is a logical value “0”, the half-cycle delay unit 40 has a predetermined pulse width pwd whose rising timing is the leading edge of the pulse supplied from the AND circuit 42. Generate a pulse.
[0056]
When the data stored in the second storage unit 18 b is a logical value “1”, the half-cycle delay unit 40 has a predetermined pulse width pwd whose rising timing is the trailing edge of the pulse supplied from the AND circuit 42. Generate a pulse.
[0057]
FIG. 12 shows a timing chart of the timing generator 28 described with reference to FIG. A timing set signal is supplied in synchronization with the delayed clock generation signal. For example, when generating a delay clock having a delay amount of 13 ns and 11 ns, the timing set signal TS1 specifies that a delay clock having a delay amount of 13 ns is generated, and the timing set signal TS2 indicates a delay amount of 11 ns. Specifies to generate a delay clock having.
[0058]
When the timing set signal TS1 is supplied, after the period delay unit 12 counts the reference clock four times, the point D in FIG. 10 is enabled (logical value “1”). The AND circuit 42 generates a pulse having a delay amount of 12 ns (point E). The half-cycle delay unit 40 uses the leading edge of the pulse supplied from the AND circuit 42 as the rising timing, and outputs a pulse having a predetermined pulse width pwd to the high resolution delay unit 16 (point F). The high resolution delay unit 16 further delays the pulse supplied from the half-cycle delay unit 40 by 1 ns to generate a delay clock having a delay amount of 13 ns.
[0059]
When the timing set signal TS2 is supplied, after the period delay unit 12 counts the reference clock three times, the point D in FIG. 10 is enabled (logical value “1”). The AND circuit 42 generates a pulse having a delay amount of 8 ns (point E). The half-cycle delay unit 40 uses the trailing edge of the pulse supplied from the AND circuit 42 as the rising timing, and outputs a pulse having a predetermined pulse width pwd to the high resolution delay unit 16 (point F). The high resolution delay unit 16 further delays the pulse supplied from the half-cycle delay unit 40 by 1 ns to generate a delay clock having a delay amount of 11 ns.
[0060]
When the delay clock is generated by the delay clock generator 10, it is necessary to store the delay path data in the linearization memory 20 in advance. The delay clock generation apparatus 10 measures the delay amount generated by the combination of each delay element by loop measurement, and stores delay path data for specifying a delay path for generating a desired delay amount in the linearization memory 20. After storing the delay path data in the linearized memory 20, the delay clock generation device 10 performs an actual operation of generating a delay clock to be supplied to the waveform shaper 26.
[0061]
FIG. 13 shows a delay amount generated by the delay clock generation device 10 during loop measurement and actual operation. A straight line A indicates a delay amount at the time of loop measurement. A straight line B indicates a delay amount in actual operation. When the delay amount is generated by the first generation method in which the delay amount is generated only by the high resolution delay unit 16, no error occurs between the loop measurement and the actual operation. However, when the delay amount is generated by the second generation method of generating the delay amount by the period delay unit 12, the half-cycle delay unit 40, and the high resolution delay unit 16, there is an error between the loop measurement and the actual operation. Arise.
[0062]
FIG. 14 is a functional block diagram of the timing generator 28 including a linearized memory storage control unit 100 that stores delay path data in the linearized memory 20 and a plurality of the delayed clock generators 10 described with reference to FIG. The linearized memory storage control unit 100 includes an OR circuit 102, a first pulse shaping unit 104, a buffer 105, a half-cycle delay detection unit 106, an AND circuit 108, an OR circuit 110, a measurement pulse generation unit 111, and a second pulse shaping unit 112. An AND circuit 114, a counter unit 116, and a delay amount measuring unit 118. The OR circuit 110 corresponds to the pulse input unit described in claim 9. When performing loop measurement, the linearized memory storage control unit 100 includes an AND circuit 108, an OR circuit 110, a second pulse shaping unit 112, an AND circuit 114, an OR circuit 102, a first pulse shaping unit 104, and a delay clock generation device. The closed circuit including 10 is enabled. When enabling the closed circuit, the linearized memory storage control unit 100 applies the logical value “1” to the Loop Enable terminals of the AND circuit 108 and the AND circuit 114. Therefore, the linearized memory storage control unit 100 can enable the closed circuit.
[0063]
The measurement pulse generator 111 generates a measurement pulse used for measuring the delay amount. For example, the measurement pulse generator 111 generates one pulse as a measurement pulse. The measurement pulse generator 111 outputs the generated measurement pulse to the closed circuit via the OR circuit 110. The measurement pulse circulates in a closed circuit including the delay clock generator 10.
The pulse width of the measurement pulse decreases or expands due to the difference between the rise time and the fall time of the semiconductor gate through which the measurement pulse passes during circulation. The first pulse shaping unit 104 and the second pulse shaping unit 112 correct the pulse width of the measurement pulse. The buffer 105 outputs the measurement pulse supplied from the first pulse shaping unit 104 to the delay clock generation devices (10a, 10b...).
[0064]
The counter unit 116 measures the number of times the measurement pulse is circulated in a certain period, and calculates the difference between the frequency when the minimum delay path having the minimum delay amount is selected and the frequency when another delay path is selected. Output to the delay amount measuring unit 118. The delay amount measuring unit 118 has a delay amount closest to a predetermined delay time based on the difference between the frequency when the minimum delay route is selected and the frequency when another delay route is selected. Select. The delay amount measuring unit 118 stores delay path data for specifying the selected delay path in the linearized memory 20.
[0065]
Here, the reason why the error described with reference to FIG. 13 occurs will be described with reference to FIG. FIG. 15A shows a pulse output from the second pulse shaping unit 112 and a pulse output from the first pulse shaping unit 104. The leading edge and trailing edge of the pulse output from the first pulse shaping unit 104 are not settling. For example, the pulse output from the first pulse shaping unit 104 can be stabilized by increasing the driving capability of the buffer 105. Further, for example, by increasing the number of stages of the buffer 105, the pulse output from the first pulse shaping unit 104 can be settled. However, increasing the drive capability of the buffer 105 or increasing the number of stages of the buffer 105 causes problems such as increased power consumption, increased power supply noise, and increased propagation delay time. Increased power consumption makes it difficult to increase the density of LSIs. Further, an increase in power supply noise and an increase in propagation delay time lead to deterioration in accuracy.
[0066]
By reducing the drive capability of the buffer 105 and reducing the number of stages of the buffer 105, power consumption can be reduced, power supply noise can be reduced, and propagation delay time can be reduced. However, like the pulse shown in FIG. 15A, the leading and trailing edges of the pulse are not settling. Since the leading edge and trailing edge of the pulse are not settled, the voltage does not reach the peak value of the pulse, causing a phase shift. This phase shift occurs due to interference between pulses, which is defined as intersymbol interference. This phase shift becomes an error between the delay amount at the time of the loop measurement described with reference to FIG. 13 and the delay amount at the actual operation.
[0067]
In FIG. 15A, a value obtained by subtracting the phase of the leading edge of the reference clock during actual operation from the phase of the leading edge of the measuring pulse during loop measurement is a, and the phase of the trailing edge of the measurement pulse during loop measurement. When the value obtained by subtracting the phase of the trailing edge of the reference clock during actual operation is b, the linearity error is b−a. Since the way of receiving interference from the previous pulse differs between the loop measurement and the actual operation, there is an error between the delay amount during the loop measurement described with reference to FIG. 13 and the delay amount during the actual operation. Also, the interference received from the previous pulse during the actual operation is greater when the leading edge of the pulse receives from the previous pulse than the difference between the actual operation of the interference received from the previous pulse at the trailing edge of the pulse and the loop measurement. Become.
[0068]
FIG. 16A shows the result of simulating intersymbol interference. FIG. 16B is an enlarged view of the vicinity of 10 ns, which is the same simulation result as FIG. From FIG. 16 (b), the phase of the curve “actual operation” indicating the output of the first pulse shaping unit 104 during actual operation and the curve “true” indicating the output of the first pulse shaping unit 104 during loop measurement are obtained. I can see the gap. FIG. 16B shows that the phase shift due to intersymbol interference is larger at the leading edge (a> b). It can also be seen that the phase shift due to intersymbol interference at the trailing edge is small. Based on this simulation result, the inventor considered that a phase shift due to intersymbol interference is suppressed by generating a delay amount at the timing of the trailing edge during loop measurement.
[0069]
FIG. 15B shows a pulse output from the second pulse shaping unit 112 and a pulse obtained by inverting the pulse supplied from the second pulse shaping unit 112 output from the first pulse shaping unit 104. In FIG. 15B, the value obtained by subtracting the phase of the leading edge of the reference clock during actual operation from the phase of the leading edge of the measuring pulse during loop measurement is c, and the phase of the trailing edge of the measurement pulse during loop measurement. When the value obtained by subtracting the phase of the trailing edge of the reference clock during actual operation is b, the linearity error is bc It becomes. By generating the delay amount at the timing of the trailing edge of the inverted measurement pulse, an error between the delay amount during loop measurement and the delay amount during actual operation can be suppressed. According to FIG. 16B, the phase shift between the curve “negative” indicating the output generated by inverting the output of the second pulse shaping unit 112 at the time of loop measurement and the curve “actual operation” is small. Recognize. Therefore, when the delay amount generated by the delay clock generation device 10 based on the timing of the leading edge of the reference clock is measured in a loop, the measurement pulse is inverted and supplied to the delay clock generation device 10 so that the intersymbol interference can be reduced. The influence can be suppressed.
[0070]
The half cycle delay detection unit 106 described with reference to FIG. 14 detects whether or not to generate a delay amount of a half cycle of the reference clock, and generates a delay clock in the first pulse shaping unit 104 based on the detected result. The measurement pulse supplied to the apparatus 10 is shaped. For example, the half-cycle delay detection unit 106 determines whether or not the delay amount for loop measurement is a delay amount generated based on the timing of the leading edge of the reference clock. When it is determined that the delay amount is generated based on the timing of the leading edge, the half cycle delay detection unit 106 instructs the first pulse shaping unit 104 to invert the measurement pulse and output it to the buffer 105. For example, the half-cycle delay detection unit 106 determines whether or not the delay amount for loop measurement is a delay amount generated based on the timing of the trailing edge of the reference clock. When it is determined that the delay amount is generated based on the timing of the trailing edge, the half-cycle delay detection unit 106 instructs the first pulse shaping unit 104 to output the measurement pulse to the buffer 105 without inversion. Therefore, the linearized memory storage control unit 100 can cause the first pulse shaping unit 104 to shape the measurement pulse to be supplied to the delay clock generation device 10 based on whether or not to generate a delay amount of a half cycle of the reference clock. it can.
[0071]
The half-cycle delay detection unit 106 requests the delay amount measurement unit 118 to correct the delay amount obtained by the loop measurement when it is determined that the delay amount is generated based on the timing of the leading edge of the reference clock. To do. The delay amount measuring unit 118 performs a process of correcting the value supplied from the counter unit 116. The correction will be described later. Therefore, since the half-cycle delay detection unit 106 can shape the measurement pulse, the influence of intersymbol interference can be suppressed. Since the influence of intersymbol interference can be suppressed, an error between the delay amount measured during loop measurement and the delay amount generated during actual operation can be suppressed.
[0072]
FIG. 17 is a detailed functional block diagram of the first pulse shaping unit 104. The first pulse shaping unit 104 includes a NAND circuit 120, a NAND circuit 122, an inverter 124, a variable delay circuit 126, an AND circuit 128, an AND circuit 130, an AND circuit 132, a variable delay circuit 134, and an OR circuit 136. The NAND circuit 120 receives a reference clock or a measurement pulse at one end and a set value sel1 at the other end. The NAND circuit 120 outputs an output value based on the logical value given to the input terminal to one end of the AND circuit 128.
[0073]
The inverter 124 inputs a reference clock or a measurement pulse and outputs an inverted signal to one end of the NAND circuit 122. The NAND circuit 122 inputs the signal supplied from the inverter 124 to one end. The NAND circuit 122 inputs the set value sel2 to the other end. The NAND circuit 122 outputs an output value based on the logical value given to the input terminal to the variable delay circuit 126. The variable delay circuit 126 delays the output value supplied from the NAND circuit 122 and outputs it to one end of the AND circuit 128. For example, the variable delay circuit 126 delays the output value supplied from the NAND circuit 122 by Δt1 and outputs it to one end of the AND circuit 128.
[0074]
The AND circuit 128 outputs a logical product of the output values supplied from the NAND circuit 120 and the variable delay circuit 126 to one end of each of the AND circuit 130 and the AND circuit 132. The AND circuit 130 inputs the logical product value supplied from the AND circuit 128 to one end, and inputs the set value sel3 to the other end. The AND circuit 130 outputs a logical product value of logical values given to the input terminals to the OR circuit 136. The AND circuit 132 inputs the logical product value supplied from the AND circuit 128 to one end, and inputs the set value sel4 to the other end. The AND circuit 132 outputs a logical product value of logical values given to the input terminals to the variable delay circuit 134. The variable delay circuit 134 delays the output value supplied from the AND circuit 132 and outputs the delayed output value to one end of the OR circuit 136. For example, the variable delay circuit 134 delays the output value supplied from the AND circuit 132 by Δt2 and outputs it to one end of the OR circuit 136. The OR circuit 136 outputs a logical sum of logical product values given to the input terminals.
[0075]
FIG. 18 shows the setting values given to the setting values sel1, sel2, sel3, and sel4 described with reference to FIG. 17 and the output waveforms from the respective functional blocks of the first pulse shaping unit 104. FIG. 18A is a timing chart when the setting value sel1 is set to “1”, the setting value sel2 is set to “1”, the setting value sel3 is set to “1”, and the setting value sel4 is set to “1”. With this setting, it is possible to output a pulse having the sum of the delay amount Δt1 of the variable delay circuit 126 and the delay amount Δt2 of the variable delay circuit 134 with the timing of the trailing edge of the input pulse as the leading edge. That is, a pulse whose phase is shifted by the pulse width of the input pulse can be generated.
[0076]
FIG. 18B shows an output waveform when the set value sel1 is set to “1”, the set value sel2 is set to “0”, the set value sel3 is set to “1”, and the set value sel4 is set to “0”. By setting the setting value sel1 to “1”, the setting value sel2 to “0”, the setting value sel3 to “1”, and the setting value sel4 to “0”, the first pulse shaping unit 104 receives the input measurement pulse. It can be inverted and output. The second pulse shaping unit 112 described in FIG. 14 has the same configuration as the detailed functional block of the first pulse shaping unit 104 described with reference to FIG. The half-cycle delay detection unit 106 described with reference to FIG. 14 sets the set value sel1 to “1”, the set value sel2 to “0”, when performing loop measurement of the delay amount generated at the timing of the leading edge of the reference clock. The first pulse shaping unit 104 is set to “1” as the set value sel3 and “0” as the set value sel4.
[0077]
FIG. 19A shows setting values set in the first pulse shaping unit 104 and the second pulse shaping unit 112 when the delay amount is generated at the timing of the leading edge of the reference clock. In the first pulse shaping unit 104, “1” is set as the set value sel1, “0” is set as the set value sel2, “1” is set as the set value sel3, and “0” is set as the set value sel4. Therefore, the first pulse shaping unit 104 can invert the measurement pulse and output it. In the second pulse shaping unit 112, “1” is set as the set value sel1, “1” is set as the set value sel2, “1” is set as the set value sel3, and “1” is set as the set value sel4. Therefore, the second pulse shaping unit 112 can output a pulse whose phase is shifted by approximately the pulse width of the input pulse.
[0078]
FIG. 19B shows setting values set in the first pulse shaping unit 104 and the second pulse shaping unit 112 when the delay amount is generated at the timing of the trailing edge of the reference clock. In the first pulse shaping unit 104, “1” is set as the set value sel1, “1” is set as the set value sel2, “1” is set as the set value sel3, and “1” is set as the set value sel4. Therefore, the first pulse shaping unit 104 can output a pulse whose phase is shifted by approximately the pulse width of the input pulse. In the second pulse shaping unit 112, “1” is set as the set value sel1, “1” is set as the set value sel2, “1” is set as the set value sel3, and “1” is set as the set value sel4. Therefore, the second pulse shaping unit 112 can output a pulse whose phase is shifted by approximately the pulse width of the input pulse. Therefore, since the first pulse shaping unit 104 can shape the measurement pulse according to the delay amount to be measured, it is possible to suppress an error between the delay amount during loop measurement and the delay amount during actual operation. it can.
[0079]
FIG. 20A shows the state of the closed circuit at the time of loop measurement when the delay amount is generated at the trailing edge timing. A delay amount corresponding to the NAND circuit 120, the inverter 124, the NAND circuit 122, the variable delay circuit 126, and the AND circuit 128 of the second pulse shaping unit 112 is P1. A delay amount of a portion corresponding to the AND circuit 130, the AND circuit 132, the variable delay circuit 134, and the OR circuit 136 of the second pulse shaping unit 112 is P2. Let P3 be the delay amount of the portion corresponding to the NAND circuit 120, inverter 124, NAND circuit 122, variable delay circuit 126, and AND circuit 128 of the first pulse shaping unit 104. A delay amount corresponding to the AND circuit 130, the AND circuit 132, the variable delay circuit 134, and the OR circuit 136 of the first pulse shaping unit 104 is set to P4. A delay amount corresponding to the high resolution delay unit 16 is assumed to be VD. Let P5 and P6 be delay amounts due to a functional block for adjusting a pulse width (not shown).
[0080]
In the first pulse shaping unit 104, “1” is set as the set value sel1, “1” is set as the set value sel2, “1” is set as the set value sel3, and “1” is set as the set value sel4. In the second pulse shaping unit 112, “1” is set as the set value sel1, “1” is set as the set value sel2, “1” is set as the set value sel3, and “1” is set as the set value sel4.
[0081]
FIG. 20B is a timing chart of each part in the state of FIG. The amount of delay caused by the closed circuit in the state of FIG. 20A is P1 + P2 + P3 + P4 + P5 + P6 + VD.
[0082]
FIG. 21A shows the state of the closed circuit at the time of loop measurement when the delay amount is generated at the timing of the leading edge. A delay amount corresponding to the NAND circuit 120, the inverter 124, the NAND circuit 122, the variable delay circuit 126, and the AND circuit 128 of the second pulse shaping unit 112 is P1. A delay amount of a portion corresponding to the AND circuit 130, the AND circuit 132, the variable delay circuit 134, and the OR circuit 136 of the second pulse shaping unit 112 is P2. Let P3 be the delay amount of the portion corresponding to the NAND circuit 120, inverter 124, NAND circuit 122, variable delay circuit 126, and AND circuit 128 of the first pulse shaping unit 104. A delay amount corresponding to the AND circuit 130, the AND circuit 132, the variable delay circuit 134, and the OR circuit 136 of the first pulse shaping unit 104 is set to P4. A delay amount corresponding to the high resolution delay unit 16 is assumed to be VD. Let P5 and P6 be delay amounts due to a functional block for adjusting a pulse width (not shown).
[0083]
In the first pulse shaping unit 104, “1” is set as the set value sel1, “0” is set as the set value sel2, “1” is set as the set value sel3, and “0” is set as the set value sel4. In the second pulse shaping unit 112, “1” is set as the set value sel1, “1” is set as the set value sel2, “1” is set as the set value sel3, and “1” is set as the set value sel4.
[0084]
FIG. 21B is a timing chart of each part in the state of FIG. The first pulse shaping unit 104 is set to “1” as the set value sel1, “0” as the set value sel2, “1” as the set value sel3, and “0” as the set value sel4. Since 104 generates the input pulse without delay, there is no delay amount P3 and no delay amount P4. Accordingly, the delay amount generated by the closed circuit in the state of FIG. 21A is P1 + P2 + P5 + P6 + VD. Therefore, since a delay amount obtained by adding P3 + P4 is generated in actual operation, the delay amount obtained by loop measurement is corrected. For example, in the actual operation, when the adjustment values of the first pulse shaping unit 104 and the second pulse shaping unit 112 have a duty ratio of 50% (P1 + P2 = P3 + P4 = half cycle of the reference clock), the delay amount obtained by loop measurement In addition, the delay amount measuring unit 118 stores the delay amount obtained by adding P3 + P4 in the linearized memory 20. For example, when the period of the reference clock is T in actual operation, the delay amount measurement unit 118 linearly sets a value obtained by subtracting the delay amount (P3 + P4) obtained by loop measurement from the period T as a delay amount in actual operation. Store in the rise memory 20.
[0085]
FIG. 22 is a flowchart of the linearized memory storage control unit 100. The half-cycle delay detection unit 106 detects whether or not the delay amount to be measured is generated at the timing of the leading edge of the reference clock (step S10). When it is detected that the delay amount is generated at the timing of the leading edge of the reference clock, the half-cycle delay detection unit 106 sets a setting value in the first pulse shaping unit 104 (step S12). For example, the half cycle delay detection unit 106 sets the first pulse shaping unit 104 to “1” for the set value sel1, “0” for the set value sel2, “1” for the set value sel3, and “0” for the set value sel4. Set. The delay clock generation device 10 sets the delay clock generation unit (step S14). For example, the delay clock generation device 10 supplies a timing set signal having a delay amount to be measured.
[0086]
In step S10, when it is detected that no delay amount is generated at the timing of the leading edge of the reference clock, the delay clock generation device 10 proceeds to step S14. When the setting of the delay clock generation unit is completed, the linearized memory storage control unit 100 enables the closed circuit, inputs a measurement pulse from the measurement pulse generation unit 111, and starts loop measurement (step S16).
[0087]
The delay amount measuring unit 118 calculates the delay amount based on the value supplied from the counter unit 116 (step S18). When calculating the delay amount, the delay amount measuring unit 118 stores the calculated delay amount in the linearized memory 20 (step S20). The delay amount measuring unit 118 determines whether or not the loop measurement may be terminated (step S22). When it is determined that the loop measurement can be terminated, the loop measurement is terminated. When it is determined not to end the loop measurement, the process proceeds to step S10. Thereby, an error between the delay amount during loop measurement and the delay amount during actual operation can be suppressed.
[0088]
As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.
[0089]
【The invention's effect】
As is apparent from the above description, according to the present invention, the amount of delay generated by the high resolution delay unit 16 can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a conventional timing generator 28. FIG.
FIG. 2 shows a timing chart of a conventional timing generator 28;
FIG. 3 shows a semiconductor test apparatus.
FIG. 4 is a block diagram illustrating one embodiment of timing generator 28. FIG.
5 is a block diagram illustrating details of one embodiment of timing generator 28. FIG.
6 shows a timing chart of the timing generator 28 shown in FIG.
FIG. 7 is a timing chart when the second generation method generates the reference clock in the first cycle and the first generation method generates the reference clock in the second cycle.
FIG. 8 is a diagram illustrating a relationship between a delay amount and data for setting a delay amount by the first generation method and the second generation method;
FIG. 9 is a block diagram showing another embodiment of the timing generator.
10 is a block diagram showing a detailed configuration of a half-cycle delay unit 40 included in the timing generator 28 shown in FIG. 9. FIG.
11 shows a timing chart of the half-cycle delay unit 40 shown in FIG.
12 shows a timing chart of the timing generator 28 shown in FIG.
FIG. 13 shows a delay amount generated by the delay clock generator 10 during loop measurement and actual operation.
14 is a detailed functional block diagram of the linearized memory storage control unit 100. FIG.
FIG. 15 shows an intersymbol error.
FIG. 16 shows a simulation result of an intersymbol error.
17 is a detailed functional block diagram of the first pulse shaping unit 104. FIG.
18 is an example of a timing chart in the first pulse shaping unit 104. FIG.
19 is an example of setting values set in the first pulse shaping unit 104 and the second pulse shaping unit 112. FIG.
20 is an example of a timing chart in the linearized memory storage control unit 100. FIG.
21 is an example of a timing chart in the linearized memory storage control unit 100. FIG.
22 is a flowchart of the linearized memory storage control unit 100. FIG.
23 is a functional block diagram of one embodiment of timing generator 28. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Delay clock generator, 12 ... Period delay part, 14 ... AND circuit, 16 ... High-resolution delay part, 18 ... Timing memory, 20 ... Linearize memory, 22. ..Reference clock generator,
24 ... Pattern generator, 26 ... Waveform shaper, 28 ... Timing generator, 30 ... Delay signal generator, 32 ... Device insertion part, 34 ... Comparator, 36 ... Device under test, 40 ... Half-cycle delay unit, 42 ... AND circuit, 44 ... Pulse width adjustment unit, 48 ... AND circuit 48, 50 ... AND circuit, 52 ... OR circuit, 54... ENOR circuit, 56... AND circuit, 58... Flip-flop, 60... OR circuit, 62. , OR circuit, 104, first pulse shaping unit, 106, half-cycle delay detection unit, 108, AND circuit, 110, OR circuit, 111, measurement pulse generation unit, 112 ... Second pulse shaping unit, 114 AND circuit 116... Counter unit 118 118 delay amount measuring unit 120 NAND circuit 122 NAND circuit 124 inverter 126 variable delay circuit 128 ..AND circuit 130 ... AND circuit 132 ... AND circuit 134 ... variable delay circuit 136 ... OR circuit

Claims (11)

A delay clock generation device that generates a delay clock having a predetermined delay amount,
A cycle delay unit that generates a delay amount that is an integral multiple of the cycle of the reference clock shorter than the predetermined delay amount;
A half-cycle delay unit for generating a half-cycle delay amount of the reference clock;
High resolution for adding the delay amount of the difference between the sum of the delay amounts generated by the period delay unit and the half cycle delay unit and the predetermined delay amount to the delay amount generated by the period delay unit and the half cycle delay unit A delay unit;
A first storage unit storing data for setting the integral multiple delay amount in the periodic delay unit;
A second storage unit for storing data for setting a half-cycle delay amount of the reference clock in the half-cycle delay unit;
The delay amount obtained by excluding the delay amount set by the data stored in the first storage unit and the delay amount set by the data stored in the second storage unit from the predetermined delay amount is obtained as the high resolution. A third storage unit for storing data to be set in the delay unit;
A linearized memory that stores a delay path in the high-resolution delay unit that generates a delay amount set by data stored in the third storage unit;
A linearized memory storage control unit for storing the delay path in the linearized memory;
The linearized memory storage controller
A pulse generator for measurement that generates a pulse for measurement having a predetermined pulse width;
A pulse input unit for inputting the measurement pulse;
A pulse shaping section for inverting the measurement pulse supplied from the pulse input section;
A counter unit for counting the number of pulses for measurement supplied by the pulse shaping unit over a predetermined time interval;
Based on the number of measurement pulses counted by the counter unit, the delay amount of the delay path is measured, and the measured delay amount and the delay path are associated with each other and stored in the linearized memory. A measuring section;
I have a,
The half cycle delay unit inputs a signal having a delay amount generated by the cycle delay unit, and supplies the input signal to the high resolution delay unit at a timing of either a leading edge or a trailing edge of the reference clock. A delay clock generation device characterized by: When the period delay unit generates the integer multiple of the delay amount with reference to either the leading edge or the trailing edge of the reference clock, the half period delay unit includes the leading edge or the trailing edge of the reference clock. The delay clock generation device according to claim 1 , wherein a pulse having the other rise timing is generated. The delay clock generation apparatus according to claim 2 , wherein the half-cycle delay unit includes a logic gate that generates a pulse whose rising timing is a trailing edge of the reference clock. A logic gate for generating a pulse having a delay amount generated by the period delay unit based on the reference clock;
The delay according to any one of claims 1 to 3 , wherein the half-cycle delay unit includes a pulse width adjustment unit that adjusts a pulse width of the pulse generated by the logic gate to a predetermined pulse width. Clock generator. The delay clock generation apparatus according to claim 4 , wherein the pulse width adjustment unit includes a delay element that generates a delay amount corresponding to the predetermined pulse width. The period delay unit includes a counter that counts the number of pulses of the reference clock;
Delay clock generator according to any one of claims 1-5, characterized in that it comprises a logic gate is determined whether equal to the data number the pulse is stored in the first storage unit. The half-cycle delay detection unit that specifies whether to invert the measurement pulse in the pulse shaping unit based on whether or not the half-cycle delay amount is generated. The delay clock generation device according to any one of 1 to 6 . The half-cycle delay detection unit instructs the pulse shaping unit to invert the measurement pulse when measuring the delay amount generated at the timing of the leading edge of the reference clock. Item 8. The delay clock generation device according to Item 7 . The pulse shaping unit, a delay clock generating apparatus according to claim 7 or 8, wherein a logic gate for inverting said measurement pulse. The delay amount measurement unit adds a shift amount between a phase generated by inverting the measurement pulse and a phase generated by not inverting the measurement pulse to the delay amount of the delay path, and delay clock generating apparatus according to claim 1, wherein 9 to be stored in. In a semiconductor test apparatus for testing a semiconductor device,
A delay clock generating apparatus according to claim 1 1 0 that generates a delayed clock having a predetermined delay amount,
A pattern generator for generating a test pattern to be input to the semiconductor device;
A waveform shaper that outputs a shaped test pattern obtained by shaping the test pattern to be applied to the semiconductor device based on the delay clock and the test pattern;
A device contact portion for inputting the shaping test pattern to the semiconductor device;
A comparison for determining the quality of the semiconductor device by comparing an output signal output from the semiconductor device to which the shaping test pattern is input and an expected value to be output from the semiconductor device output from the pattern generator A semiconductor test apparatus.

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