JP4653693B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit layout design technique, and more particularly to a CMOS type SRAM (Static Random Access Memory) semiconductor memory device.

  In recent years, miniaturization of semiconductors has progressed rapidly, and processing dimensions in the vicinity of 100 nm have begun to be realized. However, in the progress of miniaturization, lithography technology has become a bottleneck. Against this background, the layout structure of SRAM memory cells has begun to use a horizontal memory cell layout that is easy to process lithographically, instead of the vertical memory cell layout that has been mainly used conventionally.

  FIG. 20 shows a layout example of a lower layer portion of a conventional CMOS SRAM vertical memory cell. In FIG. 20, 100 is a P well, 101 is an N well, 102 is a well boundary line, 103 is a source / drain diffusion layer (an N type diffusion layer on the P well 100 and a P type diffusion layer on the N well 101). , 104 is a gate electrode, 105 is a diffusion layer 103 or a contact hole connecting the gate electrode 104 and a first layer metal wiring (not shown), 107 is an N-channel access transistor, 108 is an N-channel drive transistor, Reference numeral 109 denotes a P-channel load transistor, and 110 denotes a cell boundary frame for one bit of the memory cell.

  FIG. 21 shows a layout example of a lower layer portion of a horizontal memory cell of a conventional CMOS SRAM. In FIG. 21, the same reference numerals are assigned to the portions corresponding to FIG. 20, and reference numeral 106 denotes a shared layer that connects the diffusion layer 103 and the gate electrode 104 to the first layer metal wiring (not shown) through one contact hole. It is a contact. 20 and 21 both show a six-transistor SRAM memory cell including a pair of N-channel access transistors 107, a pair of N-channel drive transistors 108, and a pair of P-channel load transistors 109. A circuit diagram of such a memory cell is shown in FIG. In the case of the horizontal memory cell of FIG. 21, the well boundary line 102 extends in the vertical direction in FIG.

  This horizontal memory cell is normally flip-arranged as shown in FIG. In FIG. 22, 221 is a memory cell array, and 222 is a horizontal memory cell.

  The wiring layout of the horizontal memory cell is shown in FIGS. 23 shows the layout of the first layer metal wiring, FIG. 24 shows the layout of the second layer metal wiring, FIG. 25 shows the layout of the third layer metal wiring, and in FIG. 23, 111 is the first layer wiring. In FIG. 24, reference numeral 112 denotes a second layer wiring, and 113 denotes a via portion (connection portion by a via hole) that connects the first layer wiring 111 and the second layer wiring 112. Further, 114 is a positive bit line (BL in FIG. 28), 115 is a negative bit line (/ BL in FIG. 28), 116 is a VDD power supply wiring, and these are formed by the second layer wiring 112. In FIG. 25, reference numeral 117 denotes a third-layer wiring, and 118 denotes a via portion that connects the second-layer wiring 112 and the third-layer wiring 117. Further, 119 is a word line (WL in FIG. 28), 120 is a VSS power supply wiring, and these are formed by a third layer wiring 117.

  As can be seen by comparing the layout of the vertical memory cell in FIG. 20 and the horizontal memory cell in FIG. 21, in the horizontal memory cell, the diffusion layer 103 and the gate electrode 104 are patterned in a linear shape extending in the same direction. The layout is easy, and there is an advantage that lithography processing is easier than the vertical memory cell. In addition, since the cell shape is horizontally long, the length of the bit line extending in the vertical direction is shorter than that of the vertical memory cell, and the bit line capacity is small, which is advantageous for high speed and low power consumption. . A small gate width is used for the transistor in the memory cell to reduce the area, and a large number of memory cells are connected to the bit line. Therefore, the driving load of the memory cell is heavy, and the bit line Driving time is one of the most important factors in speeding up access time.

  In the above example of the horizontal memory cell, the example in which the bit line is formed by the second layer wiring (hereinafter referred to as the bit line two layer type) has been described. However, the bit line is formed by the third layer wiring. An example (hereinafter referred to as a bit line three-layer type) will also be described. The layout of the lower layer portion of the bit line three-layer horizontal memory cell and the first-layer metal wiring is the same as that in FIGS. 21 and 23 of the bit line two-layer horizontal memory cell, respectively. The layout of the second layer wiring of the bit line three-layer type lateral memory cell is shown in FIG. 26, and the layout of the third layer wiring is shown in FIG. In this bit line three-layer type, as shown in FIG. 26, the word line 351 is formed by the second layer wiring 112, and as shown in FIG. 27, the positive bit line 352, A negative bit line 353, a VDD power supply wiring 354, and a VSS power supply wiring 355 are formed.

In the bit line three-layer type, the capacitance of the bit line to the substrate is lighter than that of the bit line two-layer type. However, since a large number of wiring patterns exist in the second layer, the capacitance difference with respect to the substrate does not work much. In addition, the bit line three-layer type has a deeper via portion than the bit line two-layer type, and the distance between the via portions of the positive and negative bit lines 352 and 353 and the via portion of the VDD power supply wiring 354 is short. There is a demerit that the parasitic capacitance of the via portions of the bit lines 352 and 353 is increased. Further, as can be seen from the comparison between FIG. 25 and FIG. 27, the bit line three-layer type has more signals to be lifted to the upper layer, so the number of used via portions increases, which may be disadvantageous in terms of yield. There is. However, in the case of the bit line three-layer type, both sides of the positive and negative bit lines 352 and 353 are sandwiched between the VDD power supply wiring 354 and the VSS power supply wiring 355 as shown in FIG. As a result, both the interference between the positive / negative bit lines 352 and 353 in the memory cell and the interference with the bit line of the adjacent memory cell can be shielded.
JP-A-10-178110

  The advantages such as the ease of processing on the lithography side and the short bit line length in the horizontal memory cell have been described in the prior art. However, the horizontal memory cell also has a problem.

  In the case of the bit line two-layer type, since the shape is very horizontally long, wiring extending in the lateral direction is present very closely. Specifically, as shown in FIG. 25, the word line 119 composed of the third-layer wiring 117 and the VSS power wiring 120 are very close to each other and run in parallel over a long distance (entire memory area). However, there is a problem that, as the semiconductor device is miniaturized, the parasitic load capacitance of the word line 119 is increased, and since the wiring interval is narrow, it is weak against particles in the process process and the like, and the yield is likely to be lowered.

  In the case of the bit line three-layer type, as shown in FIG. 27, both sides of the positive and negative bit lines 352 and 353 are sandwiched between the VDD power supply wiring 354 and the VSS power supply wiring 355, Although interference between the bit lines can be shielded, as a result, the VDD power supply wiring 354, the VSS power supply wiring 355, and the positive / negative bit lines 352 and 353, which are arranged side by side, run in parallel over a long distance. . Although the parasitic load capacitances of the bit lines 352 and 353 are also lateral memory cells and have a margin in lateral width, if miniaturization progresses, there is a possibility of increase because a large number of wiring patterns exist closely. There is a problem that it is easy to cause a decrease in yield due to particles.

As an incidental situation, in recent system LSI design, the following trends are observed with miniaturization.
(1) With the increase in the number of wiring layers, the wiring cross-sectional area is reduced and the wiring interval is reduced, thereby increasing the wiring delay. In order to alleviate this, the number of used wiring layers is increased to increase the wiring width and spacing, thereby increasing the number of wiring layers of the system LSI.
-LSIs tend to have lower power supply voltages due to needs such as device scaling and lower power consumption of equipment. However, on the other hand, since many elements are integrated on one chip and there is a high need for high-speed operation, current consumption tends to increase. For this reason, it is necessary to increase the power supply width and suppress the power supply potential drop, and the number of used wiring layers tends to increase.
(2) Redundancy remedy technology • The number of mounted transistors, particularly the mounted memory capacity, is increasing in the system LSI. For this reason, the redundancy repair technique that has been used in DRAMs and the like has started to be used in SRAMs.

  In consideration of the flow (1) and (2) in the recent micro system LSI, it is required to further optimize the wiring structure of the horizontal memory cell described above.

  An object of the present invention is to provide a semiconductor memory device that can reduce the parasitic capacitance of word lines and bit lines and improve the yield.

A semiconductor memory device according to claim 1 of the present invention is arranged in a matrix on a semiconductor substrate, and each of a pair of access transistors and a pair of drive transistors respectively formed in a first conductivity type well region, It is composed of a conductive pair of load transistors which are formed in the well region of U E le region as a well region of a second conductivity type is sandwiched between two of the first conductivity type well region on a semiconductor substrate There are formed side by side in the row direction, a plurality of two respective one by one access transistor and the drive transistor and the CMOS SRAM cell in a long shape is formed Tagyo direction of the first conductivity type well region, CMOS A semiconductor memory device having a plurality of wiring layers on top of transistors constituting a type SRAM cell, each of which is formed of one wiring layer, A plurality of word lines that extend in the row direction and are connected to CMOS SRAM cells in the same row and are arranged side by side in the column direction, and a wiring layer that is one layer above the word line, each extend in the column direction. A plurality of pairs of bit lines connected to CMOS SRAM cells in the same column and arranged in the row direction and a wiring layer in the same layer as the bit lines are arranged between the paired bit lines. by a plurality of VDD power supply wiring connected to the CMOS SRAM cell in the same column, are formed in a wiring layer on the first layer than the bit line, it provided a VSS power supply line connected to the CMOS SRAM cell, V SS power supply The wiring is connected to the CMOS SRAM cell via a VSS power connection pattern formed in a wiring layer one layer lower than the VSS power wiring, and the connection between the VSS power wiring and the VSS power connection pattern is made. The connection is made by arranging a plurality of vias per one VSS power supply connection pattern .

According to a second aspect of the present invention, there is provided a semiconductor memory device arranged in a matrix on a semiconductor substrate, each of a pair of access transistors and a pair of drive transistors formed in a well region of the first conductivity type. The well region is formed of a pair of load transistors formed in the conductivity type well region, and the well region is arranged so that the second conductivity type well region is sandwiched between the two first conductivity type well regions on the semiconductor substrate. A plurality of CMOS SRAM cells each having a long shape in the row direction, each of which is formed side by side and in which one access transistor and one drive transistor are formed in each of the two first conductivity type well regions; A semiconductor memory device having a plurality of wiring layers on top of a transistor constituting a cell, each of which is formed of one wiring layer, and A plurality of word lines extending in the row direction and connected to CMOS SRAM cells in the same row and arranged in the column direction and a wiring layer one layer above the word line are formed, and each extending in the column direction is the same A plurality of pairs of bit lines that are connected to the CMOS type SRAM cell in the column and arranged in the row direction, and a wiring layer in the same layer as the bit lines, are arranged between the paired bit lines. A plurality of VDD power wirings connected to the CMOS SRAM cells in the same column and a VSS power wiring formed in a wiring layer one layer above the bit lines and connected to the CMOS SRAM cells are provided. A plurality are arranged side by side in the row direction, and are arranged so as to cover the bit lines.

A semiconductor memory device according to a third aspect of the present invention is the semiconductor memory device according to the first or second aspect , wherein each of the regions of the CMOS type SRAM cell has a width in the row direction that is twice or more as large as a width in the column direction.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the first or second aspect , the word line is bent.

According to a fifth aspect of the present invention , in the semiconductor memory device according to the first aspect of the present invention, a VDD reinforcing wiring formed of the same wiring layer as the VSS power supply wiring and connected to the VDD power supply wiring is provided. Features.

The semiconductor memory device according to claim 6 is the semiconductor memory device according to claim 5 , wherein the connection between the VDD reinforcing wiring and the VDD power supply wiring is connected to a substrate contact cell for securing a substrate potential of a transistor constituting the CMOS type SRAM cell. It is characterized by being performed in the area.

According to a seventh aspect of the present invention, in the semiconductor memory device according to the first or second aspect , the wiring in the same layer as the word line in the substrate potential securing substrate contact cell region of the transistor constituting the CMOS type SRAM cell. A power supply reinforcing wiring formed of layers and extending in the row direction is provided, and the power supply reinforcing wiring is connected to the VDD power supply wiring or the VSS power supply wiring at an intersection with the VDD power supply wiring or the VSS power supply wiring.

The semiconductor memory device according to an eighth aspect is the semiconductor memory device according to the first or second aspect , wherein the VSS power supply wiring is mesh-shaped.

The semiconductor memory device according to claim 9 is the semiconductor memory device according to claim 1 or 2 , wherein the film thickness of the wiring layer forming the VSS power supply wiring is smaller than the film thickness of the wiring layer below the VSS power supply wiring. It is characterized by being thick.

A semiconductor memory device according to a tenth aspect is the semiconductor memory device according to the first or second aspect , wherein the semiconductor memory device has only a row redundancy circuit without a column redundancy circuit.

According to the first aspect of the present invention, in a horizontal memory cell having a narrow vertical width (column direction) in which a well boundary line extends, a word line is formed by a wiring layer below a bit line. And the VSS power supply wiring are formed in different wiring layers, the parallel running distance between the bit line arranged in the horizontal direction (row direction) and the VSS power supply is shortened, and the parasitic capacitance of the bit line is reduced. In addition, it is possible to increase the yield by reducing the probability that the adjacent wiring in the same layer will cause a short circuit failure due to particles. In addition, since the bit line is normally precharged to the high potential during standby, the redundancy relief rate is improved if the short-circuit probability between the VSS power source and the bit line is reduced. In addition, since there is a VDD power supply wiring that also serves as a shield between the pair of positive and negative complementary bit lines, a decrease in bit line amplitude due to coupling between positive and negative can be prevented. Further, since the VSS power supply wiring and the VDD power supply wiring are different wiring layers, it is possible to prevent a decrease in redundant yield due to a short circuit between the power supplies of VDD and VSS.
Further, since a plurality of via portions are used for each node (island-shaped VSS pattern) below the VSS power supply line to raise it to the upper layer, the probability that all the via portions are defective is one via portion. Compared with the case of arrangement, it is significantly reduced, and yield reduction can be suppressed.

According to the second aspect of the present invention, one VSS power supply wiring is provided for each memory cell by arranging the VSS power supply wiring side by side in the horizontal direction (row direction). When having VSS power supply wirings arranged side by side in the vertical direction (column direction), when the word line is active, the cell current of all the memory cells that are in contact with the word line is covered by a single VSS power supply wiring. However, the effect of power supply voltage drop and electromigration can be mitigated more than that. In addition, since the VSS power supply wiring exists so as to cover the bit line existing in the lower layer, it becomes a shield layer for signals passing over the memory block, and the signal line is placed on the memory block at the time of chip design while preventing malfunction of the memory. It is possible to pass.

According to the third aspect of the present invention, the memory according to the first or second aspect is provided by using a horizontally long memory cell (CMOS SRAM cell) having a width in the horizontal direction that is twice or more the vertical direction. The effect of the cell can be extracted more.

According to the fourth aspect of the present invention, when a thin word line is bent and a space between the word line and the VSS pattern existing in the same layer is provided, the word line capacitance is reduced and a short circuit is generated. Probability can be reduced. Further, when the word line is thickened, the word line resistance can be reduced, and the probability of occurrence of disconnection failure of the word line can be lowered.

According to the fifth aspect of the present invention, when the current supply capability is insufficient with only the lower-layer VDD power supply wiring, the current supply capability can be enhanced by providing the VDD reinforcing wiring in the upper layer as a parallel path. .

According to the present invention described in claim 6 , the following effects can be obtained. If the lower VDD power supply wiring and the upper VDD reinforcing wiring are connected on each memory cell, for example, the wiring pattern running in parallel with the word line or the like increases. By backing the VDD power supply at the same cycle as the substrate contact cell arrangement cycle or an integer multiple thereof, the VDD power supply can have a mesh structure while avoiding an increase in the load capacity of the word line and a decrease in yield. When the word line is not used, it has a low potential, so if the yield defective word is at the low potential, redundancy can be relieved. Even if it does, the problem that the redundancy relief rate does not increase may occur. However, according to the present invention, the VDD potential can have a mesh structure while avoiding a short-circuit probability between the word line and the VDD potential.

According to the seventh aspect of the present invention, it is possible to form a stronger power supply system by forming a mesh structure by interconnecting the VSS power supply wiring and the VDD power supply wiring in the lateral direction by the power supply reinforcing wiring.

According to the eighth aspect of the present invention, the VSS power supply wiring has a mesh shape and becomes stronger.

According to the ninth aspect of the present invention, since the wiring film thickness of the VSS power supply wiring is thicker than the wiring layer film thickness below it, the sheet resistance value becomes small. Thereby, the parasitic resistance of the power supply is reduced, and the current supply capability of the power supply is increased. Also, at least in the memory cell region, there is no other signal line in the wiring layer of the VSS power supply wiring, so even if the wiring layer of the VSS power supply wiring becomes thick, there is a problem of increased coupling noise between the same-layer signal lines. Does not occur.

According to the tenth aspect of the present invention, the advantage of the memory cell according to the first aspect in which the short-circuit failure probability between the bit line and the VSS power supply is small is effectively used, and only row redundancy is provided. It is possible to reduce the area by avoiding the area increase due to the column redundant circuit mounting, and to use a high-performance memory block.

Embodiments and reference examples of the present invention will be described below. In the following, the n-th layer wiring (n = 1, 2, 3,...) Means the n-th layer metal wiring (from the bottom) formed on the lower layer layout of the memory cell, as in the conventional example. Layer).
(Reference Example 1)
Reference Example 1 will be described with reference to the drawings. The semiconductor memory device of this reference example is a CMOS type SRAM composed of a bit line two-layer lateral memory cell.

  The layout of the lower layer portion of the lateral memory cell and the layout of the first layer wiring and second layer wiring thereon are the same as those of the conventional example of FIGS. 21, 23 and 24, and the memory cell. As shown in FIG. 22, the arrangement of the flip-flops is flip-arranged, and the circuit diagram of the memory cell is shown in FIG. An example of the wiring layout in this reference example is shown in FIG. In FIG. 1, 201 is an island-shaped pattern VSS node composed of a third layer wiring, 202 is a via portion connecting the second layer wiring and the third layer wiring, and 203 is a third layer wiring and a fourth layer wiring. A via portion 204 for connecting to the layer wiring is a VSS power supply wiring composed of the fourth layer wiring.

  In the conventional bit line two-layer horizontal memory cell, as shown in FIG. 25, the VSS power supply wiring 120 runs in parallel with the word line 119 by the third-layer wiring, but in this reference example, as shown in FIG. Further, only the VSS node 201 of the connecting island-shaped pattern for allowing the VSS power supply to pass from the upper layer to the lower layer is used, and the VSS power supply wiring 204 is formed by the upper fourth layer wiring.

  As a result, the parallel running over a long distance between the word line 119 and the VSS power supply wiring 204 is eliminated, so that the parasitic capacitance of the word line 119 is reduced and the speed is increased, and the word line 119 and the VSS power supply wiring 204 due to particles are reduced. The probability of short circuit failure is reduced, and the effect of increasing the yield can be obtained. This effect is even greater when the memory cell has a shape that is long in the horizontal direction and has an aspect ratio of twice or more.

  As in the conventional example, the presence of the VDD power supply wiring 116 between the positive / negative bit lines 114 and 115 serves as a shield between the positive / negative bit lines 114 and 115. When there is no shield layer and the coupling capacitance between the positive / negative bit lines 114 and 115 is large, when the potential of one bit line is changed to the low potential by the write / read operation of the memory, the other potential to be the high potential. Since the bit line is pulled low and the potential difference between the positive / negative bit lines 114 and 115 is reduced, there is a high possibility that a sense failure or a write failure will occur during reading. The fact that the VDD power supply wiring 116 is running in parallel with the bit lines 114 and 115 is not usually a problem as long as there is column redundancy relief. Since the bit lines 114 and 115 are normally precharged to a high potential and enter a standby state, even if the VDD potential and the bit line are short-circuited, if the defective bit line portion is skipped using a redundant circuit, the DC line A faulty current or the like does not flow and can be handled as a non-defective chip.

  However, in FIG. 1, in order to lift the VSS power supply wiring 204 to the fourth layer, the via portion 203 that connects the third layer and the fourth layer wiring is required. (Hereinafter, for convenience, the n-th layer wiring is represented by Mn, and the via portion connecting the n-th layer wiring and the (n-1) -th layer wiring is represented by Vn.) The forming process is a process in which a deep hole hole having a very high aspect ratio is formed and a metal object is embedded in the hole hole, which is a process with a high degree of difficulty in process processing. For this reason, if the number of via portions necessary for configuring the logic increases, even if the parallel wiring length is reduced, the yield may be lowered as a result.

  This can be dealt with by making a plurality of via portions. FIG. 2 shows an example in which two via portions 203 connecting the third layer wiring and the fourth layer wiring are taken. FIG. 3 shows a view of FIG. 2 focusing on the metal wiring of the second layer or higher for easy viewing.

  Assuming that the probability that the via portion V3 of the process to be used is defective in formation is 1 ppm, the probability that both of them are simultaneously defective is the square of 1 ppm, which is a very small probability. Actually, since they are located close to each other, they are not completely squared, but the tendency that the formation defect formation in the process step is remarkably reduced is correct. Further, when the number of via portions is changed from one to two, the island shape pattern of the VSS node 201 in the third layer often does not increase up to twice. The reason is that even if only one via portion is taken, the size of the island shape pattern is not determined by the size of the via portion 203 and the overlap rule for the via portion, and the wiring is embedded in lithography or in the damascene wiring process. This is because there are many cases that are determined by the size rule of the single wiring pattern determined from the nature. Therefore, by increasing the number of via portions from one to two, the area increase of the island-shaped pattern of the third-layer VSS node 201 is small, and the increase in word line parasitic load capacitance and the decrease in yield are also small. As a result, by providing a plurality of vias connecting the third-layer VSS node 201 and the fourth-layer VSS power wiring 204, the effect of arranging the VSS power wiring 204 on the fourth layer is maximized. It becomes possible to pull out.

  Next, an example in which the VDD power supply is strengthened will be described with reference to FIGS. 4, 5, 6, and 7. As can be seen from FIG. 3, only the VSS power supply line 204 exists in the M4 layer, and there is a margin in the layout. Therefore, as shown in FIG. 4, it is possible to pass the M4 VDD power wiring 205 over the Pch load transistor. As a result, when only the VDD power supply wiring 116 of the second layer wiring has a large parasitic resistance value and does not have sufficient power supply strength, the VDD power supply wiring 116 of the second layer wiring is changed to the VDD power supply of the fourth layer wiring. The VDD power supply can be strengthened by backing with the wiring 205.

  Further, in order to connect the fourth-layer VDD power wiring 205 to the second-layer VDD power wiring 116 running in the lower layer, the island of the third-layer wiring in each memory cell as shown in FIG. When a power node 206 having a shape pattern is created and connected to the VDD power wiring 116 in the second layer, the word line 119 in the third layer, the word line 119, the island-shaped VDD power node 206, and the island-shaped VSS power node The parallel running distance with 201 increases, and parasitic capacitance increases and yield decreases.

  Therefore, in this reference example, as shown in FIG. 6, cells 300 (hereinafter referred to as substrate contact cells) that are periodically arranged in the memory cell array for making substrate contact. In the drawing, the number of memory cells 302 arranged between the substrate contact cells 300 is reduced.), As shown in FIG. 7, the second layer VDD power supply passes through the VDD node 301 of the third layer wiring. The wiring 116 is connected to the fourth layer VDD power supply wiring 205. Since there is no word line in the substrate contact cell portion, the third layer is vacant. In FIG. 7, the VDD node 301 of the third layer is shown as an island-shaped layout, but it may be a wiring extending in the horizontal direction on the memory array only in the substrate contact cell portion. The third-layer reinforcing power supply in the horizontal direction arranged in the substrate contact cell portion may be VDD, VSS, VDD and VSS alternately arranged, or the like. Thereby, as compared with the case where VDD connection is performed for each memory cell as shown in FIG. 5, it is possible to suppress the yield reduction and enhance the power supply capability.

  In the example of FIG. 1 and the example of FIG. 2 (FIG. 3), only the VSS power supply wiring 204 exists in the fourth layer wiring, and the VDD power supply wiring 205 as shown in FIG. 4 does not exist. . When VDD and VSS exist in the same layer metal and the VDD and VSS cause a short circuit failure, the redundant method of simply skipping the defective cell and using a spare cell flows between VDD and VSS. Since a short circuit current cannot be prevented, a defective chip cannot be made good by redundancy relief. In particular, the embedding method called damascene is used for the recent Cu wiring formation, and if there is dust in the CMP polishing process, a wiring short circuit caused by an abrasion called micro scratch may occur. For this reason, a wiring short-circuit defect may occur even if a sufficient wiring interval expected from the ability of lithography and management particles is secured. That is, a short circuit failure between the power supply between VDD and VSS cannot be remedied by a redundant remedy technique in which the memory cell is replaced with a spare one. As shown in the example of FIG. 1 and the example of FIG. In the fourth layer, only the VSS power supply line 204 can be used to prevent a decrease in redundant yield due to a short circuit between power supplies, which is very effective in view of a redundant relief yield. In addition, since the area ratio of the memory cells on the memory block is very high, and the ratio of the memory area on the system LSI is also very high, countermeasures against the memory cells can prevent chip yield. Even it is effective.

  The pattern of the VSS power supply wiring 204 arranged in the fourth layer may be a complete plate shape, but a line-and-space shape or a mesh shape described later is suitable for recent Cu damascene wiring. The reason for this is that wide wiring is likely to cause a recess in the wiring part called dishing resulting from the elasticity of the polishing pad in the CMP process, and the flatness is liable to cause lithography defects due to insufficient depth of focus. Because it becomes. This is because a layout pattern that is easy to process is formed by keeping the pattern area within a certain range within a certain area.

  When the above-described pattern of the VSS power wiring 204 in the fourth layer is made into a mesh shape, in FIG. 1 and FIG. 2 (FIG. 3), the VSS power wiring 204 extending in the vertical direction is further connected in the horizontal direction to mesh. Power supply. As a result, a stronger VSS power supply system can be formed. This may be a mesh for each memory cell, or it may be a mesh connected only at the substrate contact cell portion. Further, since the fourth layer is only the VSS power supply wiring, the above-mentioned merit relating to the redundant relief yield is not lost.

  In the example of FIG. 1 and the example of FIG. 2 (FIG. 3), the VSS power supply wiring 204 extends to cover the bit lines 114 and 115 in the same direction as the well boundary where the P well and the N well contact. If the VSS power supply wiring extends in the horizontal direction, the memory operation is as follows. The memory cells in the horizontal row selected by the word line 119 extending in the horizontal direction are turned on at the same time. Must be covered by a single VSS power line extending in the horizontal direction. However, if the VSS power supply wiring 204 in the vertical direction is provided, each memory cell has a VSS power supply, and therefore, even if memory cells in a horizontal row are simultaneously selected by the word line 119, the amount of power supply voltage decrease is suppressed. I can do it. Incidentally, even if the VDD power supply wiring does not exist in the fourth layer, it cannot be a great disadvantage as an SRAM. This is because the bit line is raised to the VDD potential after the write / read operation is performed by a precharge transistor arranged outside the memory cell area such as the data I / O portion. This is because it is only necessary to have a capability of lifting the line to the high potential side or reversing the retained data of the own cell at the time of Write, and it is not necessary to have a very strong current supply capability. Further, by arranging the VSS power wiring 204 of the fourth layer wiring so as to cover the bit lines 114 and 115, it functions as a shield when another signal line on the chip is passed through the upper layer of the memory block. Since the fourth-layer VSS power supply wiring 204 exists as a shield, the bit lines 114 and 115 operating with a minute potential difference can be protected and malfunction due to noise can be prevented.

  Next, a description will be given of a method of strengthening the power supply of VDD or VSS by using a mesh structure. When the VDD power supply wiring 116 and the VSS power supply wiring 204 extend in the vertical direction as in the example of FIG. 1 and FIG. 2 (FIG. 3), the VDD power supply is interconnected in the horizontal direction at a certain interval. In some cases, the VSS power supply may have a mesh structure. In such a case, the VDD power supply or the VSS power supply is reinforced in the direction perpendicular to the well boundary line in the third layer. VDD and VSS can pass through only one third-layer wiring in the horizontal direction when the substrate contact cell portion is configured with a minimum height. Since the word line 119 does not exist in the substrate contact cell portion, in the substrate contact cell portion, VSS or VDD, or VDD and VSS are alternately passed in the horizontal direction in the third layer wiring, and the passed wiring is connected to the VDD. By connecting at the intersection with the power supply wiring 116 or the VSS power supply wiring 204, the power supply can be strengthened in a mesh structure.

  Further, in each example in the above-described reference example, as shown in FIGS. 1 to 4, etc., the third-layer island-shaped VSS node 201 exists only at the diagonal position across the word line 119. It is. Therefore, as shown in the example of FIG. 8, the third-layer word line 207 is bent in the memory cell. Since the memory cells are flipped and arranged as shown in FIG. 22, the word lines are connected without problems in this shape. If the width is narrow like the word line 207 in FIG. 8, the distance from the island-shaped VSS node 201 is wide, the wiring capacity is reduced, and it is strong against yield defects caused by particles. In addition, when the wiring width is increased to make the bent wide word line 208 as shown in FIG. 9, the word line resistance can be reduced, and the possibility of disconnection failure of the word line 208 is reduced. The bends of the word lines 207 and 208 may be bent at 45 degrees or 90 degrees, or may be bent by gradually changing them by using many steps.

  Further, in the examples of FIGS. 1, 2 (FIG. 3) and FIG. 8, the wiring thickness of the fourth layer is increased. At least in the memory cell portion, the fourth layer has only the VSS power supply wiring 204, and there are no important signal lines such as bit lines and word lines. Therefore, even if the film thickness is increased, coupling between the short distance signal wirings is possible. Since the increase in capacity is not a problem, only the merit of reducing the sheet resistance value can be fully utilized. The power supply capability required for the memory cell is higher for VSS than for VDD. Since the VDD power wiring 116 existing in the second layer does not require a very high power supply capability, it can have a sufficient power supply capability even with a thin film thickness.

  In the reference example described above, since the VSS node 201 is only arranged in the island shape pattern in the third layer of the same layer as the word line 119 extending in the row direction as described with reference to FIG. The probability of a short circuit failure between line 119 and the VSS power supply is reduced. By taking advantage of this memory cell, it is possible to have a configuration having only a column redundancy circuit without having a row redundancy circuit as a redundancy circuit. This will be described with reference to FIG.

  FIG. 10 is a block image diagram when both the row redundancy circuit and the column redundancy circuit are mounted. In FIG. 10, 310 is a redundancy relief row decoder, 311 is a row redundancy spare memory cell, 312 is a column redundancy spare memory cell, 313 is a row decoder section, 314 is a control section, and 315 is a data input / output section.

  There are various methods of redundancy relief depending on the means for realizing the redundancy relief, but an additional circuit such as a selector circuit for shift redundancy and an address match detection circuit and a spare memory cell are always required. This has a demerit of an increase in area, but also has a demerit that specifications important for memory characteristics such as address setup time and access time deteriorate. By using the memory cell in this reference example, the probability that the word line is shorted to VSS and defective in the word line direction is reduced, so that the necessity of mounting the row redundancy relief circuit is reduced. In this case, if the bent word line shown in FIGS. 8 and 9 is used, word line defects can be further suppressed.

  By using the memory cell in which defects in the word line direction are unlikely to occur, the redundant circuit and the spare memory cell are used only for column redundancy, so that the redundancy repair row decoder 310 and the row redundancy spare memory cell in FIG. By removing 311, the area can be reduced. Also, by eliminating the row redundancy address matching circuit and shift redundancy circuit in the control unit 314 and the row decoder unit 313, specifications important for memory characteristics such as address setup time and access time are made redundant. It is possible to avoid deterioration by mounting the relief circuit.

In the case of this reference example, since the VSS power supply wiring 204 is a wiring layer different from the bit lines 114 and 115, the VSS power supply wiring as shown in FIG. 27 of the conventional example in which the word line is provided below the bit line. 355 is parallel to the bit lines 352 and 353 in the same layer for a long distance, the parasitic load capacitance of the bit lines 352 and 353 increases, and the VSS power wiring 355 and the bit lines 352 and 353 caused by particles There is no problem of yield reduction due to short circuit failure. This problem does not occur in the case of third and fourth reference examples described later.
(First embodiment)
The first embodiment will be described with reference to the drawings. The semiconductor memory device of the present embodiment is a CMOS type SRAM composed of bit line three-layer type horizontal memory cells.

  The layout of the lower layer portion of the horizontal memory cell and the layout of the first layer wiring thereon are the same as those of the bit line two-layer type of FIGS. 21 and 23, and the memory cell arrangement is also shown in FIG. FIG. 28 shows a circuit diagram of the memory cell which is flip-arranged as shown.

  An example of the wiring layout of the second and higher layers in this embodiment is shown in FIG. As shown in FIG. 11, the word line 351 is formed by the second layer wiring 112, and the positive bit line 352, the negative bit line 353, and the VDD power wiring 354 are formed by the third layer wiring, and the fourth layer wiring is formed. As a result, the VSS power supply wiring 204 is formed. In the case of the conventional bit line three-layer type in FIG. 27, the VDD power supply wiring 354, the VSS power supply wiring 355, and the positive / negative bit lines 352 and 353 run in parallel over a long distance due to the third layer wiring. As the process progresses, the parasitic load capacitance of the bit lines 352 and 353 may increase, and the yield due to particles tends to decrease. Therefore, in the present embodiment, as shown in FIG. 11, only the connection island-shaped VSS node 201 for passing the third-layer VSS power supply running in parallel with the bit lines 352 and 353 from the upper layer to the lower layer is used. In the fourth layer, the VSS power wiring 204 is provided. Since the parallel running distance of the VSS power supply that runs in parallel with the bit lines 352 and 353 is shortened, the bit line capacity is reduced, and it is strong against particles and the like in the process step, thereby improving the yield.

  Also in this case, in order to raise VSS to the VSS power supply wiring 204 in the fourth layer, the via portion 203 that connects the third layer and the fourth layer is required. As in the first reference example, the concern about a decrease in yield due to an increase in the number of via layer layers that pass logic for configuration is dealt with by using a plurality of via portions 203 in FIG. Regarding the fourth-layer wiring, only the VSS power wiring 204 exists, the VDD power wiring does not exist, and the VSS power wiring 204 extends to cover the bit lines 352 and 353 in the direction parallel to the well boundary line. There are the same effects as described in Reference Example 1.

  Further, as described in the first reference example, the VDD power supply line 205 (see FIGS. 4 and 7) is further provided in the fourth layer, and the VDD power supply line 354 is backed up to strengthen the VDD power supply. You can also

  Further, as described in Reference Example 1, the pattern of the VSS power wiring 204 in the fourth layer may be a complete plate shape, but a line and space shape or a mesh shape may be used in recent Cu damascene wiring. Suitable for

  Further, as described in the reference example 1, as shown in FIG. 11, the fourth-layer VSS power wiring 204 and the third-layer VDD power wiring 354 extending in the vertical direction are formed in the substrate contact cell portion. The power supply can be strengthened by interconnecting in the horizontal direction with a second-layer wiring in the same layer as the word line 351 so that the VDD power supply and the VSS power supply have a mesh structure.

  Further, as described in the reference example 1, by increasing the thickness of the fourth layer wiring, the sheet resistance value of the VSS power supply wiring 204 is reduced, the parasitic resistance is reduced, and the power supply capability is increased. You can also

  Further, by using the memory cell according to the present embodiment, the probability that the bit lines 352 and 353 are shorted to VSS and collectively defective in the bit line direction is reduced, so that the necessity for mounting a column redundancy relief circuit is low. Become. By making the mounted redundant circuit and spare memory cell only for row redundancy, it is possible to avoid an increase in area due to the mounting of the column redundancy relief circuit, reduce the area, and realize a high-performance memory block.

In the present embodiment, since the VSS power supply wiring 204 is a wiring layer different from the word line 351, the VSS power supply wiring 120 as shown in FIG. 25 of the conventional example in which the word line is provided above the bit line is provided. Problems such as an increase in parasitic load capacity of the word line 119 due to parallel running over a long distance in the same layer as the word line 119, and a decrease in yield due to a short defect between the VSS power supply wiring 120 and the word line 119 caused by particles. Does not occur.
(Reference Example 2)
Reference Example 2 will be described with reference to the drawings.

  In the example shown in the first embodiment and the reference example 1, the layout of the memory cell is completed up to the fourth layer. However, even if the LSI is a multi-layer wiring or there is a concern about a slight decrease in yield, the idea described in the first embodiment and the reference example 1 is used when a very high operation speed is required. Thus, a memory cell corresponding to the five-layer wiring can be configured.

  Also in this reference example, the layout of the lower layer portion of the horizontal memory cell and the layout of the first layer wiring thereon are the same as those in FIGS. 21 and 23, and the memory cell layout is also flipped as shown in FIG. The circuit diagram of the arranged memory cell is shown in FIG. An example of the wiring layout of the second layer, the third layer, the fourth layer, and the fifth layer in this reference example is shown in FIG. 12, FIG. 13, FIG. 14, and FIG.

  In Reference Example 1, the VDD power supply wiring is arranged between the positive and negative bit lines with the same layer metal serving as a shield. However, in this reference example, the VDD power supply wiring 116 is arranged in the second layer as shown in FIG. As shown in FIG. 13, positive / negative bit lines 403 and 404 are arranged in the third layer. As a result, although the shield layer between the positive / negative bit lines 403 and 404 in the own cell is eliminated, the absolute value of the bit line capacitance itself is reduced. When the width of the VDD power supply wiring is W and the distance between the VDD power supply wiring and the bit line is d, the capacitance between the positive and negative bit lines when there is no VDD power supply wiring in the same layer between the bit lines 403 and 404 is C∝ε ÷ (W + 2 * d), but when the VDD power supply wiring exists in the same layer, C∝ε ÷ d. By eliminating the shield layer, interference between positive and negative occurs, but if the distance is long and the coupling capacitance between positive and negative is small, the transition time of the bit line is shortened due to the small parasitic capacitance, and the access time is increased. Can be

  As shown in FIG. 14, the word line 419 is arranged in the fourth layer, and the VSS power supply has only the VSS node 418 of the connecting island shape pattern in the fourth layer. As shown in FIG. 15, the VSS power supply wiring 413 is arranged in the fifth layer.

  Again, in order to raise the VSS to the VSS power supply wiring 413 of the fifth layer, a plurality of via portions 414 connecting the fourth layer and the fifth layer are taken to reduce the yield due to an increase in the number of via portion layers. Suppressed. Regarding the fifth-layer wiring, only the VSS power wiring 413 exists, no VDD power wiring exists, and the VSS power wiring 413 extends so as to cover the bit lines 403 and 404 in the direction parallel to the well boundary line. Although the wiring layers are different, the same effects as described in Reference Example 1 can be obtained.

  Further, although the wiring layers are different, as described in the reference example 1, the VDD power wiring 205 (see FIGS. 4 and 7) is further provided in the fifth layer of the same layer as the VSS power wiring 413, and the second layer The VDD power supply can be strengthened by backing the VDD power supply wiring 116.

  Although the wiring layers are different, as described in Reference Example 1, the pattern of the fifth-layer VSS power wiring 413 may be a complete plate shape, but may be a line and space shape or a mesh shape. Suitable for recent Cu damascene wiring.

  Although the wiring layers are different, as described in the reference example 1, the word line 419 is bent as shown in FIG. 8, or the wiring width is increased as shown in FIG. Thus, the same effect can be obtained.

In addition, the fourth layer in which only the word line 419 exists as the signal line is thicker than the wiring layer in the third layer or less, or the fifth layer in which only the VSS power supply line 413 exists. By increasing the film thickness, resistance values of the word line 419 and the VSS power supply wiring 413 can be further suppressed, and wiring delay can be suppressed and power supply capability can be increased.
(Reference Example 3)
Reference Example 3 will be described with reference to the drawings.

  Also in this reference example, the layout of the lower layer portion of the horizontal memory cell and the layout of the first layer wiring thereon are the same as those in FIGS. 21 and 23, and the memory cell layout is also flipped as shown in FIG. The circuit diagram of the arranged memory cell is shown in FIG. An example of the wiring layout of the second layer, the third layer, the fourth layer, and the fifth layer in this reference example is shown in FIG. 16, FIG. 17, FIG. 18, and FIG.

  Similar to Reference Example 2, this reference example has a memory cell configuration corresponding to five-layer wiring. In the reference example 2, the VDD power supply wiring is the second layer and the bit line is the third layer, whereas in the present reference example, as shown in FIGS. 16 and 17, the bit lines 407 and 408 are shown. Is the second layer, and the VDD power supply wiring 410 is arranged in the third layer. As a result, as in Reference Example 2, the bit line capacitance can be reduced by removing the shield between the positive and negative bit lines. However, in this reference example 3, since there is an island-shaped pattern VDD node 409 for lifting the VDD power supply wiring 410 to the third layer, the bit lines 407 and 408 and the VDD power supply wiring 410 are arranged in different wiring layers. The effect will be slightly weakened. The layout structure in which the bit lines 407 and 408 are arranged in the second layer as in the reference example 3 has the bit line 407 and 408 in which the via portions are shallower than those in which the bit lines are arranged in the third layer. The line capacity may be light.

  The wiring performance can vary depending on various situations such as the width and interval of each layout, the cross-sectional structure and the dielectric constant of the constituent materials.

  In FIG. 18 showing the layout of the fourth layer, the word line 411 is thick and bent. The word line resistance value often becomes a problem because it is a large value because it extends over a long distance in the memory block. As in the case of the reference example 1, by bending, the word line resistance is reduced by widening the word line width while widening the distance from the island-shaped VSS node 417 of the fourth layer to reduce the capacity.

  Also, a plurality of via portions 412 for connecting the word line 411 and the lower pattern are formed. This alleviates concerns about yield reduction due to multilayer wiring and the use of multiple via layers.

  Further, the fourth layer in which only the word line 411 exists as the signal line is made thicker than the wiring layer in the third layer or less, or the fifth layer in which only the VSS power supply line 413 exists. By increasing the film thickness, the resistance values of the word line 411 and the VSS power supply wiring 413 can be further suppressed.

  In addition, as described in Reference Example 2, the wiring layer is different, but the same modification as in Reference Example 1 is possible.

  In Reference Examples 2 and 3, since there is no parallel running over a long distance between the word lines (419, 411) and the VSS power supply wiring (413), the parasitic capacitance of the word lines is reduced and the speed is increased. Needless to say, it is possible to reduce the probability that the word line and the VSS power supply wiring will cause a short circuit failure and increase the yield.

  According to the semiconductor memory device of the present invention, the parallel running distance between the bit line arranged in the horizontal direction (row direction) and the VSS power supply is shortened, the parasitic capacitance of the bit line is reduced, and the adjacent wiring in the same layer is a particle. This has the effect of reducing the probability of short circuit failure and increasing the yield, and is useful as a semiconductor memory device of CMOS SRAM (Static Random Access Memory).

Explanatory drawing of the memory cell layout concerning the reference example 1. Explanatory drawing of the memory cell layout which took two via parts for connection to VSS of the 4th layer concerning reference example 1 Memory cell layout explanatory view showing the second layer wiring or more in FIG. Explanatory drawing of the example which has VDD and VSS in the 4th layer concerning the reference example 1. Explanatory drawing of the bad example which has VDD and VSS in the 4th layer concerning the reference example 1, and backed VDD in the memory cell The figure which shows the example of a substrate contact cell insertion in the SRAM block concerning the reference example 1. Illustration of backing layout in substrate contact cell according to Reference Example 1 Memory cell layout explanatory diagram having a bent word line displaying more than the second layer wiring according to Reference Example 1. Explanatory drawing of the memory cell layout which has the bending width word line concerning the reference example 1. Layout image of row redundancy and column redundancy mounting block according to Reference Example 1 Memory cell layout explanatory diagram showing the second layer wiring or more according to the first embodiment The explanatory diagram mainly showing the second layer wiring of the memory cell layout example according to the reference example 2 and the via layer for connecting the second layer wiring and the lower layer. 3 is an explanatory diagram mainly showing the third layer wiring of the memory cell layout example according to Reference Example 2 and the via portion for connecting the third layer wiring and the lower layer. 4 is an explanatory diagram mainly showing the fourth layer wiring of the memory cell layout example according to Reference Example 2 and a via portion for connecting the fourth layer wiring and the lower layer. Explanatory diagram mainly showing the fifth layer wiring of the memory cell layout example according to Reference Example 2 and the via layer for connecting the fifth layer wiring and the lower layer. Explanatory drawing mainly showing the second layer wiring of the memory cell layout example according to Reference Example 3 and the via layer for connecting the second layer wiring and the lower layer. 3 is an explanatory diagram mainly showing the third layer wiring of the memory cell layout example according to Reference Example 3 and a via portion for connecting the third layer wiring and the lower layer. 4 is an explanatory diagram mainly showing the fourth layer wiring of the memory cell layout example according to Reference Example 3, and the via layer for connecting the fourth layer wiring and the lower layer. An explanatory diagram mainly showing the fifth layer wiring of the memory cell layout example according to Reference Example 3 and a via portion for connecting the fifth layer wiring and the lower layer. Illustration of a conventional vertical memory cell layout example Explanatory drawing around the base of a conventional horizontal memory cell layout example Memory cell layout method illustration Explanatory drawing mainly showing the first layer wiring of a conventional horizontal memory cell layout example 2 is an explanatory diagram mainly showing a second layer wiring of a conventional bit line two layer type horizontal memory cell layout example and a via portion for connecting the second layer wiring and the lower layer. Explanatory drawing mainly showing the third layer wiring of the conventional bit line two layer type horizontal memory cell layout example and the via portion for connecting the third layer wiring and the lower layer. Explanatory drawing mainly showing the second layer wiring and the via layer for connecting the second layer wiring and the lower layer in the conventional bit line three-layer horizontal memory cell layout example Explanatory drawing mainly showing the third layer wiring of the conventional bit line three layer type horizontal memory cell layout example and the via portion for connecting the third layer wiring and the lower layer. Circuit diagram of CMOS SRAM memory cell

Explanation of symbols

100 P well 101 N well 102 Well boundary line 103 Diffusion layer 104 Gate electrode 105 Contact hole 106 connecting the diffusion layer or the gate electrode and the first layer wiring 106 Connecting the diffusion layer, the gate electrode and the first layer wiring Shared contact 107 N-channel type access transistor 108 N-channel type drive transistor 109 P-channel type load transistor 110 Cell boundary frame 111 for one bit of memory cell First layer wiring 112 Second layer wiring 113 First layer and second layer Via portion 114 for connection with the layer Positive bit line (M2)
115 Negative bit line (M2)
116 VDD power supply wiring (M2)
117 Third-layer wiring 118 Via portion 119 for connection between second and third layers 119 Word line (M3)
120 VSS power supply wiring (M3)
201 VSS node 202 of third layer wiring having island shape 202 Connecting via portion 203 between second layer and third layer Connecting via portion 204 connecting third layer and fourth layer Fourth layer VSS power supply wiring 205 4th layer VDD power supply wiring,
206 VDD node 207 of island-shaped third-layer wiring arranged in memory cell Bent word line 208 Bent wide word line 300 Substrate contact substrate contact cell 302 Memory cell 301 Island shape arranged in substrate contact cell VDD node 310 of the third layer wiring of the redundancy redundancy row decoder 311 Row redundancy spare memory cell 312 Column redundancy spare memory cell 313 Row decoder portion 314 Control portion 315 Data input / output portion 351 Word line (M2)
352 Positive bit line (M3)
353 Negative bit line (M3)
354 VDD power supply wiring (M3)
355 VSS power supply wiring (M3)
401 Positive bit line connection node 402 of island-shaped second layer wiring Negative bit line connection node 403 of island-shaped second layer wiring Positive bit line (M3)
404 Negative line (M3)
405 Via portion 406 connecting the second layer and the third layer VSS node 407 of the island-shaped third layer wiring 407 Positive bit line (M2)
408 Negative bit line (M2)
409 VDD node 410 of the island-shaped second layer wiring VDD wiring (M3)
411 Bent word line (M4)
412 Via portion 413 for connecting the fourth-layer word line and the island-shaped pattern of the third layer VSS wiring (M5)
414 Via portion 415 for connecting the fifth layer VSS and the fourth layer island pattern 415 Memory cell frame 416 VSS connection via portion 417 for the fourth layer and the third layer Island-shaped fourth layer VSS node 418 of the main wiring VSS node 419 of the fourth layer wiring of the island shape Linear word line (M4)

Claims (10)

A pair of access transistors and a pair of drive transistors arranged in a matrix on a semiconductor substrate, each formed in a first conductivity type well region, and a pair of load transistors formed in a second conductivity type well region, respectively in configured, U E le region as the second conductivity type well region between the front SL two of said first conductivity type well region on the semiconductor substrate is sandwiched are formed side by side in the row direction, 2 one of a plurality of one by the access transistor and the drive transistor and the CMOS SRAM cell in a long shape is formed Tagyo direction of each of the first conductivity type well region, forming the CMOS SRAM cell A semiconductor memory device having a plurality of wiring layers on top of a transistor,
A plurality of word lines formed of one of the plurality of wiring layers, each extending in a row direction and connected to the CMOS SRAM cell in the same row, and arranged in a column direction;
A plurality of pairs of bit lines formed in the wiring layer one layer above the word line, each extending in the column direction and connected to the CMOS SRAM cell in the same column, and arranged side by side in the row direction;
A plurality of VDD power lines formed of the wiring layer in the same layer as the bit lines, each disposed between the paired bit lines and connected to the CMOS type SRAM cells in the same column;
A VSS power wiring formed in the wiring layer one layer above the bit line and connected to the CMOS SRAM cell;
Prior Symbol VSS power supply line, said being connected to the CMOS SRAM cell through the VSS power supply connection pattern formed in the wiring layer below the first layer than VSS power supply wiring, the VSS power source connected to the VSS power supply line the semiconductor memory device connected to the use pattern is characterized in that it is made by a plurality of arrangement of the via portion per one of the VSS power supply connection pattern. A pair of access transistors and a pair of drive transistors arranged in a matrix on a semiconductor substrate, each formed in a first conductivity type well region, and a pair of load transistors formed in a second conductivity type well region, respectively And the well region is formed side by side in the row direction so that the second conductivity type well region is sandwiched between two well regions of the first conductivity type on the semiconductor substrate. A plurality of CMOS SRAM cells each having a long shape in the row direction in which one access transistor and one drive transistor are formed in each one conductivity type well region, and an upper portion of the transistor constituting the CMOS SRAM cell A semiconductor memory device comprising a plurality of wiring layers,
A plurality of word lines formed of one of the plurality of wiring layers, each extending in a row direction and connected to the CMOS SRAM cell in the same row, and arranged in a column direction;
A plurality of pairs of bit lines formed in the wiring layer one layer above the word line, each extending in the column direction and connected to the CMOS SRAM cell in the same column, and arranged side by side in the row direction;
A plurality of VDD power lines formed of the wiring layer in the same layer as the bit lines, each disposed between the paired bit lines and connected to the CMOS type SRAM cells in the same column;
A VSS power wiring formed in the wiring layer one layer above the bit line and connected to the CMOS SRAM cell;
A semiconductor memory device, wherein a plurality of the VSS power supply wirings are arranged side by side in the row direction and are arranged so as to cover the bit lines . 3. The semiconductor memory device according to claim 1, wherein each of the regions of the CMOS type SRAM cell has a width in the row direction that is twice or more a width in the column direction . 3. The semiconductor memory device according to claim 1, wherein the word line is bent . 2. The semiconductor memory device according to claim 1, further comprising a VDD reinforcing wiring that is formed of a wiring layer that is the same layer as the VSS power supply wiring and is connected to the VDD power supply wiring. The semiconductor memory device according to claim 5, characterized in that said connection between the VDD reinforcing wires and the VDD power supply line, were performed in substrate potential securing the substrate contact cell region of the transistor constituting the CMOS type SRAM cell. The formed wiring layers of said word lines in the same layer in the substrate potential ensures substrate contact cell area of the transistor constituting the CMOS SRAM cell, provided the power reinforcing lines extending in the row direction, the said power reinforcing lines the semiconductor memory device according to claim 1 or 2 at the intersection between the VDD power supply wiring or the VSS power supply line, characterized in that connected to the VDD power supply wiring or the VSS power supply line. The semiconductor memory device according to claim 1, wherein the VSS power supply wiring has a mesh shape. The VSS thickness of the wiring layer forming the power supply wiring, the semiconductor memory device according to claim 1 or 2, wherein the greater thickness than the lower wiring layer than the VSS power supply line. 3. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device has only a row redundancy circuit without a column redundancy circuit.

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