JP2008211077A - Semiconductor memory cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory cell by which effects of a decrease in area, the improvement of workability, reduction in wiring load, the improvement of a redundant remedy yield and the like can be obtained by rationalizing a wiring layout in a multi-port SRAM in which several bit lines and word lines exist and whose wiring layout has a greater tendency to be tight than a one-port SRAM. <P>SOLUTION: The bit lines are arranged in second layer wiring. The word lines are arranged in third layer wiring. VSS lines are arranged in fourth layer wiring. In this case, a word line connection part (the second layer) for connecting the word lines with a lower layer and a VSS line connection part (the second layer) for connecting the VSS lines with a lower layer are arranged on the same straight line in the direction of the extension of the bit lines. Further, a difference is made between the right side and the left side of a word line system when viewed from the center of the memory cell which is arranged beside the VSS line connection part (the second layer) in the direction of the bit lines. Furthermore, the length of the cell in the longitudinal direction is suppressed by bending the word lines in the third layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory cell, and more particularly to an SRAM (Static Random Access Memory) of a semiconductor integrated circuit. The present invention particularly relates to a wiring layout of a multiport memory cell having a plurality of word lines per bit.

  Semiconductor memory cells have a high area ratio in the LSI. For this reason, the demand for a reduction in area for semiconductor memory cells is severe. The severity of this requirement is the same not only for a 1-port memory having one word line per bit but also for a multi-port memory having a plurality of word lines per bit.

  In recent generations of fine semiconductors, a configuration called a horizontal cell tends to be adopted as a layout topology of semiconductor memory cells. This is because the extending direction of the pattern of the gate electrode and the diffusion layer is uniform in each mask layer, and lithography processing of the gate electrode and the diffusion layer is easy. In conference presentations after the 65 nm generation, almost all semiconductor manufacturers adopt horizontal cells for 1-port memory cells. This flow is the same in the multiport memory cell. An example of the layout of the horizontal cell topology is described in Patent Document 4.

  Further, after the 65 nm generation, an increase in random variation in transistor characteristics due to element size reduction and a variation in SRAM cell characteristics caused by the increase will become major issues.

  There is a relationship of ΔVt∝Pelgrom coefficient × (1 / SQRT (Wg × Lg)) among device variation (ΔVt), element gate width (Wg), and gate length (Lg). If the Pelgrom coefficient is not improved, when the element size is reduced by 0.7 times between generations due to device scaling, the amount of device variation will increase by about 1.4 times. As described above, when the cell area is reduced according to the scaling trend, it is very difficult to secure the write / read characteristics of the memory cell at the Mbit level. This is a big problem in the memory field.

  As a countermeasure to this problem, a method of constraining the element size such as the gate length and the gate width to a value larger than the processing limit size determined by the scaling law can be considered. However, the need for a small area and low cost for the memory cannot be satisfied. For this reason, many methods for improving the characteristics of the memory cell by dynamically controlling the terminals of the transistors constituting the memory cell have been proposed (see Patent Document 2 and Patent Document 3).

  Hereinafter, a conventional memory cell will be described in detail.

  FIG. 44 is a circuit diagram showing a conventional 1-port memory cell. FIG. 45 is a circuit diagram showing a conventional 2-port memory cell.

  Compared with the 1-port memory cell shown in FIG. 44, it is very difficult to secure the static noise margin characteristics of the 2-port memory cell shown in FIG. This is because in the 2-port memory cell, there are two access transistors on the read side 110 and the write side 107 (access transistors 110 and 107). That is, when the write / read operation is simultaneously performed in the same row, the word lines WWL and RWL of both ports become active simultaneously, and the access transistors 107 and 110 of both ports simultaneously raise the potential level of the latch internal node 103. .

  In the two-port memory cell, in order to keep the static noise margin characteristics favorable, the drive capability of the access transistors 107 and 110 is lowered (specifically, realized by reducing the gate width or the gate length) or the drive transistor 108. It is necessary to increase the gate width. However, the reduction in the gate width of the access transistors 107 and 110 leads to a decrease in current passing through the access transistors 107 and 110 at the time of data writing and data reading, that is, a reduction in the operation speed of the memory cell. Is unacceptable. The gate width of the drive transistor 108 can be increased by referring to the circuit layout diagram shown in FIGS. 46 to 49, particularly FIG. 46 showing the layout of the base layer (layer in which the latch portion is formed). This leads to an increase in the area.

  The following countermeasures can be considered for the above-mentioned problems such as static noise margin characteristics and cell current during the simultaneous write / read operation. As shown in FIG. 50, a circuit configuration is employed in which a transistor 111 is provided and the potential of the latch internal node 103 is input to the gate of the transistor 111. By adopting this configuration, it is possible to prevent a current from flowing from the latch internal node 103 during the Read operation. Therefore, it is possible to prevent deterioration of noise margin characteristics during the read operation. Note that the number of transistors increases from eight to ten. When it is desired to reduce the area in this circuit configuration, as shown in FIG. 51, it is also possible to make the Read port a single read mode that is not complementary read (see Patent Document 1).

However, in the miniaturization process in the future, device manufacturing variation tends to increase more and more. For this reason, the number of transistors is larger than that of the 8-transistor type shown in FIG. 45, but the 10-transistor type shown in FIG. 50 is preferably used in terms of memory cell characteristics. This is because by adopting the 10-transistor type, interference from the Read port can be avoided. In this case, by reducing the gate width of the drive transistor 108, the area can be reduced as compared with the conventional configuration. 52 to 55 respectively show the base layout, the first layer wiring layout, the wiring layout below the second layer wiring, the wiring layout below the third layer wiring, and the wiring layout below the fourth layer wiring of the 10-transistor type memory cell. FIG.
JP-A-63-205890 Japanese Patent No. 1394881 US Pat. No. 6,791,864 B2 JP 2002-43441 A JP 2004-311610 A ISSCC 2005 Low-Power Embedded SRAM Modules With Expanded Margins for Writing (Renesas)

  However, since the multi-port memory has more signal lines such as bit lines and word lines than the 1-port memory, the layout of the wiring layer is very difficult.

  The multiport memory can reduce the transistor size to cope with device variations. However, in the multi-port memory, it is difficult to reduce the cell area sufficiently because the layout of metal wiring patterns such as bit lines and word lines becomes tight.

  When the size of the memory cell increases in the bit line extending direction, the bit line length becomes longer and the bit line resistance increases. Further, when the size of the memory cell is increased in the word line extending direction, the word line resistance increases. Further, not only the wiring length but also the congestion of wiring patterns in the same layer increases the coupling capacitance between the same-layer wirings, that is, the parasitic capacitance. An increase in resistance and parasitic capacitance of the bit line or word line is not preferable from the viewpoint of memory operation speed and power consumption.

  Up to this point, the problem has been described mainly on a 2-port SRAM (1W-1R type), one of which is a write port and the other is a read port. This is common to ports and triple port SRAM.

  The present invention has been made in view of the above circumstances, and can reduce the area of the memory cell while maintaining the operating characteristics and the ease of processing. In particular, the SRAM (see Patent Document 4) having a lateral layout can be reduced. An object of the present invention is to provide a semiconductor memory cell optimal for area increase.

A semiconductor memory cell according to the present invention includes:
A semiconductor memory cell comprising at least three layers and storing data statically,
A first layer formed with a latch portion as a storage area;
A second layer formed with bit lines;
A third layer on which word lines are formed,
By providing power supply lines in the third and higher layers, an arrangement space is provided in the second layer, and a section-like word line connection portion for electrically connecting the word line and the latch portion is provided in the arrangement space. The semiconductor memory cell is arranged.

  In the present invention, by providing the power supply line in the third or higher layer, an arrangement space is provided in the second layer, and a section-like word line connection portion for electrically connecting the word line and the latch portion to the arrangement space is provided. Deploy. Thereby, the fit of the word line connection portion in the second layer is improved, and the memory cell area can be reduced in the word line extending direction. Moreover, wiring congestion in the second layer can be eliminated. As a result, it is possible to provide a sufficient space between the bit lines, and the coupling capacitance (parasitic capacitance) between the bit lines can be reduced. By reducing the parasitic capacitance, the power consumption of the memory can be reduced and the processing speed can be increased. Since the fourth layer has a smaller number of wires than the third layer, when the power supply line is provided in the fourth layer, the power supply line can be made thicker. Thereby, the electrical resistance of a power supply line can be made small and a power supply can be strengthened. Also in the third layer, the power line can be made thicker in the word line extending direction.

The first layer in the present invention has a latch portion as a main component. The first layer may be formed by sequentially stacking an insulating film (contact hole is formed) and a metal wiring layer on the latch portion. In this case, the latch portion and the upper bit line are electrically connected through the metal wiring layer.
The second layer in the present invention includes a bit line and an insulating film (a via hole is formed) on which the bit line is disposed on the upper surface. The third layer includes a word line and an insulating film (a via hole is formed) on which the word line is formed.

  The present invention is mainly applied to a multiport memory in which wiring layout is difficult. An example of a multi-port memory is a two-port memory, but is not limited to this. The present invention can be applied to a multiport memory having three or more ports.

In the present invention,
By providing the power line in the third layer, an arrangement space is provided in the second layer, and a section-like power line connection part for electrically connecting the power line and the latch part is arranged in the arrangement space. It is preferable.

  Thereby, the power supply line can be arranged in the third layer, and the power supply line and the latch portion can be electrically connected. Further, the fit of the word line connection portion in the second layer is improved, and the memory cell area can be reduced in the word line extending direction.

In the present invention,
By providing the power supply line in the fourth layer, an arrangement space is provided in the second layer, and a section-like power supply line that electrically connects the power supply line and the latch portion to the arrangement space and the third layer. It is preferable to arrange the connecting portion.

  Accordingly, the power supply line can be arranged in the fourth layer, and the power supply line and the latch portion can be electrically connected. Further, the fit of the word line connection portion in the second layer is improved, and the memory cell area can be reduced in the word line extending direction.

In the present invention,
It is preferable that an arrangement space for the word line connection portion and an arrangement space for the power supply line connection portion in the second layer are provided on the same straight line parallel to the bit line.

  Thereby, the fit of the word line connection portion and the power line connection portion is further improved, and the memory cell area can be further reduced in the word line extending direction.

In the present invention,
The power supply line is preferably a VSS line.

  By providing the VSS line in the third layer or more, the VDD line can be provided in the second layer, and the VSS line and the VDD line can be provided in separate layers. As a result, the VSS line and the VDD line do not run in parallel in the same layer. Therefore, a short circuit between the VSS line and the VDD line can be prevented. Since a short circuit between the VSS line and the VDD line cannot be dealt with by redundancy relief, it is very effective to use the power supply line arranged in the third layer or higher as the VSS line.

In the present invention,
As the word line, a write word line and a read word line are provided,
As the word line connection unit, a write word line connection unit and a read word line connection unit are provided,
As the power supply line connection part, a first power supply line connection part and a second power supply line connection part are provided corresponding to the output and the inverted output of the latch part, respectively.
The read word line connection part and either the first power line connection part or the second power line connection part are provided in the same wiring layer and parallel to the bit line. Located on the same straight line,
The write word line connection portion and the other one of the first power supply line connection portion and the second power supply line connection portion are provided in the same wiring layer and are parallel to the bit line. It is preferably located on the line.

  With such a configuration, the write word line and the read word line can be easily connected in a state where a sufficient interval is provided between the write word line and the read word line. As a result, the via hole for connecting the second-layer word line connecting portion and the third-layer word line can be located closer to the center from the end of the word line connecting portion. Therefore, it is possible to obtain a wiring layout that is resistant to mask misalignment and the like and that can be easily processed by lithography or the like. In addition, the word line width can be increased, or the width of the word line connection portion of the second layer can be increased to improve the processability.

In the present invention,
It is preferable that the power line connecting portion is shared with other adjacent memory cells.

  By sharing the power line connection part with other memory cells, the pattern area of the power line connection part can be increased. Therefore, a pattern size necessary for processing such as lithography can be easily secured.

In the present invention,
The power line is preferably shared with other adjacent memory cells.
By sharing the power supply line with other adjacent memory cells, the memory cell can be reduced in the width direction of the power supply line. In addition, power consumption can be reduced by making the power supply line thicker and reducing the electrical resistance of the power supply line. Further, when the power supply line is provided in the third layer, the interval between the word line and the power supply line can be increased, and the parasitic capacitance generated between the word line and the power supply line can be reduced. Further, when the power supply line is provided in the third layer, the word line can be thickened and the electric resistance of the word line can be reduced.

In the present invention,
It is preferable that the power supply line is wired in the extending direction of the bit line or in a mesh shape.

  The power supply line is wired in the extending direction of the bit line or wired in a mesh shape, so that the memory cell group arranged in the row direction simultaneously active on the same word line becomes 1 or 2 bits. Power can be supplied one by one from the column direction (bit line direction). Therefore, the power supply system can be strengthened. When the wiring is made in the mesh structure, the power supply is strengthened also in the row direction, so that it can be further strengthened compared with the case where the wiring is made in the extending direction of the bit line.

In the present invention,
It is preferable that an arrangement space is provided in the third layer by bending the word line, and the section-like power line connection portion that electrically connects the power line and the latch portion is disposed in the arrangement space. .

  With this configuration, when the power supply line is provided in the fourth layer, the power supply line connection portion in the third layer is better accommodated, and the memory cell area can be reduced in the word line width direction. In addition, the word line can be thickened while maintaining the memory cell area. As a result, the electrical resistance of the word line can be reduced and the word line is less likely to be disconnected.

In the present invention,
A semiconductor memory cell having at least four layers and storing data statically,
A first layer formed with a latch portion as a storage area;
A second layer formed with bit lines;
A third layer in which local word lines are formed;
A fourth layer formed with global word lines that form hierarchical word lines in cooperation with the local word lines;
By providing power supply lines in the fourth and higher layers, an arrangement space is provided in the second layer, and a section-like local word line connection for electrically connecting the local word line and the latch unit to the arrangement space. It is preferable to provide a part.

  In the present invention, in a semiconductor memory cell having a hierarchical word line structure, a power supply line is provided in the fourth layer or higher layers, thereby providing an arrangement space in the second layer, and electrically connecting the word line and the latch unit to the arrangement space. A section-like word line connection portion connected to is arranged. Thereby, the fit of the word line connection portion in the second layer is improved, and the memory cell area can be reduced in the word line extending direction. It is rational that a global word line that does not require connection to the lower layer for each bit is arranged in the uppermost layer. Moreover, wiring congestion in the second layer can be eliminated. As a result, it is possible to provide a sufficient space between the bit lines, and the coupling capacitance (parasitic capacitance) between the bit lines can be reduced. By reducing the parasitic capacitance, the power consumption of the memory can be reduced and the processing speed can be increased. Since the fourth layer has fewer wires than the third layer, the power line can be made thicker by providing the power line in the fourth layer. Thereby, the electrical resistance of a power supply line can be made small and a power supply can be strengthened.

In the present invention,
The latch part is a multi-port type latch part,
The bit line includes a write bit line and a read bit line,
The word line includes a write word line and a read word line,
The word line connection unit includes a write word line connection unit and a read word line connection unit,
The write word line is connected to the write word line connection unit,
The read word line is preferably connected to the read word line connecting portion.

  With such a configuration, a multi-port memory cell can have a wiring layout that exhibits effects such as cell area suppression.

In the present invention,
The latch part is a multi-port type latch part,
The bit line includes a write bit line and a read bit line,
The word line connection unit includes a write word line connection unit and a read word line connection unit,
It is preferable that both the write word line connection unit and the read word line connection unit are connected to one word line, and the word line controls both the write operation and the read operation.

  With such a configuration, in the 1-port memory cell in which the latch unit is a multi-port type and the write control and the read control are performed by one word line, a wiring layout that has an effect such as cell area suppression is provided. It becomes possible.

  According to the present invention, the area of a semiconductor memory cell can be reduced while maintaining operating characteristics and processability. The present invention is particularly suitable for reducing the area of a multi-port type SRAM having a horizontal layout.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a wiring layout below the second wiring layer of the semiconductor memory cell according to the first example of the first embodiment. In FIG. 1, a range surrounded by a broken line corresponds to one memory cell.

  The semiconductor memory cell according to the first example of the first embodiment is a semiconductor memory cell that includes at least three layers (first layer, second layer, and third layer) and stores data statically.

  The first layer is a layer including a latch portion that is a storage area, a first insulating film layer (not shown), and a first metal wiring layer (hereinafter, the metal wiring layer is simply referred to as a wiring layer). The first wiring layer is a wiring layer for electrically connecting the latch portion and the bit line of the second wiring layer. The first wiring layer is provided on the latch portion via the first insulating film layer.

  The second layer includes a second insulating film layer (not shown) and bit lines 120, 121, 125, 126 provided on the second insulating film layer. The bit lines 120 and 126 are read bit lines. Bit lines 121 and 125 are write bit lines.

  The structure of the first layer is not particularly different from that of the conventional horizontal layout structure cell.

  The third layer is a layer including a third insulating film layer (not shown) and word lines 133 and 134 provided on the second insulating film layer. The word line 133 is a read word line, and the word line 134 is a write word line.

In the first example of the first embodiment, an arrangement space is provided in the second layer by providing VSS lines (not shown) of the power supply lines in the third and higher layers. In the arrangement space, section-like word line connection portions 127, 128, 129, and 130 for electrically connecting the word lines 133 and 134 and the latch portion are arranged. The word line connection units 127 and 128 are connected to the read word line, and the word line connection units 129 and 130 are connected to the write word line.
This improves the fit of the word line connection portions 127, 128, 129, and 130 in the second layer, and the memory cell area can be reduced in the word line extending direction (lateral direction in FIG. 1). Moreover, wiring congestion in the second layer can be eliminated. As a result, it is possible to provide a space between the wirings, and the coupling capacitance (parasitic capacitance) between the wirings can be reduced. By reducing the parasitic capacitance, the power consumption of the memory can be reduced and the processing speed can be increased.

  Of the power supply lines, the VDD line 123 is provided in the second layer. By providing the VSS line in the third or higher layer and providing the VDD line 123 in the second layer, the parallel running of the VDD line and the VSS line in the second layer as in the prior art (see FIG. 54) is eliminated. Recent SRAMs often have a redundant relief function. When a short circuit occurs between a signal node and a power supply in a certain memory cell, the use of that cell may be stopped and skipped. On the other hand, in the case of a power supply short circuit between the VDD line and the VSS line, a current flows between the power supplies and a potential drop occurs, so the power supply short circuit adversely affects other circuit units. In addition, in the case of a power supply short circuit, the sample has a large leakage current. Therefore, the power supply short-circuit reduces the product value in a low-leakage application type such as a portable device. Such a short-circuit between power supplies, which is difficult to deal with with redundancy relief, can be reduced by eliminating the parallel running of the VDD line and the VSS line. Therefore, a high yield improvement effect can be achieved.

  Although not shown, in the first embodiment, the power supply line provided in the third and higher layers can be a VDD line. In this case, the VSS line is provided in the second layer. Although not shown, in the first embodiment, it is possible to provide both the VDD line and the VSS line in the third and higher layers.

  The fourth layer generally has a smaller number of wires than the third layer. Therefore, when the power supply line is provided in the fourth layer, the power supply line can be made thicker than when the power supply line is provided in the third layer. Thereby, when the power supply line is provided in the fourth layer, the electric resistance of the power supply line can be reduced and the power supply can be strengthened.

In the first embodiment, as shown in FIG. 1, the word line connection portion 129 and the power supply line connection portion 131 in the second layer are provided on the same straight line parallel to the bit lines 120, 121, 125, and 126. Further, the word line connection unit 130 and the power supply line connection unit 132 in the second layer are provided on the same straight line parallel to the bit lines 120, 121, 125, and 126. That is, as shown in FIG. 1, the word line connection unit 129 and the power supply line connection unit 131, and the word line connection unit 130 and the power supply line connection unit 132 are arranged side by side in the bit line extending direction (vertical direction in FIG. 1). To do. Thereby, the fit of the word line connection portions 129 and 130 and the power supply line connection portions 131 and 132 is further improved, and the memory cell area can be further reduced in the word line extending direction. Of the word line connection units 127, 128, 129, and 130, the word line connection units 129 and 130 for writing may be arranged side by side with the power line connection units 131 and 132, as shown in FIG. As shown in FIG. 2, read word line connection units 127 and 128 may be used.
In the example shown in FIG. 2, the power supply line connecting portions 131 and 132 are shared with other adjacent memory cells. The power supply line connection units 131 and 132 shown in FIG. 2 are VSS line connection units. Thereby, the number of power supply line connection parts 131 and 132 can be reduced, and the width of each power supply line connection part 131 and 132 can be enlarged. Thereby, the resistance of the power supply line connecting portions 131 and 132 can be reduced. Further, when forming the power supply line connecting portions 131 and 132, a pattern area necessary for processing such as lithography can be easily secured.

(Second Embodiment)
Next, a second embodiment will be described.

  FIG. 3 is a diagram showing a wiring layout below the second wiring layer of the semiconductor memory cell according to the second embodiment. The semiconductor memory cell according to the second embodiment will be described in comparison with the semiconductor memory cell according to the first embodiment. The same components as those in the first embodiment are denoted by the same reference numerals.

  In the first embodiment, the word lines 133 and 134 and the word line connection portions 127, 128, 129, and 130 are connected at the connection positions (via placement positions) indicated by ◯ in FIGS. That is, it is necessary to connect the read word line 133 to the word line connection units 127 and 128 and connect the write word line 134 to the word line connection units 129 and 130. The word line connection portions 127, 128, 129, and 130 need to secure a pattern area necessary for processing such as lithography within a limited memory cell vertical width.

  However, in the example shown in FIG. 1, the word line connecting portion 129 cannot extend to the lower side because the power line connecting portion 131 exists on the lower side in the vertical direction. Since the power line connecting part 132 exists on the upper side in the vertical direction, the word line connecting part 130 cannot extend to the same upper side. Under such restrictions, the word line connection portions 129 and 130 are connected to the writing word line 134 extending in the horizontal direction, and the reading word line 133 is further spaced apart from the writing word line 134. It is difficult to arrange and connect the read word line 133 and the word line connecting portions 127 and 128. In order to ensure a sufficient interval between the read word line 133 and the write word line 134, it is necessary to increase the memory cell size in the vertical direction. The same applies to the example shown in FIG.

  In response to this problem, in the second embodiment, as shown in FIG. 3, in the second layer, the power supply line connecting portions 131 and 132 (power supply line connecting portion for the VSS line in the illustrated example) and the bit line extending direction ( The word line connection portions arranged in the vertical direction) are configured to select different types of word line connection portions for the left half and the right half as viewed from the center of the memory cell. In the example shown in FIG. 3, the read word line connection unit 127 and the power supply line connection unit 131 are arranged in the left half, and the write word line connection unit 130 and the power supply line connection unit 132 are arranged in the right half. Other configurations are the same as those of the first embodiment.

FIG. 2 (first embodiment) and FIG. 3 (second embodiment) will be described in comparison. In both FIG. 2 and FIG. 3, the left half of the memory cell has the same layout. That is, in both FIG. 2 and FIG. 3, the read word line connecting portion 127 is located in the same column (bit line extending direction) as the power line connecting portion 131. On the other hand, in the right half of the memory cell, the power supply line connection portion 132 is located in the same column as the read word line connection portion 128 in FIG. 2, but in FIG. is doing. In other words, in the configuration shown in FIG. 3 in contrast to the configuration shown in FIG. 2, the power supply line connection unit 132 is moved from the same column position as the read word line connection unit 128 to the same column position as the write word line connection unit 130. . Arrangement order of the power supply line connection unit 131 located in the same column (bit line extending direction) as the read word line connection unit 127 and the read word line connection unit 127, the write word line connection unit 130, and the write word The arrangement order of the power supply line connecting portions 132 located in the same column (bit line extending direction) as the line connecting portions 130 is opposite to each other in the extending direction of the bit lines.
As a result, as shown in FIG. 3, the read word line connecting portion 128 can be moved upward in the vertical direction. Accordingly, the read word line 133 can be disposed sufficiently away from the write word line. Therefore, if the interval between the read word line 133 and the write word line 134 is the same, the vertical width of the memory cell can be reduced in the configuration shown in FIG. 3 than in the configuration shown in FIG.

  Further, as described above, since the read word line connection unit 128 can be moved upward in the vertical direction, a via hole for connecting the read word line connection unit 128 and the read word line 133 is formed in the read word line. The connection portion 128 can be moved from the upper end in the vertical direction toward the center thereof. Therefore, when the read word line connection portion 128 is processed by lithography, a layout having a large allowable margin for mask displacement or the like can be obtained.

  Furthermore, a sufficient interval between the word line 133 and the word line 134 can be secured without impairing the connectivity between the read word line connection unit 128 and the read word line 133, and the occurrence of a short circuit between wirings can be suppressed. In addition, the coupling capacitance between the word lines can be reduced. In addition, the word line can be made thick to reduce the resistance and suppress the disconnection of the wiring.

  In the second embodiment, as shown in FIG. 4, the word lines 1331 and 1341 in the third layer may be bent halfway.

(Third embodiment)
Hereinafter, the third embodiment will be described.

  In the third embodiment, as shown in FIG. 5, the power supply line 135 is shared with other adjacent memory cells in the third layer, for example. Other configurations are substantially the same as those of the first embodiment. In FIG. 5, a VSS line 135 is shared with other adjacent memory cells. The VSS line 135 extends in parallel with the word lines 133 and 134. By sharing the power supply line with other adjacent memory cells, the memory cell can be reduced in the width direction of the power supply line (vertical direction in FIG. 5). In addition, power consumption can be reduced by making the power supply line thicker and reducing the electrical resistance of the power supply line. In addition, a sufficient interval between the word line 133 and the word line 134, or a distance between the word line 133 and the VSS line connecting portion 137, and an interval between the word line 134 and the VSS line connecting portion 137 is secured to suppress a short circuit between wiring lines. can do. In addition, the coupling capacitance between wirings can be reduced. In addition, the electric resistance can be reduced by making the word line thicker. Note that the VSS line 135 can be individually provided for each memory cell.

  In the third embodiment, a power supply line (VSS line 135 in the example shown in FIG. 5) is provided in the third layer, thereby providing an arrangement space in the second layer. In the arrangement space, section-like power supply line connecting portions 131 and 132 for electrically connecting the power supply line 135 and the latch portion are arranged. Thereby, the power supply line 135 can be arranged in the third layer, and the power supply line 135 and the latch part can be electrically connected via the power supply line connection parts 131 and 132.

  In the third embodiment, as shown in FIG. 6, an arrangement space may be provided in the second layer by providing the power supply line in the fourth layer. In FIG. 6, the power supply line provided in the fourth layer is a VSS line 136. In this case, the section-like power line connecting portions 131, 132, and 137 that electrically connect the power line 136 and the latch portion are disposed in the arrangement space and the third layer. Accordingly, the power supply line can be arranged on the fourth layer, and the power supply line and the latch unit can be electrically connected via the power supply line connection units 131, 132, and 137.

  As shown in FIGS. 5 and 6, the VSS lines 135 and 136 are provided in the third and higher layers. By eliminating the power supply line (VSS line) extending in the bit line extending direction in the second layer, the memory cell area can be reduced in the bit line width direction (lateral direction in FIGS. 5 and 6). In addition, since the number of wirings that run in parallel with the word line connection portions 129 and 130 is reduced, it becomes easy to secure a pattern area required in the lithography process for forming the word line connection portions 129 and 130. In addition, since the wirings that run in parallel with the bit lines 120, 121, 125, and 126 are reduced, the parasitic capacitance generated between the bit lines 120, 121, 125, and 126 can be reduced, and the probability of a wiring short can be reduced. .

  In the third embodiment, as shown in FIGS. 7 and 8, the power supply line can be wired in the extending direction of the bit line or in a mesh shape. 7 and 8, the power supply lines are VSS lines 138 and 139. In the example shown in FIG. 7, the VSS line 138 is extended in the bit line extending direction. As a result, the VSS lines 138, 138, 1 are formed from the bit line extending direction one by one or two bits to the memory cell group arranged in the row direction (word line extending direction) which are simultaneously activated by the same word line. 139 can be arranged. Therefore, as compared with the configuration of FIG. 6 in which power is supplied from the word line extending direction, the power supply system is enhanced, which can contribute to stable operation of the memory. As shown in FIG. 8, a further enhanced power supply system can be configured by using a VSS line 139 having a mesh structure in which VSS lines are further connected in the horizontal direction.

  Note that VDD lines may be provided in the second layer and the fourth layer, respectively, as shown in FIG. By disposing VDD lines 1231 and 1232 in two layers and connecting them to each other, the VDD power supply system can be strengthened. It is difficult to connect the fourth-layer VDD line 1232 and the second-layer VDD line 1231 within the memory cell in terms of securing space. Therefore, as shown in FIG. 9, TAP cells 141 are periodically inserted in the bit line extending direction in the horizontal memory cell array, and the second-layer VDD line 1231 and the fourth-layer VDD line 1232 in the TAP cell 141. Are preferably connected. The insertion pattern of the TAP cell 141 can be set as shown in FIG. 10, for example. In the example shown in FIG. 10, the plurality of memory cells 140 arranged in the bit line extending direction and the word line extending direction are replaced with TAP cells 141 periodically (every five in the illustrated example) in the bit line extending direction. If the VDD line 1232 exists in the fourth layer, the VDD line can be arranged in a mesh-like layout.

  Further, in the third embodiment, as shown in FIGS. 11 and 12, an SRAM macro is configured in the fourth layer and below, a mesh power source is configured in the fifth layer and the sixth layer, and the fifth layer and the fourth layer are configured. May be electrically connected. When such a chip design technique is used, the potential supplied from the mesh power supply to the fourth layer can be supplied as it is to the third layer or lower for each memory cell. Accordingly, a memory cell with an enhanced power supply can be configured. When there is a VSS line only in the second layer as in the prior art, a mesh power source cannot be configured. Therefore, a TAP contact portion is formed in the memory cell array, and the power source is strengthened only by lining the TAP contact portion. I could not. On the other hand, as shown in the examples shown in FIGS. 11 and 12, if the potential is supplied from the fifth layer to the fourth layer for each memory cell, the power supply can be strengthened without providing the TAP contact portion. . The memory cell operates to pull down the potential of the bit line to the low side when reading data. The operation of returning the potential of the bit line to the high side is generally performed by a precharge circuit of a peripheral circuit. The VDD only needs to be able to withstand an operation such that a slight amount of current flows during data holding and writing. Therefore, it is preferable to supply VSS to the memory cell as a strong power supply system for each memory cell from two points of potential strength against IR-Drop and memory reliability such as EM (electromigration).

(Fourth embodiment)
The fourth embodiment will be described below.
In the fourth embodiment, as shown in FIGS. 9, 13, 14, and 15, the word lines are arranged in a bent state. An arrangement space is provided in the third layer by bending the word line. In the arrangement space, a section-like power line connecting portion (power source in the example shown in FIG. 14) that electrically connects the power source line (VSS line 138 in the example shown in FIG. 14) and the latch portion in the arrangement space. A line connecting part 137) is arranged. With such a configuration, when the power supply line is provided in the fourth layer, the power supply line connection portion in the third layer is better accommodated, and the memory cell area can be reduced in the bit line extending direction. Further, the word lines 133 and 134 can be made thicker while maintaining the memory cell area. When the word lines 133 and 134 are thickened, the electrical resistance of the word lines 133 and 134 can be reduced and the word lines are difficult to break.

  The case where the word line is bent will be described in more detail in comparison with the third embodiment.

  In the example shown in FIGS. 5 and 6 according to the third embodiment, the word lines 133 and 134 and the wirings provided in parallel with the word lines 133 and 134 in the third layer (135 in FIG. 5 and the power line connecting portion in FIG. 6). 300, 301) corresponds to three lines per memory cell (hereinafter, one line is expressed in units of one grid. Three lines correspond to three grids). 5 and 6, the range of one memory cell is a rectangular range indicated by a broken line. However, there are cases where it is desired to lay out with less than 3 grids, that is, with a narrower vertical width. For example, the rule between the gate and the contact is greatly reduced, while the wiring rule of the third layer is set to a loose rule. Alternatively, when the noise margin is good, it is no longer necessary to increase the gate length of the access transistor in order to ensure the β ratio (drive transistor drive capability / access transistor drive capability). The drive capability of the drive transistor / the drive capability of the access transistor can be approximated by (Wg of the drive transistor / Lg of the drive transistor) / (Wg of the access transistor / Lg of the access transistor). The “/” shown here means division.

  In FIG. 46, the load transistor and the gate wiring are connected by the first layer metal wiring via the contact hole. However, when the shared contact formation technique as shown in FIG. Will be reduced in the direction. That is, if the shared contact hole 145, which is a slightly larger contact hole in the vertical direction as shown in FIG. 16, is used, there is no need to form separate contact holes as shown in FIG. Will be. The wiring layout of the first layer wiring is also reduced in the vertical direction as shown in FIG. In such a case, the layout of the second layer wiring and the layout of the third layer wiring mainly used for the word line become difficult. In order to reduce the vertical wiring layout in the second layer, a form similar to the second embodiment described later can be used (see FIG. 18).

  With regard to the third layer wiring, how to lay out the word lines and how to lay out the power supply line connection portion for the VSS line are the points for reducing the vertical width. In terms of processing technology, it is possible to lay out word lines with the minimum wiring width and minimum wiring interval. However, in order to reduce the wiring resistance and parasitic capacitance of the word lines, or to improve the word line processing ease. In some cases, the wiring width is increased or the wiring interval is increased in order to improve the yield.

  In such a case, as shown in FIGS. 13, 14, and 15, the VSS line 138 is arranged in the fourth layer, the VSS line connecting portion 137 is arranged in the third layer, and the word line 1331 is arranged in the third layer. , 1341 are bent halfway. This improves the fit of the power supply line connection portion 137 for the VSS line. Accordingly, the layout can be performed in a state where the vertical length of the memory cell is 2.5 grids, and the vertical length of the memory cell can be reduced. When the word lines 1331 and 1341 are bent at 90 degrees as shown in FIG. 12, there is a case where the finished width of the wiring at the bent portion becomes very thick, so as shown in FIG. Etc., and can be laid out with gentle bending.

(Fifth embodiment)
A fifth embodiment will be described.

  The present embodiment mainly relates to the hierarchical word line technology.

  A normal memory array (having a non-hierarchical word line structure) illustrated in FIG. 19 is configured in a predetermined bit unit (16 bit unit in the example shown in FIG. 20) as shown in FIG. Yes. This group constitutes one block. The grid within the block represents a memory cell. The number in the lattice is the number of the word line to which the memory cell is connected.

  However, in order to satisfy needs such as higher speed and lower power consumption, a hierarchical word line structure as shown in the conceptual diagram of FIG. 21 may be taken. In the memory array at that time, as shown in FIG. 22, each memory cell is generally connected to a local word line, and a plurality of local word lines are generally connected to a global word line.

  The number of global word lines in the hierarchical word line structure is equal to the number of 1 / local word lines relative to the number of word lines in the non-hierarchical word line structure. Therefore, a memory having a hierarchical word line structure has a shorter word line activation time than a memory having a non-hierarchical word line structure. In the non-hierarchical word line structure, when a certain memory cell is read (read), the memory cells in the entire row direction are in the read state. On the other hand, in the hierarchical word line structure, only the desired local word line can be set in the Read state, so that power consumption can be reduced. However, since a circuit for controlling each local word line is required, there is a concern that the area of the memory increases accordingly. 23 and 24 show the fourth layer wiring layout when the number of global word lines per memory cell is two and one, respectively. FIGS. 25 and 26 respectively show the wiring layout of the third layer and below when the number of global word lines per memory cell is two.

  When such a hierarchical word line structure is adopted, as shown in FIGS. 23 and 24, the VSS line 303 and the global word lines (the write global word line 301 and the read global word line 302) are arranged in the fourth layer. The VSS line 303 is shared with the memory cells adjacent in the column direction. Global word lines 301 and 302 are not connected to individual memory cells. Therefore, the global word lines 301 and 302 need only be connected to the logic circuit unit that controls the global word line. Therefore, it is reasonable to place the global word lines 301 and 302 in the fourth layer. The effect of sharing the VSS line 303 with the adjacent memory cell is as described above.

(Sixth embodiment)
A sixth embodiment will be described.

  This embodiment mainly targets other than the 2-port memory cell, and relates to the 3-port memory cell and the 1-port memory cell.

  The first to fifth embodiments have been described by taking a two-port memory cell as an example. On the other hand, the sixth embodiment is directed to a memory cell having more ports, represented mainly by 3 ports. For example, in the circuit diagram shown in FIG. 27, the Read port side has a multi-port configuration, and has a 3-port configuration as a whole. In this case, the use of a horizontal cell layout facilitates handling. That is, as shown in FIG. 28, the Read port can be added by extending the gate electrode 1030 corresponding to the latch internal node 103 in FIG. 27 in the lateral direction.

  However, in the three-port configuration, it is necessary to arrange three word lines in the cell vertical length that is the same as in the case of two ports. In such a case, by bending the word line, a wiring layout that suppresses an increase in the length in the cell vertical direction is possible (see FIGS. 29, 30, and 31). 29, 30, and 31 respectively show the first wiring layer layout, the second wiring layer layout, and the third wiring when the three word lines (the writing word line 1501 and the reading word lines 1331 and 1341) are bent. It is a figure which shows a layer layout.

  As shown in the circuit diagram of FIG. 32, the same is true for the three-port configuration when the write port side is multi-ported. That is, as shown in FIG. 33, if the diffusion layer branch wiring from the drive transistor is performed, the base of the first layer can be laid out with almost no increase in the vertical length of the memory cell. Further, by bending the word line, a layout in which the vertical length of the memory cell is suppressed is possible. 34, 35, and 36 respectively show the first wiring layer layout, the second wiring layer layout, and the third wiring when the three word lines (the reading word line 1511 and the writing word line 1332 and 1342) are bent. It is a figure which shows a layer layout.

  Here, in the example shown in FIGS. 30 and 35, it will be described that the second embodiment is used.

  As shown in FIG. 30, on the left side when viewed from the center of the cell, the read word line connection portion 151 and the VSS line connection portion 131 are located on the same column in the second layer. On the right side when viewed from the cell center, the write word line connection unit 130 and the VSS line connection unit 132 are located on the same column in the second layer. This makes it possible to arrange the read word line connection unit 128 on the upper side as compared with the case where the VSS line connection unit 132 is in a point-symmetrical position with respect to the left side of the cell. Thereby, as shown in FIG. 36, a plurality of word lines can be laid out relatively easily. The same applies when the write side of FIGS. 33 to 36 is a multi-port.

  As shown in the circuit diagram of FIG. 37, the transistor structure is a two-port type memory cell, and the bit line has two systems for writing and reading, but the word line for reading and writing is used. There is also a single Port memory cell shared by one. This memory cell includes transistors 107, 108, 109, 111, and 112, and includes a latch internal node 103 in the latch portion. Even in such a case, as shown in the layout example in FIG. 38, the VSS line is not arranged in the second layer, and the read word line connection unit 127 and the power supply line connection unit 131 are arranged in the bit line direction in the second layer. The write word line connection unit 130 and the power supply line connection unit 132 are arranged side by side in the bit line direction to reduce the lateral width of the memory cell, and the word line 1334 is bent in the third layer, so that the memory cell A layout that reduces the length in the vertical direction is possible. In this case, the first layer ground layout, the second layer wiring layout, and the third layer wiring layout are illustrated in FIGS. 39, 40, and 41, respectively. It is also possible to configure a 2-port memory cell using the wiring layouts of the first to third layers. The third layer wiring layout of the 2-port memory cell is illustrated in FIG. A circuit diagram is shown in FIG.

  The present invention relates to a multi-port SRAM (Static Random Access Memory) of a semiconductor integrated circuit. In particular, a transistor having a gate input to an internal latch node and a transistor having a gate input to a word line include a bit line and This is useful for a multi-port memory or the like having a read port configuration connected in series with the ground. The present invention can also be applied to a multiport memory having three or more ports, a 1-port memory having a configuration in which a read bit line and a write bit line are separated.

The figure which shows the wiring layout below the 2nd wiring layer of the semiconductor memory cell based on the 1st example of 1st Embodiment of this invention. The figure which shows the wiring layout below the 2nd wiring layer of the semiconductor memory cell based on the 2nd example of 1st Embodiment of this invention. The figure which shows the wiring layout below the 2nd wiring layer of the semiconductor memory cell based on the 1st example of 2nd Embodiment of this invention. The figure which shows the wiring layout below the 2nd wiring layer of the semiconductor memory cell based on the 2nd example of 2nd Embodiment of this invention. The figure which shows the wiring layout below the 3rd wiring layer of the semiconductor memory cell based on the 1st example of 3rd Embodiment of this invention. The figure which shows the wiring layout below the 4th wiring layer of the semiconductor memory cell based on the 2nd example of 3rd Embodiment of this invention. The figure which shows the wiring layout below the 4th wiring layer of the semiconductor memory cell based on the 3rd example of 3rd Embodiment of this invention. The figure which shows the wiring layout below the 4th wiring layer of the semiconductor memory cell based on the 4th example of 3rd Embodiment of this invention. The figure which shows the wiring layout below the 4th wiring layer of the semiconductor memory cell based on the 5th example of 3rd Embodiment of this invention. The figure which shows the TAP part insertion location in the memory array containing the semiconductor memory cell based on the 6th example of 3rd Embodiment of this invention. The figure which shows the semiconductor memory cell mesh power supply which concerns on the 7th example of 3rd Embodiment of this invention. The figure which shows the semiconductor memory cell mesh power supply which concerns on the 7th example of 3rd Embodiment of this invention. The figure which shows the wiring layout below the 3rd wiring layer of the semiconductor memory cell based on the 1st example of 4th Embodiment of this invention. The figure which shows the wiring layout below the 4th wiring layer of the semiconductor memory cell based on the 2nd example of 4th Embodiment of this invention. The figure which shows the wiring layout below the 4th wiring layer of the semiconductor memory cell based on the 1st example of 4th Embodiment of this invention. The figure which shows the base | substrate layout of the semiconductor memory cell which concerns on the 2nd example of 4th Embodiment of this invention. The figure which shows the wiring layout of the 1st wiring layer of the semiconductor memory cell which concerns on the 2nd example of 4th Embodiment of this invention. The figure which shows the wiring layout below the 2nd wiring layer of the semiconductor memory cell which concerns on the 3rd example of 4th Embodiment of this invention. The figure which shows the structure of the memory cell array in 3rd Embodiment of this invention. The figure which shows the non-hierarchical word line structure compared with the hierarchical word line structure in 3rd Embodiment of this invention. Image diagram of hierarchical control in hierarchical word line structure in third embodiment of the present invention The figure which shows the hierarchical word line structure in 3rd Embodiment of this invention. The figure which shows the wiring layout of the 4th wiring layer of the semiconductor memory cell which concerns on 3rd Embodiment of this invention (when passing two global word lines per cell) The figure which shows the wiring layout of the 4th wiring layer of the semiconductor memory cell which concerns on 3rd Embodiment of this invention (when passing one global word line per cell) The figure which shows the wiring layout below the 3rd wiring layer of the semiconductor memory cell based on 3rd Embodiment of this invention (when passing two global word lines per cell) The figure which shows the wiring layout below the 3rd wiring layer of the semiconductor memory cell concerning 3rd Embodiment of this invention (when passing one global word line per cell) FIG. 10 is a circuit diagram showing an example of a semiconductor memory cell according to a first example of the fourth embodiment of the present invention, and shows an example in which the read port side is configured as a multi-port configuration and configured as a three-port configuration as a whole. The figure which shows the base | substrate layout of the semiconductor memory cell which concerns on the 1st example of 4th Embodiment of this invention. The figure which shows the wiring layout of the 1st wiring layer of the semiconductor memory cell which concerns on the 1st example of 4th Embodiment of this invention. The figure which shows the wiring layout below the 2nd wiring layer of the semiconductor memory cell based on the 1st example of 4th Embodiment of this invention. The figure which shows the wiring layout below the 3rd wiring layer of the semiconductor memory cell based on the 1st example of 4th Embodiment of this invention. FIG. 10 is a circuit diagram showing a semiconductor memory cell according to a second example of the fourth embodiment of the present invention, and shows an example in which the write side is multi-ported and has a three-port configuration as a whole. The figure which shows the base | substrate layout of the semiconductor memory cell which concerns on the 2nd example of 4th Embodiment of this invention. The figure which shows the wiring layout of the 1st wiring layer of the semiconductor memory cell which concerns on the 2nd example of 4th Embodiment of this invention. The figure which shows the wiring layout below the 2nd wiring layer of the semiconductor memory cell based on the 2nd example of 4th Embodiment of this invention. The figure which shows the wiring layout below the 3rd wiring layer of the semiconductor memory cell based on the 2nd example of 4th Embodiment of this invention. Circuit diagram showing a semiconductor memory cell according to a third example of the fourth embodiment of the present invention (8-transistor type whose Read port is single-read) The figure which shows the wiring layout below the 3rd wiring layer of the semiconductor memory cell which concerns on the 3rd example of 4th Embodiment of this invention. The figure which shows the base | substrate layout of the semiconductor memory cell which concerns on the 3rd example of 4th Embodiment of this invention. The figure which shows the layout of the 1st wiring layer of the semiconductor memory cell which concerns on the 3rd example of 4th Embodiment of this invention. The figure which shows the wiring layout below the 2nd wiring layer of the semiconductor memory cell which concerns on the 3rd example of 4th Embodiment of this invention. The figure which shows the wiring layout below the 3rd wiring layer of the semiconductor memory cell based on the 3rd example of 4th Embodiment of this invention. FIG. 9 is a circuit diagram showing a semiconductor memory cell according to a fourth example of the fourth embodiment of the present invention (8-transistor type whose Read port is single-read); Circuit diagram showing a conventional 1-port memory cell Circuit diagram showing an example of a conventional 2-port memory cell (8-transistor type) The figure which shows the layout of the base layer in the conventional 2 port memory cell (refer FIG. 45) The figure which shows the wiring layout of the 1st wiring layer in the conventional 2 port memory cell (refer FIG. 45). The figure which shows the wiring layout below the 2nd wiring layer in the conventional 2 port memory cell (refer FIG. 45). The figure which shows the wiring layout of the 3rd wiring layer in the conventional 2 port memory cell (refer FIG. 45). Circuit diagram showing an example of a conventional 2-port memory cell (10-transistor type) Circuit diagram showing an example of a conventional 2-port memory cell (8-transistor type with a Read port for single readout) The figure which shows the layout of the base layer in the conventional 2 port memory cell (refer FIG. 52) The figure which shows the wiring layout of the 1st wiring layer in the conventional 2 port memory cell (refer FIG. 50). The figure which shows the wiring layout below the 2nd wiring layer in the conventional 2 port memory cell (refer FIG. 50). The figure which shows the wiring layout below the 3rd wiring layer in the conventional 2 port memory cell (refer FIG. 50).

Explanation of symbols

100 Word line 101 Positive phase bit line 102 Reverse phase bit line 103 Latch internal node 107 Access transistor 108 Drive transistor 109 Load transistor 110 Access transistors 111 and 113 added for 2 ports Read port which receives the potential of the latch internal node at the gate Transistors 112 and 114 Read port access transistor 120 connected in series with the transistor receiving the potential of the latch internal node at the gate 120 Positive phase read bit line 121 Positive phase write bit line 122 and 124 VSS line 123 VDD line 125 Reverse phase Write bit line 126 Reverse phase read bit lines 127, 128 Read word line connection (second layer)
129, 130 Write word line connection (second layer)
131, 132 VSS line connection (second layer)
133 Read word line (third layer)
134 Word line for writing (third layer)
135 VSS line (third layer) extending in the word line extension direction
136 VSS line (fourth layer) extending in the word line extending direction
137 Word line connection (third layer)
138 VSS line (fourth layer) extending in the bit line extension direction
139 Mesh-shaped VSS line (4th layer)
140 Normal Memory Cell 141 TAP Cell 145 Shared Contact Hole 150 Read Port Word Lines 151 and 152 Read Port Word Line Connection Portion (Second Layer)
153 Write port word line 154, 155 Write port word line connection (second layer)

Claims (13)

A semiconductor memory cell comprising at least three layers and storing data statically,
A first layer formed with a latch portion as a storage area;
A second layer formed with bit lines;
A third layer on which word lines are formed,
By providing power supply lines in the third and higher layers, an arrangement space is provided in the second layer, and a section-like word line connection portion for electrically connecting the word line and the latch portion to the arrangement space is provided. Arranged semiconductor memory cell.   By providing the power supply line in the third layer, an arrangement space is provided in the second layer, and a section-like power supply line connection part for electrically connecting the power supply line and the latch part is provided in the arrangement space. The semiconductor memory cell according to claim 1.   By providing the power supply line in the fourth layer, an arrangement space is provided in the second layer, and a section-like power supply line that electrically connects the power supply line and the latch portion to the arrangement space and the third layer. 2. The semiconductor memory cell according to claim 1, further comprising a connecting portion.   4. The semiconductor according to claim 2, wherein an arrangement space for the word line connection portion and an arrangement space for the power supply line connection portion in the second layer are provided on the same straight line parallel to the bit line. Memory cell.   2. The semiconductor memory cell according to claim 1, wherein the power supply line is a VSS line. As the word line, a write word line and a read word line are provided,
As the word line connection unit, a write word line connection unit and a read word line connection unit are provided,
As the power supply line connection part, a first power supply line connection part and a second power supply line connection part are provided corresponding to the output and the inverted output of the latch part, respectively.
The read word line connecting portion and either the first power line connecting portion or the second power line connecting portion are provided in the same wiring layer and parallel to the bit line Located on the same straight line,
The write word line connection portion and the other one of the first power supply line connection portion and the second power supply line connection portion are provided in the same wiring layer and parallel to the bit line. 2. The semiconductor memory cell according to claim 1, wherein the semiconductor memory cell is located on a line.   2. The semiconductor memory cell according to claim 1, wherein the power line connecting portion is shared with other adjacent memory cells.   2. The semiconductor memory cell according to claim 1, wherein the power supply line is shared with other adjacent memory cells.   2. The semiconductor memory cell according to claim 1, wherein the power supply line is wired in the extending direction of the bit line or in a mesh shape.   By bending the word line, an arrangement space is provided in the third layer, and the section-like power line connection portion that electrically connects the power line and the latch portion is arranged in the arrangement space. A semiconductor memory cell according to claim 3. A semiconductor memory cell having at least four layers and storing data statically,
A first layer formed with a latch portion as a storage area;
A second layer formed with bit lines;
A third layer in which local word lines are formed;
A fourth layer formed with global word lines that form hierarchical word lines in cooperation with the local word lines;
By providing a power supply line in the fourth layer or higher, an arrangement space is provided in the second layer, and a section-like local word line connection for electrically connecting the local word line and the latch unit to the arrangement space. Semiconductor memory cell provided with a portion. The latch part is a multi-port type latch part,
The bit lines include a write bit line and a read bit line,
The word line includes a write word line and a read word line,
The word line connection unit includes a write word line connection unit and a read word line connection unit,
The write word line is connected to the write word line connection unit,
The semiconductor memory cell according to claim 1, wherein the read word line is connected to the read word line connection unit. The latch part is a multi-port type latch part,
The bit line includes a write bit line and a read bit line,
The word line connection unit includes a write word line connection unit and a read word line connection unit,
The write word line connection unit and the read word line connection unit are both connected to one word line, and the word line controls both a write operation and a read operation. 12. A semiconductor memory cell according to 1 or 11.

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