JP4648940B2 - Method for manufacturing variable resistance element - Google Patents

Description

  The present invention comprises one electrode, the other electrode, and a variable resistor, wherein the variable resistor exists in a region sandwiched between the one electrode and the other electrode, and a voltage pulse is applied between the two electrodes. The present invention relates to a method for manufacturing a variable resistance element that changes its electrical resistance when applied.

  In recent years, various devices such as next-generation non-volatile random access memory (NVRAM: Nonvolatile Random Access Memory) capable of operating at high speed instead of flash memory include FeRAM (Ferroelectric RAM), MRAM (Magnetic RAM), and PRAM (Phase Change RAM). A structure has been proposed, and intense development competition has been conducted from the viewpoint of high performance, high reliability, low cost, and process consistency. However, each of these current memory devices has advantages and disadvantages, and it is still far from the ideal realization of a “universal memory” having the advantages of SRAM, DRAM, and flash memory.

  For these existing technologies, a resistive non-volatile memory RRAM (Resistive Random Access Memory) (registered trademark) using a variable resistive element whose electric resistance reversibly changes by applying a voltage pulse has been proposed. This configuration is shown in FIG.

  As shown in FIG. 26, the variable resistance element of the conventional configuration has a structure in which a lower electrode 103, a variable resistor 102, and an upper electrode 101 are sequentially stacked, and a voltage is applied between the upper electrode 101 and the lower electrode 103. By applying a pulse, the resistance value can be reversibly changed. A novel nonvolatile semiconductor memory device can be realized by reading a resistance value that changes by this reversible resistance change operation (hereinafter referred to as “switching operation”).

  In this nonvolatile semiconductor memory device, a plurality of memory cells including variable resistance elements are arranged in a matrix in the row direction and the column direction to form a memory cell array, and data is written to each memory cell in the memory cell array. Peripheral circuits for controlling erase and read operations are arranged. As the memory cell, a memory cell is composed of one selection transistor T and one variable resistance element R (referred to as “1T / 1R type”) because of the difference in its constituent elements. There are cells, memory cells composed of only one variable resistance element R (referred to as “1R type”), and the like. Of these, FIG. 27 shows a configuration example of a 1T / 1R type memory cell.

  FIG. 27 is an equivalent circuit diagram showing a configuration example of a memory cell array including 1T / 1R type memory cells. The gate of the selection transistor T of each memory cell is connected to the word lines (WL1 to WLn), and the source of the selection transistor T of each memory cell is connected to the source lines (SL1 to SLn) (n is a natural number). . One electrode of the variable resistance element R for each memory cell is connected to the drain of the selection transistor T, and the other electrode of the variable resistance element R is connected to the bit lines (BL1 to BLm) (m Is a natural number). The word lines WL1 to WLn are connected to the word line decoder 106, the source lines SL1 to SLn are connected to the source line decoder 107, and the bit lines BL1 to BLm are connected to the bit line decoder 105, respectively. Yes. A specific bit line, word line, and source line for write, erase, and read operations to a specific memory cell in the memory cell array 104 are selected according to an address input (not shown).

  FIG. 28 is a schematic cross-sectional view of one memory cell constituting the memory cell array 104 in FIG. In this configuration, the select transistor T and the variable resistance element R form one memory cell. The selection transistor T includes a gate insulating film 113, a gate electrode 114, a drain diffusion layer region 115, and a source diffusion layer region 116, and is formed on the upper surface of the semiconductor substrate 111 on which the element isolation region 112 is formed. The variable resistance element R includes a lower electrode 118, a variable resistor 119, and an upper electrode 120.

  Further, the gate electrode 114 of the transistor T forms a word line, and the source line wiring 124 is electrically connected to the source diffusion layer region 116 of the transistor T through the contact plug 122. The bit line wiring 123 is electrically connected to the upper electrode 120 of the variable resistance element R through the contact plug 121, while the lower electrode 118 of the variable resistance element R is connected to the transistor T through the contact plug 117. The drain diffusion layer region 115 is electrically connected.

  As described above, the selection transistor T and the variable resistance element R are arranged in series, so that the transistor of the memory cell selected by the change in the potential of the word line is turned on, and the memory selected by the change in the potential of the bit line. The cell can be selectively written or erased only to the variable resistance element R of the cell.

  FIG. 29 is an equivalent circuit diagram illustrating a configuration example of a 1R type memory cell. Each memory cell includes only the variable resistance element R, and one electrode of the variable resistance element R is connected to the word lines (WL1 to WLn), and the other electrode is connected to the bit lines (BL1 to BLm). . Each word line WL1 to WLn is connected to a word line decoder 133, and each bit line BL1 to BLm is connected to a bit line decoder 132. A specific bit line and word line for writing, erasing and reading operations to specific memory cells in the memory cell array 131 are selected in accordance with an address input (not shown).

  FIG. 30 is a schematic perspective view showing an example of a memory cell constituting the memory cell array 131 in FIG. As shown in FIG. 30, the upper electrode wiring 143 and the lower electrode wiring 141 are arranged so as to cross each other, one of which forms a bit line and the other forms a word line. In addition, the variable resistor 142 is arranged at the intersection (usually referred to as “cross point”) of each electrode. In the example of FIG. 30, for convenience, the upper electrode 143 and the variable resistor 142 are processed into the same shape, but the portions that contribute electrically to the switching operation of the variable resistor 142 are the upper electrode 143 and the lower electrode 141. It becomes the area of crossing points.

Note that the variable resistor material used for the variable resistor 119 in FIG. 28 or the variable resistor 142 in FIG. 30 is known by the giant magnetoresistive effect by Shanqing Liu, Alex Ignatiev, etc. of the University of Houston, USA. The following Patent Document 1 and Non-Patent Document 1 disclose a method for reversibly changing the electric resistance by applying a voltage pulse to the perovskite material. Although this method uses a perovskite material known for its giant magnetoresistive effect, this method is extremely epoch-making in that a resistance change of several orders of magnitude appears even at room temperature without applying a magnetic field. In the element structure exemplified in Patent Document 1, a crystalline praseodymium / calcium / manganese oxide Pr _1-x Ca _x MnO ₃ (PCMO) film which is a perovskite oxide is used as a variable resistor material. Yes.

Other variable resistor materials include oxides of transition metal elements such as titanium oxide (TiO ₂ ) films, nickel oxide (NiO) films, zinc oxide (ZnO) films, and niobium oxide (Nb ₂ O ₅ ) films. It is known from Non-Patent Document 2 and Patent Document 2 that reversible resistance change is exhibited. Among these, the phenomenon of the switching operation using NiO is reported in detail in Non-Patent Document 3.

US Pat. No. 6,204,139 JP 2002-537627 A Liu, S .; Q. In addition, “Electric-pulse-induced reversible resistance change effectin magnetosensitive films”, Applied Physics Letter, Vol. 76, pp. 2749-2751, 2000 H. Pagna, et al., “Bistable Switching in Electroformed Metal-Insulator-Metal Devices”, Phys. Stat. Sol. (A), vol. 108, pp. 11-65, 1988 Baek, I. et al. G. In addition, “Highly Scalable Non-volatile Resistive Memory Using Simple Binary Oxide Driven Asymmetric Universal Voltage Pulses”, IEDM 04, p. 587-590, 2004

  According to each of the above conventional techniques, the variable resistance element R is formed by laminating the lower electrode, the variable resistor, and the upper electrode in this order on the substrate. Therefore, in order to achieve a stable switching variable resistance element with good reproducibility, the contact resistance between the lower electrode and the variable resistor and the contact resistance between the variable resistor and the upper electrode are between the memory cells in the same wafer. Or it is essential that it is stable between wafers.

  However, in the conventional method, the surfaces of the electrode and the variable resistor are exposed to a gas / chemical solution or the like used in the machining process, and thus cannot always be said to have a clean surface. In addition, there is a problem that the contact resistance is not stable due to the influence of natural oxidation after the lower electrode and the variable resistor are formed and the influence of the film forming process atmosphere of the film deposited on the upper layer.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a variable resistance element that can achieve a stable switching operation with good reproducibility.

  In order to achieve the above object, a variable resistance element manufacturing method according to the present invention includes a first electrode, a second electrode, and a variable resistor, and the variable resistor is connected to the first electrode and the second electrode. A variable resistor that exists in a sandwiched region and changes the electrical resistance between the first electrode and the second electrode by applying a voltage pulse between the first electrode and the second electrode. A method of manufacturing an element, wherein after depositing one conductive film as a precursor of the first electrode, the second electrode, and the variable resistor, a part of the conductive film is changed to the variable resistor. The first feature is that the remaining portion of the conductive film divided by the variable resistor is the first electrode and the second electrode.

  According to the first feature of the method of manufacturing a variable resistance element according to the present invention, the first and second electrodes and the variable resistor constituting the variable resistance element are originally made of the same conductive film, A part of the conductive film is changed to a variable resistor, and the first and second electrodes are formed by dividing the conductive film by the variable resistor. Therefore, unlike the conventional manufacturing method in which one electrode is formed by depositing a conductive film after forming the variable resistor, the interface between the variable resistor and the electrode (both first and second electrodes) is formed in a film-forming atmosphere or air. Is not exposed to. For this reason, the contact resistance does not vary due to the adhesion of particles or the like to the interface, and the contact resistance can be stabilized between the memory cells in the same wafer and between different wafers. Therefore, the voltage applied to both ends of the variable resistor can be made uniform, and a variable resistor element having a stable switching operation can be formed with good reproducibility.

  The variable resistance element manufacturing method according to the present invention includes, in addition to the first feature, a conductive film deposition step of depositing the conductive film on a semiconductor substrate, and an oxidation treatment for the conductive film. And forming the variable resistor in a partial region of the conductive film and dividing the conductive film by the variable resistor to form the first electrode and the second electrode, and the oxidation step A second feature is that it includes a protective insulating film deposition step of depositing a protective interlayer insulating film on the entire surface after the process is completed.

  According to the second feature of the method of manufacturing a variable resistance element according to the present invention, the variable resistor and the first are formed from one conductive film without exposing the interface between the variable resistor and both electrodes to the atmosphere or the atmosphere. And a second electrode can be formed.

  In addition to the second feature, the variable resistance element manufacturing method according to the present invention includes the first interlayer so as to include the upper surface of the conductive film after the conductive film deposition process and before the oxidation process. A first insulating film depositing step for depositing an insulating film, and an opening formation for opening a part of the first interlayer insulating film and exposing a part of the upper surface of the conductive film after completion of the first insulating film depositing process; A third feature is that a peripheral region of the conductive film exposed through the opening is oxidized by the oxidation step.

  According to the third feature of the method for manufacturing a variable resistance element according to the present invention, the oxidation progresses from the conductive film exposed through the opening and changes into a variable resistor, so that The integrated conductive film can be changed to a configuration having first and second electrodes on both sides of a variable resistor formed around the opening, whereby the variable resistor and both electrodes can be changed. Thus, the variable resistance element can be manufactured without exposing the interface.

  In addition to the third feature, the variable resistance element manufacturing method according to the present invention includes the conductive material exposed through the opening after the opening forming process and before the oxidation process. A fourth feature is that it includes a thinning step of reducing the thickness of the conductive film located on the bottom surface of the opening by removing a part of the exposed portion of the film.

  According to the fourth feature of the variable resistance element manufacturing method according to the present invention, since the film thickness of the bottom surface of the opening is thinned, the bottom surface of the opening that has been thinned by the oxidation step is formed. Oxidation treatment over the entire thickness of the formed conductive film can be easily performed. As a result, the conductive film is divided by the variable resistor formed through the oxidation treatment, and as a result, the variable resistor having the variable resistor sandwiched between the first and second electrodes is changed to the variable resistor. It can be easily manufactured without exposing the interface between the body and both electrodes.

  In addition to the second feature, the variable resistance element manufacturing method according to the present invention includes a first insulating film deposition step of depositing a first interlayer insulating film on the semiconductor substrate before the conductive film deposition step. And an opening forming step for opening a predetermined region of the first interlayer insulating film to form at least two separated openings, and after the conductive film deposition step is completed and before the oxidation step is started. A thinning step of reducing the thickness of the conductive film deposited within a range where the conductive film deposited in a region other than the opening is not completely removed, and the conductive film deposition step includes Depositing the conductive film so as to completely fill two openings, wherein the oxidation step is greater than or equal to the film thickness of the conductive film deposited in a region other than the openings, Of the conductive film deposited from the opening to the bottom of the opening. A fifth characteristic in that the thickness of the just less than the thickness by oxidizing the conductive film is a step of forming the variable resistor.

  According to the fifth feature of the variable resistance element manufacturing method of the present invention, the film thickness of the conductive film formed in the upper layer of the bottom surface of the opening is the same as that of the conductive film deposited in the region other than the opening. Since it is configured to be thicker than the film thickness, the conductive film is oxidized from the exposed surface by an oxidation process, so that the opening of the conductive film deposited in the region other than the opening is completely oxidized. An unoxidized conductive film corresponding to the depth of the opening remains in the portion. That is, the conductive film deposited in the region other than the opening is completely oxidized, and an oxidation process is performed under the condition that the unoxidized conductive film remains in the opening. Can be divided into two conductive films (electrodes) remaining in each opening and a variable resistor. Thereby, a variable resistance element can be manufactured without exposing the interface of a variable resistor and each electrode to atmosphere or air | atmosphere.

  In addition to the second feature described above, the variable resistance element manufacturing method according to the present invention may include a local thin film region in which the conductive film deposited in the conductive film deposition step is partially thinner than others. A sixth feature is that a predetermined pre-conductive film deposition pretreatment is performed on the underlying layer of the conductive film in advance before the conductive film deposition step so as to obtain a deposited shape.

  According to the sixth aspect of the variable resistance element manufacturing method of the present invention, since the conductive film deposition step is performed after the conductive film deposition pretreatment, a part of the conductive film deposited after the conductive film deposition step is performed. In addition, a local thin film region having a thinner film thickness is formed. Accordingly, in the oxidation process, the film thickness of the local thin film region is oxidized with respect to the local thin film region and changed into a variable resistor, so that one conductive film deposited by the conductive film deposition step can be changed. The resistor can be divided into two conductive regions (electrodes). Thereby, a variable resistance element can be manufactured without exposing the interface of a variable resistor and each electrode to atmosphere or air | atmosphere.

  In addition to the sixth feature, the variable resistance element manufacturing method according to the present invention includes a first insulating film deposition step in which the conductive film deposition pretreatment includes depositing a first interlayer insulating film on a semiconductor substrate. An opening forming step of forming a tapered opening in which the opening area becomes narrower toward a predetermined region of the first interlayer insulating film, and the conductive film deposition step includes an inside of the opening. And depositing the conductive film on the entire surface so as not to completely fill, and forming the local thin film region on at least a part of the inner side wall of the opening, wherein the oxidation step exposes the conductive film The variable resistor is formed by oxidizing from the side, and at least the local thin film region is oxidized, and is formed on the bottom surface side of the opening by the local thin film region that is oxidized and changed into the variable resistor. The conductive film The divided and the conductive film from a local thin film region is formed in the upper region, and seventh feature that the step of forming the first electrode and the second electrode.

  According to the seventh feature of the variable resistance element manufacturing method of the present invention, since the opening is processed into a tapered shape before the conductive film is deposited, the conductive film deposited in the conductive film deposition step is the opening. A local thin film region is formed in the inclined portion of the inner side wall of the. Accordingly, in the oxidation process, the film thickness of the local thin film region is oxidized with respect to the local thin film region and changed into a variable resistor, so that one conductive film deposited by the conductive film deposition step can be changed. The resistor can be divided into two conductive regions (electrodes). Thereby, a variable resistance element can be manufactured without exposing the interface of a variable resistor and each electrode to atmosphere or air | atmosphere.

  In addition to the sixth feature, the variable resistance element manufacturing method according to the present invention includes a first insulating film deposition step in which the conductive film deposition pretreatment includes depositing a first interlayer insulating film on a semiconductor substrate. An opening forming step for forming an opening in a predetermined region of the first interlayer insulating film, and a sidewall insulating film forming step for forming a sidewall insulating film that becomes wider as it goes downward in the side wall surface of the opening. And the conductive film deposition step deposits a conductive film on the entire surface so as not to completely fill the inside of the opening, and the local thin film is formed on at least a part of the outer side wall of the sidewall insulating film. A step of forming a region, wherein the oxidation step oxidizes the conductive film from the exposed surface side to form the variable resistor and at least oxidizes the local thin film region to oxidize the variable film. Turn into a resistor The local thin film region separates the conductive film formed on the bottom surface side of the opening from the conductive film formed in the region above the local thin film region, and the first electrode and the second An eighth feature is that it is a step of forming an electrode.

  According to the eighth feature of the method of manufacturing a variable resistance element according to the present invention, the sidewall insulating film becomes wider in the side wall surface of the opening before being deposited on the conductive film, and becomes wider as it goes down into the side wall surface of the opening. Therefore, the conductive film deposited in the conductive film deposition step forms a local thin film region in the inclined portion of the outer side wall of the sidewall insulating film. Accordingly, in the oxidation process, the film thickness of the local thin film region is oxidized with respect to the local thin film region and changed into a variable resistor, so that one conductive film deposited by the conductive film deposition step can be changed. The resistor can be divided into two conductive regions (electrodes). Thereby, a variable resistance element can be manufactured without exposing the interface of a variable resistor and each electrode to atmosphere or air | atmosphere.

  In addition to the sixth feature described above, the method for manufacturing a variable resistance element according to the present invention includes the step of pre-depositing the conductive film, wherein the conductive film deposition pretreatment includes a part of stepped regions having different height positions of adjacent upper surfaces. A first insulating film deposition step of depositing an interlayer insulating film on the semiconductor substrate, wherein the conductive film deposition step deposits the conductive film on the entire surface including the stepped portion region, thereby forming the stepped portion region A step of forming the conductive film having the local thin film region having a shape in which the film thickness becomes thinner as approaching a corner portion where the upper step surface and the lower step surface are configured and a corner portion where the lower step surface intersects, and the oxidation step The conductive film is oxidized from the exposed surface side to form the variable resistor, and at least the local thin film region is oxidized to be oxidized and changed to the variable resistor by the local thin film region. Deposited on the surface The conductive film and divided and the conductive film is deposited on the lower surface, and ninth feature of said a first electrode and forming a second electrode are.

  According to the ninth feature of the variable resistance element manufacturing method of the present invention, the first interlayer insulating film having a part of the stepped portion where the height positions of the adjacent upper surfaces are different before the conductive film is deposited is formed. Therefore, the conductive film deposited in the conductive film deposition step is formed in the step portion region of the first interlayer insulating film between the side wall portion connecting the upper step surface and the lower step surface constituting the step portion region and the lower step surface. The local thin film region is formed in such a shape that the film thickness becomes thinner as approaching the intersecting corner. Accordingly, in the oxidation process, the film thickness of the local thin film region is oxidized with respect to the local thin film region and changed into a variable resistor, so that one conductive film deposited by the conductive film deposition step can be changed. The resistor can be divided into two conductive regions (electrodes). Thereby, a variable resistance element can be manufactured without exposing the interface of a variable resistor and each electrode to atmosphere or air | atmosphere.

  At this time, the step portion can be provided on the first interlayer insulating film by depositing the first interlayer insulating film on the base layer on which the step portion region is previously formed. In this case, it is preferable to perform the first insulating film deposition step by using a plasma CVD method with poor step coverage. Thereby, in the stepped region, it becomes easier to form the first interlayer insulating film having a shape protruding outward as it goes from the lower section to the upper stepped surface.

  In addition to the sixth feature, the variable resistance element manufacturing method according to the present invention deposits the first interlayer insulating film so that the conductive film deposition pretreatment increases the film density toward the upper layer. Forming a stepped region having different height positions on adjacent upper surfaces by peeling off the first interlayer insulating film other than the predetermined region, and forming an upper step constituting the stepped region A patterning step in which a side wall portion connecting the surface and the lower step surface is formed in a reverse taper shape projecting outward as it goes in the upper layer direction, and the conductive film deposition step covers the entire surface including the step portion region. Depositing a film is a step of forming the conductive film having a wedge-shaped local thin film region whose thickness decreases as it approaches the corner portion where the side wall portion and the lower surface intersect, and the oxidation step includes From the exposed surface side of the conductive film The conductive film is deposited on the upper surface by the local thin film region that has been oxidized and changed into the variable resistor by forming at least the local thin film region by forming the variable resistor. And the conductive film deposited on the lower surface, and forming the first electrode and the second electrode, the tenth feature.

  According to the tenth feature of the method of manufacturing a variable resistance element according to the present invention, the first interlayer insulating film is formed so that the film density increases toward the upper layer before the conductive film is deposited, and the patterning step is performed. In this case, a stepped region having an inverted taper shape projecting outward as it goes in the upper layer direction is formed. Therefore, the conductive film deposited in the conductive film deposition step is the stepped portion in the stepped region of the first interlayer insulating film. The local thin film region is formed in such a shape that the film thickness becomes thinner as approaching a corner portion where the side wall portion connecting the upper and lower step surfaces constituting the region intersects the lower step surface. Accordingly, in the oxidation process, the film thickness of the local thin film region is oxidized with respect to the local thin film region and changed into a variable resistor, so that one conductive film deposited by the conductive film deposition step can be changed. The resistor can be divided into two conductive regions (electrodes). Thereby, a variable resistance element can be manufactured without exposing the interface of a variable resistor and each electrode to atmosphere or air | atmosphere.

  In addition to the tenth feature, the variable resistance element manufacturing method according to the present invention includes the first interlayer insulating film in which the first insulating film deposition step increases the substrate temperature continuously or intermittently. The eleventh feature is that the step of depositing is performed.

  According to the eleventh feature of the method for manufacturing a variable resistance element according to the present invention, in the first insulating film deposition step, the first interlayer insulating film whose film density increases toward the upper layer portion can be formed. .

  In addition to the tenth or eleventh feature, the variable resistance element manufacturing method according to the present invention has a twelfth feature that the patterning step is performed by wet etching.

  According to the twelfth feature of the variable resistance element manufacturing method of the present invention, the first interlayer insulating film is etched away toward the lower layer portion having a lower film density than the upper layer portion having a higher film density. Therefore, a stepped region having an inversely tapered shape that protrudes outward as it goes in the upper layer direction can be formed.

  In addition to the sixth feature, the variable resistance element manufacturing method according to the present invention includes a first insulating film deposition step in which the conductive film deposition pretreatment includes depositing a first interlayer insulating film on a semiconductor substrate. A second insulating film deposition step of depositing a second interlayer insulating film having an etching rate slower than that of the first interlayer insulating film on the upper surface of the first interlayer insulating film; and the first and second interlayer insulating films other than the predetermined region By forming the stepped region where the height positions of the adjacent upper surfaces are different, the side wall portion connecting the upper step surface and the lower step surface constituting the stepped portion region is formed by the second interlayer insulating film. A patterning step in which the configured region protrudes outward from the region configured by the first interlayer insulating film, and the conductive film deposition step includes the stepped region. By depositing the conductive film on the entire surface, A step of forming the conductive film having the wedge-shaped local thin film region whose thickness becomes thinner as approaching a corner portion where the wall portion and the lower surface intersect, wherein the oxidation step is performed by removing the conductive film from the exposed surface side. The variable resistor is formed by oxidation, and at least the local thin film region is oxidized to oxidize and change to the variable resistor, and the conductive film deposited on the upper surface and the lower surface A thirteenth feature is a step of separating the deposited conductive film to form the first electrode and the second electrode.

  According to the thirteenth feature of the variable resistance element manufacturing method according to the present invention, the first interlayer insulating film and the second interlayer insulating film having an etching rate slower than that of the first interlayer insulating film are deposited before the conductive film is deposited. In the patterning step, the first interlayer insulating film serving as the lower layer is etched away from the second interlayer insulating film serving as the upper layer, and as a result, the second interlayer insulating film serving as the upper layer protrudes outward. A stepped region having a shape is formed. Then, by depositing the conductive film after the formation of the stepped portion region, the lower layer portion (the first portion is compared with the film thickness deposited outside the upper layer portion (side wall of the second interlayer insulating film) of the stepped portion region. The conductive film can be formed so that the film thickness deposited on the outside (side wall of the interlayer insulating film) becomes thin, and as a result, the local thin film region can be formed on the outer side wall of the first interlayer insulating film. Accordingly, in the oxidation process, the film thickness of the local thin film region is oxidized with respect to the local thin film region and changed into a variable resistor, so that one conductive film deposited by the conductive film deposition step can be changed. The resistor can be divided into two conductive regions (electrodes). Thereby, a variable resistance element can be manufactured without exposing the interface of a variable resistor and each electrode to atmosphere or air | atmosphere.

In the variable resistance element manufacturing method according to the present invention, in addition to the thirteenth feature, the first insulating film deposition step is a step of depositing a SiO ₂ film, and the second insulating film deposition step is The SiN film is deposited, and the patterning step is performed by wet etching using an HF chemical solution according to a fourteenth feature.

According to the fourteenth feature of the variable resistance element manufacturing method of the present invention, since the SiN film has a slower wet etching rate by HF than the SiO ₂ film, the patterning step causes the lower resistance than the lower SiO ₂ film. In addition, a stepped region having an inverted staircase shape in which the upper SiN film protrudes outward can be formed.

  In addition to the feature of any one of the sixth to fourteenth aspects, the method for manufacturing a variable resistance element according to the present invention includes an antioxidant insulating film so as to cover the upper surface of the variable resistor after the oxidation step. An anti-oxidation insulating film deposition step for depositing, and after the anti-oxidation insulating film deposition step, a patterning step for performing a patterning process on the anti-oxidation insulating film, the variable resistor, and the conductive film. Is the fifteenth feature.

  According to the fifteenth feature of the variable resistance element manufacturing method according to the present invention, it is possible to prevent the influence of oxidation on the variable resistor due to the resist ashing process or the like when the patterning process is performed on the variable resistor. A variable resistance element can be manufactured without degrading the characteristics of the variable resistor.

  In addition to the fifteenth feature, the variable resistance element manufacturing method according to the present invention has a sixteenth feature in which the antioxidant insulating film is an insulating film containing nitrogen or carbon.

  According to the sixteenth feature of the method for manufacturing a variable resistance element according to the present invention, the influence of oxidation after patterning of the first and second electrodes and the variable resistor can be prevented, and the variable resistor A variable resistance element can be manufactured without deteriorating the characteristics of the body.

  Further, in the variable resistance element manufacturing method according to the present invention, in addition to any of the sixth to sixteenth features, the conductive film deposition step deposits the conductive film by a directional sputtering film forming method. The seventeenth feature is that it is a process.

  Further, in the variable resistance element manufacturing method according to the present invention, in addition to any one of the sixth to sixteenth features, the conductive film deposition step is performed by using a lamination method of CVD film formation and sputter film formation. An eighteenth feature is that it is a step of depositing a film.

  According to the seventeenth or eighteenth feature of the variable resistance element manufacturing method according to the present invention, the conductive film deposited on the side wall of the step region and the first interlayer insulating film are deposited on the upper layer. A difference is provided between the thickness of the conductive film and the thickness of the local thin film region can be sufficiently reduced as compared with other regions. Therefore, the conductive film can be easily divided into two regions (first electrode and second electrode) by the variable resistor formed in the local thin film region by the oxidation process.

  The variable resistance element manufacturing method according to the present invention is characterized in that, in addition to any one of the first to eighteenth features, the conductive film is titanium nitride.

  According to the nineteenth feature of the method of manufacturing a variable resistance element according to the present invention, titanium oxynitride showing properties as a variable resistor capable of changing a resistance value according to an applied voltage by an oxidation process, or Since titanium oxide is formed, a variable resistance element exhibiting stable switching characteristics using titanium nitride as the first and second electrodes and titanium oxide or titanium oxynitride sandwiched between these electrodes as a variable resistor is provided. Can be realized.

  In addition to the titanium nitride, the conductive film may be made of a transition metal such as Cu, Ni, V, Zn, Nb, Ti, W, Co, or a nitride of these transition metals. In this case, the variable resistor is made of a metal oxide or metal oxynitride generated by oxidation of the transition metal or transition metal nitride used.

  According to the configuration of the present invention, the interface between the variable resistor and the first electrode and the interface between the variable resistor and the second electrode are not exposed to the atmosphere or atmosphere. No object or the like adheres and the contact resistance is stabilized. As a result, the contact resistance is stabilized between memory cells in the same wafer as well as between different wafers. As a result, a nonvolatile semiconductor memory device exhibiting stable switching characteristics can be realized.

  Embodiments of a variable resistance element manufacturing method according to the present invention (hereinafter referred to as “the present invention method” where appropriate) will be described below with reference to the drawings. In addition, the variable resistance element manufactured by the method of the present invention has two electrodes (hereinafter referred to as “first electrode” and “second electrode”), similarly to the variable resistance element included in the conventional nonvolatile semiconductor memory. And a variable resistor sandwiched between these two electrodes. Then, by applying a voltage pulse between the first electrode and the second electrode, the resistance value is reversibly changed, and the resistance value of the variable resistance element after the change is read, thereby the read resistance. The storage state (write state, erase state) associated with the value can be recognized.

[First Embodiment]
A first embodiment of the method of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIGS. 1 and 2. FIG. 1 schematically shows a schematic cross-sectional view in each process when manufacturing a semiconductor device in the present embodiment, and is divided into FIGS. 1A to 1G for each process. Show. FIG. 2 is a flowchart of the manufacturing process of the present embodiment, and each step in the following sentence represents each step of the flowchart shown in FIG.

  In addition to the schematic cross-sectional view shown in FIG. 1, each schematic structural diagram referred to for explanation in the present embodiment and each of the embodiments described later is merely schematically illustrated, and the dimensions of the actual structure The scale of FIG. 1 does not necessarily match the scale of the drawing. In addition, the numerical value of the film thickness of each film deposited in each process is merely an example, and is not limited to this value. The same applies to the following embodiments.

  First, as shown in FIG. 1A, a TiN film 14 as an example of a conductive thin film is formed on a whole surface with a thickness of 100 nm by a sputtering method on a semiconductor substrate 11 on which a transistor circuit or the like (not shown) is appropriately formed. Deposit (Step # 11).

  Next, as shown in FIG. 1B, the TiN film 14 is patterned by a known etching technique using a resist formed by a known photolithography technique as a mask (step # 12).

Next, as shown in FIG. 1C, a SiO ₂ film (first interlayer insulating film) 13 is deposited on the entire surface of the TiN film 14 to a thickness of 300 nm by the CVD method (step # 13).

  Next, as shown in FIG. 1D, the upper surface of the TiN film 14 in a local region that should function as a variable resistor is exposed by a known etching technique using a resist formed by a known photolithography technique as a mask. Then, the first interlayer insulating film 13 is opened, and the opening 15 is formed (step # 14).

  Next, as shown in FIG. 1E, the TiN film 14 located in the lower region of the opening 15 is thinned to a predetermined thickness by a known etching technique (step # 15).

Next, as shown in FIG. 1F, the outer peripheral portion of the opening 15 that is not covered with the first interlayer insulating film 13 is thermally oxidized, for example, in an atmosphere containing oxygen at 250 to 450 ° C. The TiN film 14 is oxidized to form a TiO ₂ film 16 (hereinafter referred to as “variable resistor film 16” as appropriate) as an example of a variable resistor (step # 16). At this time, thermal oxidation proceeds in a direction away from the surface of the TiN film 14 located in the outer peripheral region of the exposed opening 15 with respect to the opening 15 (downward and outward as viewed from the opening 15). To do. When this thermal oxidation progressing downward reaches the interface position between the upper surface of the semiconductor substrate 11 and the TiN film 14, the TiN film 14 located in the lower region (and the periphery thereof) of the opening 15 becomes a variable resistor. Changes to film 16. The variable resistor film 16 separates the TiN film 14 into one electrode (first electrode) 14a and the other electrode (second electrode) 14b.

Next, as shown in FIG. 1G, a protective interlayer insulating film 17 such as SiO _{2 is} deposited to 700 nm by the CVD method, and is flattened by a flattening technique such as a known CMP method (step # 17). .

  According to the method of the present invention, the variable resistor film 16 is formed by oxidizing the TiN film 14. As a result of the formation of the variable resistor film 16, the TiN film 14 is divided into two parts (first electrode 14a and second electrode 14b), whereby the variable resistor 16 is narrowed between the two electrodes. A variable resistance element (present invention element) is formed. That is, both the electrodes 14a and 14b and the variable resistor film 16 are originally the same TiN film 14 laminated in the same process (step # 11), and both the electrodes 14a and 14b, the variable resistor film 16 and Therefore, the contact resistance does not vary under the influence of the atmosphere in the film forming process unlike the conventional method. Therefore, according to the method of the present invention, the contact resistance can be stabilized between the memory cells in the same wafer and between different wafers, so that the voltage applied to both ends of the variable resistor film 16 can be made uniform. Thus, a variable resistance element having a stable switching operation can be formed with good reproducibility.

  Furthermore, the area of the electrically contributing region of the variable resistor can be reduced by a simpler method than the area limited by the lithographic processable area in the prior art. Current consumption can be reduced, and a variable resistance element having a stable switching operation that does not cause write failure due to low resistance can be formed with good reproducibility and at low cost. In addition, said effect can be show | played similarly also in each 2nd-7th embodiment mentioned later.

  In step # 15, a process of thinning the TiN film 14 located in the lower region of the opening 15 to a predetermined thickness was performed. This step is preferable for reducing the current consumption by reducing the area of the electrically contributing region of the variable resistor, and realizing a memory cell capable of stable switching operation that does not become unwritable with good reproducibility. Although it is a process, it is not necessarily required as a process for producing the element of the present invention. In a fourth embodiment to be described later, an experimental result in which the switching characteristics of the memory cells are compared by changing the film thickness of the variable resistor is shown. The thinner the variable resistor, the more stable switching operation becomes possible. To clarify. In addition, by performing the thinning process according to step # 15, it is possible to shorten the oxidation time required to oxidize the first electrode 14a and the second electrode 14b in step # 16. is there.

The first interlayer insulating film 13 deposited in step # 13 and the protective interlayer insulating film 17 deposited in step # 17 are both SiO ₂ films. These interlayer insulating films are made of SiO ₂ films. Any suitable insulating film having oxidation resistance, such as a SiN film, a SiON film, a SiOF film, or a SiOC film, can be used. The first interlayer insulating film 13 and the protective interlayer insulating film 17 may be formed of insulating films made of different materials. The same applies to the following second to sixth embodiments.

  In step # 11, the semiconductor substrate 11 which is the base for forming the TiN film 14 is provided with a transistor circuit or the like as appropriate. However, the circuit is not necessarily formed. The same applies to the following embodiments.

  In Step # 13 and Step # 17, each interlayer insulating film is deposited by the CVD method. However, any appropriate method such as pulsed laser deposition, rf-sputtering, electron beam evaporation, thermal evaporation, spin-on deposition, or the like is used. It is also possible to deposit using a deposition technique. The same applies to each of the following embodiments unless otherwise specified.

  Furthermore, a metal wiring (not shown) formed for making electrical contact with each of the first electrode 14a and the second electrode 14b can be appropriately formed either before or after the TiN film 14 is deposited. The same applies to each of the following embodiments unless otherwise specified.

[Second Embodiment]
A second embodiment of the method of the present invention (hereinafter referred to as “this embodiment” where appropriate) will be described with reference to FIGS. 3 and 4. FIG. 3 schematically shows a schematic cross-sectional view in each process when manufacturing a semiconductor device in this embodiment, and is divided into FIGS. 3A to 3G for each process. Show. FIG. 4 is a flowchart of the manufacturing process of the present embodiment, and each step in the following sentence represents each step of the flowchart shown in FIG.

First, as shown in FIG. 3A, an SiO ₂ film (first interlayer insulating film) 13 is formed on the entire surface of a semiconductor substrate 11 on which a transistor circuit or the like (not shown) is appropriately formed with a thickness of 100 nm by a CVD method. (Step # 21).

  Next, as shown in FIG. 3B, the first interlayer insulating film 13 is patterned by a known etching technique using a resist formed by a known photolithography technique as a mask so that the upper surface of the semiconductor substrate 11 is exposed. Openings 15a and 15b are formed in (step # 22). At this time, the formation position of the first electrode and the second electrode formed in a later process is opened, and the first electrode formation scheduled position (opening 15a) and the second electrode formation scheduled position (opening 15b). ), The first interlayer insulating film 13 is left in the region sandwiched between the two. Hereinafter, the first interlayer insulating film 13 existing in the region sandwiched between the openings 15a and 15b is referred to as a “first interlayer insulating film 13a”.

  Next, as shown in FIG. 3C, the film thickness of the first interlayer insulating film 13 in which the TiN film 14 as an example of the conductive thin film is deposited on the semiconductor substrate 11 by the sputtering method at least in step # 21. A larger film thickness (for example, 150 nm) is deposited on the entire surface (step # 23). Thereby, the TiN film 14 deposited in the opening 15 is filled up to a position higher than the upper surface position of the first interlayer insulating film 13 which fills the entire opening 15 and is deposited around the opening 15. It will be.

  Next, as shown in FIG. 3D, the TiN film 14 formed on the upper surface of the first interlayer insulating film 13 is thinned by a known CMP technique or etching technique until it reaches a predetermined thickness (step # 24). . At this time, the film thickness of the TiN film 14 deposited in the opening 15 and in the upper region thereof should not be thinner than the film thickness of the TiN film 14 deposited in the upper region of the first interlayer insulating film 13. .

  Next, as shown in FIG. 3E, the TiN film 14 is patterned by a known etching technique using a resist formed by a known photolithography technique as a mask. Specifically, it is formed on the first interlayer insulating film 13 other than the first interlayer insulating film 13 formed in the upper region of the opening 15a and the opening 15b and the region sandwiched between the two regions. The TiN film 14 is removed by etching.

Next, as shown in FIG. 3 (f), for example, by thermally oxidizing in an atmosphere of 250 to 450 ° C. containing oxygen, a TiN film 14 is oxidized, TiO ₂ film as an example of a variable resistor 16 (hereinafter referred to as “variable resistor film 16” as appropriate) is formed (step # 26). At this time, thermal oxidation is performed such that the TiN film 14 deposited in the upper region of the first interlayer insulating film 13a is oxidized from the upper surface to the interface position with the first interlayer insulating film 13a. As a result, the openings 15a and 15b are still filled with the unoxidized TiN film 14, and the variable resistor film 16 is formed on the top and the first interlayer insulating film 13a. It will be. That is, in this step, the TiN film 14 is filled with the unoxidized TiN film 14a (first electrode) filled in the opening 15a and the unoxidized TiN film 14b (first electrode) filled in the opening 15b. 2 electrodes).

Next, as shown in FIG. 3G, a protective interlayer insulating film 17 such as SiO _{2 is} deposited to 700 nm by a CVD method, and is flattened by a flattening technique such as a known CMP method (step # 27). .

  Also in this embodiment, the variable resistor film 16 is formed by oxidizing the TiN film 14 as in the first embodiment. As a result of the formation of the variable resistor film 16, the TiN film 14 is divided into two parts (first electrode 14a and second electrode 14b), whereby the variable resistor 16 is narrowed between the two electrodes. A held variable resistance element is formed. Accordingly, the interface between the electrodes 14a and 14b and the variable resistor film 16 is not exposed to gas, air, or the like, so that the contact resistance varies due to the influence of the atmosphere in the film forming process as in the conventional method. In other words, the contact resistance can be stabilized between the memory cells in the same wafer and between different wafers. Thereby, the voltage applied to both ends of the variable resistor film 16 can be made uniform, and a variable resistor element having a stable switching operation can be formed with good reproducibility.

[Third Embodiment]
A third embodiment of the method of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIGS. FIG. 5 schematically shows a schematic cross-sectional view in each step when manufacturing a semiconductor device in this embodiment, and is divided into FIG. 5A to FIG. 5E for each step. Show. FIG. 6 is a flowchart of the manufacturing process of the present embodiment, and each step in the following sentence represents each step of the flowchart shown in FIG.

First, as shown in FIG. 5 (a), 400 nm in the transistor circuit or the like (not shown) and a SiO ₂ film (first interlayer insulating film) on the semiconductor substrate 11 which is suitably formed of metal wires 21 13 by CVD (Step # 31).

  Next, as shown in FIG. 5B, the metal wiring 21 is exposed in the first interlayer insulating film 13 with a hole diameter of about 200 nm, for example, by a known etching technique using a resist formed by a known photolithography technique as a mask. The opening 22 is patterned until it is done (step # 32). At this time, the taper etching is performed so that the opening area in the opening 22 becomes narrower as the opening area progresses from the upper area to the lower area.

  Next, as shown in FIG. 5C, a TiN film 14 as an example of a conductive thin film is deposited on the semiconductor substrate 11 to a thickness of 60 nm by sputtering (step # 33). In step # 32, since the hole shape of the opening portion 22 is processed into a tapered shape, the TiN film 14 is deposited on the inclined portion of the inner wall of the opening portion 22. As a result, in the opening portion 22, the upper position is changed to the lower position. As the process proceeds, the TiN film 14 can be formed so that the film thickness becomes thinner, and a portion in the TiN film 14 that is thinner than the other regions (hereinafter referred to as “local thin film region”). Can be formed. At this time, the TiN film 14 is deposited so that the opening 22 is not completely filled with the TiN film 14.

Next, as shown in FIG. 5D, for example, the TiN film 14 is oxidized by thermal oxidation in an atmosphere containing oxygen at 250 to 450 ° C., and a TiO ₂ film as an example of a variable resistor is formed. 16 (hereinafter referred to as “variable resistor film 16” as appropriate) is formed (step # 34). At this time, the thermal oxidation reaches the interface position between the TiN film 14 and the first interlayer insulating film 13 from the surface of the TiN film 14 deposited on the inner side wall of the opening 22 (in other words, at least In the local thin film region, the TiN film 14 is formed on the inner side wall of the opening 22 by oxidizing the thickness of the TiN film 14 included in the local thin film region. To change. At this time, the TiN film 14 formed at the bottom surface position of the opening 22 is not completely oxidized by performing the oxidation treatment under the predetermined conditions of the pressure condition, the temperature condition, and the treatment time, and the region has A partially unoxidized TiN film 14 is left. That is, an unoxidized TiN film 14 is formed on the bottom surface of the opening 22 in contact with the upper surface of the metal wiring 21, and the variable resistor film 16 in which the TiN film 14 is oxidized in the upper region. Is formed. By the step # 34, the TiN film 14 is separated into the electrode (first electrode) 14a that contacts the metal wiring 21 via the variable resistor film 16 and the other electrode (second electrode) 14b. As an example, when the TiN film 14 is deposited on the inner side wall of the opening 22 with a film thickness of about 9 nm, the heat of about 40 minutes is obtained at 300 ° C. under normal pressure (760 Torr). By performing the oxidation treatment, the TiN film 14 deposited on the side wall portion can be completely oxidized. In this case, when the TiN film 14 having a thickness sufficiently larger than 9 nm is deposited on the bottom surface of the opening 22, the TiN film 14 formed on the bottom of the opening 22 is completely oxidized. Instead, a part of the non-oxidized TiN film 14 remains in contact with the metal wiring 21.

Next, as shown in FIG. 5E, a protective interlayer insulating film 17 such as SiO _{2 is} deposited by 700 nm by the CVD method, and flattened by a flattening technique by a known CMP method or the like (step # 35). .

  Also in this embodiment, the variable resistor film 16 is formed by oxidizing the TiN film 14 as in the first or second embodiment. As a result of the formation of the variable resistor film 16, the TiN film 14 is divided into two parts (first electrode 14a and second electrode 14b), whereby the variable resistor 16 is narrowed between the two electrodes. A held variable resistance element is formed. Accordingly, the interface between the electrodes 14a and 14b and the variable resistor film 16 is not exposed to gas, air, or the like, so that the contact resistance varies due to the influence of the atmosphere in the film forming process as in the conventional method. In other words, the contact resistance can be stabilized between the memory cells in the same wafer and between different wafers. Thereby, the voltage applied to both ends of the variable resistor film 16 can be made uniform, and a variable resistor element having a stable switching operation can be formed with good reproducibility.

  In the present embodiment, when the patterning process is performed on the TiN film 14 and the variable resistor film 16, it is preferable to form a predetermined antioxidant insulating film in advance before performing the patterning process.

  7 and 8 are a schematic cross-sectional view and a flowchart according to another manufacturing process of the present embodiment. As shown in FIG. 7E, after the thermal oxidation process (step # 34) is finished, an oxidation-preventing insulating film 18 such as SiON, SiN, SiOC, or SiC is deposited to a thickness of about 50 nm by the CVD method (step # 36). Thereafter, as shown in FIG. 7F, the antioxidant insulating film 18, the variable resistor film 16, and the TiN film 14 are patterned by a known etching technique using a resist formed by a known photolithography technique as a mask ( Step # 37). Thereafter, as shown in FIG. 7G, a protective interlayer insulating film 17 is deposited and planarized as in FIG. 5E (step # 35).

  As described above, by forming the oxidation-preventing insulating film 18 in advance before the patterning process according to step # 37, it is possible to prevent the influence of oxidation on the variable resistor film 16 due to the resist ashing process or the like in the patterning process. A variable resistance element can be manufactured without degrading the characteristics of the variable resistor.

[Fourth Embodiment]
A fourth embodiment of the method of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIGS. 9 to 13. FIG. 9 schematically shows a schematic cross-sectional view in each process when manufacturing a semiconductor device in this embodiment, and is divided into FIG. 9A to FIG. 9G for each process. Show. FIG. 10 is a flowchart of the manufacturing process of the present embodiment, and each step in the following sentence represents each step of the flowchart shown in FIG.

First, as shown in FIG. 9A, an SiO ₂ film (first interlayer insulating film) 13 is formed by a CVD method on a semiconductor substrate 11 on which a transistor circuit or the like (not shown) and a metal wiring 21 are appropriately formed by a CVD method. (Step # 41).

  Next, as shown in FIG. 9B, the metal wiring 21 having a predetermined hole diameter of about 400 nm is formed in the first interlayer insulating film 13 by a known etching technique using a resist formed by a known photolithography technique as a mask. Opening 32 is formed in the upper region of metal wiring 21 until the upper portion is exposed (step # 42).

Next, as shown in FIG. 9C, a SiO ₂ film (sidewall forming insulating film) 31 is deposited on the entire surface so as not to completely fill the opening 32 (for example, about 170 nm). Step # 43).

  Next, as shown in FIG. 9D, the entire surface is etched back by a known etching technique so that the upper surface of the metal wiring 21 is exposed, and the width becomes wider as it goes downward into the side wall surface of the opening 32. A side wall 31a is formed (step # 44).

  Next, as shown in FIG. 9E, a TiN film 14 as an example of a conductive thin film is deposited on the entire surface of the semiconductor substrate 11 to a thickness of 60 nm by sputtering (step # 45). At this time, since the side wall 31a is formed in step # 44, the TiN film 14 is deposited on the outer wall portion of the side wall 31a. As a result, the film thickness is increased from the upper position to the lower position in the opening 32. The TiN film 14 can be formed so as to be thin, and a local thin film region having a smaller thickness than other regions can be formed in the TiN film 14 as in the third embodiment. At this time, the TiN film 14 is deposited so that the inside of the opening 32 is not completely filled with the TiN film 14.

Next, as shown in FIG. 9F, for example, the TiN film 14 is oxidized by thermal oxidation in an atmosphere containing oxygen at 250 to 450 ° C., and a TiO ₂ film as an example of a variable resistor is formed. 16 (hereinafter referred to as “variable resistor film 16” as appropriate) is formed (step # 46). At this time, the thermal oxidation reaches the interface position between the TiN film 14 and the first interlayer insulating film 13 from the surface of the TiN film 14 deposited on the outer wall portion of the sidewall 31a (in other words, at least locally In the thin film region, the TiN film 14 deposited on the inner side wall of the opening 32 is formed on the variable resistor film 16 by oxidizing the thickness of the TiN film 14 of the local thin film region. Change. At this time, the TiN film 14 formed at the bottom surface position of the opening 32 (that is, the top surface position of the metal wiring 21) is completely obtained by performing the oxidation treatment under predetermined conditions of the pressure condition, the temperature condition, and the processing time. The TiN film 14 that remains partially oxidized is left in the region without being oxidized. That is, the non-oxidized TiN film 14 is formed on the bottom surface of the opening 32 at a portion in contact with the upper surface of the metal wiring 21, and the variable resistor film 16 on which the TiN film 14 is oxidized in the upper region. Is formed. By the step # 46, the TiN film 14 is separated into the electrode (first electrode) 14a in contact with the metal wiring 21 and the other electrode (second electrode) 14b through the variable resistor film 16. . As an example, as in the third embodiment, thermal oxidation treatment may be performed for about 40 minutes at 300 ° C. under normal pressure (760 Torr).

Next, as shown in FIG. 9G, a protective interlayer insulating film 17 such as SiO _{2 is} deposited by 700 nm by the CVD method, and flattened by a flattening technique by a known CMP method or the like (step # 47). .

  Also in this embodiment, the variable resistor film 16 is formed by oxidizing the TiN film 14 as in the first to third embodiments. As a result of the formation of the variable resistor film 16, the TiN film 14 is divided into two parts (first electrode 14a and second electrode 14b), whereby the variable resistor 16 is narrowed between the two electrodes. A held variable resistance element is formed. Accordingly, the interface between the electrodes 14a and 14b and the variable resistor film 16 is not exposed to gas, air, or the like, so that the contact resistance varies due to the influence of the atmosphere in the film forming process as in the conventional method. In other words, the contact resistance can be stabilized between the memory cells in the same wafer and between different wafers. Thereby, the voltage applied to both ends of the variable resistor film 16 can be made uniform, and a variable resistor element having a stable switching operation can be formed with good reproducibility.

  FIG. 11 is a graph showing the switching characteristics of the variable resistance element manufactured based on the method of the present invention according to this embodiment. The horizontal axis represents the thickness of the TiN film 14 deposited in step # 45, and the variable resistance The resistance value of the element is plotted as a vertical axis (logarithmic scale).

  That is, the first pulse voltage (voltage −2.6 [V], pulse width 35 [nsec]. In the drawing, “Pulse 1” is applied to the variable resistance element manufactured based on the method of the present invention. (Notation) and a second pulse voltage (voltage +2.0 [V], pulse width 35 [nsec], expressed as “Pulse2” in the drawing) are alternately applied, and a resistance value (readout resistance) measured after each voltage application Value) of the measurement result range is displayed on a graph. At this time, the reading resistance was measured using a plurality of samples manufactured by changing the thickness of the TiN film 14 deposited in Step # 45 (three types in FIG. 11). In the reading process, a resistance value measured by applying a voltage of 0.5 [V] is shown.

  According to FIG. 11, the value of the read resistance after the application of the second pulse voltage has little variation among the samples and there is not much difference between the samples, but the value of the read resistance after the application of the first pulse voltage varies. It can be seen that the degree of variation increases as the thickness of the TiN film 14 increases. In other words, it is suggested that by reducing the thickness of the TiN film 14, variations in the read resistance can be suppressed, and stable switching characteristics are realized.

  In the present embodiment, when the patterning process is performed on the TiN film 14 and the variable resistor film 16, a predetermined antioxidant insulating film is formed in advance before the patterning process is performed, as in the third embodiment. Is preferred.

  12 and 13 are a schematic cross-sectional view and a flowchart according to another manufacturing process of the present embodiment. As shown in FIG. 12G, after the thermal oxidation process (step # 46) is completed, an oxidation-preventing insulating film 18 such as SiON, SiN, SiOC, or SiC is deposited to a thickness of about 50 nm by the CVD method (step # 48). Thereafter, as shown in FIG. 12H, the antioxidant insulating film 18, the variable resistor film 16, and the TiN film 14 are patterned by a known etching technique using a resist formed by a known photolithography technique as a mask ( Step # 49). Thereafter, as shown in FIG. 12I, a protective interlayer insulating film 17 is deposited and planarized as in FIG. 9G (step # 47).

  In this manner, by forming the oxidation-preventing insulating film 18 in advance before the patterning process according to step # 49, it is possible to prevent the influence of oxidation on the variable resistor film 16 due to the resist ashing process or the like in the patterning process. A variable resistance element can be manufactured without degrading the characteristics of the variable resistor.

[Fifth Embodiment]
A fifth embodiment of the method of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIGS. 14 to 17. FIG. 14 schematically shows a schematic cross-sectional view in each process when manufacturing a semiconductor device in this embodiment, and is divided into FIGS. 14A to 14E for each process. Show. FIG. 15 is a flowchart of the manufacturing process of the present embodiment, and each step in the following sentence represents each step of the flowchart shown in FIG.

First, as shown in FIG. 14A, an SiO ₂ film (first interlayer insulating film) 13 is formed by CVD on a semiconductor substrate 11 on which a transistor circuit (not shown) and a metal wiring 21 are appropriately formed by a CVD method. (Step # 51). In the present embodiment, unlike the third and fourth embodiments, it is assumed that a metal wiring 21 having a predetermined film thickness is formed to protrude on the semiconductor substrate 11. At this time, as a method of forming the first interlayer insulating film 13, it is desirable to use a plasma CVD method having poor step coverage (step coverage). As a result, a step portion 41 of the first interlayer insulating film 13 is formed around the position where the metal wiring 21 is formed in an inversely tapered shape in which the first interlayer insulating film 13 protrudes outward in the upper region.

  Next, as shown in FIG. 14B, the upper surface of the metal wiring 21 is exposed by a known etching technique using a resist formed by a known photolithography technique as a mask (step # 52). Even in this case, the step portion 41 is still formed.

  Next, as shown in FIG. 14C, a TiN film 14 as an example of a conductive thin film is deposited on the semiconductor substrate 11 to a thickness of 60 nm by sputtering (step # 53). At this time, since the step portion 41 has an inversely tapered shape as described above, the TiN film 14 can be formed so that the thickness thereof decreases from the upper portion to the lower portion of the step portion 41. As in the third or fourth embodiment, a local thin film region having a smaller film thickness than other regions can be formed in the TiN film 14.

Next, as shown in FIG. 14D, for example, the TiN film 14 is oxidized by thermal oxidation in an atmosphere containing oxygen at 250 to 450 ° C., and a TiO ₂ film as an example of a variable resistor is formed. 16 (hereinafter referred to as “variable resistor film 16” as appropriate) is formed (step # 54). At this time, the thermal oxidation reaches the interface of the first interlayer insulating film 13 from the surface of the TiN film 14 deposited on the outer wall portion of the step portion 41 (in other words, at least in the local thin film region, the local thin film). Thus, the TiN film 14 on the outer wall portion of the step portion 41 is changed to the variable resistor film 16. At this time, the TiN film 14 formed in the upper region in contact with the metal wiring 21 is not completely oxidized by performing the oxidation treatment under the predetermined conditions of the pressure condition, the temperature condition, and the treatment time. The partially unoxidized TiN film 14 is left. By the step # 54, the TiN film 14 is separated into an electrode (first electrode) 14a that is in contact with the metal wiring 21 via the variable resistor film 16 and another electrode (second electrode) 14b. As an example, as in the third embodiment, thermal oxidation treatment may be performed for about 40 minutes at 300 ° C. under normal pressure (760 Torr).

Next, as shown in FIG. 14E, a protective interlayer insulating film 17 such as SiO _{2 is} deposited by 700 nm by the CVD method and flattened by a flattening technique by a known CMP method or the like (step # 55). .

  Also in this embodiment, the variable resistor film 16 is formed by oxidizing the TiN film 14 as in the first to fourth embodiments. As a result of the formation of the variable resistor film 16, the TiN film 14 is divided into two parts (first electrode 14a and second electrode 14b), whereby the variable resistor 16 is narrowed between the two electrodes. A held variable resistance element is formed. Accordingly, the interface between the electrodes 14a and 14b and the variable resistor film 16 is not exposed to gas, air, or the like, so that the contact resistance varies due to the influence of the atmosphere in the film forming process as in the conventional method. In other words, the contact resistance can be stabilized between the memory cells in the same wafer and between different wafers. Thereby, the voltage applied to both ends of the variable resistor film 16 can be made uniform, and a variable resistor element having a stable switching operation can be formed with good reproducibility.

  In the present embodiment, when the patterning process is performed on the TiN film 14 (14a, 14b) and the variable resistor film 16, a predetermined oxidation is performed before the patterning process is performed, as in the third and fourth embodiments. It is preferable to form a prevention insulating film.

  16 and 17 are a schematic cross-sectional view and a flowchart according to another manufacturing process of the present embodiment. As shown in FIG. 16E, after the thermal oxidation process (step # 54) is finished, an anti-oxidation insulating film 18 such as SiON, SiN, SiOC, or SiC is deposited to a thickness of about 50 nm by the CVD method (step # 56). Thereafter, as shown in FIG. 16 (f), with the resist formed by a known photolithography technique as a mask, the antioxidant insulating film 18, the variable resistor film 16, and the TiN film 14 (14a, 14b) are known by a known etching technique. ) Is patterned (step # 57). Thereafter, as shown in FIG. 16G, a protective interlayer insulating film 17 is deposited and planarized as in FIG. 9G (step # 55).

  As described above, by forming the oxidation-preventing insulating film 18 in advance before the patterning process according to step # 57, it is possible to prevent the influence of oxidation on the variable resistor film 16 due to the resist ashing process or the like in the patterning process. A variable resistance element can be manufactured without degrading the characteristics of the variable resistor.

[Sixth Embodiment]
A sixth embodiment of the method of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIGS. FIG. 18 schematically shows a schematic cross-sectional view in each step when manufacturing a semiconductor device in the present embodiment, and is divided into FIG. 18A to FIG. 18F for each step. Show. FIG. 19 is a flowchart of the manufacturing process of the present embodiment, and each step in the following sentence represents each step of the flowchart shown in FIG.

First, as shown in FIG. 18A, an SiO ₂ film (first interlayer insulating film) 13 is formed on a semiconductor substrate 11 on which a transistor circuit or the like (not shown) is appropriately formed by a CVD method at a substrate temperature of 200 ° C. Then, the film is deposited on the entire surface with a thickness of 400 nm while being raised to about 400 ° C. (step # 61). Since the deposition rate of the first interlayer insulating film 13 formed on the semiconductor substrate 11 is affected by the substrate temperature, the first interlayer insulating film 13 is moved from the semiconductor substrate 11 side toward the upper surface by the step # 61. The film quality will continuously change from sparse to dense.

  Next, as shown in FIG. 18B, the first interlayer insulating film 13 is patterned by a known etching technique using a resist (resist film 51) formed by a known photolithography technique as a mask, and the step portion 52 is formed. Form (step # 62).

  Next, as shown in FIG. 18C, wet etching is performed with a chemical solution such as HF for several minutes without removing the resist film 51 by ashing (step # 63). At this time, since the film density of the first interlayer insulating film 13 is reduced in the depth direction by the process of step # 61, the stepped portion 52 is processed into an inversely tapered shape as a result of the etching progressing as the film density is lower. Is done.

  Next, after removing the resist film 51, as shown in FIG. 18D, a TiN film 14 as an example of a conductive thin film is deposited on the entire surface of the semiconductor substrate 11 to a thickness of 60 nm by sputtering (step). # 64). At this time, since the stepped portion 52 has an inversely tapered shape, the film thickness of the TiN film 14 can be continuously reduced from the upper step portion to the lower step portion of the stepped portion 52, As in the third to fifth embodiments, a local thin film region having a smaller film thickness than other regions can be formed in the TiN film 14.

Next, as shown in FIG. 18E, for example, the TiN film 14 is oxidized by thermal oxidation in an atmosphere containing oxygen at 250 to 450 ° C., and a TiO ₂ film as an example of a variable resistor is formed. 16 is formed (step # 65). At this time, the thermal oxidation reaches from the surface of the TiN film 14 deposited on the outer wall portion of the step portion 52 to the interface of the first interlayer insulating film 13 and the interface of the semiconductor substrate 11 (in other words, at least locally In the thin film region, the TiN film 14 corresponding to the thickness of the TiN film 14 of the local thin film region is oxidized), whereby the TiN film 14 in a part of the outer wall portion of the stepped portion 52 is changed to the variable resistor film 16. . At this time, as in the fifth embodiment, the oxidation process is performed under predetermined conditions of the pressure condition, the temperature condition, and the processing time, thereby forming the upper surface of the first interlayer insulating film 13 that is the upper position of the stepped portion 52. The TiN film 14 formed and the TiN film 14 formed on the upper surface of the semiconductor substrate 11 at the lower position of the stepped portion 52 are not completely oxidized, and partially unoxidized TiN films 14 are respectively formed in the regions. Remain. By the step # 65, the TiN film 14 is stepped from the electrode (first electrode) 14a formed at the upper position of the stepped portion 52 (the upper surface of the first interlayer insulating film 13) via the variable resistor film 16. It is separated into an electrode (second electrode) 14b formed at the lower position of the portion 52 (the upper surface of the semiconductor substrate 11). As an example, as in the third embodiment, thermal oxidation treatment may be performed for about 40 minutes at 300 ° C. under normal pressure (760 Torr).

Next, as shown in FIG. 18F, a protective interlayer insulating film 17 such as SiO _{2 is} deposited by a CVD method to a thickness of 700 nm and flattened by a flattening technique such as a known CMP method (step # 67). ).

  Also in this embodiment, the variable resistor film 16 is formed by oxidizing the TiN film 14 as in the first to fifth embodiments. As a result of the formation of the variable resistor film 16, the TiN film 14 is divided into two parts (first electrode 14a and second electrode 14b), whereby the variable resistor 16 is narrowed between the two electrodes. A held variable resistance element is formed. Accordingly, the interface between the electrodes 14a and 14b and the variable resistor film 16 is not exposed to gas, air, or the like, so that the contact resistance varies due to the influence of the atmosphere in the film forming process as in the conventional method. In other words, the contact resistance can be stabilized between the memory cells in the same wafer and between different wafers. Thereby, the voltage applied to both ends of the variable resistor film 16 can be made uniform, and a variable resistor element having a stable switching operation can be formed with good reproducibility.

  In the present embodiment, when the patterning process is performed on the TiN film 14 (14a, 14b) and the variable resistor film 16, a predetermined oxidation is performed before the patterning process is executed, as in the third to fifth embodiments. It is preferable to form a prevention insulating film.

  20 and 21 are a schematic cross-sectional view and a flowchart according to another manufacturing process of the present embodiment. As shown in FIG. 20F, after the thermal oxidation process (step # 65) is finished, an oxidation-preventing insulating film 18 such as SiON, SiN, SiOC, or SiC is deposited to a thickness of about 50 nm by the CVD method (step # 67). Thereafter, as shown in FIG. 20 (g), using a resist formed by a known photolithography technique as a mask, the antioxidant insulating film 18, the variable resistor film 16, and the TiN film 14 (14a, 14b) by a known etching technique. ) Is patterned (step # 68). Thereafter, as shown in FIG. 20G, a protective interlayer insulating film 17 is deposited and planarized as in FIG. 18F (step # 66).

  As described above, by forming the oxidation-preventing insulating film 18 in advance before the patterning process according to Step # 68, it is possible to prevent the influence of oxidation on the variable resistor film 16 due to the resist ashing process or the like in the patterning process. A variable resistance element can be manufactured without degrading the characteristics of the variable resistor.

[Seventh Embodiment]
A seventh embodiment of the method of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIGS. FIG. 22 schematically shows a schematic cross-sectional view in each step when manufacturing a semiconductor device in the present embodiment, and is divided into FIGS. 22A to 22F for each step. Show. FIG. 23 is a flowchart of the manufacturing process of the present embodiment, and each step in the following sentence represents each step of the flowchart shown in FIG.

First, as shown in FIG. 22 (a), a SiO ₂ film (first interlayer insulating film) 13 is formed with a thickness of 200 nm on a semiconductor substrate 11 on which a transistor circuit or the like (not shown) is appropriately formed by a CVD method. A SiN film (second interlayer insulating film) 61 is deposited on the entire surface of the first interlayer insulating film 13 to a thickness of 200 nm by the CVD method (step # 72).

  Next, as shown in FIG. 22B, the first interlayer insulating film 13 and the second interlayer insulating film 61 are formed by a known etching technique using a resist (resist film 51) formed by a known photolithography technique as a mask. Is patterned to form a stepped portion 62 (step # 73).

Next, as shown in FIG. 22C, wet etching is performed with a chemical solution such as HF for several minutes without removing the resist film 51 by ashing (step # 74). At this time, since SiO ₂ which is the material of the first interlayer insulating film 13 has a faster wet etch rate of HF than SiN which is the material of the second interlayer insulating film 61, the first interlayer insulating film 61 is compared with the first interlayer insulating film 61. The insulating film 13 has a larger amount of etching removal, and as a result, the stepped portion 62 is opposite to the first interlayer insulating film 13 that is the lower layer, and the second interlayer insulating film 61 that is the upper layer protrudes outward. Processed into a staircase shape.

  Next, as shown in FIG. 22D, after the resist film 51 is removed, a TiN film 14 as an example of a conductive thin film is deposited on the entire surface of the semiconductor substrate 11 to a thickness of 60 nm by sputtering (step) # 75). At this time, since the stepped portion 62 has a reverse staircase shape, the lower layer portion is compared with the thickness of the TiN film 14 deposited outside the upper layer portion (side wall of the second interlayer insulating film 61) of the stepped portion 62. (Side wall of the first interlayer insulating film 13) The TiN film 14 deposited on the outside can be formed so as to be thin, and in the TiN film 14, other films can be formed in the same manner as in the third to sixth embodiments. A local thin film region having a smaller film thickness than the region can be formed.

Next, as shown in FIG. 22E, for example, the TiN film 14 is oxidized by thermal oxidation in an atmosphere containing oxygen at 250 to 450 ° C., and a TiO ₂ film as an example of a variable resistor is formed. 16 is formed (step # 76). At this time, the thermal oxidation reaches the interface of the first interlayer insulating film 13 or the second interlayer insulating film 61 and the interface of the semiconductor substrate 11 from the surface of the TiN film 14 deposited on the outer wall portion of the stepped portion 62. (In other words, at least in the local thin film region, the film thickness of the TiN film 14 included in the local thin film region is oxidized), whereby the TiN film 14 in a part of the outer wall portion of the stepped portion 62 is variable. It changes to the resistor film 16. At this time, the TiN film 14 formed on the upper surface of the second interlayer insulating film 61 that is the upper position of the stepped portion 52 by performing oxidation treatment under predetermined conditions of the pressure condition, the temperature condition, and the processing time, In addition, the TiN film 14 formed on the upper surface of the semiconductor substrate 11 at the lower position of the stepped portion 52 is not completely oxidized, and partially unoxidized TiN films 14 are left in the regions. By the step # 76, the TiN film 14 is stepped from the electrode (first electrode) 14a formed at the upper position of the stepped portion 52 (the upper surface of the second interlayer insulating film 61) via the variable resistor film 16. It is separated into an electrode (second electrode) 14b formed at the lower position of the portion 52 (the upper surface of the semiconductor substrate 11). As an example, as in the third embodiment, thermal oxidation treatment may be performed for about 40 minutes at 300 ° C. under normal pressure (760 Torr).

Next, as shown in FIG. 22F, a protective interlayer insulating film 17 such as SiO _{2 is} deposited by 700 nm by the CVD method, and is flattened by a flattening technique by a known CMP method or the like (step # 77). .

  Also in this embodiment, the variable resistor film 16 is formed by oxidizing the TiN film 14 as in the first to sixth embodiments. As a result of the formation of the variable resistor film 16, the TiN film 14 is divided into two parts (first electrode 14a and second electrode 14b), whereby the variable resistor 16 is narrowed between the two electrodes. A held variable resistance element is formed. Accordingly, the interface between the electrodes 14a and 14b and the variable resistor film 16 is not exposed to gas, air, or the like, so that the contact resistance varies due to the influence of the atmosphere in the film forming process as in the conventional method. In other words, the contact resistance can be stabilized between the memory cells in the same wafer and between different wafers. Thereby, the voltage applied to both ends of the variable resistor film 16 can be made uniform, and a variable resistor element having a stable switching operation can be formed with good reproducibility.

  In the present embodiment, when the patterning process is performed on the TiN film 14 (14a, 14b) and the variable resistor film 16, a predetermined oxidation is performed before the patterning process is performed, as in the third to sixth embodiments. It is preferable to form a prevention insulating film.

  24 and 25 are a schematic cross-sectional view and a flowchart according to another manufacturing process of the present embodiment. As shown in FIG. 24F, after the thermal oxidation process (step # 76) is finished, an oxidation-preventing insulating film 18 such as SiON, SiN, SiOC, or SiC is deposited to about 50 nm by the CVD method (step # 78). Thereafter, as shown in FIG. 24G, with the resist formed by a known photolithography technique as a mask, the antioxidant insulating film 18, the variable resistor film 16, and the TiN film 14 (14a, 14b) are known by a known etching technique. ) Is patterned (step # 79). Thereafter, as shown in FIG. 24H, a protective interlayer insulating film 17 is deposited and planarized as in FIG. 22F (step # 77).

  As described above, by forming the oxidation-preventing insulating film 18 in advance before the patterning process in Step # 79, it is possible to prevent the influence of the oxidation due to the resist ashing process or the like in the patterning process on the variable resistor film 16. A variable resistance element can be manufactured without degrading the characteristics of the variable resistor.

  The TiN film 14 deposition step (steps # 11 and # 23) in the first and second embodiments described above is not limited to the sputtering method, and pulsed laser deposition, e-beam evaporation, thermal evaporation, and organometallic deposition. , Using any suitable deposition technique, including spin-on deposition, and metal organic chemical vapor deposition.

  On the other hand, in the deposition process (steps # 33, # 45, # 53, # 64, # 75) of the TiN film 14 in the third to seventh embodiments described above, two electrodes (first electrode 14a, second electrode) 14b) in order to provide a difference between the film thickness of the TiN film 14 and the film thickness of the local thin film region constituting the variable resistor 16 (the film thickness of the TiN film 14 deposited in the local thin film region is the film thickness of both electrodes). For this purpose, it is preferable to deposit using a directional sputtering film forming method such as collimated sputtering, long throw sputtering, or ionized sputtering. Further, the film thickness of the variable resistor 16 can be controlled by using a laminated film of the CVD method and the sputtering method.

In addition, as the oxidation step (steps # 16, # 26, # 34, # 46, # 54, # 65, # 76) in each of the above-described embodiments, the gas types include O ₂ , O ₃ , H ₂ O, N Other than the thermal oxidation method using molecules containing oxygen such as ₂ O and NO, a plasma oxidation method or an ion implantation method may be used.

In each of the above-described embodiments, the variable resistor film 16 is a TiO ₂ film. However, a TiO _{2 -X} N _X film having variable resistance characteristics can be obtained by appropriately adjusting oxidation conditions such as an oxidation temperature and an oxygen concentration. It is also possible. Furthermore, although the conductive thin film 14 is a TiN film, it may be formed of a transition metal such as Cu, Ni, V, Zn, Nb, Ti, W, Co, or a nitride of a transition metal. At this time, the variable resistor film 16 is made of a metal oxide or metal oxynitride formed by oxidizing the material used as the conductive thin film 14.

The schematic sectional drawing for every process in the manufacturing process of 1st Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. The flowchart which shows the manufacturing process of 1st Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. Schematic sectional view for each step in the manufacturing process of the second embodiment of the variable resistance element manufacturing method according to the present invention. The flowchart which shows the manufacturing process of 2nd Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. Schematic sectional view for each step in the manufacturing process of the third embodiment of the variable resistance element manufacturing method according to the present invention. The flowchart which shows the manufacturing process of 3rd Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. Schematic cross-sectional view for each step in another manufacturing step of the third embodiment of the variable resistance element manufacturing method according to the present invention. The flowchart which shows another manufacturing process of 3rd Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. Schematic sectional view for each step in the manufacturing process of the fourth embodiment of the variable resistance element manufacturing method according to the present invention. The flowchart which shows the manufacturing process of 4th Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. The graph which shows the switching characteristic of the variable resistance element manufactured based on the manufacturing process of the manufacturing method of 4th Embodiment concerning this invention. Schematic sectional view for each step in another manufacturing step of the fourth embodiment of the variable resistance element manufacturing method according to the present invention. The flowchart which shows another manufacturing process of 4th Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. Schematic sectional view for each step in the manufacturing process of the fifth embodiment of the variable resistance element manufacturing method according to the present invention. The flowchart which shows the manufacturing process of 5th Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. Schematic sectional view for each step in another manufacturing step of the fifth embodiment of the variable resistance element manufacturing method according to the present invention. The flowchart which shows another manufacturing process of 5th Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. Schematic sectional view for each step in the manufacturing process of the sixth embodiment of the variable resistance element manufacturing method according to the present invention. The flowchart which shows the manufacturing process of 6th Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. Schematic cross-sectional view for each step in another manufacturing process of the sixth embodiment of the variable resistance element manufacturing method according to the present invention. The flowchart which shows another manufacturing process of 6th Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. Schematic sectional view for each step in the manufacturing process of the seventh embodiment of the variable resistance element manufacturing method according to the present invention. The flowchart which shows the manufacturing process of 7th Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. Schematic sectional view for each step in another manufacturing process of the seventh embodiment of the variable resistance element manufacturing method according to the present invention. The flowchart which shows another manufacturing process of 7th Embodiment of the manufacturing method of the variable resistance element which concerns on this invention. Schematic structure diagram of variable resistance element with conventional configuration Equivalent circuit diagram showing one configuration example of 1T / 1R type memory cell Cross-sectional schematic diagram of 1T / 1R type memory cell Equivalent circuit diagram showing one configuration example of 1R type memory cell Cross-sectional schematic diagram of 1R type memory cell

Explanation of symbols

11: Semiconductor substrate 13: First interlayer insulating film (SiO ₂ film)
13a: first interlayer insulating film 14: conductive thin film (TiN film)
14a: 1st electrode 14b: 2nd electrode 15: Opening part 15a: Opening part (1st electrode formation plan position)
15b: Opening (second electrode formation planned position)
16: Variable resistor film (TiO ₂ film)
17: Protective interlayer insulating film 18: Antioxidation insulating film 21: Metal wiring 22: Opening part 31: Side wall forming insulating film 31a: Side wall 32: Opening part 41: Step part 51: Resist film 52: Step part 61 : Second interlayer insulating film (SiN film)
62: Stepped portion 101: Upper electrode 102: Variable resistor 103: Lower electrode 104: Memory cell array 106: Word line decoder 107: Source line decoder 111: Semiconductor substrate 112: Element isolation region 113: Gate insulating film 114: Gate electrode 115 : Drain diffusion layer region 116: source diffusion layer region 117: contact plug 118: lower electrode 119: variable resistor 120: upper electrode 121: contact plug 123: bit line wiring 124: source line wiring 131: memory cell array 132: bit line Decoder 133: Word line decoder 141: Lower electrode wiring 142: Variable resistor 143: Upper electrode wiring BL1-BLm: Bit line R: Variable resistance element SL1-SLn: Source line T: Select transistor WL1-WLn Word line

Claims (18)

A first electrode, a second electrode, and a variable resistor, wherein the variable resistor is in a region sandwiched between the first electrode and the second electrode, and the first electrode, the second electrode, A method of manufacturing a variable resistance element in which an electrical resistance between the first electrode and the second electrode changes by applying a voltage pulse between the first electrode and the second electrode,
A conductive film deposition step of depositing a first conductive film on the semiconductor substrate as a precursor of the first electrode, the second electrode, and the variable resistor;
By subjecting the conductive film to an oxidation treatment, a part of the conductive film is changed to the variable resistor, and the conductive film is divided by the variable resistor so that the first electrode and the first electrode are separated. An oxidation step to form two electrodes;
And a protective insulating film deposition step of depositing a protective interlayer insulating film on the entire surface after the oxidation step is completed . After completion of the conductive film deposition process and before the oxidation process starts,
A first insulating film deposition step of depositing a first interlayer insulating film so as to include an upper surface of the conductive film;
An opening forming step of opening a part of the first interlayer insulating film and exposing a part of the upper surface of the conductive film after the first insulating film deposition process is completed;
The method of manufacturing a variable resistance element according to claim 1 , wherein a peripheral region of the conductive film exposed through the opening is oxidized by the oxidation step. After the opening forming process is completed and before the oxidation process is started, by removing a part of the exposed portion of the conductive film exposed through the opening, the conductive film located on the bottom surface of the opening is removed. The method of manufacturing a variable resistance element according to claim 2 , further comprising a thinning step for reducing the film thickness. Before the conductive film deposition step, a first insulating film deposition step for depositing a first interlayer insulating film on the semiconductor substrate, and at least two separated openings by opening a predetermined region of the first interlayer insulating film And forming an opening.
Before the oxidation step starts after the completion of the conductive film depositing step, to the extent that the conductive film deposited on a region other than the opening is not completely removed, it thinned to reduce the film thickness before Kishirubedenmaku Having a process,
The conductive film deposition step is a step of depositing the conductive film so as to completely fill the two openings;
The oxidation step is equal to or greater than the thickness of the conductive film deposited in a region other than the opening and less than the thickness of the conductive film deposited from the upper surface position to the bottom surface of the opening. manufacturing method for a variable resistance element according to claim 1, characterized in that the step of only forming the variable resistor by oxidizing the conductive film. Before the conductive film deposition step, the conductive film deposited in the conductive film deposition step is preliminarily formed on the underlying layer of the conductive film so that the conductive film deposited in the conductive film deposition step has a partial thin film region with a thinner thickness than others. The method for manufacturing a variable resistance element according to claim 1 , wherein a predetermined pretreatment for conductive film deposition is performed on the conductive film. The conductive film deposition pretreatment includes a first insulating film deposition step of depositing a first interlayer insulating film on a semiconductor substrate, and a tapered shape in which an opening area becomes narrower as it proceeds downward to a predetermined region of the first interlayer insulating film. An opening forming step for forming the opening, and
The conductive film deposition step is a step of depositing the conductive film on the entire surface so as not to completely fill the inside of the opening, and forming the local thin film region on at least a part of the inner side wall of the opening. ,
In the oxidation step, the variable resistor is formed by oxidizing the conductive film from the exposed surface side, and at least the local thin film region is oxidized to be oxidized and changed into the variable resistor. The conductive film formed on the bottom side of the opening and the conductive film formed in the region above the local thin film region are divided by the region to form the first electrode and the second electrode. The method of manufacturing a variable resistance element according to claim 5 , wherein the method is a process. The conductive film deposition pretreatment includes a first insulating film deposition step of depositing a first interlayer insulating film on a semiconductor substrate, an opening forming step of forming an opening in a predetermined region of the first interlayer insulating film, A sidewall insulating film forming step of forming a sidewall insulating film that becomes wider as it goes downward in the side wall surface of the opening, and
The conductive film deposition step is a step of depositing a conductive film on the entire surface so as not to completely fill the inside of the opening, and forming the local thin film region on at least a part of the outer side wall of the sidewall insulating film. Yes,
In the oxidation step, the variable resistor is formed by oxidizing the conductive film from the exposed surface side, and at least the local thin film region is oxidized to be oxidized and changed into the variable resistor. The conductive film formed on the bottom side of the opening and the conductive film formed in the region above the local thin film region are divided by the region to form the first electrode and the second electrode. The method of manufacturing a variable resistance element according to claim 5 , wherein the method is a process. The conductive film deposition pre-treatment includes a first insulating film deposition step of depositing on the semiconductor substrate a first interlayer insulating film partially including a stepped region having different height positions of adjacent upper surfaces;
In the conductive film deposition step, the conductive film is deposited on the entire surface including the stepped portion region, so that a side wall portion connecting the upper step surface and the lower step surface constituting the stepped portion region and a corner portion where the lower step surface intersects. The step of forming the conductive film having the local thin film region of a shape that the film thickness becomes thinner as approaching,
In the oxidation step, the variable resistor is formed by oxidizing the conductive film from the exposed surface side, and at least the local thin film region is oxidized to be oxidized and changed into the variable resistor. The conductive film deposited on the upper stage surface and the conductive film deposited on the lower stage surface are divided by a region to form the first electrode and the second electrode. The manufacturing method of the variable resistance element of Claim 5 . In the conductive film deposition pretreatment, a first insulating film deposition step for depositing a first interlayer insulating film so that the film density increases in the upper layer direction, and the first interlayer insulating film other than a predetermined region is peeled off. In the reverse taper shape, a stepped region is formed in which the height positions of the adjacent upper surfaces are different from each other, and the side wall portion connecting the upper step surface and the lower step surface constituting the stepped portion region protrudes outward toward the upper layer direction. And a patterning step,
The wedge-shaped local thin film region where the conductive film deposition step deposits the conductive film over the entire surface including the stepped portion region, and the film thickness becomes thinner toward the corner portion where the side wall portion and the lower step surface intersect. Forming the conductive film having:
In the oxidation step, the variable resistor is formed by oxidizing the conductive film from the exposed surface side, and at least the local thin film region is oxidized to be oxidized and changed into the variable resistor. The conductive film deposited on the upper stage surface and the conductive film deposited on the lower stage surface are divided by a region to form the first electrode and the second electrode. The manufacturing method of the variable resistance element of Claim 5 . 10. The method of manufacturing a variable resistance element according to claim 9 , wherein the first insulating film deposition step is a step of depositing the first interlayer insulating film while continuously or intermittently increasing the substrate temperature. . The patterning step, the manufacturing method of the variable resistance element according to claim 9 or claim 10 characterized in that it is carried out by wet etching. The conductive film deposition pretreatment includes a first insulating film deposition step of depositing a first interlayer insulating film on a semiconductor substrate, and a second etching rate lower than that of the first interlayer insulating film on the upper surface of the first interlayer insulating film. A second insulating film deposition step for depositing an interlayer insulating film and a stepped region where the height positions of adjacent upper surfaces are different by peeling the first and second interlayer insulating films other than the predetermined region, A side wall portion that connects the upper and lower surfaces constituting the stepped portion region has a region formed of the second interlayer insulating film protruding outward from a region formed of the first interlayer insulating film. And a patterning process to make an inverted staircase shape,
The wedge-shaped local thin film region where the conductive film deposition step deposits the conductive film over the entire surface including the stepped portion region, and the film thickness becomes thinner toward the corner portion where the side wall portion and the lower step surface intersect. Forming the conductive film having:
The oxidation process, thereby forming the variable resistor by oxidizing the exposed surface side of the conductive film, by oxidizing at least the local thin film region, the local film and changed to the variable resistor is oxidized The conductive film deposited on the upper stage surface and the conductive film deposited on the lower stage surface are divided by a region to form the first electrode and the second electrode. The manufacturing method of the variable resistance element of Claim 5 . The first insulating film deposition step is a step of depositing a SiO ₂ film;
The second insulating film deposition step is a step of depositing a SiN film;
The method of manufacturing a variable resistance element according to claim 12 , wherein the patterning step is performed by wet etching using an HF chemical solution. An anti-oxidation insulating film deposition step of depositing an anti-oxidation insulating film so as to cover the upper surface of the variable resistor after the oxidation step;
Wherein after completion oxidation-preventing insulating film deposition process, the oxidation-preventing insulating film, any of the variable resistor, and claims 5 to claim 13, characterized in that it comprises a patterning step of patterning process to the conductive film A method for manufacturing the variable resistance element according to claim 1. The method for manufacturing a variable resistance element according to claim 14 , wherein the antioxidant insulating film is an insulating film containing nitrogen or carbon. Manufacturing method for a variable resistance element according to any one of claims 5 to claim 15, wherein the conductive film deposition step, characterized in that a step of depositing the conductive layer by directional sputtering method. The variable resistance element according to any one of claims 5 to 15 , wherein the conductive film deposition step is a step of depositing the conductive film by a lamination method of CVD film formation and sputter film formation. Manufacturing method. Manufacturing method for a variable resistance element according to any one of claims 1 to 17, wherein the conductive film is titanium nitride.

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