JP4646859B2 - USB device and USB connection system - Google Patents

Description

The present invention relates to a USB device and a USB connection system that connect a host device and a USB device with a USB cable, for example , and execute a forced operation such as a hard reset when the system runs away.

  Conventionally, an ATM installed in a financial institution is connected to a host device through a communication line. In this ATM, an internal communication failure may occur due to a line abnormality or an internal module hang-up. This internal communication failure has a certain frequency in the field and is difficult to eliminate completely.

  For this reason, the existing ATM is provided with a recovery means using a dedicated AC power ON / OFF function. Since this recovery means uses a dedicated line for recovery, the cost is inevitably increased.

  Under such circumstances, in recent years, there has been a movement to introduce a highly versatile USB (Universal Serial Bus) as ATM internal communication.

  In a USB connection device, as a method of executing a reset in the event of a communication failure or CPU runaway to restore a USB device, a device that adds a dedicated line in addition to the USB line and resets the USB device via this dedicated line A control system has been proposed (see Patent Document 1). However, the method of resetting via a dedicated line in addition to the USB line as described above has a problem that a significant increase in cost is caused by providing a separate dedicated line, and a general-purpose USB device must be modified.

  As another method for recovering a USB device by executing a reset, a USB device that detects a reset on the USB line and automatically resets the USB device when a communication abnormal state is found has also been proposed. . (See Patent Document 2).

  There has also been proposed a system that detects a bus reset signal (SE0) on the USB line and executes a recovery from the energy saving state of the USB device or a self-reset operation. (See Patent Document 3).

  On the other hand, devices that require high reliability, such as ATM, need not only to have a function to intentionally reset and recover when there is a communication failure or CPU runaway, but also to prevent reset at unintended timing There is. That is, there is a need for a function that ignores the reset signal and does not execute the reset even when the USB connector is disconnected or when the power is turned off or during the startup of the operating system.

  However, in the method of detecting the bus reset signal (SE0) on the USB line and automatically resetting the USB device, the USB device always executes reset when the USB line is in the bus reset state. For this reason, even if the reset should not be executed originally, the self-reset is executed unconditionally, and there is a problem that the communication quality of the USB is impaired.

  Also, in the method of detecting the bus reset signal (SE0) on the USB line and checking the state of the CPU to execute self-reset, the USB line is disconnected when the USB connector is disconnected or when the host power is turned off. Since the signal becomes the same as the bus reset signal (SE0), there is a problem that the state of the CPU changes or self-reset is executed.

  In an automatic machine such as ATM that requires high reliability, when the USB connector is disconnected, it is necessary to perform an abnormal process as a transmission line connection error. However, as described above, if the self-reset is executed at an unintended timing when the USB connector is disconnected, correct abnormality processing cannot be performed and a problem may occur. Specifically, for example, after the reset is canceled and the CPU is restarted, there is a possibility that a problem such as inconsistency occurs in the position information of the banknote that has been in the middle of the transfer until then in the ATM.

  In addition, if a self-reset is executed in the built-in device when the power is turned off, there is a problem that a connection error is erroneously recognized after the CPU is restarted. In detail, powering off the ATM does not turn off all the power of each built-in device at the same time. First, turn off the power to the main control unit having the USB host controller, and then turn on the power to each built-in device. Turn off. Therefore, if a self-reset is executed for the built-in device when the power is turned off as described above, the USB host is already turned off if the reconnection operation with the USB host is executed after the reset is released and the CPU is restarted. Therefore, it will be erroneously recognized as a connection error.

JP 2003-131956 A JP 2002-373036 A JP-A-2005-352942

In view of the above-described problems, the present invention can execute operation control such as hard reset from a host to a USB device using a standard USB cable, and can perform reset operation when the USB connector is disconnected or the power is turned off. An object is to provide a USB device that is not executed and a USB connection system , and to ensure high reliability in the USB device.

  The present invention is a USB device that connects to a host via a USB cable and performs data communication, the reset signal receiving unit receiving a reset signal from the host via the USB cable, and the host from the host via the USB cable. A USB device comprising: a power supply state determination unit that determines a state of power supply to be performed; and a reset execution unit that receives the reset signal and executes a reset when the power supply is not cut off It is characterized by.

According to the present invention, a USB device that can execute an operation control such as a hard reset from a host to a USB device using a standard USB cable, and that does not execute a reset operation when the USB connector is disconnected or turned off , and A USB connection system can be provided, and high reliability in a USB device can be realized.

An embodiment of the present invention will be described below with reference to the drawings.
First, the configuration of the USB connection system 1 will be described with reference to the entire block diagram shown in FIG.

  In this embodiment, the USB connection system 1 is constituted by the entire ATM, the host 10 is constituted by an ATM main control unit, and the USB device 30 is constituted by each device incorporating the ATM. USB is used as internal transmission of ATM.

  The USB connection system 1 is configured by connecting a host 10 and a USB device 30 via a USB hub 20 with a USB cable 25. The USB hub 20 includes a USB cable 25 for USB connection to the host 10 and a plurality (four in the illustrated example) of USB ports 21 to which the USB cable 25 for connecting the USB device 30 can be attached and detached. As a result, a plurality of USB devices 30 can be controlled by a single host 10.

  The USB cable 25 is a cable for performing data transmission according to the USB standard, and includes a VBUS line 25a, a D + line 25b, a D- line 25c, and a GND line 25d.

The VBUS line 25a is a power supply line that supplies 5V power.
The D + line 25b and the D− line 25c are signal lines through which the host 10 and the USB device 30 transmit / receive data.
The GND line 25d is a 0V reference potential line.

  The host 10 includes a USB host controller 11 that controls communication with the USB device 30 via the USB cable 25.

  The USB device 30 is provided with a USB device controller 31 as USB communication means to which the VBUS line 25a, D + line 25b, and D- line 25c in the USB cable 25 are connected. A VBUS state monitoring circuit 35 is connected to the VBUS line 25a in parallel with the USB device controller 31.

  A reset execution determination circuit 34 is connected to the subsequent stage of the USB device controller 31 and the VBUS state monitoring circuit 35. A CPU 32 is also connected to the subsequent stage of the USB device controller 31.

  A USB device controller 31, a reset circuit 33 as a soft reset execution unit and a hard reset execution unit, and a reset execution determination circuit 34 are connected to the subsequent stage of the CPU 32. The USB device controller 31 and the CPU 32 are connected to the subsequent stage of the reset circuit 33.

The CPU 32 is a main control unit of the USB device 30 and executes various control operations of the entire USB device 30.
As one of the control operations, the CPU 32 performs a first initial setting for the USB device controller 31 immediately after the power is turned on. In the first initial setting, only the setting for enabling USB communication between the USB host controller 11 and the USB device controller is performed, and the USB device controller 31 is set not to send the interrupt signal INT1 when the bus reset signal (SE0) is received. .
Further, the CPU 32 confirms the establishment of the USB connection by responding to the vendor request to the host 10, and then performs the second initial setting for the USB device controller 31. In the second initial setting, the USB device controller 31 is set to send the interrupt signal INT1 when the bus reset signal (SE0) is received.
Here, the bus reset signal (SE0) indicates a state in which the host 10 outputs 0V to D + and D−, which are signals in the USB cable 25, for a predetermined time or more.

When the USB device controller 31 detects the bus reset signal (SE0), the USB device controller 31 executes a process of sending an interrupt signal INT1 to the CPU 32 and the reset execution determination circuit 34.
When the USB device controller 31 detects that the state of the VBUS line 25a has changed from a high level (a state where 5V power is supplied) to a low level (a state where no 5V power is supplied), the USB device controller 31 sends an interrupt signal INT0 to the CPU 32. Send to

  The VBUS state monitoring circuit 35 monitors whether the state of the VBUS line 25a is at a high level or a low level.

  After detecting the interrupt signal INT1, the CPU 32 executes necessary data storage processing and the like before resetting, and at the same time as a soft reset start time (hereinafter referred to as 500 mS for explanation of the operation. Whether or not to execute a soft reset.

  If the interrupt signal INT0 is received from the USB device controller 31 within a certain time (500 mS), it can be determined that the VBUS signal from the VBUS line 25a has become a low level. It is determined that the interrupt signal INT1 by SE0) has been received, and the soft reset is not executed. At the same time, the reset execution determination circuit 34 stops the reset execution determination operation.

  On the other hand, if the interrupt signal INT0 is not received from the USB device controller 31 within a predetermined time (500 mS), the CPU 32 executes a soft reset.

  After receiving the interrupt signal INT1 from the USB device controller 31, the reset execution determination circuit 34 determines whether or not to send a reset execution signal to the reset circuit 33 for a fixed time (hereinafter, referred to as reset stop time). For the explanation of the operation, it is 1 second, but this is not the case).

  When a reset prohibition signal is received from the VBUS monitoring circuit 35 within a certain time (1 second) or when a reset execution determination operation stop signal is received from the CPU 32, the reset execution determination circuit 34 stops the determination operation, A reset signal is not sent to the reset circuit 33.

  On the other hand, if the reset prohibition signal is not received from the VBUS state monitoring circuit 35 within a certain time (1 second), the interrupt signal INT1 is sent from the USB device controller 31 by the bus reset signal (SE0) sent from the host 10. However, the CPU 32 is out of control and determines that the software reset cannot be executed, and sends a reset signal to the reset circuit 33.

  When the reset circuit 33 receives a hard reset execution signal from the reset execution determination circuit 34 or a soft reset signal from the CPU 32, the reset circuit 33 issues a reset signal to the entire USB device.

  With the above configuration, when the USB device 30 receives the bus reset signal (SE0) received from the host 10, the USB device 30 monitors the state of the VBUS signal to reset in the bus reset state when the USB connector is disconnected or the power is turned off. Can be executed only when the bus reset signal (SE0) sent from the host 10 is received. The reset circuit 33 and the VBUS state monitoring circuit 35 function as reset forcing means for forcibly executing reset.

  Next, the operation of the USB device 30 will be described together with the flowchart shown in FIG. 2 and the timing charts shown in FIGS. 3, 4, and 5.

  First, when the host 10 outputs a bus reset signal (SE0) and the USB device controller 31 receives the bus reset signal as shown at timing A (see FIG. 3) (step S1), the USB device controller 31 receives the CPU 32. Then, the interrupt signal INT1 is output to the reset execution determination circuit 34 (step S2). Here, the USB device controller 31 that executes step S1 functions as a reset signal receiving means.

When receiving the interrupt signal INT1 from the USB device controller 31, the CPU 32 enters a soft reset execution waiting state for 500 ms (step S3).
When the reset execution determination circuit 34 receives the interrupt signal INT1 from the USB device controller 31, the reset execution determination circuit 34 enters a reset effective waiting state for one second (step S4).

  On the other hand, the USB device controller 31 detects that the output of the VBUS line 25a has changed from the High level to the Low level (that is, the power supply has been cut off) as shown in the timing B (see FIG. 4) (step S5). ), An interrupt signal (INT0) is output to the CPU 32 (step S6). Here, the USB device controller 31 executing step S5 functions as a power supply state determination unit.

  The VBUS monitoring circuit 35 monitors whether the output of the VBUS line 25a is at the high level or the low level (step S7), and transmits the output state of the VBUS line 25a to the reset execution determination circuit 34. To do.

  When the CPU 32 receives the interrupt signal INT0 from the USB device controller 31 within the waiting time of 500 ms (step S8: Yes), it issues a reset prohibition signal to the reset circuit 33 (step S9).

  On the other hand, if the interrupt signal INT0 has not been received (step S8: No), a soft reset signal is issued to the reset circuit 33 after a waiting time of 500 ms as shown in timing C (see FIG. 3) (step S10). ) And the determination operation stop for the reset execution determination circuit 34 (step S11).

  When the reset execution determination circuit 34 detects the low level of the VBUS line 25a within the waiting time of 1 second (step S12: Yes), it issues a reset prohibition signal to the reset circuit 33 (step S13).

  On the other hand, when the low level of the VBUS line 25a is not detected during the 1 second waiting time (step S12: No), as shown in the timing D (see FIG. 4), the hard reset signal is output after the completion of the 1 second waiting time. Is issued (step S14).

  When the reset circuit 33 receives the reset prohibition signal in step S9 or S13, the reset circuit 33 does not reset the USB device 30 (step S15) and maintains the current operation state.

  On the other hand, when the reset signal of step S10 or S14 is received, the reset circuit 33 resets the USB device 30 (step S15). At this time, when a soft reset signal is received, a soft reset is executed for the USB device 30, and when a hard reset signal is received, a hard reset (entire reset) is executed for the USB device 30.

  One of the soft reset and the hard reset is executed. More specifically, when a bus reset signal (SE0), which is a reset signal, is issued from the host 10, the USB device controller 31 of the USB device 30 detects the bus reset signal (SE0) and, as shown at timing A, An interrupt signal INT1 is output.

  If there is no change in the VBUS signal from high to low during 500 ms waiting for soft reset execution, that is, if no interrupt signal INT0 is received, a soft reset signal is issued as shown in timing C, and the USB device 30 is issued. To reset. At the same time, the reset determination operation is stopped for the reset execution determination circuit 34.

  When this soft reset is executed, the operation after timing C in FIG. 3 is canceled by the soft reset as shown by hatching in the figure, so that the hard reset execution wait count is also canceled and the hard reset is not executed. .

  In addition, if the CPU 32 runs out of control upon receiving the interrupt signal INT0, a soft reset signal cannot be issued at timing C. However, since a hard reset signal is issued at timing D in FIG. 4, a hard reset is performed on the USB device 30.

  Further, when the USB device controller 31 receives a bus reset signal (SE0) due to a connector disconnection or a bus reset state when the power is turned off, the reset operation cannot be executed.

  More specifically, when detecting the bus reset signal (SE0), the USB device controller 31 outputs an interrupt signal INT1 as shown at timing A in FIG. If the VBUS signal changes from High to Low during 500 ms waiting for soft reset execution, an interrupt signal INT0 is output as shown in timing B of FIG. 5, and the CPU 32 issues a reset prohibition signal. As a result, even if a hard reset signal is issued as shown at timing D, the USB device 30 is not reset.

  Even when the CPU 32 cannot issue the reset prohibition process at the timing B, the VBUS state monitoring circuit 35 detects the VBUS low level and issues a reset prohibition signal at the timing B. Do not perform a reset.

  As a result of the above operation, when the bus reset signal is received when the USB connector is disconnected or the power is turned off, the USB device 30 is not reset, and the host 10 issues a bus reset signal (SE0) issued to recover the failure of the USB device 30. ) Only, a reset can be issued to the USB device 30 and the failure of the USB device 30 can be recovered.

FIG. 6 is a flowchart of the operation of invalidating the bus reset signal (SE0) during the activation of the BIOS or the operating system.
When the host 10 and the USB device 30 are powered on (step S21), the CPU 32 of the USB device 30 performs the first initial setting for the USB device controller 31. In the first initial setting, setting for enabling USB connection with the host 10 is performed, and output of the interrupt signal INT1 to the USB device controller 31 is prohibited (step S31).

  Accordingly, even if the bus reset signal is received during the activation of the BIOS or during the activation of the operating system, the USB device controller 31 does not issue the interrupt signal INT1, and therefore the USB device 30 is not reset.

  Thereafter, the operation system of the host 10 is activated (step S22), and when the host 10 detects a USB device (in this embodiment, the USB device 30) (step S23: detected), the host 10 connects to the USB device 30 via USB connection. Is established (step S24). At this time, the CPU 32 performs setting again as the second initial setting for the USB device controller 31, and at this time, the output of the interrupt signal INT1 is changed to be valid (step S32). The CPU 32 executing this step S32 functions as a reset execution enable / disable switching unit.

The host 10 activates an appropriate application (step S25), and ends the power ON process. Thereafter, when a normal response does not return from the USB device 30, the host 10 is configured to transmit a bus reset signal to the USB device 30 to execute a reset operation.
The USB device 30 waits for detection of a bus reset (SE0) (step S33). When the bus reset (SE0) is detected thereafter, the USB device 30 executes the reset process described with reference to FIG.

  With the above operation, the host 10 can prevent the reset operation from being executed at a timing unnecessary for the USB device 30, that is, before the USB connection between the host 10 and the USB device 30 is established.

  That is, the signal of the USB cable 25 may be in the bus reset (SE0) state several times during the activation of the BIOS or during the activation of the operating system. In such a case, the reset can not be performed.

  As a result, errors on the operating system can be prevented. More specifically, for example, when the USB device 30 self-resets due to a bus reset during the BIOS startup, the USB connection system 1 is released from the reset state, and before the CPU 32 restarts, the next bus reset (SE0) state is entered. There is. At this time, although the USB host controller 11 recognizes the USB device 30 at the first bus reset, it cannot recognize the USB device 30 at the second bus reset. In such a case, an error occurs in the operating system, but this can be avoided by the above-described operation.

FIG. 7 is a flowchart showing an operation of a retry process when the host 10 executes a bus reset.
When a communication error occurs in communication with the USB device 30, the USB host controller 11 of the host 10 transmits a bus reset signal (SE 0) to the USB device 30 (step S 41).

  If the reconnection between the host 10 and the USB device 30 is completed before the waiting time that is a predetermined time elapses, that is, the host 10 transmits a signal to the USB device 30 and the host 10 transmits the signal to the USB device 30. If a normal response signal can be obtained from (step S42: Yes), the USB host controller 11 terminates the reset process as normal termination (step S43).

  When reconnection is not possible, that is, when a normal response signal is not obtained from the USB device 30 (step S42: No), the USB host controller 11 determines whether or not the retry process has been executed a predetermined number of times. (Step S44).

  If the set number of retry processes has not been executed (step S44: No), the USB host controller 11 executes the retry process and returns the process to step S41 (step S45). In this retry process, the process is returned to step S41 to repeat the bus reset and increase the number of retries by one. The SB host controller 11 that executes the retry process functions as a retry unit.

  If retry processing for the set number of times has been executed (step S44: Yes), the USB host controller 11 ends the processing as abnormal termination (step S46).

  With the above operation, even if the host 10 and the USB device 30 cannot be connected by a single bus reset, the reset process can be executed again to reconnect. If this reconnection attempt is repeated for a set number of times and if reconnection is not possible, it can be terminated abnormally.

  With the configuration and operation described above, the USB device 30 can execute the reset operation based on the reset signal. Therefore, for example, a hard reset of the entire USB device 30 can be performed, and the availability can be increased.

  In addition, the USB device 30 can be forced to execute a reset operation based on a bus reset signal from the host 10, and a reset operation can be prohibited for an unintended bus reset signal, thereby realizing a highly reliable system. Is possible.

  Further, even when the USB cable 25 is in the same state as the bus reset when the USB connector is disconnected or the power is turned off, the reset operation is not executed, and the reset is performed only in response to an arbitrary reset signal to the VBUS state monitoring circuit 35. Can be executed.

  The host 10 may be configured to execute a retry process of transmitting a reset signal again when a communication error is not resolved even after a predetermined time has elapsed after transmitting a bus reset signal. As a result, the host 10 can reliably recover from the failure of the USB device 30.

  In addition, the USB connection system 1 may be used in a personal computer or the like without being limited to the ATM example. In this case, for example, a personal computer can be used as the host 10 and a scanner, a printer, or the like can be used as the USB device 30, and the USB device 30 can be forced to execute a reliable reset process or reset prohibition process.

  In addition, this invention is not limited only to the structure of the above-mentioned embodiment, Many embodiments can be obtained.

The block diagram of the whole USB connection system. The flowchart which shows operation | movement of a USB connection system. The timing chart which shows the timing of reset. The timing chart which shows the timing of reset. The timing chart which shows the timing of reset. The flowchart of the operation | movement which invalidates the bus reset signal in the middle of starting. The flowchart of operation | movement of the retry process of a bus reset.

DESCRIPTION OF SYMBOLS 1 ... USB connection system, 10 ... Host, 25 ... USB cable, 30 ... USB apparatus, 31 ... USB device controller, 32 ... CPU, 33 ... Reset circuit

Claims (6)

A USB device that communicates with a host via a USB cable for data communication,
Reset signal receiving means for receiving a reset signal from the host through the USB cable;
Power supply state determination means for determining a state of power supply performed from the host via the USB cable;
A USB device comprising: a reset execution means for receiving the reset signal and executing a reset when the power supply is not interrupted. The reset execution means performs a soft reset execution means for executing a soft reset by software based on a soft reset signal received via the USB cable, and a hard reset for forcibly performing a reset operation based on the reset signal Hard reset execution means to
The hard reset execution means is configured to execute a hard reset after elapse of a fixed time longer than a soft reset start time at which the soft reset execution means starts executing a soft reset after receiving the reset signal by the reset signal receiving means. The USB device according to claim 1. 3. The USB device according to claim 1, further comprising: a reset execution enable / disable switching unit that switches the reset by the reset execution unit from an inexecutable state to an executable state when connection with the host is established. 4. The USB device according to claim 3, wherein the reset execution enable / disable switching unit is configured to switch a reset by the reset execution unit to an inexecutable state when the power is turned on. A USB connection system in which a host device and a USB device are connected by a USB cable,
In the USB device,
Reset signal receiving means for receiving a reset signal from the host through the USB cable;
Power supply state determination means for determining a state of power supply performed from the host via the USB cable;
A reset execution means for receiving the reset signal and executing a reset when the power supply is not cut off;
In the host device,
An error state determination means for determining an error state in which a normal response does not return from the USB device;
A USB connection system comprising reset signal transmission means for transmitting a reset signal to the USB device when it is determined in the error state determination process that an error state has occurred. 6. The USB connection system according to claim 5, further comprising retry means for executing a retry process of transmitting the reset signal again when the error state is not resolved even after a predetermined time has elapsed since the reset signal was transmitted.

Images