JP4642030B2 - Semiconductor device and control method thereof - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a technique that enables a high-speed operation and a sufficient operation margin of a semiconductor memory having a dual operation function.

  Flash memory has been rapidly spreading in recent years as an electrically rewritable semiconductor memory device, and stores NAND type and programs used for data storage represented by memory cards and is built into electronic devices. It is classified as NOR type. In a typical NOR flash memory, data (“1” or “0”) is stored depending on whether or not charges are accumulated in the floating gate. A unit cell of such a NOR flash memory is composed of one MOS transistor, and includes a control gate (upper gate) and a floating gate (lower gate).

In an operation of reading (reading) data from a specific memory cell, a positive bias (for example, 5 V) is applied to the control gate of the selected memory cell, and a bias of about 1 V is applied to the drain from the sense amplifier. When there is an electric charge in the floating gate, the bias applied to the control gate is canceled by the electric charge accumulated in the floating gate, and the memory cell does not pass a cell current (non-conducting) and reads data “0”. Conversely, when there is no charge in the floating gate, the bias applied to the control gate does not cancel out, so that the memory cell passes a cell current (conduction) and reads data “1”. The sense amplifier reads these cell currents and outputs data “0” or “1” as a voltage. At this time, the larger the difference between the cell current I _c1 at the time of data “1” and the cell current I _c0 at the time of data “0”, the easier it is for the sense amplifier to read, and it is possible to increase the operation speed and the operation margin. Become.

  FIG. 1 is a block diagram for explaining the configuration of a sense amplifier. A selected memory cell 11a is connected to a sense amplifier 13a via a decoder 12a. On the other hand, the reference cell 11b for data reference is connected to the sense amplifier 13b via the decoder 12b, and the sense amplifier 13a and the sense amplifier 13b are connected to the differential sense amplifier 17, so that the memory cell 11a becomes the reference cell 11b. It is connected. In this figure, 14a and 14b, 15a and 15b, and 16a and 16b are a source switch, parasitic resistance, and ground (GND) connected to the memory cell 11a and the reference cell 11b, respectively.

Here, a parasitic resistance 15a due to wiring or the like exists between the memory cell 11a and the GND 16a. When the cell current I _c in the parasitic resistance 15a flows, the potential of the source switch 14a that is connected to the memory cell 11a (i.e., the source potential) rather than the GND level, the product of the parasitic resistance value R and the cell current I _c It has a given V _s (= I _c · R). In general, since the memory cell is an n-channel transistor, the cell current I _c is given by I _c = β · V _ds (V _gs −V _t −V _ds / 2). Here, β is a proportional constant, V _gs is a gate-source voltage, V _ds is a drain-source voltage, and V _t is a threshold voltage. According to the above equation, it can be understood that when the source potential V _s increases, the cell-current I _c decreases because the gate-source voltage V _gs and the drain-source voltage V _ds decrease. Since the cell current I _c with miniaturization of the device so that the inevitably reduced, impact of variation of the source potential V _s will be gradually increased along with the miniaturization of elements with respect to the read operation.

  By the way, in the conventional flash memory, the read operation by the processor cannot be executed while the write operation or the erase operation is in progress, and the flash memory status register is periodically polled before the read operation to the flash memory is started. For example, the end of the writing operation or the erasing operation must be detected, so that there has been a problem that data rewriting is extremely slow and unusable compared to a memory such as a DRAM or SRAM. In order to alleviate this problem, a dual operation function has been introduced in which other data can be read while data is programmed or erased (rewritten).

  FIG. 2 is a block diagram for explaining an internal configuration example of a conventional flash memory having a dual operation function that enables the above-described simultaneous operation. In this configuration, the memory cell array is divided into several banks (four in FIG. 2), and data from another bank can be read while one bank is rewriting data. .

  This memory cell array 200 includes four banks of memory cells of the 0th bank 201, the 1st bank 202, the 2nd bank 203, and the 3rd bank 204, and for address reading (AR) and address writing provided in each bank. Read address switch and write address switch (AR0 to AR3 and AW0 to AW3) for read-in (AW) and read data switch and write data switch (DR0 to DR3 and DW0) for data read (DR) and data write (DW) To DW3), source switches S0 to S3 provided in association with individual banks for connecting the four banks to the read reference 205 and / or the write reference 206, and connected to the ground terminal 212, and for data reading Sense amplifier 207a and output A data read sense amplifier block 207 having a circuit 207b and connected to the read reference 205, a write sense amplifier 208a, a write circuit 208b, and an erasing circuit 208c and having a circuit connected to the write reference 206. A sense amplifier block 208, an address buffer 209 having an address terminal 211 and connectable to four banks, a data read sense amplifier block 207, a data write sense amplifier block 208, and a controller 210 connected to the address buffer 209; An output circuit 207b provided in the data read sense amplifier block 207 and an I / O terminal 213 connected to the write circuit 208b provided in the data write sense amplifier block 208 are provided.

  That is, the memory cell array 200 is a read circuit that reads data from each bank 201 to 204 in order to realize a dual operation function in which other data can be read while programming or erasing (rewriting) data. One of the write circuits for performing data rewriting can be connected, and the read circuit is connected only to the bank that performs read, while the write circuit is connected only to the bank that performs write. As a result, the read operation during the write operation can be executed simultaneously.

  Here, the write operation includes a verify operation for verifying whether writing or erasing has been performed to a predetermined level, which is essentially the same as the read operation. Although the read operation may be performed during the verify operation, in the configuration in which the ground wiring is commonly used for the read and write as in the configuration illustrated in FIG. 2, only one of the read and the verify is being executed. As a result, the current flowing in the ground wiring increases more than the time, and the voltage drop due to the parasitic resistance also increases. For this reason, the source potential of each memory cell selected by reading or writing rises more than when only one of reading or verifying is being executed, leading to a decrease in cell current. As a result, as described above, the read speed of the read or verify operation decreases and the margin decreases.

  The present invention eliminates the above-mentioned disadvantages of a conventional flash memory having a dual operation function, and enables a high-speed operation and a sufficient operation margin regardless of whether or not the dual operation operation is performed. The purpose is to provide.

In order to solve such a problem, the present invention provides a semiconductor device operable simultaneously in a data read mode and a verify mode , and a first ground wiring for grounding an internal circuit of the semiconductor device in the data read mode . In the second operation mode, the semiconductor device is independently provided with a second ground wiring for grounding the internal circuit. The internal circuit includes a plurality of banks, and the first and second ground lines are provided in common to the plurality of banks independently of each other. One first bank of the plurality of banks operates in the data read mode, and in parallel, the second bank of the plurality of banks operates in the write mode. The first bank is connected to the first ground wiring, and the second bank is connected to the second ground wiring in the verify mode of the write mode.

  This semiconductor device can have a configuration having a first ground terminal connected to the first ground wiring and a second ground terminal connected to the second ground wiring.

  In the semiconductor device, the first ground wiring and the second ground wiring may have substantially the same length.

Before Symbol semiconductor device may be configured to have a switch for connecting said plurality of banks to selectively said first and second ground wiring.

  In the semiconductor device, each of the plurality of banks may include a plurality of nonvolatile memory cells.

  In the semiconductor device, the semiconductor device is, for example, a nonvolatile semiconductor memory device.

The present invention also relates to a method for controlling a semiconductor device including a plurality of banks and capable of simultaneously operating in a write mode including a data read mode and a verify mode, wherein a plurality of first banks are provided in the data read mode. in the step of grounding through the first ground wiring provided commonly for the banks, the second bank of Oite plurality of banks in verify mode in the write mode, common and first into a plurality of banks And grounding via a second ground wiring provided independently of the ground wiring.

  In the semiconductor memory device of the present invention, since the read ground and the write write ground are provided independently, the source potential of the memory cell is either read or verified even if the read and verify operations are performed simultaneously. Only one of the potentials can be made equal to the potential during execution, and a stable read operation can be realized at a high speed and with an increased margin regardless of whether or not the operation is a dual operation.

It is a block diagram for demonstrating the structure of a sense amplifier. It is a block diagram for demonstrating the example of an internal structure of the conventional flash memory provided with the dual operation function which enables simultaneous operation. It is a block diagram for demonstrating the internal structural example of the flash memory of this invention. (A) and (b) show the state of each switch when the first bank is caused to perform a read operation when the second bank is in a write operation in the flash memory having the configuration shown in FIGS. It is a figure for demonstrating. (A) And (b) is a figure which shows the mode of the source potential at the time of making a 2nd bank perform read-out operation when the 3rd bank is performing write-in operation | movement.

  The semiconductor memory device of the present invention will be described below with reference to the drawings. In the following description, the semiconductor memory device is assumed to be a NOR flash memory.

  FIG. 3 is a block diagram for explaining an internal configuration example of the flash memory according to the present invention. In this flash memory, a read ground 312a and a verify write ground 312b are provided independently. As a result, even if the read and verify operations are performed simultaneously, the source potential of the memory cell can be made equal to the potential when only one of the read and verify operations is being performed. Therefore, a stable read operation can be realized at a high speed by increasing the margin.

  Referring to FIG. 3, the memory cell array 300 includes four banks of memory cells of the 0th bank 301, the 1st bank 302, the 2nd bank 303, and the 3rd bank 304, and an address read (AR) provided in each bank. ) And address write (AW) read address switches and write address switches (AR0 to AR3 and AW0 to AW3) and data read (DR) and data write (DW) read data switches and write data switches ( DR0 to DR3 and DW0 to DW3), read source switches SR0 to SR3 provided in association with the four banks and connected to the read ground terminal 312a, and write ground provided in association with the individual banks. Light source switch connected to terminal 312b SW0 to SW3, a data read sense amplifier 307a having a data read sense amplifier 307a and an output circuit 307b, connected to the read reference 305, a data write sense amplifier 308a, a write circuit 308b, and an erase circuit 308c. , A data write sense amplifier block 308 connected to the write reference 306, an address buffer 309 having an address terminal 311 and connectable to four banks, a data read sense amplifier block 307, and a data write sense amplifier The controller 310 connected to the block 308 and the address buffer 309, the output circuit 307b provided in the data read sense amplifier block 307, and the write circuit provided in the data write sense amplifier block 308 And I / O terminal 313 to be connected to the 308b, and a.

  In the configuration example shown in FIG. 3, the cell array is divided into four banks (301 to 304), and a decoder circuit (not shown) is provided in each bank. Even in this configuration, the read operation is not different from the conventional structure when not in the write state. An address to be read is designated and inputted to the address terminal 311 from the outside, and the address buffer 309 outputs this signal as a read address. The controller 310 operates the switch group so as to transmit the read address only to the selected bank. In the bank selected by the read address, the memory cell corresponding to the address is selected by the decoder. The controller 310 operates the switch group so as to connect only the selected bank to the sense amplifier 307a of the read circuit. As a result, the data in the memory cell is determined by the sense amplifier 307a, and the result is output to the I / O terminal 313 via the output circuit 307b to execute the read operation. At this time, the ground wiring 320 through which the cell current flows is connected to the read ground terminal 312a, and no current flows through the write ground terminal 312b. A ground wiring 322 through which a cell current flows is connected to the write ground terminal 312b. The ground lines 320 and 322 are provided in common to the banks 301 to 304, respectively. The ground wiring 320 is connected to a read ground terminal 312a, and the ground wiring 322 is provided with a write ground terminal 312b. The ground wirings 320 and 322 may have different lengths, but are preferably substantially the same length. The read ground terminal 312a and the write ground terminal 312b may constitute independent external connection terminals, or may be connected to form a single external connection terminal. In the latter case, the read and write switch groups are arranged as close as possible to the common external connection terminal. Note that the read and write operations can be defined as the first and second operation modes, respectively.

  On the other hand, when the device is in the write state, the controller 310 causes the address buffer 309 to output the write address, and operates the switch group so that the write address is transmitted only to the selected bank. At the same time, the switch group is operated so as to connect the sense amplifier 308a, the write circuit 308b, and the erase circuit 308c of the write circuit as necessary. The selected bank rewrites the data in the memory cell corresponding to the designated address. Here, considering a case where a read operation is performed during the verify operation, first, an address to be read during the verify operation is input to the address terminal 311 from the outside. The controller 310 operates the address buffer 309 and the switch group so that this address is transmitted only to the bank in which the read is selected as a read address independent of the verify address. After that, as in the case of only the read operation described above, the memory cell corresponding to the read-selected bank is selected and connected to the sense amplifier 307a, and after determining the data, the data is transferred to the I / O terminal. To 313. At this time, the cell current in the read operation and the cell current in the verify operation flow through the read ground terminal 312a and the write ground terminal 312b, respectively. However, since these two currents pass through independent paths, Each value is the same as the current value in the case of only the read operation or the write operation, and the current value in the dual operation does not increase unlike the conventional configuration.

  FIG. 4A shows the state of each switch when the first bank 302 is caused to execute a read operation when the second bank 303 is in the write operation in the flash memory of the present invention having the configuration shown in FIG. It is a figure for demonstrating. It is obvious that the operation at the time of dual operation by any combination of other banks can be executed in the same manner as the example described below by setting the switch to be turned on / off as the corresponding switch of each bank. is there. For comparison, in the flash memory having the conventional configuration shown in FIG. 2, the state of each switch when the first bank 202 is caused to perform a read operation when the second bank 203 is performing a write operation is illustrated. This is shown in 4 (b). 5A and 5B show a case where the first bank is caused to execute a read operation when the second bank is performing a write operation (that is, FIG. 4A and FIG. 4). The state of the source potential (corresponding to the switch state of (b)) is shown.

  Referring to FIG. 4A, the write address switch AW2 and the write data switch DW2 of the second bank 303 during the write operation are turned on, and are electrically connected to the address buffer 309 and the write reference 306. Further, when the write source switch SW2 is turned on, the second bank 303 is connected to the write ground 312b. On the other hand, the read address switch AR1 and the read data switch DR1 of the first bank 302 that executes the read operation are turned on, and are electrically connected to the address buffer 309 and the read reference 305. Further, when the read source switch SR1 is turned on, the first bank 302 is connected to the read ground 312a. All other switches are off.

  In order to perform reading of the first bank 302, the address of the memory cell belonging to this bank is designated and inputted from the outside to the address terminal 311, and this signal is output as a read address by the address buffer 309. The controller 310 operates the switch group as shown in FIG. 4A so as to transmit only to the first bank 302. The controller 310 operates the switch group so as to connect only the selected first bank 302 to the sense amplifier 307a of the read circuit. As a result, the data in the memory cell is determined by the sense amplifier 307a, and the result is output to the I / O terminal 313 via the output circuit 307b to execute the read operation. At this time, the ground wiring 320 through which the cell current flows is connected to the read ground terminal 312a, and no current flows through the write ground terminal 312b.

  On the other hand, during the write operation (programming or erasure) of the second bank 303, the controller 310 outputs the write address to the address buffer 309 so that the write address is transmitted only to the selected second bank 303. Operate the switch group. At the same time, the switch group is operated so as to connect the sense amplifier 308a, the write circuit 308b, and the erase circuit 308c of the write circuit as necessary. The selected second bank 303 rewrites the data in the memory cell corresponding to the designated address. Here, considering a case where a read operation is performed during the verify operation, first, an address to be read during the verify operation is input to the address terminal 311 from the outside. The controller 310 operates the address buffer 309 and the switch group so that this address is transmitted only to the first bank 302 that is read-read as a read address independent of the verify address. After that, as in the case of only the read operation described above, the read-selected first bank 302 selects the corresponding memory cell and connects it to the sense amplifier 307a, determines the data, and then converts the data to I / O terminal 313 for output. At this time, the cell current in the read operation and the cell current in the verify operation flow through the read ground terminal 312a and the write ground terminal 312b, respectively. However, since these two currents pass through independent paths, Each value is the same as the current value in the case of only the read operation or the write operation, and the current value does not increase in the dual operation.

  As described above, in the flash memory according to the present invention, the read ground 312a and the verify write ground 312b are provided independently. Therefore, as shown in FIG. 5A, the read and verify operations are executed simultaneously. Even if this is done, it becomes possible to make the source potential of the memory cell equal to the potential when only one of read or verify is being executed, and stable read by increasing the margin at high speed regardless of whether or not it is a dual operation operation. Operation is realized.

  On the other hand, in the conventional configuration shown in FIG. 4B, since the ground wiring is used in common for reading and writing, only one of the read and verify flows to the ground wiring than during execution. The current increases, and the voltage drop due to parasitic resistance also increases. As a result, as shown in FIG. 5B, the source potential of each memory cell selected by reading or writing rises higher than when only one of reading or verifying is being executed and the cell current is increased. Will lead to a decrease.

  As described above, in the semiconductor memory device of the present invention, high-speed reading of a read operation and a sufficient operation margin can be ensured regardless of whether or not a dual operation operation is being performed.

As described above, the present invention provides a technique that enables a high-speed operation and a sufficient operation margin of a semiconductor device having a dual operation function. The present invention includes not only a semiconductor memory device such as a flash memory, but also a semiconductor device such as a system LSI having a storage unit with the above-described configuration.

Claims (7)

A semiconductor device capable of simultaneously operating in data read and verify modes,
An internal circuit having a plurality of banks each having a plurality of memory cells;
A first ground wiring for grounding the internal circuit in the data read mode is provided in common to said plurality of banks,
Wherein together provided in common to a plurality of banks provided independently of the first ground wiring, a first of the plurality of banks and a second ground wiring for grounding the internal circuit in the verify mode A bank operates in the data read mode, and a second bank of the plurality of previous banks operates in a write mode in parallel;
The first bank is connected to the first ground wiring to receive a memory cell source potential, and the second bank is connected to the second ground wiring in the verify mode in the write mode to A semiconductor device that receives a source potential .   The semiconductor device according to claim 1, further comprising: a first ground terminal connected to the first ground wiring; and a second ground terminal connected to the second ground wiring.   3. The semiconductor device according to claim 1, wherein the first ground wiring and the second ground wiring have substantially the same length. The semiconductor device includes a semiconductor device according to any one claim of claims 1-3 having a switch for connecting said plurality of banks to selectively said first and second ground wiring. Each of the plurality of banks, a semiconductor device of claim 1 further comprising a plurality of nonvolatile memory cells. The semiconductor device a semiconductor device as described in any one of claims 1-5 which is a non-volatile semiconductor memory device. A method for controlling a semiconductor device including a plurality of banks and capable of simultaneously operating in a write mode including a data read mode and a verify mode ,
A step of supplying the memory cell source potential and the ground through a first ground wiring provided to one first bank of the plurality of banks in the data read mode in common to said plurality of banks,
Wherein the second bank of the plurality of banks in the verify mode, the first second ground memory cell source grounded via the wiring provided in common to independently and the plurality of banks and a ground wire method comprising the steps of supplying a potential.

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