JP4641000B2 - Light receiving amplifier circuit and optical pickup - Google Patents

Description

  The present invention relates to a light receiving amplifier circuit incorporated in a light receiving amplifier element IC (OPIC: registered trademark) mounted on an optical pickup device used for reproducing / recording an optical disk, and more particularly, to receive a signal light reflected from an optical disk. The present invention relates to a light receiving amplifier circuit of an amplifier element.

  An optical disc apparatus for reproducing / recording an optical disc includes an optical pickup that irradiates the optical disc with a laser beam for reproduction / recording and receives reflected light from the optical disc. The optical pickup is provided with a light receiving element that receives the reflected light or monitors the laser light emitted from the laser light source and converts it into an electric signal, and a light receiving amplifier circuit that amplifies the converted electric signal. It has been.

  In recent years, writable optical discs such as CD-R / RW and DVD-R / RW have been used in addition to read-only optical discs such as CD-ROM and DVD-ROM. Since the disk is irradiated with a larger amount of light than sometimes, the difference in the light input level in writing / reproducing is large. Also, it is necessary to cope with the difference in reflectivity for each optical disc depending on the type of the optical disc.

  Therefore, a light receiving amplifier circuit is proposed in which a plurality of feedback circuits that can be selected by switching are provided in the light receiving amplifier circuit to change the amplifier gain (see, for example, Patent Document 1 and Patent Document 2).

  FIG. 34 shows a conventional light receiving amplifier circuit 91. The light receiving amplifier circuit 91 is a light receiving amplifier circuit in which offset voltage correction circuits Cd1 to Cdn are provided at the positive input terminal of the differential amplifier in the light receiving amplifier circuit of Patent Document 1. Further, the feedback circuits C1 to Cn are used as switch means. Are provided with transistors (bipolar transistors) SW1 to SWn, and switching control is performed by conduction / non-conduction of the transistors SW1 to SWn.

  In the light receiving amplifier circuit 91, a light receiving element (photodiode) PD1 that receives an optical signal is connected to the negative input terminal of the differential amplifier Amp1, and the optical signal of the return light from the optical disk is converted into a current IPD1 by the light receiving element PD1. Is done. A plurality of feedback circuits C1 to Cn including transistors SW1 to SWn (PNP transistors) and feedback resistors FB1 to FBn are connected in parallel between the negative input terminal and the output terminal of the differential amplifier Amp1. Current sources CS1 to CSn are connected to the base terminals of the transistors SW1 to SWn, and the currents ISW1 to ISWn are turned on / off to control saturation / nonsaturation of the transistors SW1 to SWn, that is, conduction / nonconduction. Do.

  The feedback resistors FB1 to FBn have different impedances, and the feedback circuits C1 to Cn are selected according to the magnitude of the current IPD1. The selection of the feedback circuits C1 to Cn is performed by controlling the conduction / non-conduction of the transistors SW1 to SWn. For example, at the time of writing in which the current IPD1 from the light receiving element PD1 increases, a feedback circuit with a low gain is selected and the current IPD1 When reproduction is small, a feedback circuit with a high gain is selected.

  In addition, in order to reduce the offset voltage (difference between the output voltage and the reference voltage when there is no input), the reference voltage source VS1 is connected to the positive input terminal of the differential amplifier Amp1, and the positive input of the differential amplifier Amp1. A plurality of offset voltage correction circuits Cd1 to Cdn having transistors SWd1 to SWdn and resistors FBd1 to FBdn are connected in parallel between the terminal and the reference voltage source VS1. Current sources CSd1 to CSdn are connected to the base terminals of the transistors SWd1 to SWdn, respectively, and saturation / nonsaturation of the transistors SWd1 to SWdn, that is, conduction / non-conduction is controlled by turning the currents ISWd1 to ISWdn on and off. I do.

  The resistors FBd1 to FBdn have different impedances, the resistance values of the resistor FBd1 and the feedback resistor FB1 are equal to each other, and the resistance values of the resistor FBdk (k = 2 to n) and the feedback resistor FBk (k = 2 to n) are also respectively Equal to each other. When the feedback circuit C1 is selected, the offset voltage correction circuit Cd1 is selected. Similarly, when the feedback circuit Ck (k = 2 to n) is selected, the offset voltage correction circuit Cdk (k = 2 to n). Is selected. As described above, the offset voltage is reduced by selecting the offset voltage correction circuits Cd1 to Cdn in accordance with the selection of the feedback circuits C1 to Cn.

  FIG. 35 shows another conventional light receiving amplifier circuit 92. The light receiving amplifier circuit 92 has a configuration in which, in the light receiving amplifier circuit disclosed in Patent Document 2, a transistor is provided in each of the feedback circuits C1 to Cn instead of the switch circuit, and switching control is performed by conduction / non-conduction of the transistor.

  The light receiving amplifier circuit 92 includes a first stage amplifier circuit including an amplifier Amp2 and a dummy amplifier Ampd, and a subsequent stage amplifier circuit including a differential amplifier Amp3. The output from the amplifier Amp2 is input to the non-inverting terminal of the differential amplifier Amp3, is compared with the output voltage from the dummy amplifier Ampd, and is output.

  A light receiving element PD1 for converting an optical signal into a current IPD1 is connected to an input terminal of the amplifier Amp2, and a plurality of feedback circuits C1 to Cn including feedback resistors FB1 to FBn and transistors SW1 to SWn are provided in parallel. ing. Current sources CS1 to CSn are connected to the base terminals of the transistors SW1 to SWn, and the conduction / non-conduction of the transistors SW1 to SWn is controlled by turning on / off the currents ISW1 to ISWn. The feedback resistors FB1 to FBn have different impedances, and the feedback circuits C1 to Cn are selected according to the magnitude of the current IPD1. For example, a feedback resistor having a low impedance is selected during writing when the current IPD1 from the light receiving element PD1 is large, and a feedback resistor having a high impedance is selected during reproduction when the current IPD1 is small.

  The dummy amplifier Ampd is also provided with a plurality of offset voltage correction circuits Cd1 to Cdn including resistors FBd1 to FBdn and transistors SWd1 to SWdn in parallel. Current sources CSd1 to CSdn are connected to the base terminals of the transistors SWd1 to SWdn, and the conduction / non-conduction of the transistors SWd1 to SWdn is controlled by turning the currents ISWd1 to ISWdn on and off. The feedback resistors FB1 to FBn also have different impedances, and the offset voltage correction circuits Cd1 to Cdn of the dummy amplifier Ampd are selected in accordance with the selection of the feedback resistor of the amplifier Amp2.

  An input resistor R1 is provided on each of the two input sides of the differential amplifier Amp3, and a resistor R2 is provided on the feedback circuit of the differential amplifier Amp3. A resistor R2 is also connected between the positive input terminal of the differential amplifier Amp3 and the resistor R1, and the resistor R2 is further connected to the reference voltage source VS2. As a result, the gain of the differential amplifier Amp3 is fixed at R2 / R1.

With the configuration of the two light receiving amplifier circuits 91 and 92, the optical pickup device can obtain good reproduction characteristics even for a low reflection disk while supporting a high-speed writing mode with a large optical input.
JP 2003-234623 A (released on August 22, 2003) JP 2003-187484 A (published July 4, 2003)

  However, in the above conventional configuration, since a transistor is used for selecting a feedback circuit, the input current from the light receiving element and the output voltage of the light receiving amplifier circuit are not linear, and an error occurs in the output signal. There is a problem of end.

In Figure 34 in particular, the current ISW1 is ON, i.e. when only the feedback circuit C1 to the transistor SW1 is provided with a feedback resistor FB1 conducting is selected, the resistance value of the feedback resistor FB1 the Rf1, the transistor SW1 ZSW1 As impedance, the output voltage Vo1 is
Vo1 = IPD1 × (Rf1 + ZSW1 ) ... (1)
It becomes. Here, the feedback resistance value Rf1 is constant regardless of the current IPD1.

On the other hand, the impedance ZSW1 is obtained as follows. In general, the collector-emitter voltage Vce (sat) when a transistor is saturated is
Vce (sat) = VT x ln ((αF ・ (1−αR) ・ IC + IS (1−αF ・ αR) + αF ・ IB) /
(αR ・ (αF−1) ・ IC + IS (1−αF ・ αR) + αF ・ αR ・ IB))
= VT × ln (((1−αR) ・ IC + IB) / (αR ・ IB)) (2)
It becomes. Here, each parameter in the above equation is
IS: Saturation current during reverse operation <IB, IC
IB: Base current IC: Collector current IE: Emitter current VT: Thermal voltage
αF: Forward current gain at base ground (≈1)
αR: Reverse current gain at base ground β: Current gain during forward operation (IC / IB)
rE: emitter resistance rC: collector resistance, and αR, β, rE, rC are eigenvalues (constants) of the transistor. If IB is constant, the collector-emitter resistance Ron of the saturation transistor can be expressed by the change of VCE (sat) with respect to IC. Therefore, when VCE (sat), that is, equation (2) is partially differentiated by the collector current IC, .
Ron = σ Vce (sat) / σ IC
= VT × (1−αR) / (IB + (1−αR) · IC) (3)
Since ZSW1 in the equation (1) corresponds to the collector-emitter resistance of the transistor SW1 , that is, the equation (3) , it is assumed that IB = ISW1, IC = IPD1, and the input current of the differential amplifier is sufficiently small to be ignored.
ZSW1 = VT × (1−αR) / (ISW1 + (1−αR) ・ IPD1) (4)
Thus, it can be seen that the impedance ZSW1 changes depending on the magnitude of the current IPD1 from the light receiving element PD1.

From the expression (4), the output voltage Vo1 represented by the expression (1) is
Vo1 = IPD1 x (Rf1 + ZSW1)
= IPD1 x (Rf1 + VT x (1-αR) / (ISW1 + (1-αR) · IPD1) ) (5)
When the gain of the light receiving amplifier circuit is Ra,
Ra = Vo1 / IPD1
= ZFB1 + ZSW1
= Rf1 + VT × (1−αR) / (ISW1 + (1−αR) ・ IPD1) (6)
It becomes.

Here, if the amount of change in the impedance ZSW1 when ΔDSW changes in the range of 0 to the maximum value is ΔZSW1, the amount of change Ra of the gain Ra does not change regardless of the current resistance IPD1.
ΔRa = ΔZSW1 (7)
And
The change rate ΔRa / Ra of the gain Ra is
ΔRa / Ra = ΔZSW1 / Ra
= ΔZSW1 / (Rf1 + ZSW1) (8)
It becomes.

  Particularly in recent years, the current IPD1 from the light receiving element increases due to an increase in the laser emission light accompanying an increase in the recording speed of the optical disc. Therefore, the feedback resistance value Rf1 is reduced for the purpose of preventing output saturation of the light receiving amplifier circuit. Accordingly, the gain change rate increases even if the gain change amount is the same.

  That is, as shown in FIG. 36A, when the feedback resistance value Rf1 is large, the rate of change of the gain Ra is small, and the error of the output voltage with respect to the current from the light receiving element PD1 is also small. As shown, when the feedback resistance value Rf1 is small, the rate of change of the gain Ra is large, and the error of the output voltage with respect to the current from the light receiving element PD1 increases.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a light receiving amplifier circuit in which chip area and manufacturing cost are reduced by using a bipolar transistor as a switching element for selecting a feedback circuit. An object of the present invention is to realize a light receiving amplifier circuit with a small output voltage error.

In order to solve the above problems, a light receiving amplifier circuit according to the present invention includes a light receiving element, an amplifier that converts and amplifies a current generated in the light receiving element into a voltage, a first resistor and a feedback circuit that turns on and off the first resistor. comprising 1 a transistor and a plurality of feedback circuits connected in series, and a plurality of offset voltage correction circuit for correcting the output voltage at the time a current is not from the individual with respect to the light receiving element of the feedback circuit, the The light receiving element is connected to a first input terminal of the amplifier, and the plurality of feedback circuits are connected in parallel between a connection point between the light receiving element and the first input terminal and an output terminal of the amplifier, impedance of the first resistor are different from each other, the offset voltage correction circuit in the light receiving amplifier circuit are connected in parallel between the second input terminal and a reference voltage source of the amplifier, the upper Comprising a first bias current source for generating a first bias current supplied to the first transistor, the bias current source is connected to the light receiving element and the plurality of feedback circuits, the first transistor is conducting, the A current obtained by adding the current generated in the light receiving element and the first bias current flows .

  According to the above configuration, when the first transistor is a PNP transistor, the current flowing through the collector terminal of the first transistor is increased by the bias current, and when the first transistor is an NPN transistor, the emitter of the first transistor is Since the current flowing through the terminal increases by the bias current, the change in the gain of the feedback circuit with respect to the change in the detection signal of the light receiving element is reduced. Therefore, an effect is obtained that an output voltage with less error can be obtained as compared with the conventional light receiving amplifier circuit.

  In the light receiving amplifier circuit according to the present invention, the first bias current source may cause the first bias current to flow through a connection point between the light receiving element and the amplifier.

  According to the above configuration, the first bias current can be automatically supplied to the first transistor as the feedback circuit is selected.

  In the light receiving amplifier circuit according to the present invention, only one bias current source is provided, and the first bias current source causes the first bias current to flow through the light receiving element and the connection point.

  According to the above configuration, since the bias current also flows through the first resistor, the dynamic range of the light receiving amplifier circuit is reduced. However, since only one first bias current source is provided in the light receiving amplifier circuit, the manufacturing cost is reduced. There is an effect that it can be suppressed.

  In the light receiving amplifier circuit according to the present invention, the first bias current source is provided corresponding to each of the feedback circuits, and the first transistor is connected only when the first transistor is conductive. An operation control circuit for operating the bias current source is provided.

  According to the above configuration, although it is necessary to provide a plurality of first bias current sources, the bias current value can be switched according to the selection of the feedback circuit.

  In the light receiving amplifier circuit according to the present invention, the first bias current source is provided corresponding to each of the feedback circuits, and the first bias current source includes the first resistor and the first transistor in each feedback circuit. It is characterized by being connected between.

  According to the above configuration, although it is necessary to provide a plurality of first bias current sources, since the first bias current does not flow through the first resistor, the first bias current source passes through the connection point between the light receiving element and the amplifier. As a result, the decrease in the dynamic range can be suppressed as compared with the configuration in which the first bias current is supplied.

  The light-receiving amplifier circuit according to the present invention includes an operation control circuit that operates the first bias current source to which the first transistor is connected only when the first transistor is conductive. .

  According to the above configuration, the operation control circuit operates the corresponding first bias current source only when the first transistor is conductive, so that the bias current value is automatically switched according to the selection of the feedback circuit. There is an effect that can be.

  In the light-receiving amplifier circuit according to the present invention, the operation control circuit includes a constant current source that generates a constant current, a diode-connected second transistor that supplies the constant current, and a base that is commonly connected to the second transistor. The first bias current source including a third transistor that turns on / off the first transistor is a fourth transistor that forms a current mirror circuit with the second transistor.

  According to the above configuration, since the base of the third transistor and the base of the fourth transistor are connected in common to the base of the second transistor, the third transistor for turning ON / OFF the first transistor and the first bias The fourth transistor, which is a current source, is linked. Accordingly, there is an effect that the corresponding bias current source can be switched with a simple configuration as the feedback circuit is selected.

  The light receiving amplifier circuit according to the present invention further includes a plurality of offset voltage correction circuits for correcting the output voltage when there is no current from the light receiving element for each of the feedback circuits, and the offset voltage correction circuit includes: A second resistor connected in parallel between the second input terminal of the amplifier and a reference voltage source; and a fifth transistor connected in series with the second resistor to turn on / off the offset voltage correction circuit; A second bias current source for generating a second bias current flowing through the fifth transistor, the first bias current and the second bias current flowing simultaneously are equal in current value, and the feedback circuit and the offset voltage correction The corresponding circuits are selected one by one, and the first resistor in the selected feedback circuit and the selected offset voltage correction circuit are selected. That the second resistor, more preferably resistance to each other are the same.

  According to said structure, by providing an offset voltage correction circuit, the output voltage at the time of no signal can be suppressed, and the reduction | decrease of a dynamic range can be suppressed. Further, since the resistance values of the first resistor and the corresponding second resistor are equal to each other, and the first bias current and the second bias current that are simultaneously supplied have the same current value, the offset voltage can be further suppressed. There is an effect.

In the light receiving amplifier circuit according to the present invention, the upper Symbol offset voltage correction circuit includes a second resistor, and a fifth transistor for ON / OFF the offset voltage correction circuit is connected to the second resistor in series, the fifth transistor A second bias current source that generates a second bias current to be supplied to the first bias current, and the first bias current and the second bias current that are simultaneously supplied have the same current value, and the feedback circuit and the offset voltage correction circuit correspond to each other. Each of them is selected one by one, and the first resistor in the selected feedback circuit and the second resistor in the selected offset voltage correction circuit have the same resistance value.

  According to said structure, there exists an effect that a 2nd bias current can be automatically sent through a 5th transistor with selection of an offset voltage correction circuit.

  The light receiving amplifier circuit according to the present invention further includes a plurality of offset voltage correction circuits for correcting the output voltage when there is no current from the light receiving element for each of the feedback circuits, and the offset voltage correction circuit includes: A second resistor connected in parallel between the second input terminal of the amplifier and a reference voltage source; and a fifth transistor connected in series with the second resistor to turn on / off the offset voltage correction circuit; A second bias current source for generating a second bias current flowing through the fifth transistor, the first bias current and the second bias current flowing simultaneously are equal in current value, and the feedback circuit and the offset voltage correction The corresponding circuits are selected one by one, and the first resistor in the selected feedback circuit and the selected offset voltage correction circuit are selected. And the second resistor having the same resistance value, the one second bias current source is provided, the second bias current source is connected to the second input terminal, and the second bias current source and the second resistor are connected to each other. More preferably, the second bias current flows through a connection point with the second input terminal.

  According to the above configuration, since only one first bias current source and one second bias current source are provided, the manufacturing cost can be reduced.

  The light receiving amplifier circuit according to the present invention further includes a plurality of offset voltage correction circuits for correcting the output voltage when there is no current from the light receiving element for each of the feedback circuits, and the offset voltage correction circuit includes: A second resistor connected in parallel between the second input terminal of the amplifier and a reference voltage source; and a fifth transistor connected in series with the second resistor to turn on / off the offset voltage correction circuit; A second bias current source for generating a second bias current flowing through the fifth transistor, the first bias current and the second bias current flowing simultaneously are equal in current value, and the feedback circuit and the offset voltage correction The corresponding circuits are selected one by one, and the first resistor in the selected feedback circuit and the selected offset voltage correction circuit are selected. The second resistors have the same resistance value, and the second bias current source is provided corresponding to each of the offset voltage correction circuits, and is connected to the second input terminal. The second bias current is allowed to flow through a connection point between a two-bias current source and the second input terminal, and the operation control circuit connects the fifth transistor only when the fifth transistor is conductive. The second bias current source is further operated, a constant current source for generating a constant current, a diode-connected second transistor for supplying the constant current, and the base of the second transistor and the base are connected in common. A third transistor for turning on / off the first transistor; and a sixth transistor for turning on / off the fifth transistor. The first bias current source includes the second transistor. A fourth transistor constituting the register a current mirror circuit, said second bias current source is more preferably a seventh transistor constituting the second transistor and the current mirror circuit.

  According to the above configuration, the base of the third transistor that turns on / off the first transistor, the base of the fourth transistor that is the first bias current source, the base of the sixth transistor that turns on / off the fifth transistor, and the second The base of the seventh transistor, which is a bias current source, is commonly connected to the base of the second transistor. Therefore, since the ON / OFF of each transistor is interlocked, the corresponding offset voltage correction circuit, the first bias current, and the second bias current can be switched in accordance with the selection of the feedback circuit.

  The light receiving amplifier circuit according to the present invention further includes a plurality of offset voltage correction circuits for correcting the output voltage when there is no current from the light receiving element for each of the feedback circuits, and the offset voltage correction circuit includes: A second resistor connected in parallel between the second input terminal of the amplifier and a reference voltage source; and a fifth transistor connected in series with the second resistor to turn on / off the offset voltage correction circuit; A second bias current source for generating a second bias current flowing through the fifth transistor, the first bias current and the second bias current flowing simultaneously are equal in current value, and the feedback circuit and the offset voltage correction The corresponding circuits are selected one by one, and the first resistor in the selected feedback circuit and the selected offset voltage correction circuit are selected. The second resistors have the same resistance value, and the second bias current source is provided corresponding to each of the offset voltage correction circuits. And the fifth transistor may be connected.

  According to said structure, when the 1st bias current is provided for every feedback circuit between the feedback resistance and the collector terminal of the 1st transistor, the output voltage at the time of no signal can be suppressed suitably. Further, although it is necessary to provide a plurality of first bias current sources and a plurality of second bias current sources, the first bias current does not flow through the first resistor, so that the dynamic range is hardly reduced.

  The light receiving amplifier circuit according to the present invention further includes a plurality of offset voltage correction circuits for correcting the output voltage when there is no current from the light receiving element for each of the feedback circuits, and the offset voltage correction circuit includes: A second resistor connected in parallel between the second input terminal of the amplifier and a reference voltage source; and a fifth transistor connected in series with the second resistor to turn on / off the offset voltage correction circuit; A second bias current source for generating a second bias current flowing through the fifth transistor, the first bias current and the second bias current flowing simultaneously are equal in current value, and the feedback circuit and the offset voltage correction The corresponding circuits are selected one by one, and the first resistor in the selected feedback circuit and the selected offset voltage correction circuit are selected. The second resistors have the same resistance value, and the second bias current source is provided corresponding to each of the offset voltage correction circuits. And the operation control circuit further operates the second bias current source to which the fifth transistor is connected only when the fifth transistor is conducting, and A constant current source for generating a current; a diode-connected second transistor for supplying the constant current; a second transistor and a base connected in common; and a third transistor for turning on / off the first transistor; A sixth transistor for turning on / off the fifth transistor, and the first bias current source includes a current mirror circuit and the second transistor. A fourth transistor constituting the said second bias current source is more preferably a seventh transistor constituting the second transistor and the current mirror circuit.

  According to the above configuration, the base of the third transistor that turns on / off the first transistor, the base of the fourth transistor that is the first bias current source, the base of the sixth transistor that turns on / off the fifth transistor, and the second The base of the seventh transistor, which is a bias current source, is commonly connected to the base of the second transistor. Therefore, since the ON / OFF of each transistor is interlocked, the corresponding offset voltage correction circuit, the first bias current, and the second bias current can be switched in accordance with the selection of the feedback circuit.

  In the light receiving amplifier circuit according to the present invention, the characteristics of all the transistors provided in the light receiving amplifier circuit are the same, and the impedance between the connection point of each first bias current source in the feedback circuit and the output terminal is More preferably, as the first feedback circuit impedance, a product of the first feedback circuit impedance and the first bias current is larger than a collector-emitter voltage at the time of saturation of a transistor provided in the light receiving amplifier circuit.

  According to the above configuration, since the collector-emitter voltage of the third transistor is higher than the collector-emitter voltage when the transistor is saturated, the transistor for securing the collector-emitter voltage of the third transistor in the amplifier. There is an effect that it is not necessary to provide.

  In the light receiving amplifier circuit according to the present invention, it is more preferable that a product of the first bias current and the first feedback circuit impedance is smaller than a base-emitter voltage of a transistor provided in the light receiving amplifier circuit.

  According to the above configuration, the no-signal output voltage of the photoreceiver amplifier circuit is lower than the no-signal output voltage of the conventional photoreceiver amplifier circuit that does not supply a bias current, thus ensuring a wider dynamic range than the conventional photoreceiver amplifier circuit. There is an effect that can be done.

In the light receiving amplifier circuit according to the present invention, the first bias current is turned ON / OFF in accordance with the ON / OFF of the feedback circuit, the sum of the impedance between the first resistor and the first transistor in each feedback circuit first As the second feedback circuit impedance, the smaller the second feedback circuit impedance of the selected feedback circuit is, the larger the first bias current source is selected. The larger the second feedback circuit impedance of the selected feedback circuit is, the larger the current is More preferably, the first bias current source having a small value is selected.

  According to the above configuration, when the impedance of the feedback circuit is large, the gain change rate is small, so that the bias current can be reduced and the power consumption can be suppressed. Further, since the gain change rate increases as the impedance of the feedback circuit decreases, the gain change rate can be suppressed by increasing the bias current.

  In the light receiving amplifier circuit according to the present invention, the first bias current is obtained by multiplying the product of the maximum value of the current from the light receiving element and the second feedback circuit impedance and the current when there is no current from the light receiving element. More preferably, the sum with the output voltage is set to be smaller than the maximum allowable output voltage of the amplifier.

  According to the above configuration, even when the current supplied from the light receiving element is maximum, the output voltage does not exceed the maximum allowable output voltage of the light receiving amplifier circuit, so that the distortion of the output signal does not occur. Play.

  An optical pickup according to the present invention includes the light receiving amplifier circuit.

  According to said structure, the optical pick-up which can detect the output voltage with few errors with respect to the reflected light of a laser is realizable.

As described above, the light receiving amplifier circuit according to the present invention includes a light receiving element, an amplifier that converts a current generated in the light receiving element into a voltage and amplifies the first resistor, and a first transistor that turns on and off a feedback circuit. includes but a plurality of feedback circuits connected in series, and a plurality of offset voltage correction circuit for correcting the output voltage at when the current from the light receiving element is not for individual the feedback circuit, the light receiving element The plurality of feedback circuits are connected in parallel between a connection point between the light receiving element and the first input terminal and an output terminal of the amplifier, and are connected to the first input terminal of the amplifier. the impedance are different from each other, the offset voltage correction circuit in the light receiving amplifier circuit are connected in parallel between the second input terminal and a reference voltage source of the amplifier, said first Trang Comprising a first bias current source for generating a first bias current applied to the static, the bias current source is connected to the light receiving element and the plurality of feedback circuits, the first transistor is conducting, the light receiving element In this configuration, a current obtained by adding the current generated in step 1 and the first bias current flows .

  As a result, the current flowing through the first transistor increases by the bias current, so that the change in the gain of the feedback circuit with respect to the change in the detection signal of the light receiving element is reduced. Therefore, an effect is obtained that an output voltage with less error can be obtained as compared with the conventional light receiving amplifier circuit.

[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 shows a configuration of a light receiving amplifier circuit 1 according to the present embodiment.

  The light receiving amplifier circuit 1 has a configuration in which a bias current source CSB1a is added to the conventional light receiving amplifier circuit 91 shown in FIG. The bias current source CSB1a is connected to the light receiving element PD1 and the feedback resistors FB1 to FBn, and generates a bias current IBIAS1a.

  For example, when only the current source CS1 is ON and only the transistor SW1 is conducting, the collector current of the transistor SW1 flowing through the feedback resistor FB1 is IPD1 + IBIAS1a. That is, the light receiving amplifier circuit 1 increases the collector current of the transistor SW1 by the bias current IBIAS1a as compared with the light receiving amplifier circuit 91.

Here, it is assumed that the current from the light receiving element PD1 changes in the range of 0 to IPD1max. At this time, in the light receiving amplifier circuit 91, the collector current of the transistor SW1 also changes in the range of 0 to IPD1max. Therefore, the change amount ΔRa of the current gain is obtained from the equations (4) and (7):
ΔRa = ΔZSW1
= VT × (1−αR) / (ISW1 + (1−αR) · 0) −
VT × (1−αR) / (ISW1 + (1−αR) ・ IPD1max)
＝ VT × (1−αR) ・ (1 / ISW1−1 / (ISW1 + (1−αR) ・ IPD1max)
＝ VT × (1−αR) ² ・ IPD1max / (ISW1 ・ (ISW1 + (1−αR) ・ IPD1max)) (9)
It becomes.

On the other hand, in the configuration of this embodiment, when the current IPD1 from the light receiving element PD1 changes in the range of 0 to IPD1max, the collector current of the transistor SW1 changes in the range of IBIAS1a to IBIAS1a + IPD1max. From 4) and formula (7)
ΔRa = ΔZSW1
＝ VT × (1−αR) / (ISW1 + (1−αR) ・ IBIAS1a) −
VT × (1−αR) / (ISW1 + (1−αR) ・ (IBIAS1a + IPD1max))
＝ VT × (1−αR) ・ (1 / ISW1−1 / (ISW1 + (1−αR) ・ IPD1max))
＝ VT × (1−αR) ² ・ IPD1max /
((ISW1 + (1−αR) ・ IBIAS1a) ・ (ISW1 + (1−αR) ・ (IBIAS1a + IPD1max))))
... (10)
It becomes.

  Here, when the formula (9) is compared with the formula (10), the numerator is equal, but the denominator is larger in the formula (10), so the formula (10) is smaller than the formula (9). Therefore, the amount of gain change is smaller in the configuration of the light receiving amplifier circuit 1 than the amount of change in the current IPD1 from the light receiving element PD1.

  That is, as shown in FIG. 3, the amount of change in the impedance of the transistor decreases as the collector current increases. Therefore, by increasing the collector current by the bias current IBIAS1a, the transistor impedance is changed with respect to the change in the current IPD1 from the light receiving element PD1. Less impedance change.

  Therefore, the configuration of the present embodiment has a smaller amount of gain change than the conventional configuration, and the error of the output voltage Vo1 with respect to the current IPD1 from the light receiving element PD1 is improved.

  In the above case, the transistor SW1 is a PNP type transistor. However, when the transistor SW1 is an NPN type transistor, the bias current IBIAS1a increases the emitter current of the transistor ISW1, and the result similar to the expression (10) is obtained.

  FIG. 2 shows a configuration of the light receiving amplifier circuit 2 according to the present embodiment.

  The light receiving amplifier circuit 2 is configured by adding a bias current source CSB1a to the conventional light receiving amplifier circuit 92 shown in FIG. The bias current source CSB1a is connected to the light receiving element PD1 and the feedback resistors FB1 to FBn, and generates a bias current IBIAS1a.

  Similarly to the light receiving amplifier circuit 1 in the light receiving amplifier circuit 2, for example, when only the current source CS1 is ON and only the transistor SW1 is conductive, the collector current of the transistor SW1 flowing through the feedback resistor FB1 is IPD1 + IBIAS1a. That is, the light receiving amplifier circuit 2 increases the collector current of the transistor SW1 by the bias current IBIAS1a as compared with the light receiving amplifier circuit 92.

  Similarly to the light receiving amplifier circuit 1, the amount of change in the gain of the feedback circuit with respect to the change in the current IPD1 from the light receiving element PD1 is established as in equations (9) and (10). The amount of change in gain is less than that.

  In the light receiving amplifier circuit 1, when the feedback circuit C1 is selected, the offset voltage correction circuit Cd1 is selected. Similarly, when the feedback circuit Cn is selected, the offset voltage correction circuit Cdn is selected. . That is, the offset voltage is reduced by selecting the offset voltage correction circuits Cd1 to Cdn in accordance with the selection of the feedback circuits C1 to Cn, respectively.

  FIG. 4 shows a specific circuit configuration example of the switching means of the offset voltage correction circuit accompanying the feedback circuit selection in the light receiving amplifier circuit 1.

  The collector of the transistor QSW1 is connected to the base of the transistor SW1 of the feedback circuit C1, and the emitter of the transistor QSW1 is grounded. In the offset voltage correction circuit Cd1, the collector of the transistor QSWd1 is connected to the base of the transistor SWd1, and the emitter of the transistor QSWd1 is grounded. Both the base of the transistor QSW1 and the base of the transistor QSWd1 are commonly connected to the base and collector of the transistor QCM1a, and the emitter of the transistor QCM1a is grounded. The base and collector of the transistor QCM1a are connected to the current source CSCM1a and the collector of the transistor SWCM1a. The current source CSCM1a generates a constant current ICM1a, the base of the transistor SWCM1a is connected to the power supply VS3a, and the emitter of the transistor SWCM1a is grounded.

  In the above configuration, when the transistor SWCM1a is turned on / off, the transistor QCM1a is turned on / off, and the transistor QSW1 and the transistor QSWd1 are turned on / off. When the transistor QCM1a is turned on, a constant current ISW1 and a constant current ISWd1 are generated, and the transistors SW1 and SWd1 are also turned on / off in conjunction with each other. Here, since the current source CSCM1a, the transistor QCM1a, the transistor QSW1 and the transistor QSWd1 form a current mirror circuit, the constant current ISW1 and the constant current ISWd1 are equal to each other.

  Next, FIGS. 5 and 6 show a configuration in which the bias current is switched according to the selection of the feedback circuit and the bias current is changed according to the change in the current from the light receiving element.

  FIG. 5 shows a configuration of the light receiving amplifier circuit 3 according to the present embodiment.

  From equation (10), the larger the bias current IBIAS 1a, the smaller the amount of gain change. Therefore, when the feedback resistance value Rfn is small, that is, when a feedback circuit having a low impedance is selected, the bias current adjustment circuit 9 increases the bias current IBIAS1a in order to suppress the gain change rate in the equation (8). It is desirable.

  On the other hand, when the feedback resistance value Rfn is large, that is, when a feedback circuit having a large impedance is selected, the gain change rate is not significantly affected even if the gain change amount is large from the equation (8). The current adjustment circuit may reduce the bias current IBIAS1a. Thereby, power consumption can be suppressed.

  Therefore, in the light receiving amplifier circuit 3, in the configuration of the light receiving amplifier circuit 1, a plurality of bias current sources CSB1a to CSBna are connected in parallel to the light receiving element PD1 and the feedback resistors FB1 to FBn instead of the single bias current source CSB1a. The bias currents IBIAS1a to IBIASna are generated, respectively. The magnitudes of the bias currents IBIAS1a to IBIASna are different, and the bias current sources CSB1a to CSBna are selected in accordance with the selection of the feedback circuits C1 to Cn.

  That is, when only the current source CS1 is ON and only the transistor SW1 is conductive, only the bias current source CSB1a is selected accordingly, and the collector current of the transistor SW1 is increased by the bias current IBIAS1a. Similarly, when only the current source CSk (k = 2 to n) is ON and only the transistor SWk (k = 2 to n) is conductive, only the bias current source CSBka (k = 2 to n) is selected accordingly. The collector current of the transistor SWk (k = 2 to n) is increased by the bias current IBIASka (k = 2 to n).

  At this time, the magnitude of the bias current IBIASna is inversely proportional to the resistance value of the feedback resistor FBn of the selected feedback circuit Cn. For example, if the resistance values increase in the order of the feedback resistance values Rf1 to Rfn of the feedback resistors FB1 to FBn, the corresponding bias currents IBIAS1a to IBIASna decrease in current order.

  Further, the light receiving amplifier circuit 3 is provided with an output voltage detection circuit 8 (current detection circuit) and a bias current adjustment circuit 9.

  The output voltage detection circuit 8 is connected to the output terminal, and indirectly detects the current value of the current IPD1 by detecting the output voltage Vo1.

  The bias current adjusting circuit 9 is a circuit for adjusting the magnitudes of the bias currents IBIAS1a to IBIASna. Taking the bias current IBIAS1a as an example, the bias current adjusting circuit 9 adjusts the bias current IBIAS1a as follows.

  First, when the output voltage Vo1 detected by the output voltage detection circuit 8 increases / decreases as the current IPD1 from the light receiving element PD1 increases / decreases, the bias current adjustment circuit 9 decreases the bias current IBIAS1a accordingly. / Has the ability to increase.

  The bias current adjusting circuit 9 further has a function of keeping the sum of the current IPD1 and the bias current IBIAS 1a constant. When the bias current IBIAS 1a is adjusted in this way, the collector currents of the transistors SW1 to SWn become constant, and the impedances of the transistors SW1 to SWn do not change. Therefore, the relationship of the output voltage Vo1 with respect to the current IPD1 becomes more linear.

  The bias current adjusting circuit 9 has a function of adjusting the output voltage Vo1 so as not to exceed the maximum output voltage (Vo1max) of the light receiving amplifier circuit 3. That is, the bias current adjusting circuit 9 adjusts the bias current value as follows.

For example, when only the transistor SW1 is ON and the maximum value (IPD1max) of the current from the light receiving element PD1 is known in advance, the offset current is Vod,
Volmax> (IPD1max × (Rf1 + ZSW1) + IBIAS1 × (Rf1 + ZSW1) + Vod (11)
It becomes. Here, IBIAS1 × (Rf1 + ZSW1) + Vod corresponds to the output voltage Vo1 of the light receiving amplifier circuit 1 when there is no signal from the light receiving element PD1 (hereinafter referred to as “no signal”). When the output voltage Vo1 of the light receiving amplifier circuit 3 at the time of no signal is Vo1min,
Volmax−Volmin> IPD1max × (Rf1 + ZSW1) (12)
If the condition is satisfied, the output waveform does not exceed Vo1max, and the distortion of the output signal due to the decrease of the dynamic range does not occur. As described above, the bias current adjustment circuit 9 adjusts the bias current so as to satisfy Expression (12) based on the detected value of the output voltage Vo1 by the output voltage detection circuit 8.

  FIG. 6 shows a configuration of the light receiving amplifier circuit 4 according to the present embodiment. In the light receiving amplifier circuit 4, in the configuration of the light receiving amplifier circuit 2, a plurality of bias current sources CSB1a to CSBna are connected in parallel to the light receiving element PD1 and the feedback resistors FB1 to FBn instead of the single bias current source CSB1a. Bias currents IBIAS1a to IBIASna are generated, respectively. The magnitudes of the bias currents IBIAS1a to IBIASna are different, and the bias current source is selected in accordance with the selection of the feedback circuits C1 to Cn. Similarly to the light receiving amplifier circuit 3, the light receiving amplifier circuit 4 is provided with an output voltage detecting circuit 8 and a bias current adjusting circuit 9.

  In the light receiving amplifier circuit 4, the switching of the bias current accompanying the selection of the feedback circuit and the functions of the output voltage detection circuit 8 and the bias current adjusting circuit 9 are substantially the same as those in the case of the light receiving amplifier circuit 3.

  Next, specific circuit configurations of the bias current switching means, the output voltage detection circuit 8 and the bias current adjustment circuit 9 associated with the feedback circuit selection will be described with reference to FIGS.

  FIG. 7 shows a specific circuit configuration of the bias current switching means associated with the feedback circuit selection in the light receiving amplifier circuit 3. Here, a case where only the transistor SW1 is turned on and only the bias current IBIAS1a is selected will be described as an example.

  Circuit A shows a specific configuration of a bias current switching means associated with feedback circuit selection. The collector of transistor QBIAS1a is connected to the cathode of light receiving element PD1, and the base of transistor QBIAS1a is connected to the base of transistor QCM1a. Yes. The emitter of the transistor QBIAS 1a is grounded.

  The base and collector of the transistor QCM1a are connected to each other, and the emitter of the transistor QCM1a is grounded. The collector of the transistor QCM1a is connected to the current source CSCM1a and the collector of the transistor SWCM1a, the emitter of the transistor SWCM1a is grounded, and the base is connected to the power supply VS3a. The current source CSCM1a generates a constant current ICM1a, and the current source CSCM1a, the transistor QCM1a, and the transistor QBIAS1a constitute a current mirror circuit, thereby generating a bias current IBIAS1a.

  The base of the transistor QSW1 is also connected to the base of the transistor QCM1a in common with the base of the transistor QBIAS1a. As a result, the transistor QCM1a is turned on / off as the transistor SWCM1a is turned on / off, and the transistor QBIAS1a and the transistor QSW1 are turned on / off in conjunction with each other. Thus, when the feedback circuit C1 including the feedback resistor FB1 is selected, the bias current IBIAS1a is selected accordingly.

  Although omitted in FIG. 7, the feedback circuit Ck (k = 2 to n) and the bias current IBIASka (k = 2 to n) are also connected to the circuit A, and the feedback circuit Ck (k = 2 to n). ) Is selected, the bias current IBIASka (k = 2 to n) is selected accordingly.

  FIG. 8 shows a circuit configuration in which only the transistor SW1 is turned on in the light receiving amplifier circuit 1 provided with only one bias current source, and an output voltage detection circuit 8 and a bias current adjustment circuit 9 are further added.

  The circuit B shows specific configurations of the output voltage detection circuit 8 and the bias current adjustment circuit 9, and includes transistors QBIAS1a, QB1a, QB1ab, and QB1ac, and a resistor RB1a. In this circuit, the base of the transistor QBIAS1a is connected to the base of the transistor QB1aa, and the emitter of the transistor QBIAS1a is grounded. The base and collector of the transistor QB1aa are connected to each other. The emitter of the transistor QB1aa is grounded, and the collector of the transistor QB1aa is connected to the collector of the transistor QB1ab. The emitter of the transistor QB1ab is connected to the power supply Vcc, and the base of the transistor QB1ab is connected to the base of the transistor QB1ac. The base and collector of the transistor QB1ac are connected to each other, and the emitter of the transistor QB1ac is connected to the power supply Vcc, like the emitter of the transistor QB1ab. The collector of the transistor QB1ac is connected to one end of the resistor RB1a, and the other end of the resistor RB1a is connected to the output terminal Vo1 and the emitter of the transistor SW1. In the above circuit, the resistor RB1a constitutes the output voltage detection circuit 8, and the transistors QB1aa to QB1ad constitute the bias current adjustment circuit 9.

  In the above configuration, the output voltage Vo1 is detected by the resistor RB1a. Since the transistors QB1ac and QB1ab and the transistors QB1aa and SWB1a constitute current mirror circuits, respectively, the magnitude of the bias current IBIAS1a is the resistance value of the resistor RB1a is ZRB1b, and the base-emitter voltage of the transistor QB1ac is VbeQB1ac. Then, it becomes as follows.

IBIAS1a = (Vcc-Vo1-VbeQB1ac) / ZRB1a (13)
As a result, the bias current IBIAS1a decreases / increases as the output voltage Vo1 increases / decreases.

  Further, FIG. 9 shows a configuration in which, in the light receiving amplifier circuit 3, the bias current is adjusted simultaneously with the adjustment of the bias current as well as the selection of the feedback circuit. Here, a case where only the transistor SW1 is turned on and only the bias current IBIAS1a is selected will be described as an example.

  In the circuit C, the base of the transistor QBIAS1a is connected to the base of the transistor QB1aa, and the emitter of the transistor QBIAS1a is grounded. The base of the transistor QSW1 is also common to the base of the transistor QBIAS1a, and is connected to the base of the transistor QB1aa. The collector of the transistor QSW1 is connected to the base of the transistor SW1, and the emitter of the transistor QSW1 is grounded. The base and collector of the transistor QB1aa are connected to each other. The emitter of the transistor QB1aa is grounded, and the collector of the transistor QB1aa is connected to the collector of the transistor QB1ad and the collector of the transistor QB1ab. The base of the transistor QB1ad is connected to the power supply VS4a, and the emitter of the transistor QB1ad is grounded. The emitter of the transistor QB1ab is connected to the power supply Vcc, and the base of the transistor QB1ab is connected to the base of the transistor QB1ac. The base and collector of the transistor QB1ac are connected to each other, and the emitter of the transistor QB1ac is connected to the power supply Vcc, like the emitter of the transistor QB1ab. The collector of the transistor QB1ac is connected to one end of the resistor RB1a, and the other end of the resistor RB1b is connected to the output terminal Vo1 and the emitters of the transistors SW1 to SWn of the feedback circuits C1 to Cn.

  Thereby, the magnitude of the bias current IBIAS1a satisfies the above equation (13), and the bias current IBIAS1a decreases / increases as the output voltage Vo1 increases / decreases.

  In addition, the transistor QB1aa is turned on / off with the turning off / on of the transistor QB1ad, and the ON / OFF of the transistor QBIAS1a and the transistor QSW1 is linked to select the bias current IBIAS1a with the selection of the feedback circuit C1.

  Although omitted in FIG. 9, the feedback circuit Ck (k = 2 to n) and the bias current IBIASka (k = 2 to n) are the same as those of the circuit C including the resistor RBka (k = 2 to n) and the like. When the feedback circuit Ck (k = 2 to n) is selected, the bias current IBIASka (k = 2 to n) is selected accordingly.

  FIG. 10 shows a configuration of the light receiving amplifier circuit 5 according to the present embodiment. The light receiving amplifier circuit 5 has a configuration in which the bias current source CSB1da is connected to the offset voltage correction circuits Cd1 to Cdn of the light receiving amplifier circuit 1.

  The bias current source CSB1da is connected to the positive input terminal of the differential amplifier Amp1, and generates a bias current IBIAS1da. As a result, the collector current of the transistor SWdn in the selected offset voltage correction circuit Cdn increases by the bias current IBIASnda.

  FIG. 11 shows the configuration of the light receiving amplifier circuit 6 according to the present embodiment. The light receiving amplifier circuit 6 has a configuration in which a bias current source CSB1da is connected to the offset voltage correction circuits Cd1 to Cdn of the light receiving amplifier circuit 2. The bias current source CSB1da is connected to the input terminal of the dummy amplifier Ampd and generates a bias current IBIAS1da. As a result, the collector current of the transistor SWdn in the selected offset voltage correction circuit Cdn increases by the bias current IBIASnda.

  Here, the relationship between the bias current IBIAS 1a and the bias current IBIAS 1da will be described below.

  FIG. 12 shows a configuration in the case where the feedback circuit C1 and the offset voltage correction circuit Cd1 are selected in the light receiving amplifier circuit 5, and the feedback circuit and the offset voltage correction circuit that are not selected are shown for simplicity. Absent. Further, it is assumed that there is no signal and the current IPD1 = 0 from the light receiving element PD1.

  Here, the potential difference between the positive input terminal of the differential amplifier Amp1 and the reference voltage source VS1 is VFBd1a, the potential difference between the light receiving element PD1 and the output terminal Vo1 is VFB1a, the current to the positive input terminal of the differential amplifier Amp1 is Ib2a, the difference When the current to the negative input terminal of the dynamic amplifier Amp1 is Ib1a and the potential difference between the positive input terminal and the negative input terminal of the differential amplifier Amp1 is VoffAa, the offset voltage Vod of the differential amplifier is as follows.

Vod = Vo1-VS1
= VS1-VFBd1a-VoffAa + VFB1a-VS1
= VFB1a-VFBd1a-VoffAa (14)
When the bias current source CSB1a and the bias current source CSB1da are connected, VoffAa = 0
Vod = VFB1a−VFBd1a−VoffAa
≒ ((ZFB1 + ZSW1) x (Ib1a + IBIAS1a))-((ZFBd1 + ZSWd1) x (Ib2a + IBIAS1da))
... (15)
Here, if ZFB1 = ZFBd1, ZSW1 = ZSWd1, and Ib1a = Ib2a = 0, then
Vod = ((ZFB1 + ZSW1) × (IBIAS1a−IBIAS1da) (16)
It becomes. At this time,
IBIAS1a = IBIAS1da (17)
If Vod holds, Vod = 0 and the offset voltage Vod can be minimized.

Similarly, when other feedback circuits and offset voltage correction circuits are selected,
IBIASka ＝ IBIASkda (k = 2〜n ) … （18）
Is established, the offset voltage Vod can be minimized.

  Therefore, the magnitudes of the respective bias currents generated by the bias current source connected to the feedback circuit and the bias current source connected to the offset voltage correction circuit selected corresponding thereto are equal to each other.

  FIG. 13 shows a configuration of the light receiving amplifier circuit 7 according to the present embodiment. The feedback circuit of the differential amplifier Amp1 in the light receiving amplifier circuit 7 is the same as that of the light receiving amplifier circuit 3 in FIG. 5, and the offset voltage correction circuits Cd1 to Cdn are also provided with bias current sources CSB1da to CSBnda, respectively.

  That is, a plurality of bias current sources CSB1da to CSBnda are connected in parallel to the positive input terminal of the differential amplifier Amp1, and generate bias currents IBIAS1da to IBIASnda, respectively. Here, the offset voltage correction circuits Cd1 to Cdn and the bias current sources CSB1da to CSBnda are individually linked. That is, when the offset voltage correction circuit Cd1 is selected, the bias current source CSB1da is selected. Similarly, when the offset voltage correction circuit Cdk (k = 2 to n) is selected, the bias current source CSBkda (k = 2 to n) is selected. Is selected.

  As in the case of the light receiving amplifier circuit 3, the magnitude of the bias current IBIASka (k = 2 to n) is equal to that of the feedback resistor FBk (k = 2 to n) of the selected feedback circuit Ck (k = 2 to n). It is in inverse proportion to the resistance value. Also, as shown in equations (17) and (18), for IBIAS1a to IBIASna and IBIAS1da to IBIASnda, IBIAS1a and IBIAS1da are equal, and similarly, IBIASka (k = 2 to n) and IBIASkda (k = 2 to n) are also equal. .

  The light receiving amplifier circuit 7 is provided with an output voltage detection circuit 8 and a bias current adjustment circuit 9. The output voltage detection circuit 8 and the bias current adjustment circuit 9 adjust the magnitudes of the bias currents IBIAS1a to IBIASna and the bias currents IBIAS1da to IBIASnda as shown in the equations (11) and (12).

  FIG. 14 shows a specific circuit configuration for linking the offset voltage correction circuit Cd1 and the bias current source CSB1da in the light receiving amplifier circuit 7. As shown in FIG. 14, the light receiving amplifier circuit 7 includes the light receiving amplifier circuit 3 of FIG. 7 further including a bias current source CSB1da, a transistor QBIASd1a, and a transistor QSWd1. The gates of transistor QBIASd1a and transistor QSWd1 are both connected in common to the gate and collector of transistor QCM1. The collector of the transistor QBIASd1a is connected to the positive input terminal of the differential amplifier Amp1, and the emitter of the QBIASd1a is grounded. The collector of the transistor QSW1da is connected to the base of the transistor SWd1, and the emitter of the transistor QSW1da is grounded.

  Thereby, ON / OFF of the transistor QBIASd1a and the transistor QSW1da is interlocked, and similarly, ON / OFF of the transistor QBIAS1a and the transistor QSW1 is also interlocked. Therefore, when the feedback circuit C1 is selected, the offset voltage correction circuit Cd1, the bias current IBIAS1a, and the bias current IBIAS1da are selected. Further, since the current source CSCM1a, the transistor QBIAS1a, and the transistor QBIASd1a constitute a current mirror circuit, the bias current IBIAS1a and the bias current IBIAS1da are equal to each other.

  Although omitted in FIG. 14, the feedback circuit Ck (k = 2 to n) is selected similarly for the feedback circuit Ck (k = 2 to n) and the offset voltage correction circuit Cdk (k = 2 to n). Then, the offset voltage correction circuit Cdk (k = 2 to n), the bias current IBIASka (k = 2 to n), and the bias current IBIASkda (k = 2 to n) are selected. In addition, the bias current IBIASka (k = 2 to n) and the bias current IBIASkda (k = 2 to n) are equal to each other.

  FIG. 15 shows a circuit configuration in which only the transistor SW1 is turned on and only the bias current IBIAS 1a is selected in the light receiving amplifier circuit 7, and the output voltage detection circuit 8 and the bias current adjustment circuit 9 are further added. ing.

  The circuit D shows a specific configuration of the output voltage detection circuit 8 and the bias current adjustment circuit 9, and is configured by adding a transistor QBIAS1da to the circuit B of FIG. The base of the transistor QBIAS1da is commonly connected to the base and collector of the transistor QB1aa together with the base of the transistor QBIAS1a. The collector of the transistor QBIAS1da is connected to the positive input terminal of the differential amplifier Amp1, and the emitter of the transistor QBIAS1da is grounded. Transistor SWBd1, transistor SWB1a and transistor QB1aa constitute a current mirror circuit. Thereby, the bias current IBIAS1a and the bias current IBIAS1da are equal to each other, and the ON / OFF of the transistor SWBd1 and the transistor SWB1a are interlocked.

  The configuration of transistor QB1ab, transistor QB1ac, resistor RB1a, and power supply Vcc is substantially the same as that in FIG.

  Further, FIG. 16 shows a configuration that simultaneously realizes switching of the bias current accompanying the feedback circuit selection as well as the adjustment of the bias current.

  The circuit E has a configuration in which a transistor QBIAS1da and a transistor QSWd1 are further added to the circuit C in FIG. The collector of the transistor QBIAS1da is connected to the positive input terminal of the differential amplifier Amp1, and the emitter of the transistor QBIAS1da is grounded. The collector of the transistor QSWd1 is connected to the base of the transistor SWd1, and the emitter of the transistor QSWd1 is grounded. The base of the transistor QSWd1, the base of the transistor QBIAS1da, the base of the transistor QBIAS1a, and the base of the transistor QSW1 are commonly connected to the base of the transistor QB1aa.

  Thereby, the bias current IBIAS1a satisfies the above equation (13), and the bias current IBIAS1a and the bias current IBIAS1da satisfy the above equation (17). Further, ON / OFF of the transistor QSW1 and the transistor QBIAS1a and ON / OFF of the transistor QSWd1 and the transistor QBIAS1da are interlocked, and the offset voltage correction circuit Cd1, the bias current IBIAS1a, and the bias current IBIAS1da are selected in accordance with the selection of the feedback resistor C1. The Further, since the transistor QB1aa, the transistor QBIAS1a, and the transistor QBIAS1da form a current mirror circuit, the bias current IBIAS1a and the bias current IBIAS1da are equal to each other.

  Although omitted in FIG. 16, the feedback circuit Ck (k = 2 to n), the offset voltage correction circuit Cdk (k = 2 to n), the transistor QBIASka (k = 2 to n), and the transistor QBIASdka (k = 2) ˜n) is also connected to a circuit similar to the circuit E including the resistor RBka (k = 2 to n) and the like, and when the feedback circuit Ck (k = 2 to n) is selected, the offset voltage The correction circuit Cdk (k = 2 to n), the bias current IBIASka (k = 2 to n), and the bias current IBIASkda (k = 2 to n) are selected. In addition, the bias current IBIASka (k = 2 to n) and the bias current IBIASkda (k = 2 to n) are equal to each other.

  FIG. 17 is a circuit diagram showing a specific configuration of the differential amplifier Amp1 in the light receiving amplifier circuit 3 in FIG. The differential amplifier Amp1 includes a grounded emitter amplifier circuit CC1 (hereinafter “amplifier circuit CC1”) and a grounded collector amplifier circuit CC2 (hereinafter “amplifier circuit CC2”). The amplifier circuit CC1 has a transistor Q1 and a current source I1, and the amplifier circuit CC2 has a transistor Q2 and a current source I2. The light receiving element PD1 is connected to the base of the transistor Q1 that is the input of the amplifier circuit CC1, and the base of the transistor Q2 that is the input of the amplifier circuit CC2 is connected to the collector of the transistor Q1 that is the output of the amplifier circuit CC1. The emitter of the transistor Q2, which is the output of the amplifier circuit CC2, corresponds to the output of the light receiving amplifier circuit 3.

  Further, feedback resistors FB1 to FBn selected by conduction / non-conduction of the transistors SW1 to SWn are connected in parallel between the base of the transistor Q1 and the output of the light receiving amplifier circuit 3, for example, the transistor SW1 and the feedback resistor. In the feedback circuit C1 connected to FB1, a current source circuit including a current mirror circuit CM1a is provided.

Here, in order for the light receiving amplifier circuit 3 of FIG. 17 to operate, the collector-emitter voltage of the transistors QSW1 to QSWn of the current mirror circuits CM1a to CMNA in each current source circuit is the collector-emitter voltage when the transistor is saturated. Must be higher than Vce (sat). For example, when the collector-emitter voltage of QSW1 is VceQSW1,
VceQSW1 = VbeQ1 + ((IPD1 + Ib1 + IBIAS1a) x Rf1) + ((IPD1 + Ib1 + IBIAS1) x ZSW1)-VbeSW1
... (19)
It becomes. Here, VbeQ1 and VbeSW1 are the base-emitter voltages of the transistors Q1 and SW1, respectively, and Ib1 is the base current of the transistor Q1.

When IPD1 = 0, VceQSW1 is minimum. Therefore, assuming that the characteristics of each transistor are the same, and VbeQ1 = VbeSW1, Ib1 is very small and approximates Ib1 = 0, the minimum value VceQSW1min of VceQSW1 is
VceQSW1min = IBIAS1 x (Rf1 + ZSW1) (20)
It becomes. Here, if VceQSW1min is higher than the collector-emitter voltage Vce (sat) when the transistor is saturated, the light receiving amplifier circuit operates.
IBIAS1 × (Rf1 + ZSW1)> Vce (sat) (21)
If this condition is satisfied, the light receiving amplifier circuit operates.

Similarly, when another feedback circuit is selected,
IBIASk × (Rfk + ZSWk)> Vce (sat) (k = 2 to n) (22)
That is, it is sufficient that the product of the bias current value and the impedance of the transistor SWk (k = 2 to n) as the feedback circuit selection switch is larger than the collector-emitter voltage when the transistor is saturated.

When the formula (21) is not satisfied, that is,
IBIAS1 × (Rf1 + ZSW1) ≦ Vce (sat) (23)
In this case, as shown in FIG. 18, in addition to the configuration of FIG. 17, a transistor Q3 is newly provided at the emitter of the transistor Q1, so that the collector-emitter voltage of the transistor QSWn is between the collector and emitter when the transistor is saturated. It must be greater than the voltage. The transistor Q3 functions as a diode by connecting the base and the collector.

In this case, the collector-emitter voltage of the transistor QSW1 is
VceQSW1 = VbeQ3 + VbeQ1 + ((IPD1 + Ib1 + IBIAS1a) x Rf1) + ((IPD1 + Ib1 + IBIAS1) x ZSW1)-VbeSW1 (24)
The minimum value of the collector-emitter voltage of the transistor QSW1 is IPD1 = 0, Vbe1 = VbeSW1, and Ib1 = 0 as in the case of the equation (20).
VceQSW1min = VbeQ3 + (IBIAS1 x (Rf1 + ZSW1)) (25)
It becomes.

Therefore, in the configuration of FIG.
VbeQ3 + (IBIAS1 × (Rf1 + ZSW1))> Vce (sat) (26)
If this condition is satisfied, the light receiving amplifier circuit operates.

FIG. 19 shows the configuration of a comparative example in which no bias current is supplied, and the bias currents IBIAS1a to IBIASna and the transistors QBIAS1 to QBIASn for switching are excluded from the configuration of FIG. In this case, the collector-emitter voltage of the transistor QSW1 is
VceQSW1 = Vbe3 + Vbe1 + ((IPD1 + Ib1) × Rf1) + ((IPD1 + Ib1) × ZSW1) −VbeSW1 (27)
The minimum value of the collector-emitter voltage of QSW1 is IPD1 = 0, Vbe1 = VbeSW1, and Ib1 = 0.
VceQSW1min = VbeQ3 (28)
It becomes. In the configuration of FIG.
VbeQ3> Vce (sat) (29)
Since the light receiving amplifier circuit does not operate unless the above condition is satisfied, the collector-emitter voltage of the transistor QSW1 is secured by the transistor Q3.

Further, assuming that the output voltages at the time of no signal of the light receiving amplifier circuit of FIG. 18 and the light receiving amplifier circuit of FIG. 19 are VOLmin18 and VOLmin19, respectively.
VOLmin18 = Vbe1 + (IBIAS1 × (Rf1 + ZSW1)) (30)
VOLmin19 = Vbe1 + Vbe3 (31)
It becomes.

Here, in order to ensure the dynamic range of the photoreceiver amplifier circuit of the present embodiment wider than the dynamic range of the conventional photoreceiver amplifier circuit, VOLmin18 <VOLmin19 should be satisfied.
IBIAS1 × (Rf1 + ZSW1) <Vbe3 (32)
Should be satisfied. That is, the bias current may be adjusted so that the product of the bias current and the impedance of the feedback circuit is lower than the base-emitter voltage of the transistor.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS.

  FIG. 20 shows a configuration of the light receiving amplifier circuit 11 according to the present embodiment.

  The light receiving amplifier circuit 11 is configured by adding bias current sources CSB1b to CSBnb to the conventional light receiving amplifier circuit 91 shown in FIG. 34, and the bias current sources CSB1b to CSBnb generate bias currents IBIAS1b to IBIASnb, respectively. The bias current sources CSB1b to CSBnb are connected between the feedback resistors FB1 to FBn and the transistors SW1 to SWn for each of the feedback circuits C1 to Cn. That is, the bias current source CSB1b is between the feedback resistor FB1 and the transistor SW1, and the bias current source CSBkb (k = 2 to n) is the feedback resistor FBk (k = 2 to n) and the transistor SWk (k = 2 to n). Are connected to each of the feedback circuits C1 to Cn.

Here, the difference between the second embodiment and the first embodiment will be described. In the first embodiment, since the bias current IBIAS 1a also flows through the feedback resistors FB1 to FBn, the dynamic range of the light receiving amplifier circuit 1 decreases due to the voltage increase at the feedback resistors FB1 to FBn. That is, taking the case where only the transistor SW1 is ON in FIG. 1 as an example, the output voltage Volmin of the light receiving amplifier circuit when there is no signal is the offset voltage Vod.
Volmin = Vod + (IBIAS × (ZFB1 + ZSW1)) (33)
Thus, Volmin increases and the dynamic range decreases by (IBIAS × (ZFB1 + ZSW1)).

  On the other hand, in the second embodiment, the bias current source IBIAS1b is connected between the feedback resistor FB1 and the transistor SW1. Therefore, since the bias current IBIAS1b does not flow through the feedback resistor FB1, a voltage rise in the feedback resistor FB1 does not occur when there is no signal, and a decrease in the dynamic range is suppressed as compared with the configuration of the first embodiment.

That is, in the case where only the transistor SW1 is ON in FIG. 20, the output voltage Volmin when there is no signal is
Volmin = Vod + (IBIAS × ZSW1) (34)
Therefore, compared with the equation (33), the configuration in the second embodiment has a smaller output voltage when there is no signal.

  Further, the bias current sources CSB1b to CSBnb are selected in accordance with the selection of the feedback circuits C1 to Cn, respectively. For example, when only the transistor SW1 is turned on and the feedback circuit C1 is selected, the bias current source CSB1b is selected. Similarly, only the transistor SWk (k = 2 to n) is turned on and the feedback circuit Ck (k = 2 to 2) is selected. When n) is selected, the bias current source CSBkb (k = 2 to n) is selected.

  Further, the light receiving amplifier circuit 11 is provided with an output voltage detection circuit 18 (current detection circuit) and a bias current adjustment circuit 19. The output voltage detection circuit 18 is connected to the output terminal, and indirectly detects the current value of the current IPD1 by detecting the output voltage Vo1.

  The bias current adjustment circuit 19 is a circuit that adjusts the magnitudes of the bias currents IBIAS1b to IBIASnb. Taking the bias current IBIAS1b as an example, the bias current IBIAS1b is adjusted as follows.

  First, when the output voltage Vo1 detected by the output voltage detection circuit 8 increases / decreases as the current IPD1 from the light receiving element PD1 increases / decreases, the bias current adjustment circuit 19 decreases the bias current IBIAS1b accordingly. / Has the ability to increase.

  The bias current adjusting circuit 19 further has a function of keeping the sum of the current IPD1 and the bias current IBIAS1b constant. When the bias current IBIAS1b is adjusted in this way, the collector currents of the transistors SW1 to SWn become constant, and the impedances of the transistors SW1 to SWn do not change. Therefore, the relationship of the output voltage with respect to the current IPD1 becomes more linear.

  The bias current adjusting circuit 19 has a function of adjusting the output voltage Vo1 so as not to exceed the maximum output voltage (Vo1max) of the light receiving amplifier circuit 11. That is, the bias current adjustment circuit 19 adjusts the bias current value as follows.

For example, when only the transistor SW1 is ON and the maximum value (IPD1max) of the current from the light receiving element PD1 is known in advance, the offset current is Vod,
Volmax> (IPD1max x (Rf1 + ZSW1) + IBIAS1 x ZSW1 + Vod (35)
It becomes. Here, IBIAS1 × ZSW1 + Vod corresponds to the output voltage Vo1 of the light receiving amplifier circuit 11 when there is no signal from the light receiving element PD1 (hereinafter referred to as “no signal”). When the output voltage Vo1 of the light receiving amplifier circuit 11 at the time of no signal is Vo1min,
Volmax−Volmin> IPD1max × (Rf1 + ZSW1) (36)
If the condition is satisfied, the output waveform does not exceed Vo1max, and the distortion of the output signal due to the decrease of the dynamic range does not occur. As described above, the bias current adjusting circuit 19 adjusts the bias current so as to satisfy Expression (36) based on the detected value of the output voltage Vo1 by the output voltage detecting circuit 18.

  21 has a configuration in which bias current sources CSB1b to CSBnb are added to the conventional light receiving amplifier circuit 92 shown in FIG. 35. The bias current sources CSB1b to CSBnb are bias currents IBIAS1b to IBIASnb, respectively. Is generated. The bias current sources CSB1b to CSBnb are connected between the feedback resistors FB1 to FBn and the transistors SW1 to SWn for each of the feedback circuits C1 to Cn. That is, the bias current source CSB1b is between the feedback resistor FB1 and the transistor SW1, and the bias current source CSBkb (k = 2 to n) is the feedback resistor FBk (k = 2 to n) and the transistor SWk (k = 2 to n). Are connected to each of the feedback circuits C1 to Cn.

  Also in this case, for example, assuming that only the transistor SW1 is conductive, the bias current IBIAS1b flows through the collector of the transistor SW1, but does not flow through the feedback resistor FB1. Therefore, the decrease in the dynamic range of the output voltage when there is no signal in the light receiving amplifier circuit 12 is suppressed as compared with the case of the light receiving amplifier circuit 2 shown in FIG.

  Further, the bias current sources CSB1b to CSBnb are selected in accordance with the selection of the feedback circuits C1 to Cn, respectively. For example, when only the transistor SW1 is turned on and the feedback circuit C1 is selected, the bias current source CSB1b is selected. Similarly, only the transistor SWk (k = 2 to n) is turned on and the feedback circuit Ck (k = 2 to 2) is selected. When n) is selected, the bias current source CSBkb (k = 2 to n) is selected.

  Further, the light receiving amplifier circuit 12 is also provided with an output voltage detection circuit 18 and a bias current adjustment circuit 19. The bias current adjustment circuit 19 is a circuit that adjusts the magnitude of the bias current IBIAS1b, and adjusts the bias current IBIAS1b as in the above equations (35) and (36).

  Next, specific circuit configurations of the bias current switching means, the output voltage detection circuit 18 and the bias current adjustment circuit 19 associated with the feedback circuit selection will be described with reference to FIGS.

  FIG. 22 shows a circuit configuration in which only the transistor SW1 is turned on and only the bias current IBIAS 1a is selected in the light receiving amplifier circuit 11, and further a bias current switching means associated with the feedback circuit selection is added. Yes.

  The circuit F shows a specific configuration of the bias current switching means associated with the feedback circuit selection. The collector of the transistor QBIAS1b is connected between the feedback resistor FB1 and the collector of the transistor SW1, and the base of the transistor QBIAS1b is the transistor QCM1b. Connected to the base. The emitter of the transistor QBIAS 1b is grounded.

  The base and collector of the transistor QCM1b are connected to each other, and the emitter of the transistor QCM1b is grounded. The collector of the transistor QCM1b is connected to the current source CSCM1b and the collector of the transistor SWCM1b, the emitter of the transistor SWCM1b is grounded, and the base is connected to the power supply VS3b. The current source CSCM1b generates a constant current ICM1b, and the current source CSCM1b, the transistor QCM1b, and the transistor QBIAS1b constitute a current mirror circuit, thereby generating a bias current IBIAS1b.

  The base of the transistor QSW1 is also connected to the base of the transistor QCM1b in common with the base of the transistor QBIAS1b. As a result, the transistor QCM1b is turned on / off as the transistor SWCM1a is turned on / off, and the transistor QBIAS1b and the transistor QSW1 are turned on / off in conjunction with each other. Thus, when the feedback circuit C1 is selected, the bias current IBIAS1b is selected accordingly.

  Although omitted in FIG. 22, the feedback circuit Ck (k = 2 to n) is also connected to a circuit similar to the circuit F, and when the feedback circuit Ck (k = 2 to n) is selected, Accordingly, the bias current IBIASkb (k = 2 to n) is selected.

  FIG. 23 shows a case where only the transistor SW1 is turned on and only the bias current IBIAS 1a is selected in the light receiving amplifier circuit 12, and a bias current switching means is added to the feedback circuit selection.

  The circuit G shows a specific configuration of the bias current switching means associated with the feedback circuit selection. The collector of the transistor QBIAS1b is connected between the feedback resistor FB1 and the collector of the transistor SW1, and the base of the transistor QBIAS1b is the transistor QCM1b. Connected to the base. The emitter of the transistor QBIAS 1b is grounded.

  The base and collector of the transistor QCM1b are connected to each other, and the emitter of the transistor QCM1b is grounded. The collector of the transistor QCM1b is connected to the current source CSCM1b and the collector of the transistor SWCM1b, the emitter of the transistor SWCM1b is grounded, and the base is connected to the power supply VS3b. The current source CSCM1b generates a constant current ICM1b, and the current source CSCM1b, the transistor QCM1b, and the transistor QBIAS1b constitute a current mirror circuit, thereby generating a bias current IBIAS1b.

  The base of the transistor QSW1 is also connected to the base of the transistor QCM1b in common with the base of the transistor QBIAS1b. As a result, the transistor QCM1b is turned on / off as the transistor SWCM1b is turned on / off, and the transistor QBIAS1b and the transistor QSW1 are turned on / off in conjunction with each other. Thus, when the feedback circuit C1 is selected, the bias current IBIAS1b is selected accordingly.

  Although omitted in FIG. 23, a circuit similar to the circuit G is also connected to the feedback circuit Ck (k = 2 to n), and when the feedback circuit Ck (k = 2 to n) is selected, Accordingly, the bias current IBIASkb (k = 2 to n) is selected.

  FIG. 24 shows a circuit configuration in which only the transistor SW1 is turned on and only the bias current IBIAS1b is selected in the light receiving amplifier circuit 11, and the output voltage detection circuit 18 and the bias current adjustment circuit 19 are further added. ing. Further, the bias current is switched at the same time as the feedback circuit is selected.

  The circuit H shows a specific configuration of the output voltage detection circuit 18, the bias current adjustment circuit 19, and the bias current switching means associated with the feedback circuit selection. The base of the transistor QBIAS1b is connected to the base of the transistor QB1ba in common with the base of the transistor QSW1, and the emitter of the transistor QBIAS1b is grounded. The collector of the transistor QSW1 is connected to the base of the transistor SW1, and the emitter of the transistor QSW1 is grounded. The base and collector of the transistor QB1ba are connected to each other. The emitter of the transistor QB1ba is grounded, and the collector of the transistor QB1ba is connected to the collector of the transistor QB1bd and the collector of the transistor QB1bb. The base of the transistor QB1bd is connected to the power supply VS4b, and the emitter of the transistor QB1bd is grounded. The emitter of the transistor QB1bb is connected to the power supply Vcc, and the base of the transistor QB1bb is connected to the base of the transistor QB1bc. The base and collector of the transistor QB1bc are connected to each other, and the emitter of the transistor QB1bc is connected to the power supply Vcc, like the emitter of the transistor QB1bb. The collector of the transistor QB1bc is connected to one end of the resistor RB1b, and the other end of the resistor RB1b is connected to the output terminal Vo1 and the emitters of the transistors SW1 to SWn of the feedback circuits C1 to Cn. In the above circuit, the resistor RB1b constitutes the output voltage detection circuit 18, and the transistors QB1ba to QB1ad constitute the bias current adjustment circuit 19.

  In the above configuration, the output voltage Vo1 is detected by the resistor RB1b. Since the transistors QB1bc and QB1bb, and the transistors QB1ba and QBIAS1b constitute current mirror circuits, respectively, the magnitude of the bias current IBIAS1b is the resistance value of the resistor RB1b is ZRB1b, and the base-emitter voltage of the transistor QB1bc is VbeQB1bc. Then, it becomes as follows.

IBIAS1b = (Vcc−Vo1−VbeQB1bc) / ZRB1b (37)
As a result, the bias current IBIAS1b decreases / increases as the output voltage Vo1 increases / decreases.

  Further, when the resistance value ZRB1b of the resistor RB1b is equal to the resistance value Rf1 of the resistor FB1, the collector current IPD1 + IBIAS1b of the transistor SW1 is as follows.

From equation (37)
IBIAS1b = (Vcc−Vo1−VbeQB1bc) / ZRB1b
= (Vcc−VbeQB1bc − ((IPD1 × (Rf1 + ZSW1)) + (IBIAS1b × ZSW1))) / ZRB1b (38)
Organize
(1+ (ZSW1 / ZRB1b)) × IBIAS1b = ((ZRB1b + ZSW1) / ZRB1b) × IBIAS1b
= (Vcc−VbeQB1bc− (IPD1 × (Rf1 + ZSW1))) / ZRB1b (39)
Therefore,
IBIAS1b = ((Vcc−VbeQB1bc− (IPD1 × (Rf1 + ZSW1))) / ZRB1b) × (ZRB1b / (ZRB1b + ZSW1))
= (Vcc−VbeQB1bc− (IPD1 × (Rf1 + ZSW1))) / (ZRB1b + ZSW1) (40)
Therefore, the collector current IPD1 + IBIAS1b of the transistor SW1 is
IPD1 + IBIAS1b = IPD1 + ((Vcc−VbeQB1bc− (IPD1 × (Rf1 + ZSW1))) / (ZRB1b + ZSW1))
= (IPD1 x (ZRB1b + ZSW1)-IPD1 x (Rf1 + ZSW1) + Vcc-VbeQB1bc) / (ZRB1b + ZSW1)
= (IPD1 × (ZRB1b-Rf1)) / (ZRB1b + ZSW1) + (Vcc-VbeQB1bc) / (ZRB1b + ZSW1)
... (41)
Here, when both sides are differentiated by IPD1,
d (IPD1 + IBIAS1b) / dIPD1 = (ZRB1b-Rf1) / (ZRB1b + ZSW1) (42)
From the above, if ZRB1b = Rf1,
d (IPD1 + IBIAS1b) / dIPD1 = 0 (43)
Therefore,
IPD1 + IBIAS1b = const. (44)
That is, the collector current IPD1 + IBIAS1b of the transistor SW1 is constant regardless of the current IPD1, and the impedance of the transistor SW1 does not change even if the current IPD1 changes. Therefore, the gain of the feedback circuit does not change and a more accurate output voltage can be detected.

  Further, ON / OFF of the transistor QBIAS1b and the transistor QSW1 is interlocked, and the bias current IBIAS1b is selected along with the selection of the feedback circuit C1.

  Although omitted in FIG. 24, the feedback circuit Ck (k = 2 to n) is similarly connected to a circuit similar to the circuit H including the resistor RBkb (k = 2 to n) and the like. When the circuit Ck (k = 2 to n) is selected, the bias current IBIASkb (k = 2 to n) is selected.

Similarly, if ZRBkb = Rfk (k = 2 to n),
IPD1 + IBIASkb = const. (K = 2 to n) (45)
Is established. Therefore, the collector current IPD1 + IBIASKkb (k = 2 to n) of the transistor SWn (k = 2 to n) is constant regardless of the current IPD1, and the impedance of the transistor SWn (k = 2 to n) even if the current IPD1 changes. Does not change.

  FIG. 25 shows a configuration of the light receiving amplifier circuit 13 according to the present embodiment. The light receiving amplifier circuit 13 is configured by connecting bias current sources CSB1db to CSBndb to the offset voltage correction circuits Cd1 to Cdn of the light receiving amplifier circuit 11. is there. The bias current source CSB1db is connected between the resistor FBd1 of the offset voltage correction circuit Cd1 and the collector of the transistor SWd1, and generates a bias current IBIAS1db. Similarly, the bias current source CSBkdb (k = 2 to n) includes the resistor FBdk (k = 2 to n) of the offset voltage correction circuit Cdk (k = 2 to n) and the collector of the transistor SWdk (k = 2 to n). The bias current source CSBkda (k = 2 to n) generates a bias current IBIASkda (k = 2 to n). Thus, the collector current of the transistor SWdk (k = 2 to n) in the selected offset voltage correction circuit Cdk (k = 2 to n) increases by the bias current IBIASkdb (k = 2 to n), and the offset voltage Vod Is reduced.

  FIG. 26 shows a configuration of the light receiving amplifier circuit 14 according to the present embodiment. The light receiving amplifier circuit 14 has a configuration in which the bias current sources CSB1db to CSB1db are connected to the offset voltage correction circuits Cd1 to Cdn of the light receiving amplifier circuit 12. is there. The bias current source CSB1db is connected between the resistor FBd1 of the offset voltage correction circuit Cd1 and the collector of the transistor SWd1, and generates a bias current IBIAS1da. Similarly, the bias current source CSBkdb (k = 2 to n) includes the resistor FBdk (k = 2 to n) of the offset voltage correction circuit Cdk (k = 2 to n) and the collector of the transistor SWdk (k = 2 to n). The bias current source CSBk (k = 2 to n) da generates a bias current IBIASkda (k = 2 to n). Thus, the collector current of the transistor SWdk (k = 2 to n) in the selected offset voltage correction circuit Cdk (k = 2 to n) increases by the bias current IBIASkdb (k = 2 to n), and the offset voltage Vod Is reduced.

  Here, the relationship between the bias current IBIAS1b and the bias current IBIAS1db will be described below.

  FIG. 27 shows a configuration when the feedback circuit C1 and the offset voltage correction circuit Cd1 are selected in the light receiving amplifier circuit 13, and the feedback circuit and the offset voltage correction circuit that are not selected are shown for the sake of simplicity. Absent. Further, it is assumed that there is no signal and the current IPD1 = 0 from the light receiving element PD1.

  Here, the potential difference between the positive input terminal of the differential amplifier Amp1 and the reference voltage source VS1 is VFBd1b, the potential difference between the light receiving element PD1 and the output terminal Vo1 is VFB1b, and the current to the positive input terminal of the differential amplifier Amp1 is Ib2b. When the current to the negative input terminal of the dynamic amplifier Amp1 is Ib1b and the potential difference between the positive input terminal and the negative input terminal of the differential amplifier Amp1 is VoffAb, the offset voltage Vod of the differential amplifier is as follows.

Vod = Vo1-VS1
= VS1−VFBd1b−VoffAb + VFB1b−VS1
= VFB1b-VFBd1b-VoffAb (46)
When the bias current source CSB1b and the bias current source CSB1db are connected, VoffAb = 0
Vod = VFB1b−VFBd1b−VoffAb
≒ (ZFB1 x Ib1b) + ((ZSW1 x (Ib1b + IBIAS1b))-((ZFBd1 x Ib2b) + ((ZSWd1 x (Ib2b + IBIAS1b)))
... (47)
Here, if ZFB1 = ZFBd1, ZSW1 = ZSWd1, and Ib1b = Ib2b = 0, then
Vod = ((ZSW1 × IBIAS1b)-(ZSWd1 × IBIAS1b)
= ZSW1 × (IBIAS1b-IBIAS1b) (48)
It becomes. At this time,
IBIAS1b = IBIAS1db (49)
If Vod holds, Vod = 0 and the offset voltage Vod can be minimized.

Similarly, when other feedback circuits and offset voltage correction circuits are selected,
IBIASkb = IBIASkdb (k = 2 to n) (50)
Is established, the offset voltage Vod can be minimized.

  Therefore, the magnitudes of the respective bias currents generated by the bias current source connected to the feedback circuit and the bias current source connected to the offset voltage correction circuit selected corresponding thereto are equal to each other.

  FIG. 28 shows a specific circuit configuration for linking the offset voltage correction circuit Cd1 and the bias current source CSB1db in the light receiving amplifier circuit 13. The circuit I has a configuration in which a transistor QBIASd1b and a transistor QSWd1 are further provided in the circuit F of FIG. The bases of the transistors QBIASd1b and QSW1d are both connected in common with the base of the transistor QCM1. The collector of the transistor QBIASd1b is connected between the resistor FBd1 of the offset voltage correction circuit Cd1 and the collector of the transistor SWd1, and the emitter of the transistor QBIASd1b is grounded. The collector of the transistor QSWd1 is connected to the base of the transistor SWd1, and the emitter of the transistor QSW1d is grounded.

  Thereby, ON / OFF of the transistor QBIASd1b and the transistor QSWd1 is interlocked, and similarly, ON / OFF of the transistor QBIAS1b and the transistor QSW1 is also interlocked. Since current source CSCM1b, transistor QBIAS1b, transistor QSW1, transistor QBIASd1b, and transistor QSWd1 form a current mirror circuit, bias current IBIAS1b and bias current IBIAS1db are equal to each other.

  Although omitted in FIG. 28, the feedback circuit Ck (k = 2 to n) is selected similarly for the feedback circuit Ck (k = 2 to n) and the offset voltage correction circuit Cdk (k = 2 to n). Then, the offset voltage correction circuit Cdk (k = 2 to n), the bias current IBIASkb (k = 2 to n), and the bias current IBIASkdb (k = 2 to n) are selected. Also, the bias current IBIASkb (k = 2 to n) and the bias current IBIASkdb (k = 2 to n) are equal to each other.

  FIG. 29 shows a specific circuit configuration for linking the offset voltage correction circuit Cd1 and the bias current source CSB1db in the light receiving amplifier circuit 14. The circuit J has a configuration in which the transistor QBIASd1b and the transistor QSWd1 are further added to the circuit H in FIG. 24, and the bases of the transistor QBIASd1b and the transistor QSW1d are both connected in common to the base of the transistor QCM1. The collector of the transistor QBIASd1b is connected between the resistor FBd1 of the offset voltage correction circuit Cd1 and the collector of the transistor SWd1, and the emitter of the transistor QBIASd1b is grounded. The collector of the transistor QSW1d is connected to the base of the transistor SWd1, and the emitter of the transistor QSWd1 is grounded.

  Thereby, ON / OFF of the transistor QBIASd1b and the transistor QSWd1 is interlocked, and similarly, ON / OFF of the transistor QBIAS1b and the transistor QSW1 is also interlocked. Since current source CSCM1b, transistor QBIAS1b, transistor QSW1, transistor QBIASd1b, and transistor QSWd1 form a current mirror circuit, bias current IBIAS1b and bias current IBIAS1db are equal to each other.

  Although omitted in FIG. 29, the feedback circuit Ck (k = 2 to n) is selected similarly for the feedback circuit Ck (k = 2 to n) and the offset voltage correction circuit Cdk (k = 2 to n). Then, the offset voltage correction circuit Cdk (k = 2 to n), the bias current IBIASkb (k = 2 to n), and the bias current IBIASkdb (k = 2 to n) are selected. Also, the bias current IBIASkb (k = 2 to n) and the bias current IBIASkdb (k = 2 to n) are equal to each other.

  FIG. 30 shows a configuration that simultaneously realizes switching of the bias current accompanying the selection of the feedback circuit along with adjustment of the bias current. The circuit K has a configuration in which a transistor QBIASd1b and a transistor QSWd1 are further added to the circuit H in FIG. The collector of the transistor QBIASd1b is connected between the resistor FBd1 of the offset voltage correction circuit Cd1 and the collector of the transistor SWd1, and the emitter of the transistor QBIASd1b is grounded.

  The collector of the transistor QSWd1 is connected to the base of the transistor SWd1, and the emitter of the transistor QSWd1 is grounded. The base of the transistor QBIASd1b and the base of the transistor QSWd1 are commonly connected to the base of the transistor QB1ba together with the base of the transistor QBIAS1b and the base of the transistor QSW1.

  Thereby, the bias current IBIAS1b satisfies the above formula (37), and the bias current IBIAS1b and the bias current IBIAS1db satisfy the above formula (49). Further, ON / OFF of the transistor QSW1 and the transistor QBIAS1b and ON / OFF of the transistor QSWd1 and the transistor QBIASd1b are linked, and the bias current IBIAS1b is selected along with the selection of the feedback circuit C1 including the resistor RB1, and the resistor FBd1 is included. With the selection of the offset voltage correction circuit Cd1, the bias current IBIAS1db is selected.

  Further, when the resistance value ZRB1b of the resistor RB1b and the resistance value Rf1 of the feedback resistor FB1 are equal, the collector current IPD1 + IBIAS1b of the transistor SW1 satisfies the above equation (44), and the impedance of the transistor SW1 does not change even when the current IPD1 changes. . Therefore, the gain of the feedback circuit does not change and a more accurate output voltage can be detected.

  Although omitted in FIG. 30, the feedback circuit Ck (k = 2 to n) and the offset voltage correction circuit Cdk (k = 2 to n) similarly include a resistor RBkb (k = 2 to n). When a circuit similar to the circuit E is connected and the feedback circuit Ck (k = 2 to n) is selected, the offset voltage correction circuit Cdk (k = 2 to n), the bias current IBIASkb (k = 2 to n) ) And a bias current IBIASkdb (k = 2 to n) are selected.

  Further, from the equation (50), the bias current IBIASkb (k = 2 to n) and the bias current IBIASkdb (k = 2 to n) are equal to each other, and the resistance value ZRBkb (k = k = 2 to n) of the resistor RBkb (k = 2 to n). 2 to n) and the resistance value Rfk (k = 2 to n) of the feedback resistor FBk (k = 2 to n) are equal, the collector current IPD1 + IBIASK of the transistor SWk (k = 2 to n) is (k = 2 to 2). n) satisfies the above formula (45).

  FIG. 31 is a circuit diagram showing a specific configuration of the differential amplifier Amp1 in the light receiving amplifier circuit 11 of FIG. The differential amplifier Amp1 includes a grounded emitter amplifier circuit CC1 (hereinafter “amplifier circuit CC1”) and a grounded collector amplifier circuit CC2 (hereinafter “amplifier circuit CC2”). The amplifier circuit CC1 has a transistor Q1 and a current source I1, and the amplifier circuit CC2 has a transistor Q2 and a current source I2. The cathode of the light receiving element PD1 is connected to the base of the transistor Q1 which is the input of the amplifier circuit CC1, and the base of the transistor Q2 which is the input of the amplifier circuit CC2 is connected to the collector of the transistor Q1 which is the output of the amplifier circuit CC1. Yes. The emitter of the transistor Q2, which is the output of the amplifier circuit CC2, corresponds to the output of the light receiving amplifier circuit 11.

  Further, feedback resistors FB1 to FBn selected by conduction / non-conduction of the transistors SW1 to SWn are connected in parallel between the base of the transistor Q1 and the output of the light receiving amplifier circuit 11, for example, the transistor SW1 and the feedback resistor. In the feedback circuit connected to FB1, a current source circuit including a current mirror circuit CM1b is provided.

Here, in order for the light receiving amplifier circuit of FIG. 31 to operate, the collector-emitter voltage of the transistors QSW1 to QSWn of the current mirror circuits CM1b to CMnb in each current source circuit is equal to the collector-emitter voltage Vce when the transistor is saturated. Must be higher than (sat). For example, when the collector-emitter voltage of QSW1 is VceQSW1,
VceQSW1 = VbeQ1 + ((IPD1 + Ib1) x Rf1) + ((IPD1 + Ib1 + IBIAS1) x ZSW1)-VbeSW1
... (51)
It becomes. Here, VbeQ1 and VbeSW1 are the base-emitter voltages of the transistors Q1 and SW1, respectively, and Ib1 is the base current of the transistor Q1.

Since VceQSW1 is minimum when IPD1 = 0, assuming that the characteristics of each transistor are the same, VbeQ1 = VbeSW1, Ib1 is very small, and Ib1 = 0 is approximated, the minimum value VceQSW1min of VceQSW1 is
VceQSW1min ＝ IBIAS1 × ZSW1 (52)
It becomes. Here, if VceQSW1min is higher than the collector-emitter voltage Vce (sat) when the transistor is saturated, the light receiving amplifier circuit operates.
IBIAS1 × ZSW1> Vce (sat) (53)
If this condition is satisfied, the light receiving amplifier circuit operates.

Similarly, when another feedback circuit is selected,
IBIASk × ZSWk> Vce (sat) (k = 2 to n) (54)
That is, it is sufficient that the product of the bias current value and the impedance of the transistor SWk (k = 2 to n) as the feedback circuit selection switch is larger than the collector-emitter voltage when the transistor is saturated.

When the expression (53) is not satisfied, that is,
IBIASk × ZSWk ≦ Vce (sat) (k = 2 to n) (55)
In this case, as shown in FIG. 32, in addition to the configuration of FIG. 31, a transistor Q3 is newly provided at the emitter of the transistor Q1, so that the collector-emitter voltage of the transistor QSWk (k = 2 to n) It is necessary to make it larger than the collector-emitter voltage at the time of saturation. The transistor Q3 functions as a diode by connecting the base and the collector.

In this case, the collector-emitter voltage of the transistor QSW1 is
VceQSW1 = VbeQ3 + VbeQ1 + ((IPD1 + Ib1) x Rf1) + ((IPD1 + Ib1 + IBIAS1) x ZSW1)-VbeSW1
... (56)
The minimum value of the collector-emitter voltage of the transistor QSW1 is IPD1 = 0, Vbe1 = VbeSW1, and Ib1 = 0 as in the case of the equation (15).
VceQSW1min ＝ VbeQ3 + (IBIAS1 × ZSW1) (57)
It becomes.

Therefore, in the configuration of FIG.
VbeQ3 + (IBIAS1 × ZSW1)> Vce (sat) (58)
If this condition is satisfied, the light receiving amplifier circuit operates.

If the output voltage of the light receiving amplifier circuit of FIG.
VOLmin31 = Vbe1 + (IBIAS1 × ZSWn) (59)
It becomes.

Here, in order to ensure a wider dynamic range of the light receiving amplifier circuit of the present embodiment than that of the light receiving amplifier circuit of the comparative example, the output voltage of the light receiving amplifier circuit of FIG. 19 when there is no signal is VOLmin19. VOLmin31 <VOLmin19, so from equation (31)
IBIAS1 × ZSWn <Vbe3 (60)
Should be satisfied. That is, the bias current may be adjusted so that the product of the bias current and the impedance of the feedback circuit is lower than the base-emitter voltage of the transistor.

[Embodiment 3]
Another embodiment of the present invention will be described below with reference to FIG. Also in the present embodiment, the same reference numerals are given to components having the same functions as the components in the first and second embodiments, and the description thereof is omitted.

  FIG. 33 shows the configuration of the optical pickup 101 according to the present embodiment.

  As shown in FIG. 33, the optical pickup 101 includes a laser diode 111, light receiving ICs 112 and 113 for laser power monitoring, a signal light receiving IC 114, a collimator lens 115, a spot lens 116, a beam splitter 117, a collimator lens 118, and an objective lens 119. It has.

  A laser diode 111 as a laser light source emits two types of laser beams, a 780 nm laser beam for CD and a 650 nm laser beam for DVD. The drive current supplied to the laser diode 111 is generated by a laser driver (not shown).

  The laser power monitoring light receiving ICs 112 and 113 incorporate any of the light receiving amplifier circuits 1 to 7 and the light receiving amplifier circuits 11 to 14 of the above-described first or second embodiment. Diode) PD1 is arranged. The light receiving ICs 112 and 113 for laser power monitoring are ICs for receiving a part of the laser beam emitted from the laser diode 111 and converting it into an electric signal as a detection signal. The position of the light receiving IC for laser power monitoring is not limited to the illustrated position as long as it can receive an amount necessary for detecting the laser beam.

  In the optical pickup 101 configured as described above, the laser beam emitted from the laser diode 111 is converted into a parallel light beam by the collimator lens 115 and deflected by the beam splitter 117. The laser beam from the beam splitter 117 is further focused on the optical disk 120 by the objective lens 119 through the collimator lens 118. The laser beam reflected from the optical disk 120 passes through the objective lens 119 and the collimator lens 118, passes through the beam splitter 117, and is then focused on the signal light receiving IC 114 by the spot lens 116. In the signal light receiving IC 114, the laser beam is converted into an electric signal, and an RF signal, a tracking error signal, and the like are generated from the electric signal.

  On the other hand, the laser power monitoring light receiving ICs 112 and 113 receive the laser beam emitted from the laser diode 111, and the laser beam is received by any one of the built-in light receiving amplifier circuits 1 to 7 and light receiving amplifier circuits 11 to 14. Is detected as an output voltage Vo1 (detection signal). This detection signal is given to a laser driver (not shown). The laser driver controls the drive current of the laser diode so that the power of the laser beam becomes a predetermined value while monitoring the detection signals from the light receiving ICs 112 and 113 for monitoring the laser power.

  As described above, in the optical pickup 101, the laser power monitoring light receiving ICs 112 and 113 incorporate any one of the light receiving amplifier circuits 1 to 7 and the light receiving amplifier circuits 11 to 14, so that the laser power monitoring light receiving IC is provided. Since the detection signal for the received laser beam has little error with respect to the intensity of the laser beam, the laser power can be controlled with high accuracy.

  In the present embodiment, it has been described that the laser power monitoring light receiving ICs 112 and 113 include any one of the light receiving amplifier circuits 1 to 7 and the light receiving amplifier circuits 11 to 14, but the signal light receiving IC 114 is the light receiving amplifier circuit. Any one of 1 to 7 and the light receiving amplifier circuits 11 to 14 may be incorporated.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and the embodiments can be obtained by appropriately combining technical means disclosed in different embodiments. The form is also included in the technical scope of the present invention.

  The light receiving amplifier circuit according to the present invention can be suitably applied to an optical disc apparatus capable of accurate current-voltage conversion with little error with respect to an input signal from a light receiving element.

1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 1. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 2. FIG. It is a graph which shows the relationship between the gain of a light reception amplifier circuit, and the collector current of the transistor provided in the feedback circuit. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 1. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 3. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 4. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 3. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 1. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 3. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 5. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 6. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 5. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 7. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 7. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 7. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 7. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 3. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 3. FIG. It is a circuit diagram which shows the electrical constitution of the light reception amplifier circuit which concerns on the comparative example with respect to this invention. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 11. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 12. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 11. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 12. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 11. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 13. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 14. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 13. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 13. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 14. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 13. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 11. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of a light receiving amplifier circuit 11. FIG. 1, showing an embodiment of the present invention, is a circuit diagram showing an electrical configuration of an optical pickup 101. FIG. FIG. 9 is a circuit diagram showing a conventional technique and showing an electrical configuration of a light receiving amplifier circuit 91; FIG. 9 is a circuit diagram showing a conventional technique and showing an electrical configuration of a light receiving amplifier circuit 92; It is a graph which shows the relationship between the gain of a light reception amplifier circuit, and the collector current of the transistor provided in the feedback circuit.

Explanation of symbols

1 to 6, 11 to 14 Light receiving amplifier circuit 8, 18 Output voltage detection circuit (current detection circuit)
9, 19 Bias current adjustment circuit 101 Optical pickup 111 Laser diode (laser light source)
112, 113 Light receiving IC for laser power monitor
114 Light receiving IC for signal
Amp1, 3 Differential amplifier Amp2 Amplifier Ampd Dummy amplifier C1-Cn Feedback circuit Cd1-Cdn Offset voltage correction circuit CM1a Current mirror circuit CM1b Current mirror circuit FB1-FBn Feedback resistor (first resistor)
FBd1 to FBdn resistance (second resistance)
CSB1a to CSBna Bias current source (first bias current source)
CSB1da to CSBnda Bias current source (second bias current source)
CSB1b to CSBnb Bias current source (first bias current source)
CSB1da to CSBnda Bias current source (second bias current source)
IBIAS1a to IBIASna Bias current (first bias current)
IBIAS1da to IBIASnda Bias current (second bias current)
IBIAS1b to IBIASnb Bias current (first bias current)
IBIAS1db to IBIASndb Bias current (second bias current)
PD1 Light receiving element (photodiode)
SW1 to SWn transistors (first transistor)
QCM1a to QCMna transistor (second transistor)
QCM1b to QCMnb transistors (second transistors)
QSW1 to QSWn transistors (third transistor)
QBIAS1a to QBIASna transistors (4th transistor)
QBIAS1b to QBIASnb transistors (4th transistor)
SWd1 to SWdn transistors (5th transistor)
QSWd1 to QSWdn transistors (6th transistor)
QBIAS1da to QBIASnda transistors (seventh transistor)
QBIAS1db to QBIASndb transistors (seventh transistor)

Claims (18)

A plurality of feedback circuits in which a light-receiving element, an amplifier that converts a current generated in the light-receiving element into a voltage and amplifies, a first resistor and a first transistor that turns on and off the feedback circuit, and the feedback circuit; A plurality of offset voltage correction circuits for correcting the output voltage when there is no current from the light receiving element for each of the,
The light receiving element is connected to a first input terminal of the amplifier;
The plurality of feedback circuits are connected in parallel between a connection point between the light receiving element and the first input terminal, and an output terminal of the amplifier,
The impedances of the first resistors are different from each other,
The offset voltage correction circuit is a photoreceiver amplifier circuit connected in parallel between the second input terminal of the amplifier and a reference voltage source ,
A first bias current source for generating a first bias current flowing through the first transistor ;
The bias current source is connected to the light receiving element and the plurality of feedback circuits,
A light receiving amplifier circuit, wherein a current obtained by adding the current generated in the light receiving element and the first bias current flows through the first transistor that is conducting .   2. The light receiving amplifier circuit according to claim 1, wherein the first bias current source causes the first bias current to flow through a connection point between the light receiving element and the amplifier.   3. The light receiving amplifier circuit according to claim 2, wherein only one bias current source is provided, and the first bias current source causes the first bias current to flow through the light receiving element and the connection point.   An operation control circuit comprising the first bias current source corresponding to each of the feedback circuits and operating the first bias current source to which the first transistor is connected only when the first transistor is conductive. The light receiving amplifier circuit according to claim 2, further comprising:   The first bias current source is provided individually corresponding to the feedback circuit, and the first bias current source is connected between the first resistor and the first transistor in each feedback circuit. The light receiving amplifier circuit according to claim 1, wherein:   6. The light receiving amplifier circuit according to claim 5, further comprising an operation control circuit that operates the first bias current source to which the first transistor is connected only when the first transistor is conductive. . The operation control circuit includes a constant current source that generates a constant current, a diode-connected second transistor that supplies the constant current, a base connected to the second transistor, and a base connected to the first transistor. The light-receiving amplifier circuit according to claim 4, wherein the first bias current source includes a fourth transistor that forms a current mirror circuit with the second transistor. Upper Symbol offset voltage correction circuit generates a second resistor, and a fifth transistor for ON / OFF the offset voltage correction circuit is connected to the second resistor in series with a second bias current supplied to the fifth transistor A second bias current source;
The first bias current and the second bias current that flow simultaneously are equal in current value,
The feedback circuit and the offset voltage correction circuit corresponding to each other are selected one by one, and the first resistance in the selected feedback circuit and the second resistance in the selected offset voltage correction circuit have the same resistance value. The light receiving amplifier circuit according to claim 1, wherein: Further, each of the feedback circuits includes a plurality of offset voltage correction circuits for correcting an output voltage when there is no current from the light receiving element.
The offset voltage correction circuit is connected in parallel between the second input terminal of the amplifier and a reference voltage source. The offset voltage correction circuit is turned on / off by connecting a second resistor and the second resistor in series. And a second bias current source for generating a second bias current flowing through the fifth transistor,
The first bias current and the second bias current that flow simultaneously are equal in current value,
The feedback circuit and the offset voltage correction circuit corresponding to each other are selected one by one, and the first resistance in the selected feedback circuit and the second resistance in the selected offset voltage correction circuit have the same resistance value. And
3. The second bias current source is connected to the second input terminal, and the second bias current flows through a connection point between the second bias current source and the second input terminal. The light receiving amplifier circuit described in 1. Further, each of the feedback circuits includes a plurality of offset voltage correction circuits for correcting an output voltage when there is no current from the light receiving element.
The offset voltage correction circuit is connected in parallel between the second input terminal of the amplifier and a reference voltage source. The offset voltage correction circuit is turned on / off by connecting a second resistor and the second resistor in series. And a second bias current source for generating a second bias current flowing through the fifth transistor,
The first bias current and the second bias current that flow simultaneously are equal in current value,
The feedback circuit and the offset voltage correction circuit corresponding to each other are selected one by one, and the first resistance in the selected feedback circuit and the second resistance in the selected offset voltage correction circuit have the same resistance value. And
One second bias current source is provided, the second bias current source is connected to the second input terminal, and the second bias current source is connected to the second bias current source via a connection point between the second bias current source and the second input terminal. The light receiving amplifier circuit according to claim 3, wherein a current flows. Further, each of the feedback circuits includes a plurality of offset voltage correction circuits for correcting an output voltage when there is no current from the light receiving element.
The offset voltage correction circuit is connected in parallel between the second input terminal of the amplifier and a reference voltage source. The offset voltage correction circuit is turned on / off by connecting a second resistor and the second resistor in series. And a second bias current source for generating a second bias current flowing through the fifth transistor,
The first bias current and the second bias current that flow simultaneously are equal in current value,
The feedback circuit and the offset voltage correction circuit corresponding to each other are selected one by one, and the first resistance in the selected feedback circuit and the second resistance in the selected offset voltage correction circuit have the same resistance value. And
The second bias current source is provided corresponding to each of the offset voltage correction circuits, is connected to the second input terminal, and has a connection point between the second bias current source and the second input terminal. And passing the second bias current through
The operation control circuit further operates the second bias current source to which the fifth transistor is connected only when the fifth transistor is conductive.
A constant current source for generating a constant current; a diode-connected second transistor for supplying the constant current; a third transistor for commonly turning on and off the first transistor; A sixth transistor for turning on / off the fifth transistor,
The first bias current source is a fourth transistor that forms a current mirror circuit with the second transistor,
5. The light receiving amplifier circuit according to claim 4, wherein the second bias current source is a seventh transistor constituting a current mirror circuit with the second transistor. Further, each of the feedback circuits includes a plurality of offset voltage correction circuits for correcting an output voltage when there is no current from the light receiving element.
The offset voltage correction circuit is connected in parallel between the second input terminal of the amplifier and a reference voltage source. The offset voltage correction circuit is turned on / off by connecting a second resistor and the second resistor in series. And a second bias current source for generating a second bias current flowing through the fifth transistor,
The first bias current and the second bias current that flow simultaneously are equal in current value,
The feedback circuit and the offset voltage correction circuit corresponding to each other are selected one by one, and the first resistance in the selected feedback circuit and the second resistance in the selected offset voltage correction circuit have the same resistance value. And
The second bias current source is provided corresponding to each of the offset voltage correction circuits, and is connected between the second resistor and the fifth transistor in each offset voltage correction circuit. The light receiving amplifier circuit according to claim 5, wherein: Further, each of the feedback circuits includes a plurality of offset voltage correction circuits for correcting an output voltage when there is no current from the light receiving element.
The offset voltage correction circuit is connected in parallel between the second input terminal of the amplifier and a reference voltage source. The offset voltage correction circuit is turned on / off by connecting a second resistor and the second resistor in series. And a second bias current source for generating a second bias current flowing through the fifth transistor,
The first bias current and the second bias current that flow simultaneously are equal in current value,
The feedback circuit and the offset voltage correction circuit corresponding to each other are selected one by one, and the first resistance in the selected feedback circuit and the second resistance in the selected offset voltage correction circuit have the same resistance value. And
The second bias current source is provided individually corresponding to the offset voltage correction circuit, and is connected between the second resistor and the fifth transistor in each offset voltage correction circuit,
The operation control circuit further operates the second bias current source to which the fifth transistor is connected only when the fifth transistor is conductive.
A constant current source for generating a constant current; a diode-connected second transistor for supplying the constant current; a third transistor for commonly turning on and off the first transistor; A sixth transistor for turning on / off the fifth transistor,
The first bias current source is a fourth transistor that forms a current mirror circuit with the second transistor,
The light receiving amplifier circuit according to claim 6, wherein the second bias current source is a seventh transistor that forms a current mirror circuit with the second transistor. The impedance between the connection point of each first bias current source in the feedback circuit and the output terminal is defined as a first feedback circuit impedance.
14. The product of the first feedback circuit impedance and the first bias current is larger than a collector-emitter voltage at the time of saturation of a transistor provided in the light receiving amplifier circuit. The light receiving amplifier circuit described.   15. The light receiving amplifier circuit according to claim 14, wherein a product of the first bias current and the first feedback circuit impedance is smaller than a base-emitter voltage of a transistor provided in the light receiving amplifier circuit. The first bias current is turned ON / OFF in accordance with the ON / OFF of the feedback circuit, the sum of the impedance between the first resistor and the first transistor as the second feedback circuit impedance at each feedback circuit,
The smaller the second feedback circuit impedance of the selected feedback circuit is, the larger the first bias current source is selected. The larger the second feedback circuit impedance of the selected feedback circuit is, the smaller the first bias is. 16. The light receiving amplifier circuit according to claim 4, wherein a current source is selected. The first bias current is the sum of the product of the maximum value of the current from the light receiving element and the second feedback circuit impedance and the output voltage of the amplifier when there is no current from the light receiving element. The light receiving amplifier circuit according to claim 16, wherein the light receiving amplifier circuit is set to be smaller than a maximum allowable output voltage. Claims 1 to an optical pickup, characterized in that a light receiving amplifier circuit according to any one of 17.

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