JP4080403B2 - Light receiving amplifier circuit and optical pickup - Google Patents

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light receiving element with a built-in circuit mounted on an optical pickup used for reproducing / recording an optical disk, and particularly suitable for use in a front monitor element that outputs a signal for monitoring / controlling laser power. The present invention relates to an amplifier circuit and an optical pickup.

  An optical disc apparatus for reproducing / recording an optical disc includes an optical pickup that irradiates the optical disc with a laser beam for reproduction / recording and receives reflected light from the optical disc. The optical pickup receives the reflected light and monitors the laser light emitted from the laser light source to convert it into an electric signal and a light receiving amplifier circuit for amplifying the converted electric signal. And are provided. In recent years, since the optical pickup can be easily designed in a small size, an IC in which a light receiving element and a light receiving amplifier circuit are integrated on one chip is used for the optical pickup.

  FIG. 12 shows a light receiving amplifier circuit including a conventional differential amplifier circuit. In this light receiving amplifier circuit, the light received by the photodiode PD21 is converted into a photocurrent, and the photocurrent output from the photodiode PD21 is an inverting amplifier (current −) in which a feedback resistor R22 is connected to a differential amplifier circuit. The voltage is converted into a voltage by a voltage conversion circuit), and an output voltage Vo proportional to the photocurrent is obtained. The differential amplifier circuit in the light receiving amplifier circuit includes transistors Q21 to Q25 and constant current sources CS21 and CS22.

  The NPN transistors Q21 and Q22 form a differential transistor pair, and the PNP transistors 23 and 24 that supply collector currents to the transistors Q21 and Q22, respectively, constitute a current mirror circuit. The input voltage Vs is input as a reference voltage to the base of the transistor Q21 (non-inverting input terminal of the differential amplifier circuit) via the input resistor R21. The photocurrent of the photodiode PD21 is supplied from the emitter of Q25 via the resistor R22. The constant current source CS21 supplies a constant current so that the sum of the emitter currents of the transistors Q21 and Q22 is constant. The NPN transistor Q25 as an output transistor forms an emitter follower circuit, and outputs an output voltage Vo from the collector of the transistor Q24. The constant current source CS22 supplies a constant current to the transistor 25.

The offset voltage of the differential amplifier circuit configured as described above will be described. In the following description, the characteristics of the NPN transistors are common, the characteristics of the PNP transistors are also common, and variations between the transistors are not considered. In the differential amplifier circuit shown in FIG. 12, the output voltage Vo when there is no input is
Vo = Vs-(Ibn1 x Rf)-Vben1 + Vben2 + (Ibn2 x Rf)
= Vs− (Rf × Icn1 / hFEn) −VT × ln (Icn1 / Is) + VT × ln (Icn2 / Is) + (Rf × Icn2 / hFEn)
= Vs + ((Icn2-Icn1) x Rf / hFEn) + VT x ln (Icn2 / Icn1) (1)
Here, each parameter in the above equation is shown as follows.
hFEn: NPN transistor current gain
VT: Thermoelectromotive force represented by kT / q (k is Boltzmann constant, T is absolute temperature, and q is electronic charge)
Ibn1: Base current of transistor Q21
Ibn2: Base current of transistor Q22
Vben1: Base-emitter voltage of transistor Q21
Vben2: Base-emitter voltage of transistor Q22
Icn1: collector current of transistor Q21
Icn2: collector current of transistor Q22
Icp1: Collector current of transistor Q23
Icp2: Collector current of transistor Q24
Ibp1: Base current of transistor Q23
Ibp2: Base current of transistor Q24
Ibp3: Base current of transistor Q25
Rf: Resistance values of the resistors R21 and R22 Therefore, the difference voltage between the output voltage Vo and the reference voltage Vs, that is, the offset voltage Voff is expressed by the following equation.

Voff = Vo-Vs = ((Icn2-Icn1) * Rf / hFEn) + VT * ln (Icn2 / Icn1) (2)
From this equation, it can be seen that the difference between Icn1 and Icn2 causes the offset voltage. Conversely, if Icn1 = Icn2, Voff = 0 and no offset voltage is generated.

The main cause of the difference between Icn1 and Icn2 is the base current (Ibp1, Ibp2) of the current mirror circuit, which is composed of transistors Q23 and Q23 and is used as an active load. In the circuit of FIG.
Icn1 = Icp1 + Ibp1 + Ibp2 (3)
Icn2 = Icp2-Ibn3 (4)
The relationship holds. Also, as the characteristics of the current mirror circuit, since Icp = Icp1 = Icp2 and Ibp = Ibp1 = Ibp2, the difference between Icn1 and Icn2 is
Icn1−Icn2 = 2 × Ibp + Ibn3 (5)
And causes an offset voltage. The first term on the right side of Equation (5) is the base current error (sum of base currents) of the current mirror circuit used as an active load, and the second term is the base current of the emitter follower circuit used as the output circuit.

  Conventionally, the circuit of FIG. 13 has been used to compensate for this error. In this circuit, an NPN transistor Q26, a PNP transistor Q27, and constant current sources CS23 and CS24 are added to the circuit of FIG. A transistor Q26 and a constant current source CS23 are connected in series between the power supply voltage Vcc and the ground line, and similarly, a transistor Q27 and a constant current source CS24 are connected in series. The bases of the transistors Q26 and 27 are both connected to the collector of the transistor Q23. In the circuit of FIG. 13 configured as described above, if Ibn4 and Ibn5 are the base currents of the transistors Q26 and Q27, respectively, Icn1, Icn2 and their difference are expressed by the following equations.

Icn1 = Icp1 + Ibp1 + Ibp2-Ibn4-Ibn5 (6)
Icn2 = Icp2-Ibn3 (7)
Icn1-Icn2 = 2 × Ibp + Ibn3-Ibn4-Ibn5 (8)
However, if Ibp = Ibp1 = Ibp2 and Icn3 = Icn4 (collector current of the transistor Q26), then Ibn3 = Icn3 / hFEn = Icn4 / hFEn = Ibn4, so that the current IEE flowing through the constant current source CS21 is IEE = 2 × When approximated with Icp, equation (8) is expressed as the following equation.

Icn1−Icn2 = 2 × Ibp−Ibn5
= 2 × (Icp / hFEp) − (Icn5 / hFEn)
= (IEE / hFEp)-(Icn5 / hFEn) (9)
Here, hFEp is a current amplification factor of the PNP transistor.

  Here, if Icn5 which is the collector current of the transistor Q28 is adjusted so that (IEE / hFEp) = (Icn5 / hFEn), Icn1 = Icn2 and no offset voltage is generated.

  Alternatively, the circuit of FIG. 14 has been conventionally used to compensate for the errors of Icn1 and Icn2. In this circuit, the transistor Q27 and the constant current source CS24 are deleted from the circuit of FIG. 13, and a PNP transistor Q28 and a constant current source CS25 are provided. A constant current source 25 and a transistor Q28 are connected in series between the power supply voltage Vcc and the ground line. The base of the transistor Q28 is connected to the collector of the transistor Q24. In the circuit configured as described above, Icn1, Icn2 and a difference between them are expressed by the following equations.

Icn1 = Icp1 + Ibp1 + Ibp2-Ibn4 (10)
Icn2 = Icp2-Ibn3 + Ibp3 (11)
Icn1−Icn2 = 2 × Ibp + Ibn3-Ibn4-Ibp3 (12)
However, if Ibp = Ibp1 = Ibp2 and Icn3 = Icn4, then Ibn3 = Icn3 / hFEn = Icn4 / hFEn = Ibn4. Therefore, when the current IEE flowing through the constant current source CS21 is approximated to 8 by IEE = 2 × Icp, (12) is expressed by the following equation.

Icn1−Icn2 = 2 × Ibp−Ibp3
= 2 × (Icp / hFEp) − (Icp3 / hFE1)
= (IEE / hFEp)-(Icp3 / hFEp) (13)
Here, if the current Icp3 flowing through the constant current source CS25 is Icp3 = IEE,
Icn1−Icn2 = (IEE / hFEp) − (IEE / hFEp) = 0 (14)
Thus, Icn1 = Icp1, and the offset voltage is compensated.

Note that Patent Documents 1 (FIG. 1) and 2 are cited as prior art documents disclosing a functionally equivalent circuit that is different in configuration from the circuit of FIG. In the differential amplifier circuit disclosed in Patent Document 1, the transistor for correcting the base current according to Equation (13) and the output transistor are common transistors. Further, in the circuit of Patent Document 2, since the transistor and the output transistor constituting the current mirror circuit are both NPN type transistors, the above correction of the base current is performed by one NPN type transistor.
JP 2000-114888 A (released on April 21, 2000) JP-A-8-130421 (published on May 21, 1996)

  The front monitor element in the optical pickup is a laser light quantity monitoring element that receives a laser beam and outputs a monitor voltage corresponding to the light quantity. The laser driver controls the drive current of the laser light source based on the monitor voltage fed back from the front monitor element so that the laser beam has a predetermined laser power value.

  In recent years, with the increase in the recording speed of optical disks, the laser power during recording has increased. However, the output voltage range of the front monitor element is limited. For example, when the power supply voltage = 5V and the reference voltage = 2.5V, only an output voltage range of less than 2.5V can be secured. For this reason, if the amount of incident light increases due to an increase in laser power, the voltage corresponding to the incident light cannot be output unless the sensitivity of the front monitor element is lowered accordingly. On the other hand, since it is not necessary to increase the laser power during reproduction as in recording, if the sensitivity of the front monitor element is lowered in accordance with the laser power during recording, the output signal during reproduction will be small. For this reason, it is necessary to reduce the error of the output voltage, that is, the offset voltage and the offset voltage temperature characteristic, in order to accurately output a voltage corresponding to the laser power particularly during reproduction.

  Here, in the integrated circuit, hFEp and hFEn usually vary independently. Therefore, in order to compensate for the offset voltage, the base current Ibp of the PNP transistor is compensated by the base current Ibn5 of the NPN transistor. And hFEn vary, equation (9) is not zero and an offset voltage is generated. Conventionally, hFEn and hFEp have different temperature characteristics and change independently. Therefore, the offset voltage varies with temperature, and the temperature characteristics increase. In this regard, in the circuit of FIG. 14, since the base current Ibp of the PNP transistor is compensated by the base current Ibp3 of the same PNP transistor, Ibp and Ibp3 always have zero because they have the same temperature characteristics and the same variation.

  However, in the circuit of FIG. 14, when the voltage Va of the collector of the transistor Q24 is high because the value of Vcc−Vs is small, the transistor Q28 is turned off, particularly under the condition of Vcc−Va <Vbep3 + Vicp3. Since Ibp3 becomes zero, Ibp is not corrected. Note that Vbep3 of the transistor Q28 is a base-emitter voltage necessary for the operation of the transistor Q28, and Vicp3 is a voltage necessary for the operation of the current source CS25.

  Therefore, Expression (13) is expressed as the following expression.

Icn1−Icn2 = 2 × Ibp−Ibp3
= (IEE / hFEp)-(Icp3 / hFEp)
= (IEE / hFEp) (15)
For this reason, since Icn1 = Icn2 does not hold, the offset voltage cannot be made zero.

  The present invention has been made in view of the above problems, and its purpose is to compensate for the offset voltage and the offset voltage temperature characteristic so that the front monitor element can accurately output a voltage corresponding to the laser power. An object of the present invention is to provide a light receiving amplifier circuit having a differential amplifier circuit.

  The light-receiving amplifier circuit of the present invention includes a differential amplifier circuit that includes a differential transistor pair and a first current mirror circuit serving as an active load of the differential transistor pair, and outputs a voltage corresponding to the output current of the light-receiving element. In the light receiving amplifier circuit, in order to solve the above problem, the difference between the currents flowing through the differential transistor pair represented by the sum of the base currents of the transistor pairs constituting the first current mirror circuit is calculated. A correction means for reducing a correction current having the same value, the same temperature characteristic, and the same variation as the sum of the base currents is provided.

  In the light receiving amplifier circuit, the correction means includes a second current mirror circuit having the same configuration as the first current mirror circuit, a collector current of the main transistor of the second current mirror circuit, and base currents of the main and sub transistors. The first constant current circuit for extracting the first current mirror and the second current mirror circuit for extracting the correction current from the collector current of the sub transistor of the second current mirror circuit and the correction current from the collector current of the main transistor of the first current mirror circuit and the base current of both transistors. It is preferable to have two constant current circuits.

  The light receiving amplifier circuit preferably includes a correction current adjusting unit that is provided between the differential amplifier circuit and the correction unit and adjusts the correction current.

  In the light receiving amplifier circuit, it is preferable that the correction current adjusting unit adjusts the correction current by changing a voltage at a connection point between the second constant current circuit and a sub-transistor of the second current mirror circuit. .

  In this light receiving amplifier circuit, the correction current adjusting means is connected between a connection point between the second constant current circuit and the second current mirror circuit and a point at which the correction current of the first current mirror circuit is drawn. It is preferable that an inter-circuit transistor is provided, and that the connection point voltage is made variable by making the base voltage of the inter-circuit transistor variable.

  In the light receiving amplifier circuit, it is preferable that the correction current adjusting unit includes a variable voltage generating unit that applies a variable base voltage to the inter-circuit transistor. Specifically, the variable voltage generating means is configured as the following (1) to (3).

  (1) The variable voltage generating means is a variable voltage source.

  (2) The variable voltage generating means includes a plurality of diodes connected in series with a variable number of connections, and a current source for supplying current to the diodes.

  (3) The variable voltage generating means includes a plurality of series-connected resistors having a variable number of connections, and a current source for supplying a current to the resistors.

  In the light receiving amplifier circuit having the first and second constant current circuits, the correction means includes a current value adjusting means for adjusting a current value of the first constant current circuit and a current value of the second constant current circuit. It is preferable. Specifically, the current value adjusting means includes a diode-connected first transistor, a first variable resistor that makes the emitter resistance of the first transistor variable, and a constant current source that supplies current to the first transistor. And the first constant current circuit includes a second transistor having a base commonly connected to the first transistor, and a second variable resistor that makes the emitter resistance of the second transistor variable. The two constant current circuit includes a third transistor having a base commonly connected to the first transistor, and a third variable resistor that makes the emitter resistance of the third transistor variable.

  An optical pickup according to the present invention includes any one of the light receiving amplifier circuits described above. In particular, the light receiving amplifier circuit is preferably used for detecting the amount of laser beam emitted from a laser light source.

  In a differential amplifier circuit having a differential transistor pair and a current mirror circuit (first current mirror circuit) serving as an active load, as described above (Equation (5)), the offset voltage of the differential amplifier circuit is , Depending on the difference in current flowing through the individual transistors of the differential transistor pair, and the current difference is approximately expressed by the sum of the base currents of the transistor pairs constituting the current mirror. Therefore, in the light receiving amplifier circuit according to the present invention, the correction current having the same value, the same temperature characteristic, and the same variation as the sum of the base currents is subtracted by the correction means from the sum of the base currents generated in the differential amplifier circuit. Thus, the offset voltage can be substantially canceled regardless of the temperature.

  Specifically, as described above, the correcting means is realized by including the second current mirror circuit and the first and second constant current circuits. In this configuration, when the collector current of the main transistor of the second current mirror circuit and the base currents of the main and sub-transistors are extracted by the first constant current circuit, the collector current described above is supplied to the sub-transistor of the second current mirror circuit. The same collector current flows. The collector current is extracted by the second constant current circuit. At this time, the correction current is extracted from the collector current of one transistor of the first current mirror circuit and the base current of both transistors.

  With the above configuration, the offset voltage is ideally zero, but actually, the base current depends on the temperature gradient of the chip and the difference in element arrangement between the first current mirror circuit (active load) and the second current mirror circuit. It is conceivable that a gradual difference occurs between the sum of the two and the correction current. In order to eliminate this difference, the correction current is adjusted by providing the correction current adjusting means as described above.

  Specifically, since the base-emitter voltage and the collector-emitter voltage in the main transistor of the second current mirror circuit are equally fixed, the correction current adjusting means, as described above, The correction current is adjusted by making the voltage at the connection point with the sub-transistor (the collector thereof) of the second current mirror circuit variable by, for example, variable voltage generating means.

  Specifically, as the variable voltage generating means, the means as described in the above (1) to (3) are used, but the variable voltage generating means is not limited to these means as long as the variable voltage can be generated.

In the light receiving amplifier circuit having the first and second constant current circuits, the correction current can be adjusted by providing the correction means with the current value adjustment means as described above. The current value adjusting means described above is
Specifically, the base of the first transistor that is diode-connected and the base of the second transistor of the second constant current circuit and the base of the third transistor of the third constant current circuit are connected in common, so Three transistors form a current mirror circuit. Therefore, the correction current drawn into the second constant current circuit can be adjusted by adjusting the resistance values of the first to third variable resistors.

  The optical pickup of the present invention includes each light receiving amplifier circuit configured as described above, thereby compensating for the offset voltage of the differential amplifier circuit in the light receiving amplifier circuit. Therefore, in particular, when the light receiving amplifier circuit is used as a front monitor element for detecting the light amount of the laser beam emitted from the laser light source, the light receiving amplifier circuit accurately detects a voltage corresponding to the laser power for light amount detection. Can be output.

[Embodiment 1]
One embodiment of the light receiving amplifier circuit according to the present invention will be described below with reference to FIGS.

  FIG. 1 shows a configuration of a light receiving amplifier circuit 1 according to the present embodiment.

  The light receiving amplifier circuit 1 includes transistors Q1 to Q6, a differential amplifier circuit having constant current sources CS1 to CS3 and a correction current generation circuit 11, an input resistor R1, and a feedback resistor R2.

  The PNP transistors Q1 and Q2 form a differential transistor pair in the differential amplifier circuit, and both emitters are connected to the constant current source CS1. The constant current source CS1 is a circuit that maintains a constant current IEE of the current Icn1 flowing through the transistor Q1 and the current Icn2 flowing through the transistor Q2 at a constant value. A reference voltage Vs is applied to the reference voltage input terminal T1, and an input resistor R1 is connected between the reference voltage input terminal T1 and the base of the transistor Q1 serving as a non-inverting input terminal of the differential amplifier circuit 1. ing. On the other hand, the cathode of the photodiode PD1 as a light receiving element is connected to the base of the transistor Q2 serving as the inverting input terminal of the differential amplifier circuit 1. The anode of the photodiode PD1 is connected to the ground line. The base of the transistor Q2 is connected to the output terminal T2 of the light receiving amplifier circuit 1 via the feedback resistor R2.

  The PNP transistors Q3 and Q4 constitute a current mirror circuit as an active load. The emitters of the transistors Q3 and Q4 are connected to a power supply line to which the power supply voltage Vcc is applied. The bases of the transistors Q3 and Q4 are connected to each other and to the collector of the transistor Q3. The collector of the transistor Q3 is connected to the collector of the transistor Q1 and the base of the transistor Q5, and is also connected to the correction current generation circuit 11.

  The power supply line is connected to the collector of the NPN transistor Q5. A constant current source CS2 is connected between the emitter of the transistor Q5 and the ground line. On the other hand, the base of the transistor Q6 is connected to the collector of the transistor Q4. The power supply line is connected to the collector of the NPN transistor Q6. A constant current source CS3 is connected between the emitter of the transistor Q6 and the ground line. The transistor Q6 constitutes an output circuit composed of an emitter follower circuit, and outputs an output voltage Vo from the emitter to the output terminal constant 2.

  The correction current generation circuit 11 is a circuit that generates a correction current Ioffset drawn from the collector of the transistor Q3 and the bases of the transistors Q3 and Q4. The correction current Ioffset has the same value, the same temperature characteristic, and the same variation as the sum of the base currents of the transistors Q3 and Q4.

  The differential amplifier circuit constitutes an inverting amplifier that functions as a current-voltage conversion circuit by connecting a feedback resistor R2 between the output terminal T2 and a non-inverting input terminal (base of the transistor Q2). In the light receiving amplifier circuit 1 configured as described above, the light received by the photodiode PD1 is converted into a photocurrent, and the photocurrent output from the photodiode PD1 is converted into a voltage by the inverting amplifier. An output voltage Vo proportional to is obtained.

  Here, the offset voltage of the differential amplifier circuit in the light receiving amplifier circuit 1 will be described.

Each parameter in each equation used in the following description is shown as follows.
hFEn: NPN transistor current gain hFEp: PNP transistor current gain
Icn1: Collector current of transistor Q1
Icn2: collector current of transistor Q2
Icn3: collector current of transistor Q5
Icn4: Collector current of transistor Q6
Icp1: Collector current of transistor Q3
Icp2: Collector current of transistor Q4
Ibp1: Base current of transistor Q3
Ibp2: Base current of transistor Q4
Ibp3: Base current of transistor Q5
IEE: Current flowing through the constant current source CS1 First, Icn1 and Icn2 are expressed by the following equations.

Icn1 = Icp1 + Ibp1 + Ibp2-Ibn4-Ioffset (15)
Icn2 = Icp2-Ibn3 (16)
Since Icp1 = Icp2 as a characteristic of the current mirror circuit of the transistors Q3 and Q4, the difference between Icn1 and Icn2 is expressed by the following equation.

Icn1-Icn2 = Ibp1 + Ibp2 + Ibn3-Ibn4-Ioffset (17)
However, if Ibp = Ibp1 = Ibp2 and Icn3 = Icn4, then Ibn3 = Icn3 / hFEn = Icn4 / hFEn = Ibn4. Therefore, by approximating IEE = 2 × Icp = Icp1 + Icp2, equation (17) is It is expressed as follows.

Icn1−Icn2 = 2 × Ibp−Ioffset
= 2 × (Icp / hFEp) −Ioffset
= (IEE / hFEp) -Ioffset (18)
Therefore, if the correction current Ioffset is generated by the correction current generation circuit 11 so that IEE / hFEp = Ioffset and the same temperature characteristic and the same variation as IEE / hFEp, the offset voltage is always irrespective of the temperature / hFEp variation. It becomes zero.

  Next, a specific circuit for generating the correction current Ioffset by the correction current generation circuit 11 will be described. FIG. 2 shows a configuration of the light receiving amplifier circuit 1 including such a circuit.

  As shown in FIG. 2, the light receiving amplifier circuit 1 includes current mirror circuits 12 and 13.

  The current mirror circuit 12 as the first current mirror circuit is a circuit in which the base of the transistor Q3 (main transistor) and the base of the transistor Q4 (subtransistor) are connected to each other, and the base and collector of the transistor Q3 are connected. It is. In the current mirror circuit 13 as the second current mirror circuit, the base of the PNP transistor Q7 (main transistor) and the base of the transistor Q8 (subtransistor) are connected to each other, and the base and collector of the transistor Q7 are connected. Circuit. Transistors Q7 and Q8 have the same characteristics as transistors Q3 and Q4, respectively, so that current mirror circuit 13 has the same configuration as current mirror circuit 12.

  The emitters of the transistors Q7 and Q8 are connected to the power supply line. The light receiving amplifier circuit 1 includes constant current sources CS4 and CS5. The constant current source CS4 is connected between the collector of the transistor Q7 and the ground line, and the constant current source CS5 is connected between the collector of the transistor Q8 and the ground line. In the light receiving amplifier circuit 1, a correction current generation circuit 11 is configured by the current mirror circuit 13 and the constant current sources CS4 and CS5.

  In the light receiving amplifier circuit 1 described above, when the collector current of the transistor Q7 of the current mirror circuit 13 and the base currents of the transistors Q7 and Q8 are extracted by the constant current source CS4, the collector of the transistor Q7 is connected to the transistor Q8 of the current mirror circuit 13. The same collector current as the current flows. The collector current is extracted by the constant current source CS5. At this time, the correction current is also extracted from the collector current of the transistor Q3 of the current mirror circuit 12 and the base currents of the transistors Q3 and Q4.

  Here, offset voltage correction by the correction current generation circuit 11 configured as described above will be described.

Each parameter in each equation used in the following description is shown as follows.
Vbep1: Base-emitter voltage of transistor Q1
Vcep4: Collector-emitter voltage of transistor Q8
Icp3: Collector current of transistor Q7
Icp4: Collector current of transistor Q8
Ibp3: Base current of transistor Q7
Ibp4: Base current of transistor Q8
IEE / 2: Current flowing in constant current sources CS4 and CS5 As described above, if Ibp = Ibp1 = Ibp2 and IEE is approximated as IEE = 2 × Icp = Icp1 + Icp2, the collector currents of transistors Q7 and Q8 are given by It is expressed as follows.

Icp3 = (IEE / 2)-(Ibp3 + Ibp4) (19)
Icp4 = Icp3 (20)
IEE / 2 = Icp4 + Ioffset (21)
Therefore, from these equations, the correction current is determined as follows. However, Formula (22) is calculated | required by approximating IEE / 2 with IEE / 2 = Icp3 = Icp4.

Ioffset = (IEE / 2)-Icp4
= (IEE / 2)-Icp3
= (IEE / 2)-((IEE / 2)-(Ibp3 + Ibp4))
= Ibp3 + Ibp4
= (Icp3 / hFEp) + (Icp4 / hFEp)
= (Icp3 + Icp4) / hFEp
= IEE / hFEp (22)
Thus, the above equation (18) is expressed as follows.

Icn1−Icn2 = (IEE / hFEp) −Ioffset
= (IEE / hFEp)-(IEE / hFEp)
= 0 (23)
From the above equation, the base current error (IEE / hFEp) of the current mirror circuit 12 as the active load is canceled by the correction current having the completely same characteristic. This is because the current mirror circuits 12 and 13 have the same configuration. As a result, the offset voltage is always zero regardless of element characteristic variations (excluding in-plane variations of the same element) and temperature. In the light receiving amplifier circuit 1, since the base and collector of the transistor Q3 are connected, the base-emitter voltage and the collector-emitter voltage are equal in the transistor Q3. Vbep1 = Vcep4 holds. As a result, Vcep4 does not decrease to such an extent that the transistor Q8 does not operate. Therefore, in this photoreceiver amplifier circuit 1, a circuit for offset correction operates like the conventional photoreceiver amplifier circuit shown in FIG. It will not disappear.

[Embodiment 2]
Another embodiment of the light receiving amplifier circuit according to the present invention will be described below with reference to FIGS. In the present embodiment, components having the same functions as those in the above-described second embodiment are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 3 shows a configuration of the light receiving amplifier circuit 2 according to the present embodiment.

  Similar to the light receiving amplifier circuit 1 shown in FIG. 1, the light receiving amplifier circuit 2 includes transistors Q1 to Q6, constant current sources CS1 to CS3, an input resistor R1 and a feedback resistor R2, and transistors Q7 and Q8 as the correction current generation circuit 11. And constant current sources CS4 and CS5. Further, the light receiving amplifier circuit 2 includes a correction current adjustment circuit 21. The correction current adjustment circuit 21 is a circuit that finely adjusts the correction current generated by the correction current generation circuit 11 to an appropriate value, and is provided between the collector of the transistor Q3 and the collector of the transistor Q8. .

  Although the offset voltage is ideally zero by the light receiving amplifier circuit 1 shown in FIG. 2, the temperature gradient of the chip in which the light receiving amplifier circuit 1 is integrated, the current mirror circuit 12 (active load) and the current mirror are actually used. It is conceivable that there is a tendency difference between (IEE / hFEp) and Ioffset in Expression (23) due to the difference in the element arrangement with the circuit 13. In order to correct this, the correction current adjustment circuit 21 described above is provided, and the offset voltage is reduced to zero by adjusting the correction current Ioffset using the correction current adjustment circuit 21 based on the actual chip characteristics after the trial manufacture of the chip. Can be adjusted.

  Here, adjustment of the correction current in the light receiving amplifier circuit 2 will be described with reference to FIG.

Each parameter in each equation used in the following description is shown as follows. Note that description of parameters already used in the first embodiment is omitted here.
Vbep3: Base-emitter voltage of transistor Q7
Vbep4: Base-emitter voltage of transistor Q8
Vcep3: Collector-emitter voltage of transistor Q7
VT: Thermoelectromotive force represented by kT / q (k is Boltzmann constant, T is absolute temperature, and q is electronic charge)
Is: Reverse saturation current
VA: Early voltage Also in the light receiving amplifier circuit 2, the equation (22) is established in the same manner as the light receiving amplifier circuit 1 (see FIG. 2). In the equation (22), IEE / 2 is approximated as IEE / 2 = Icp3 = Icp4. However, in reality, the collector currents Icp3 and Icp4 of the transistors Q7 and Q8 of the current mirror circuit 13 cause an error as shown in the following equation due to the collector-emitter voltages (Vcep3 and Vcep4).

Icp3 = Is x (1 + Vcep3 / VA) x exp (Vbep3 / VT) (24)
Icp4 = Is x (1 + Vcep4 / VA) x exp (Vbep4 / VT) (25)
Therefore, when Vbep3 = Vbep4 = Vbep and IEE / 2 is approximated as Icp3 = IEE / 2, the sum of both collector currents is expressed by the following equation.

Icp3 + Icp4 = Is x exp (Vbep / VT) x (2+ (Vcep3 + Vcep4) / VA)
= 2 x Is x exp (Vbep / VT) x (1 + Vcep3 / VA)
+ Is x exp (Vbep / VT) x (Vcep4-Vcep3) / VA
= 2 x Icp3 + Is x exp (Vbep / VT) x (Vcep4-Vcep3) / VA
= IEE + Is x exp (Vbep / VT) x (Vcep4-Vcep3) / VA (26)
Therefore, Formula (22) is expressed as follows.

Ioffset = (Icp3 + Icp4) / hFEp
= (IEE + Is x exp (Vbep / VT) x (Vcep4-Vcep3) / VA) / hFEp
= IEE / hFEp + ΔIoffset (27)
In the above equation, ΔIoffset is an adjustment amount of the correction current expressed by the following equation.

ΔIoffset = (Is × exp (Vbep / VT) × (Vcep4−Vcep3) / VA) / hFEp
Here, as shown in FIG. 4, it is clear that the collector-emitter voltage and the base-emitter voltage of the transistor Q7 are equal to each other (Vcep3 = Vbep3) and fixed. For this reason, ΔIoffset is determined by Vcep4. Therefore, the offset voltage can be adjusted by adjusting Ioffset by changing Vcep4 by the correction current adjusting circuit 21.

  5 to 8 show the light receiving amplifier circuit 2 including a specific configuration of the correction current adjusting circuit 21 for making Vcep4 variable. Hereinafter, each correction current adjustment circuit 21 will be described with reference to these drawings.

  First, the light receiving amplifier circuit 2 shown in FIG. 5 includes an NPN transistor Q9 as the correction current adjusting circuit 21. The collector of the transistor Q9 is connected to the collector of the transistor Q3 (the bases of the transistors Q3 and Q4), which is a point for drawing out the correction current, and the emitter of the transistor Q9 is connected to the collector of the transistor Q8. A base voltage VbA for adjusting the correction current is applied to the base of the transistor Q9. Since the collector voltage Vc4 of the transistor Q8 is lower than the base-emitter voltage VbenA of the transistor Q9 than the base voltage VbA, Vc4 and Vcep4 can be changed by changing the base voltage VbA.

  In order to make the base voltage VbA variable, it may be configured as shown in FIGS.

  In the configuration shown in FIG. 6, a variable voltage source 21a connected to the base of the transistor Q9 is provided.

  The configuration shown in FIG. 7 includes diodes D1 to D3 connected in series and a current source CS6. The anode of the diode D1 is connected to the base of the transistor Q9, and the cathode of the diode D3 is connected to the ground line. In such a configuration, the base voltage VbA (= Vcc−Vf) is determined by the forward voltages (Vf) of the diodes D1 to D3 generated when current is supplied from the constant current source CS6 to the diodes D1 to D3. In this configuration, the base voltage VbA can be changed by changing the number of diodes D1 to D3 connected in series. For example, if the connection point of the diodes D2 and D3 and the ground line are short-circuited, the diodes D1 and D2 are connected in series.

  The configuration shown in FIG. 8 includes resistors R3 to R5 connected in series and a current source CS7. The resistors R3 to R5 and the current source CS7 are connected in series between the power supply line and the ground line, and the connection point between the resistor R5 and the current source CS7 is connected to the base of the transistor Q9. In this configuration, the base voltage VbA is determined by the resistors R3 to R5. The base voltage VbA can be changed by changing the current value of the current source CS7 or changing the resistance values of the resistors R3 to R5. In order to change the resistance values of the resistors R3 to R5, for example, only the resistors R4 and R5 are electrically connected to the power supply line by short-circuiting the connection point between the power supply line and the resistors R3 and R4.

  As described above, in any of the configurations shown in FIGS. 6 to 8, it is possible to easily adjust the tendency error of the offset voltage from the evaluation result of the actual trial manufacture. Also, other configurations for changing the base voltage VbA of the transistor Q9 are conceivable and are not limited to the above configuration.

[Embodiment 3]
Still another embodiment of the light receiving amplifier circuit according to the present invention will be described below with reference to FIGS. Also in the present embodiment, components having the same functions as those in the first and second embodiments described above are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 9 shows a configuration of the light receiving amplifier circuit 3 according to the present embodiment.

  Similar to the light receiving amplifier circuit 1 shown in FIG. 2, the light receiving amplifier circuit 3 includes transistors Q1 to Q6, constant current sources CS1 to CS3, an input resistor R1 and a feedback resistor R2, and transistors Q7 and Q8 as the correction current generating circuit 11. And constant current sources CS4 and CS5. Further, the light receiving amplifier circuit 3 includes a current value adjustment circuit 31 that adjusts the current values of the constant current sources CS4 and CS5. The current value adjustment circuit 31 adjusts the current values of the constant current sources CS4 and CS5 in order to adjust the correction current.

  Here, the current value adjustment by the current value adjustment circuit 31 will be described.

Each parameter in each equation used in the following description is shown as follows. Note that description of parameters already used in the first and second embodiments is omitted here.
I1: Current flowing through constant current source CS4
I2: Current flowing through the constant current source CS5 ΔI1: Adjustment of I1 by the current value adjustment circuit 31 ΔI2: Adjustment of I2 by the current value adjustment circuit 31 The correction current Ioffset is expressed as follows.

Icp3 = I1− (Ibp3 + Ibp4) (28)
Icp4 = Icp3 (29)
I2 = Icp4 + Ioffset (30)
Ioffset = I2-Icp4
= I2-Icp3
= I2−I1 + (Ibp3 + Ibp4)
= I2-I1 + (Icp3 + Icp4) / hFEp
= (I2-I1) + (I1 + I2) / hFEp
= ((IEE / 2 + ΔI1) − (IEE / 2 + ΔI2)) + ((IEE / 2 + ΔI1) + (IEE / 2 + ΔI2))) / hFEp
= (ΔI1−ΔI2) + (IEE + ΔI1 + ΔI2) / hFEp
= IEE / hFEp + ΔIoffset
However, ΔIoffset in the above equation is expressed as the following equation.

ΔIoffset = (ΔI1−ΔI2) + (ΔI1 + ΔI2) / hFEp (31)
In this manner, the correction current Ioffset can be adjusted by adjusting the current values of the constant current sources CS4 and CS5 by the current value adjusting circuit 31. Thereby, the offset voltage can be compensated with higher accuracy than the light receiving amplifier circuit 1 of the first embodiment.

  Next, a specific circuit for adjusting the correction current Ioffset by the current value adjustment circuit 31 will be described. FIG. 10 shows a configuration of the light receiving amplifier circuit 3 including such a circuit.

  As shown in FIG. 10, the light receiving amplifier circuit 3 includes a constant current source CS8, an NPN transistor Q11, and a variable resistor R11 as the current value adjusting circuit 31.

  The collector and base of the transistor Q11 are connected, and the emitter is connected to the ground line via the variable resistor R11. A constant current source CS8 is connected between the collector of the transistor Q11 and the power supply line.

  On the other hand, the constant current source CS4 includes an NPN transistor Q12 and a variable resistor R12, and the constant current source CS5 includes an NPN transistor Q13 and a variable resistor R13. The collector of the transistor Q12 is connected to the collector of the transistor Q7, and the emitter is connected to the ground line via the variable resistor R12. The collector of the transistor Q13 is connected to the collector of the transistor Q8, and the emitter is connected to the ground line via the variable resistor R13. The bases of the transistors Q11 to Q13 are connected to each other. Thereby, the circuit composed of the transistors Q11 to Q13 and the variable resistors R11 to R13 constitutes a current mirror circuit 32 as a third current mirror circuit.

  In the light receiving amplifier circuit 3 configured as described above, in the current mirror circuit 32, the emitter resistances of the transistors Q11 to Q13 are changed by the variable resistors R11 to R13. Accordingly, the correction current Ioffset can be adjusted by changing the current I1 flowing through the constant current source CS4 and the current I2 flowing through the constant current source CS5 from the reference current value IEE / 2.

[Embodiment 4]
An embodiment relating to an optical pickup including the light receiving amplifier circuit of the present invention will be described with reference to FIG. Also in the present embodiment, the same reference numerals are given to components having the same functions as the components in the first to third embodiments, and the description thereof is omitted.

  FIG. 11 shows a configuration of the optical pickup according to the present embodiment.

  As shown in FIG. 11, this optical pickup includes a laser diode 111, light receiving ICs 112 and 113 for laser power monitoring, a signal light receiving IC 114, a collimator lens 115, a spot lens 116, a beam splitter 117, a collimator lens 118, and an objective lens 119. I have.

  A laser diode 111 as a laser light source emits two types of laser beams, a 780 nm laser beam for CD and a 659 nm laser beam for DVD. The drive current supplied to the laser diode 111 is generated by a laser driver (not shown).

  The laser power monitoring light receiving ICs 112 and 113 incorporate any of the light receiving amplifier circuits 1 to 3 of the first to third embodiments described above, and a photodiode PD1 is disposed on the light receiving surface. The light receiving ICs 112 and 113 for laser power monitoring are ICs for receiving a part of the laser beam emitted from the laser diode 111 and converting it into an electric signal as a detection signal. The position of the light receiving IC for laser power monitoring is not limited to the illustrated position as long as it can receive an amount necessary for detecting the laser beam.

  In the optical pickup configured as described above, the laser beam emitted from the laser diode 111 is converted into a parallel light beam by the collimator lens 115 and deflected by the beam splitter 117. The laser beam from the beam splitter 117 is further focused on the optical disk 120 by the objective lens 119 through the collimator lens 118. The laser beam reflected from the optical disk 120 passes through the objective lens 119 and the collimator lens 117, passes through the beam splitter 117, and is then focused on the signal light receiving IC 114 by the spot lens 116. In the signal light receiving IC 114, the laser beam is converted into an electric signal, and an RF signal, a tracking error signal, and the like are generated from the electric signal. And is deflected by 52 and received by the light receiving photodiode PD.

  On the other hand, the laser power monitoring light receiving ICs 112 and 113 receive the laser beam emitted from the laser diode 111 and detect the laser beam as an output voltage Vo (detection signal) by any of the built-in light receiving amplifier circuits 1 to 3. . This detection signal is given to a laser driver (not shown). The laser driver controls the drive current of the laser diode so that the power of the laser beam becomes a predetermined value while monitoring the detection signals from the light receiving ICs 112 and 113 for monitoring the laser power.

  As described above, in the optical pickup, the laser power monitoring light receiving ICs 112 and 113 incorporate any one of the light receiving amplifier circuits 1 to 3, so that they are not affected by variations in characteristics of elements such as transistors and temperature. The offset voltage of the differential amplifier circuit can always be zero. As a result, even if the sensitivity of the laser power monitoring light receiving ICs 112 and 113 is lowered in accordance with the laser power at the time of reproduction which is lower than that at the time of recording, the laser beam (laser power) can be accurately emitted without being affected by the offset voltage It can be detected accurately. Therefore, the laser power can be controlled with high accuracy.

  In the present embodiment, it has been described that the laser power monitoring light receiving ICs 112 and 113 include any one of the light receiving amplifier circuits 1 to 3. However, the signal light receiving IC 114 includes any one of the light receiving amplifier circuits 1 to 3. It may be built in. The signal light receiving IC 114 is not required to strictly reduce the offset voltage unlike the laser power monitoring light receiving ICs 112 and 113, but a process in which the characteristics of the NPN transistor and the PNP transistor constituting the differential amplifier circuit are greatly different. Therefore, when the offset voltage does not satisfy the specification value, the offset voltage can be lowered by using the light receiving amplifiers 1 to 3, which is effective.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and the embodiments can be obtained by appropriately combining technical means disclosed in different embodiments. The form is also included in the technical scope of the present invention.

  Offset voltage and offset voltage temperature characteristics are improved by correcting the base current error of the current mirror circuit, which is the active load of the differential amplifier circuit in the light receiving amplifier circuit, using the base current error of the current mirror circuit of the same configuration. To do. Accordingly, the light receiving amplifier circuit can be applied to a front monitor element that can accurately output a voltage corresponding to the laser power in the optical pickup.

1 is a circuit diagram showing a configuration of a light receiving amplifier circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating in detail a configuration of a correction current generation circuit in the light receiving amplifier circuit of FIG. 1. It is a circuit diagram which shows the structure of the light reception amplifier circuit which concerns on Embodiment 2 of this invention. FIG. 3 is a circuit diagram for explaining an operation of adjusting a correction current in the light receiving amplifier circuit of FIG. 2. FIG. 4 is a circuit diagram illustrating in detail a configuration of a correction current adjustment circuit in the light receiving amplifier circuit of FIG. 3. FIG. 4 is a circuit diagram illustrating in detail a configuration in which a base voltage is applied to a transistor of a correction current adjustment circuit in the light receiving amplifier circuit of FIG. 3. 4 is a circuit diagram showing in detail another configuration for applying a base voltage to a transistor of a correction current adjustment circuit in the light receiving amplifier circuit of FIG. FIG. 4 is a circuit diagram showing in detail another configuration for applying a base voltage to a transistor of a correction current adjusting circuit in the light receiving amplifier circuit of FIG. 3. It is a circuit diagram which shows the structure of the light reception amplifier circuit which concerns on Embodiment 3 of this invention. FIG. 9 is a circuit diagram illustrating in detail a configuration of a current value flow adjustment circuit in the light receiving amplifier circuit of FIG. 8. It is a figure which shows the structure of the optical pick-up concerning Embodiment 4 of this invention. It is a circuit diagram which shows the conventional light receiving amplifier circuit. It is a circuit diagram which shows the other conventional light receiving amplifier circuit. FIG. 10 is a circuit diagram showing still another conventional light receiving amplifier circuit.

Explanation of symbols

1-3 Photosensitive amplifier circuit 11 Correction current generation circuit 12 Current mirror circuit (first current mirror circuit)
13 Current mirror circuit (second current mirror circuit)
21 Correction current adjustment circuit (correction current adjustment means)
21a Variable voltage source (variable voltage generating means)
31 Current value adjustment circuit (current value adjustment means)
32 Current mirror circuit (third current mirror circuit)
111 Laser diode (laser light source)
112, 113 Light receiving IC for laser power monitor
CS1 to CS3 constant current source CS4 constant current source (first constant current circuit)
CS5 constant current source (second constant current circuit)
CS6, CS7 Current source CS8 Constant current source D1-D3 Diode PD1 Photodiode (light receiving element)
R3 to R5 Resistor R11 Variable resistor (first variable resistor)
R12 variable resistor (second variable resistor)
R13 Variable resistor (third variable resistor)
Q1, Q2 transistors (differential transistor pair)
Q3, Q7 transistor (main transistor)
Q4, Q8 transistors (sub-transistors)
Q9 Transistor (transistor between circuits)
Q11 transistor (first transistor)
Q12 transistor (second transistor)
Q13 Transistor (third transistor)

Claims (12)

In a light receiving amplifier circuit including a differential amplifier pair and a differential amplifier circuit that has a first current mirror circuit serving as an active load of the differential transistor pair and outputs a voltage corresponding to the output current of the light receiving element.
From the difference between the currents flowing through the differential transistor pair represented by the sum of the base currents of the transistor pairs constituting the first current mirror circuit, the same value, the same temperature characteristics and the same as the sum of the base currents of the transistor pairs A correction means for reducing the correction current having variation is provided ,
The correcting means includes a second current mirror circuit having the same configuration as the first current mirror circuit, and a first constant current for extracting a collector current of a main transistor and base currents of a main transistor and a sub transistor of the second current mirror circuit. And a second constant current circuit that extracts the collector current of the sub-transistor of the second current mirror circuit and extracts the correction current from the collector current of the main transistor of the first current mirror circuit and the base current of both transistors. receiving amplifier circuit, characterized in that it has. Wherein provided between the differential amplifier circuit and the correcting means, the light receiving amplifier circuit according to claim 1, characterized in that it comprises a correction current adjusting means for adjusting the correction current. The correction current adjusting means to claim 2, characterized by adjusting the correction current by the voltage at the node between the secondary transistor of the second constant current circuit and the second current mirror circuit to the variable The light receiving amplifier circuit described. The correction current adjusting means includes an inter-circuit transistor connected between a connection point between the second constant current circuit and a sub-transistor of the second current mirror circuit and a point at which the correction current of the first current mirror circuit is drawn. The light receiving amplifier circuit according to claim 3 , wherein the connection point voltage is made variable by changing a base voltage of the inter-circuit transistor. 5. The light receiving amplifier circuit according to claim 4 , wherein the correction current adjusting means includes variable voltage generating means for applying a variable base voltage to the inter-circuit transistor. 6. The light receiving amplifier circuit according to claim 5 , wherein the variable voltage generating means is a variable voltage source. 6. The light receiving amplifier circuit according to claim 5 , wherein the variable voltage generating means includes a plurality of diodes connected in series with a variable number of connections, and a current source for supplying a current to the diodes. 6. The light receiving amplifier circuit according to claim 5 , wherein the variable voltage generating means includes a plurality of series-connected resistors having a variable number of connections, and a current source for supplying a current to the resistors. It said correcting means, the light receiving amplifier circuit according to claim 1, characterized in that it comprises a current value adjustment means for adjusting the current value of the current value and the second constant current circuit of the first constant current circuit . The current value adjusting means includes a diode-connected first transistor, a first variable resistor that makes the emitter resistance of the first transistor variable, and a constant current source that supplies current to the first transistor,
The first constant current circuit includes a second transistor having a base commonly connected to the first transistor, and a second variable resistor that makes the emitter resistance of the second transistor variable,
The second constant current circuit includes a third transistor having a base commonly connected to the first transistor, and a third variable resistor that makes the emitter resistance of the third transistor variable. The light receiving amplifier circuit according to claim 9 . Claims 1 to an optical pickup, characterized in that a light receiving amplifier circuit according to any one of 10. The optical pickup according to claim 11 , wherein the light receiving amplifier circuit is used for detecting a light amount of a laser beam emitted from a laser light source.

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