JP4634665B2 - Capacitor built-in circuit board and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit board with a built-in capacitor and a method for manufacturing the same, and more particularly to a circuit board with a built-in capacitor that is disposed between a mounting board and an LSI chip and is suitable for electrically connecting the two.
[0002]
[Prior art]
In recent years, as the density of large-scale integrated circuit elements (LSIs) has increased, the operation speed has increased year by year. When the operating speed of the LSI increases, voltage noise and voltage fluctuation of the power supply bus line are likely to occur due to switching of the electronic circuit. In order to suppress voltage noise and voltage fluctuation, it is effective to arrange a decoupling capacitor between the power supply bus line and the ground bus line. A technique has been proposed in which this decoupling capacitor is built in an intermediate substrate (interposer) disposed between an LSI chip and a mounting substrate (motherboard).
[0003]
[Problems to be solved by the invention]
In order to increase the capacitance of the decoupling capacitor, barium strontium titanate ((Ba, Sr) TiO 2 is used as a dielectric material._Three) Or the like is used. However, signal vias are also arranged on the intermediate substrate. When a high dielectric constant material is used as the material of the intermediate substrate, the parasitic capacitance between the signal via and the power supply bus line and the parasitic capacitance between the signal via and the ground bus line are increased. This increase in parasitic capacitance results in signal propagation delay.
[0004]
An object of the present invention is to provide a circuit board with a built-in capacitor capable of increasing the capacitance of a decoupling capacitor and suppressing an increase in signal propagation delay, and a method for manufacturing the same.
[0005]
[Means for Solving the Problems]
  According to one aspect of the invention,
  A dielectric layer having a top surface and a bottom surface defined and formed of a dielectric material;
  Each of the first connecting member, the second connecting member, and the second connecting member formed of a conductive material from the top surface of the dielectric layer to the bottom surface of the dielectric layer through the dielectric layer. 3 connecting members;
  A first electrode disposed on any one of an upper surface, a bottom surface, and an inside of the dielectric layer and connected to the first connection member;
  The dielectric layer is disposed on any one of the upper surface, the bottom surface, and the inside of the dielectric layer, sandwiches at least a part of the dielectric layer, constitutes a capacitor together with the first electrode, and is connected to the second connection member A second electrode and
Have
  Of the dielectric layer, the dielectric constant of the portion in contact with the third connecting member is a low dielectric constant region lower than the dielectric constant of the other portion.And
  The dielectric constant of the boundary portion between the low dielectric constant region and the other region gradually decreases as the distance from the third connecting member approaches.A circuit board with a built-in capacitor is provided.
[0006]
The first connecting member and the second connecting member are coupled by a capacitor. If one is connected to the power bus line and the other is connected to the ground bus line, voltage fluctuations caused by switching can be suppressed. Moreover, since the dielectric constant around the third connecting member is lowered, the parasitic capacitance between the third connecting member and the other conductive member can be reduced. The propagation delay of the electric signal applied to the third connecting member can be suppressed.
[0007]
According to another aspect of the present invention, (a) preparing a base substrate on which a first conductive via, a second conductive via, and a third conductive via penetrating in the thickness direction are formed; (B) forming a first electrode connected to the first conductive via on the surface of the base substrate and not overlapping the second and third conductive vias; and (c). Forming a dielectric film made of a dielectric material so as to cover the first electrode; and (d) performing ion implantation on a region of the dielectric film around the third conductive via. A step of reducing the dielectric constant of the ion-implanted region by lowering the dielectric constant of the other region; and (e) the first electrode sandwiching the dielectric film on the dielectric film. Forming a second electrode opposite to the second conductive via and connected to the second conductive via; and (f) the dielectric Forming an insulating protective film on the film and the second electrode; and (g) penetrating the protective film in the thickness direction, respectively, the first electrode and the second electrode, respectively. And a step of forming a fourth conductive via, a fifth conductive via, and a sixth conductive via electrically connected to the third conductive via. A method is provided.
[0008]
By ion implantation, a region having a low dielectric constant is formed. Therefore, the manufacturing process can be simplified as compared with the case where another member having a low dielectric constant is disposed.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a schematic side view of an electronic circuit device in which an LSI chip is mounted on a mounting substrate via an intermediate substrate. A plurality of pads 2 are formed on the main surface of the mounting substrate 1. A plurality of pads 4 are formed on the bottom surface of the intermediate substrate (interposer) 3. The pads 4 on the intermediate substrate 3 are connected to the corresponding pads 2 on the mounting substrate 1 by bumps 5.
[0010]
A plurality of pads 6 are also formed on the upper surface of the intermediate substrate 3. Each of the plurality of pads 6 is connected to a corresponding pad 4 formed on the bottom surface by a via penetrating the inside of the intermediate substrate 3. A plurality of pads 8 are formed on the surface of the LSI chip 7. The pad 8 is connected to the corresponding pad 6 of the intermediate substrate 3 via the bump 9.
[0011]
FIG. 2 shows a cross-sectional view of a circuit board with a built-in capacitor according to an embodiment of the present invention. A silicon oxide film 10B is formed by thermal oxidation on the surface of a substrate 10A made of silicon, and the substrate 10A and the silicon oxide film 10B constitute a base substrate 10. A plurality of conductive vias penetrating the substrate in the thickness direction are formed in the base substrate 10. FIG. 2 shows a power supply via 11V, a grounding via 11G, and a signal via 11S among the plurality of vias.
[0012]
Pads 4V, 4G, and 4S are formed on the bottom surface of the base substrate 10.
The pads 4V, 4G, and 4S are connected to the power supply via 11V, the ground via 11G, and the signal via 11S, respectively. These pads 4V, 4G, and 4S are flip-chip bonded to the mounting substrate 1 via the bumps 5 shown in FIG.
[0013]
The lower electrode 20 covers a part of the upper surface of the base substrate 10. The lower electrode 20 is made of TiO with a thickness of 25 to 30 nm.₂It has a two-layer structure of a film 20A and a Pt film 20B having a thickness of 100 to 150 nm. The lower electrode 20 is connected to the power supply via 11V, passes through the side of the signal via 11S, and continues to the vicinity of the grounding via 11S. That is, the lower electrode 20 does not overlap any of the signal via 11S and the ground via 11G. The lower electrode 20 has a planar shape such that the shortest distance from the edge to the signal via 11S is longer than the shortest distance to the ground via 11G.
[0014]
A dielectric film 22 made of a first high dielectric constant material having a thickness of 100 to 150 nm is formed so as to cover the lower electrode 20. The dielectric film 22 is made of, for example, barium strontium titanate ((Ba, Sr) TiO 2._Three(Hereinafter referred to as BST). Via holes 22V, 22G, and 22S are formed in the dielectric film 22. The via holes 22V, 22G, and 22S are disposed at positions corresponding to the power supply via 11V, the grounding via 11G, and the signal via 11S of the base substrate 10, respectively. A region around the via hole 22S in the dielectric film 22 is a low dielectric constant region 23 having a lower dielectric constant than other regions. The low dielectric constant region 23 is formed by ion-implanting titanium (Ti) and oxygen (O) into BST as will be described later.
[0015]
An intermediate electrode 30 made of Pt is formed on the surface of the first dielectric film 22. The intermediate electrode 30 is connected to the ground via 11 </ b> G via the via hole 22 </ b> G formed in the first dielectric film 22. Further, the intermediate electrode 30 passes through the side of the low dielectric constant region 23 and continues to the vicinity of the via hole 22V. The intermediate electrode 30 has a planar shape in which the shortest distance from the edge to the inner peripheral surface of the via hole 22S is longer than the shortest distance to the inner peripheral surface of the via hole 22V.
[0016]
A second dielectric film 32 having a thickness of 100 to 150 nm is formed so as to cover the intermediate electrode 30. Via holes 32V, 32G, and 32S are formed in the dielectric film 32 of the second layer. The via holes 32V, 32G, and 32S are disposed at the same positions as the via holes 22V, 22G, and 22S formed in the first dielectric film 22, respectively. A region around the via hole 32S in the dielectric film 32 is a low dielectric constant region 33 like the first-layer dielectric film 22.
[0017]
An upper electrode 40 made of Pt and having a thickness of 100 to 150 nm is formed on the surface of the second dielectric film 32. The upper electrode 40 is connected to the lower electrode 20 via the via holes 22V and 32V, and has substantially the same planar shape as the lower electrode 20.
[0018]
A protective film 50 made of polyimide and having a thickness of 5 to 10 μm is formed so as to cover the upper electrode 40. Via holes 50 </ b> V, 50 </ b> G, and 50 </ b> S are formed in the protective film 50. The via holes 50V, 50G, and 50S are arranged at the same positions as the via holes 32V, 32G, and 32S formed in the second dielectric film 32, respectively.
[0019]
Pads 6V, 6G, and 6S made of Pt are formed on the surface of the protective film 50. The pad 6V is connected to the upper electrode 40 via a chip-side power supply via 51V that fills the via hole 50V. The pad 6G is connected to the intermediate electrode 30 via a chip-side ground via 51G that fills the via holes 50G and 32G. The pad 6S is connected to the signal via 11S via a chip-side signal via 51S that fills the via holes 50S, 32S, and 22S.
[0020]
A power supply voltage is supplied from the mounting substrate 1 shown in FIG. 1 to the LSI chip 7 through the power supply via 11V, the lower electrode 20, the upper electrode 40, the chip side power supply via 51V, and the pad 6V. The ground bus line of the LSI chip 7 is connected to the ground line of the mounting substrate 1 through the pad 6G, the chip-side ground via 51G, the intermediate electrode 30, and the ground via 11G. Electric signals are transmitted and received between the mounting substrate 1 and the LSI chip 7 through the signal via 11S, the chip-side signal via 51S, and the pad 6S.
[0021]
The lower electrode 20 and the intermediate electrode 30 facing each other with the first-layer dielectric film 22 interposed therebetween, and the intermediate electrode 30 and the upper electrode 40 facing each other with the second-layer dielectric film 32 interposed therebetween are decoupling capacitors. Configure. For this reason, voltage noise and voltage fluctuation caused by switching in the LSI chip 7 can be suppressed. Of the dielectric films 22 and 32, the periphery of the signal via 11 </ b> S and the chip-side signal via 51 </ b> S through which an electric signal is transmitted is formed as low dielectric constant regions 23 and 33. For this reason, it is possible to reduce the parasitic capacitance between the signal via 11S and the chip-side signal via 51S and the other wiring. Thereby, the propagation delay of a signal can be prevented.
[0022]
Next, with reference to FIGS. 3 and 4, a method for manufacturing the circuit board with a built-in capacitor shown in FIG. 1 will be described.
[0023]
A base substrate 10 shown in FIG. The base substrate 10 can be manufactured by the following method, for example.
[0024]
First, a Cr film having a thickness of 50 nm and a Cu film having a thickness of 1500 nm are sequentially formed on one surface of the silicon substrate (the upper surface in FIG. 3A). These two layers are formed by sputtering, for example. A resist pattern having openings corresponding to the vias 11V, 11S, and 11G is formed on the other surface (the lower surface in FIG. 3A) of the silicon substrate. Using this resist pattern as a mask, the silicon substrate is etched by inductively coupled plasma etching using a reactive gas.
A via hole is formed, and a laminated structure of a Cr film and a Cu film remains on the bottom surface.
[0025]
A silicon oxide film is formed on the inner surface of the via hole by chemical vapor deposition. The silicon oxide film deposited on the laminated structure of the Cr film and the Cu film remaining on the bottom surface of the via hole is removed by dry etching. A laminated structure of a Cr film and a Cu film is used as a seed layer, and a via hole is filled with a metal such as Pt, Au, or Cu by plating. Pads 4V, 4S, and 4G are formed, and two layers of a Cr film and a Cu film formed on the upper surface are removed by wet etching. The base substrate 10 is manufactured through the steps so far.
[0026]
As the base substrate, a multilayer ceramic substrate disclosed in Japanese Patent Application Laid-Open No. 11-274408 (US application 09/031236) may be used.
[0027]
A Ti film having a thickness of 10 nm is formed on the upper surface of the base substrate 10 (the surface on which the silicon oxide film 10B is formed) by sputtering. A heat treatment is performed at 650 to 700 ° C. for 30 minutes in an oxidizing atmosphere such as air or oxygen to oxidize the Ti film. As a result, TiO with a thickness of 25 to 30 nm₂A film 20A is formed. This TiO₂A Pt film 20B having a thickness of 100 nm is formed on the film 20A by sputtering. TiO₂The film 20A has an effect of improving the adhesion of the Pt film 20B.
[0028]
TiO₂Two layers of the film 20A and the Pt film 20B are patterned, and the lower electrode 20 constituted by the two layers is left. This two-layer patterning is performed, for example, by masking the surface of the lower electrode 20 to be left behind with a resist pattern and milling using Ar ions.
[0029]
Steps up to the state shown in FIG. A dielectric film 22 made of barium strontium titanate (BST) is formed on the base substrate 10 so as to cover the lower electrode 20. The dielectric film 22 made of BST can be formed by, for example, RF magnetron sputtering, sol-gel method, metal organic chemical vapor deposition (MO-CVD), or the like. An example of film forming conditions when the dielectric film 22 is formed by RF magnetron sputtering is shown below.
[0030]
As a target, a BST sintered body having an atomic ratio of Ba: Sr: Ti = 7: 3: 10 is used. The film forming temperature is 600 ° C. Ar gas and O₂The gas flow rates are 80 sccm and 10 sccm, respectively. The atmospheric pressure is 4 Pa (30 mTorr). The RF power to be input is 300W. The composition ratio of Ba and Sr in the BST film formed under these conditions was about 65:35.
[0031]
Via holes 22V, 22S, and 22G are formed in the dielectric film 22 by milling using Ar ions.
[0032]
As shown in FIG. 3C, the surface of the dielectric film 22 is covered with a resist mask 60. The resist mask 60 is provided with an opening 60A that encloses the via hole 22S when viewed in a line of sight parallel to the substrate normal.
[0033]
Ti ions and O ions are implanted into the dielectric film 22 using the resist mask 60 as a mask. The Ti ion implantation conditions are, for example, acceleration energy of 100 keV and a dose of 1 × 10.¹⁷cm^-2The O ion implantation conditions are, for example, an acceleration energy of 35 keV and a dose amount of 2 × 10.¹⁷cm^-2It is. After the ion implantation, the resist mask 60 is removed, and heat treatment is performed at 650 ° C. for 15 minutes in an oxygen atmosphere of 1 atm. TiO at the interface (grain boundary) of BST microcrystal_xAs a result, the dielectric constant of the ion-implanted portion decreases. The dielectric constant also decreases when high energy ions collide with atoms in the dielectric film 22 and the long-range crystallinity is destroyed.
[0034]
A suitable ion implantation condition varies depending on the thickness of the dielectric film 22. Acceleration energy is preferably set such that the concentration distribution peak in the depth direction of the implanted ions is located substantially at the center of the dielectric film 22. For example, the acceleration energy could be selected from the range of 10-500 keV. The preferred range of dose is 1 × 10¹³~ 1x10¹⁸cm^-2It is.
[0035]
As shown in FIG. 4D, a low dielectric constant region 23 is formed in the ion-implanted portion. In FIG. 4D, the boundary between the low dielectric constant region 23 and the other high dielectric constant regions is clearly shown. In practice, however, the dielectric constant gradually changes in the vicinity of the boundary for the following reason. To do. When ions are incident on the dielectric film 22 exposed on the bottom surface of the opening 60A shown in FIG. 3C, the crystallinity of this portion is destroyed. The incident ions repeatedly collide with the constituent atoms of the dielectric film 22 and travel in the lateral direction. Therefore, even in the region covered with the resist mask 60, the crystallinity of the region in the vicinity of the opening 60A is destroyed. The degree of crystallinity collapse decreases as the distance from the opening 60A increases. The excessive Ti and O concentrations also decrease as the distance from the opening 60A increases. For this reason, a region where the dielectric constant gradually changes is formed in the vicinity of the outer periphery of the opening 60A.
[0036]
Returning to FIG. 4D, the description will be continued. A Pt film having a thickness of 100 nm is formed on the dielectric film 22 by sputtering. The intermediate electrode 30 is left by patterning this Pt film. A second dielectric film 32 made of BST and having a thickness of 100 nm is formed so as to cover the intermediate electrode 30. Via holes 32V, 32S, and 32G are formed in the dielectric film 32 of the second layer.
[0037]
As shown in FIG. 4E, a resist mask 65 is formed on the second dielectric film 32. An opening 65A that includes the via hole 32S is formed in the resist mask 65, and the resist mask 65 has the same planar shape as the resist mask 60 shown in FIG.
[0038]
Ti ions and O ions are implanted into the second dielectric film 32 using the resist mask 65 as a mask. The ion implantation conditions are the same as the ion implantation conditions for the first dielectric film 22 described with reference to FIG. After the ion implantation, the resist mask 60 is removed and heat treatment is performed. This heat treatment condition is also the same as the heat treatment condition after ion implantation into the first dielectric film 22.
[0039]
As shown in FIG. 4F, a low dielectric constant region 33 is formed around the via hole 32S. A region where the dielectric constant gradually changes is formed at the boundary between the low dielectric constant region 33 and the surrounding high dielectric constant region as in the case of the first low dielectric constant region 23.
[0040]
A Pt film having a thickness of 100 nm is formed on the second dielectric film 32. By patterning this Pt film, the upper electrode 40 is left. A protective film 50 made of polyimide and having a thickness of 5 to 10 μm is formed so as to cover the upper electrode 40. Via holes 50V, 50S, and 50G are formed in the protective film 50. The protective film 50, the via holes 50V, 50S, and 50G are formed, for example, by performing spin coating, exposure, development, and baking of a photosensitive polyimide raw material.
[0041]
As shown in FIG. 2, conductive vias 51V, 51S, and 51G that fill the via holes and pads 6V, 6S, and 6G continuous with these vias are formed. These conductive vias and pads are formed of Pt. The embedding of the conductive vias 51V, 51S, and 51G and the deposition of the Pt film for forming the pads 6V, 6S, and 6G may be performed in separate steps or in the same step.
[0042]
In the method of disposing a member made of a material having a low dielectric constant different from the material of the dielectric films 22 and 32 around the signal vias 11S and 51S shown in FIG. 2, the manufacturing process becomes complicated and the yield decreases. Is concerned. In the manufacturing method described above, the low dielectric constant regions 23 and 33 are formed in part of the dielectric films 22 and 32 by the ion implantation shown in FIGS. 3C and 4E. For this reason, the low dielectric constant regions 23 and 33 can be formed relatively easily.
[0043]
In the above embodiment, Ti ions and O ions are implanted into the dielectric films 22 and 32 made of BST, and TiO is formed on the grain boundary._xHowever, other elements that form oxides may be implanted. For example, Si and O may be implanted. At this time, for example, the acceleration energy of Si ions is 60 keV, and the dose is 1 × 10.¹⁷cm^-2The acceleration energy of O ions is 35 keV, and the dose amount is 2 × 10.¹⁷cm^-2And it is sufficient. In addition, the heat treatment after ion implantation may be performed, for example, at 650 ° C. for 30 minutes in an oxygen atmosphere of 1 atm. By this heat treatment, the BST grain boundary is made of SiO.₂Grows and the dielectric constant of the ion-implanted portion decreases.
[0044]
Further, Mn ions may be implanted into the dielectric films 22 and 32. When heat treatment is performed after Mn is injected, the injected Mn is replaced with Ti and acts as an acceptor. As a result, the dielectric constant of the region where Mn is implanted decreases. Mn ions are preferably implanted with a plurality of acceleration energies of, for example, 10 keV, 50 keV, 100 keV, 150 keV, and 200 keV. The dose amount is, for example, 1 × 10 as a whole.¹⁷cm^-2The ion implantation conditions for each acceleration energy are set so that
[0045]
In the above embodiment, the silicon substrate 10A is used as the base of the base substrate 10, but a semiconductor substrate other than silicon may be used. For example, germanium (Ge) or silicon germanium (SiGe) may be used, or a III / V group compound semiconductor may be used. Examples of III / V group compound semiconductors include GaAs, InAs, InP, and the like.
[0046]
In the above embodiment, TiO is used as the adhesion layer of the lower electrode 20 shown in FIG.₂Although the film 20A is used, a film made of another material that improves the adhesion of the Pt film may be used. As the material of the adhesion layer, for example, a noble metal, an alloy of noble metals, an alloy of a noble metal and another metal, a conductive noble metal oxide, a conductive metal oxide, a conductive metal nitride, or the like can be used. It is also possible to use an insulating metal oxide or an insulating metal nitride. When an insulating material is used, it is necessary to form an opening in a region corresponding to the power supply via 11V in the adhesion layer so that the Pt film 20B shown in FIG. 2 and the power supply via 11V are in contact with each other. is there. Furthermore, it is good also as a contact | adherence layer by laminating | stacking the layer which consists of these materials. These materials include TiO₂Besides, Ir, Zr, Ti, IrO_x, PtO_x, ZrO_xTiN, TiAlN, TaN, TaSiN, and the like.
[0047]
In the above embodiment, Pt is used for a part of the lower electrode 20, the intermediate electrode 30 and the upper electrode 40 shown in FIG. 2, but other conductive materials may be used. For example, transition metals, noble metals, alloys of noble metals, alloys of noble metals and other metals, conductive noble metal oxides, and the like can be used. Furthermore, it is good also as a structure which laminated | stacked the layer which consists of these materials. Examples of these materials are Pt, Pd, Ir, Ru, Rh, Re, Os, PtO._x, IrO_x, RuO_x, Au, Ag, Cu and the like.
[0048]
In the above embodiment, BST is used as the material of the dielectric films 22 and 32 shown in FIG. 2, but other general formulas ABO_ThreeA high dielectric constant material having a perovskite structure represented by Here, A is an element that becomes a monovalent to trivalent cation. B is a metal element constituting an acidic oxide, and examples thereof include Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Re, Cu, Ag, and Au. General formula ABO_ThreeAs an example of a high dielectric constant material having a perovskite structure represented by_Three, Pb (Zr, Ti) O_Three, Pb (Mg, Nb) O_ThreeEtc.
[0049]
In the above embodiment, excessively low Ti and O ions are implanted into BST to form the low dielectric constant regions 23 and 33. However, it is possible to reduce the dielectric constant by implanting impurities. For example, ABO_ThreeNa, K, Rb, and Cs serving as donors may be implanted by replacing the atoms at site A of the structure. Further, Y may be implanted as an impurity. When the atomic radius of site A is smaller than the atomic radius of site B, Y replaces the atom of site A to become a donor, and when the atomic radius of site A is larger than the atomic radius of site B, Y Replaced to be an acceptor. In addition to this, even if La at the site A is replaced and La as the donor is replaced, Nb at the site B is replaced and Nb as the donor is replaced, and Mn, Fe, Al, Ga as the acceptor is implanted by replacing the atoms at the site B Good. A plurality of types of impurities may be implanted.
[0050]
As other high dielectric constant materials, the general formula A₂B₂O_xA compound having a pyrochlore structure represented by (x is 6 or 7) can also be used. Examples of such compounds include Pb₂(Zr, Ti)₂O₇, Pb₂(Mg, Nb)₂O₇Etc.
[0051]
In addition, other high dielectric constant materials include copper-based oxide materials (eg, Ba_0.9Nd_0.1CuO₂), Tungsten bronze structure oxide material (eg Sr)_0.6Ba_0.4Nb₂O₆), Bismastantalate having a layered structure (for example, SrBi)₂Ta₂O₉), Bismuth niobate having a layered structure (for example, Sr)_0.76Bi_0.24Nb₂O₉), A bismaster iterate having a layered structure (eg Bi_FourTi_ThreeO₁₂) Etc. may be used.
[0052]
The dielectric constant can be lowered by implanting constituent element ions into these high dielectric constant materials to break the crystallinity of the long range order.
[0053]
In the above embodiment, after ion implantation into the dielectric films 22 and 32 made of BST, heat treatment is performed, and TiO is formed at the interface (grain boundary) of the fine crystal grains._xHowever, this heat treatment is unnecessary when the dielectric constant is lowered mainly by breaking the crystallinity. In addition, TiO is present at the interface of BST microcrystal grains._xIn order to obtain a sufficient effect of lowering the dielectric constant, the heat treatment temperature is preferably set to 700 to 800 ° C.
[0054]
In the above embodiment, as shown in FIG. 2, the decoupling capacitor electrode connected to the power supply via 11V has two layers of the lower electrode 20 and the upper electrode 40, but only one of them is used. It is good also as a 1 layer structure. Further, the electrode of the decoupling capacitor connected to the grounding via 11G may be a plurality of layers, and the electrode connected to the power supply via 11V may be three or more layers.
[0055]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0056]
【The invention's effect】
As described above, according to the present invention, by implanting ions into a part of the dielectric film having a high dielectric constant, the dielectric constant of the portion into which ions are implanted is lowered. When the dielectric constant around the signal via of the capacitor interposer is lowered, the signal propagation delay due to the parasitic capacitance can be suppressed.
[Brief description of the drawings]
FIG. 1 is a side view of an electronic circuit device using a circuit board with a built-in capacitor according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a circuit board with a built-in capacitor according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a substrate for explaining a method of manufacturing a circuit board with a built-in capacitor according to an embodiment of the present invention (part 1);
FIG. 4 is a sectional view (No. 2) of the substrate for explaining the method of manufacturing the circuit board with built-in capacitor according to the embodiment of the present invention.
[Explanation of symbols]
1 Mounting board
2, 4, 6, 8 pads
3 Intermediate board
5, 9 Bump
7 LSI chip
10 Base substrate
Via for 11V and 51V power supply
11G, 51G Grounding via
11S, 51S signal via
20 Lower electrode
22 First layer dielectric film
22V, 22S, 22G via
30 Intermediate electrode
32 Second layer dielectric film
32V, 32S, 32G via
40 Upper electrode
50 Protective film
60, 65 resist mask

Claims (9)

A dielectric layer having a top surface and a bottom surface defined and formed of a dielectric material;
Each of the first connecting member, the second connecting member, and the second connecting member formed of a conductive material from the upper surface of the dielectric layer to the bottom surface of the dielectric layer through the dielectric layer. 3 connecting members;
A first electrode disposed on any one of an upper surface, a bottom surface, and an inside of the dielectric layer and connected to the first connection member;
The dielectric layer is disposed on any one of the upper surface, the bottom surface, and the inside of the dielectric layer, sandwiches at least a part of the dielectric layer, constitutes a capacitor together with the first electrode, and is connected to the second connection member A second electrode;
Of the dielectric layer, the dielectric constant of the part in contact with the third connecting member is a low dielectric constant region lower than the dielectric constant of the other part ,
A circuit board with a built-in capacitor in which a dielectric constant at a boundary portion between the low dielectric constant region and another region gradually decreases as the third connection member is approached . A base substrate in contact with the bottom surface of the dielectric layer;
The base substrate, penetrating in the thickness direction thereof, the first connecting member, to claim 1 and a second connecting member, and a third plurality of conductive vias that are connected to the connecting member The circuit board with a built-in capacitor as described. A dielectric layer having a top surface and a bottom surface defined and formed of a dielectric material;
Each of the first connecting member, the second connecting member, and the second connecting member formed of a conductive material from the upper surface of the dielectric layer to the bottom surface of the dielectric layer through the dielectric layer. 3 connecting members;
A first electrode disposed on any one of an upper surface, a bottom surface, and an inside of the dielectric layer and connected to the first connection member;
The dielectric layer is disposed on any one of the upper surface, the bottom surface, and the inside of the dielectric layer, sandwiches at least a part of the dielectric layer, constitutes a capacitor together with the first electrode, and is connected to the second connection member A second electrode and
Have
Of the dielectric layer, the dielectric constant of the part in contact with the third connecting member is a low dielectric constant region lower than the dielectric constant of the other part,
The low dielectric constant region is a region der Ruki Yapashita built-in circuit board obtained by destroying the crystallinity of the dielectric layer. A dielectric layer having a top surface and a bottom surface defined and formed of a dielectric material;
Each of the first connecting member, the second connecting member, and the second connecting member formed of a conductive material from the upper surface of the dielectric layer to the bottom surface of the dielectric layer through the dielectric layer. 3 connecting members;
A first electrode disposed on any one of an upper surface, a bottom surface, and an inside of the dielectric layer and connected to the first connection member;
The dielectric layer is disposed on any one of the upper surface, the bottom surface, and the inside of the dielectric layer, sandwiches at least a part of the dielectric layer, constitutes a capacitor together with the first electrode, and is connected to the second connection member A second electrode and
Have
Of the dielectric layer, the dielectric constant of the part in contact with the third connecting member is a low dielectric constant region lower than the dielectric constant of the other part,
Said dielectric layer comprises a number of fine crystal grains of a dielectric material, the low in the dielectric constant region, Ruki Yapashita built-in circuit board has an oxide is grown on the interface of the fine grains. A dielectric layer having a top surface and a bottom surface defined and formed of a dielectric material;
Each of the first connecting member, the second connecting member, and the second connecting member formed of a conductive material from the upper surface of the dielectric layer to the bottom surface of the dielectric layer through the dielectric layer. 3 connecting members;
A first electrode disposed on any one of an upper surface, a bottom surface, and an inside of the dielectric layer and connected to the first connection member;
The dielectric layer is disposed on any one of the upper surface, the bottom surface, and the inside of the dielectric layer, sandwiches at least a part of the dielectric layer, constitutes a capacitor together with the first electrode, and is connected to the second connection member A second electrode and
Have
Of the dielectric layer, the dielectric constant of the part in contact with the third connecting member is a low dielectric constant region lower than the dielectric constant of the other part,
A capacitor in which the dielectric layer is an oxide having a perovskite structure represented by a general formula ABO ₃ , and in the low dielectric constant region, a part of atoms of the site A or the site B are replaced by impurity atoms Built-in circuit board. (A) preparing a base substrate on which a first conductive via, a second conductive via, and a third conductive via penetrating in the thickness direction are formed;
(B) forming, on the surface of the base substrate, a first electrode connected to the first conductive via and not overlapping the second and third conductive vias;
(C) forming a dielectric film made of a dielectric material so as to cover the first electrode;
(D) By performing ion implantation in a region around the third conductive via in the dielectric film, the dielectric constant of the ion implanted region is made lower than the dielectric constant of other regions. Process,
(E) forming a second electrode on the dielectric film, facing the first electrode across the dielectric film and connected to the second conductive via;
(F) forming an insulating protective film on the dielectric film and the second electrode;
(G) a fourth conductive via penetrating the protective film in the thickness direction and electrically connected to the first electrode, the second electrode, and the third conductive via, respectively; And a step of forming a fifth conductive via and a sixth conductive via. 7. The circuit board with a built-in capacitor according to claim 6 , wherein in the step (d), ions are implanted into the dielectric film, and the dielectric constant of the ion-implanted region is lowered by breaking the crystallinity of the dielectric film. Production method. In the step (d), an element that reacts with oxygen to form an oxide and oxygen are ion-implanted into the dielectric film, and after the ion implantation, a heat treatment is performed to form microcrystal grains constituting the dielectric film. 7. The method of manufacturing a circuit board with a built-in capacitor according to claim 6 , wherein an oxide of an ion-implanted element is grown on the interface of the capacitor. The dielectric layer is an oxide having a perovskite structure represented by the general formula ABO ₃ , and in the step (d), impurity element ions for substituting a part of atoms of the site A or the site B are implanted, The method for manufacturing a circuit board with a built-in capacitor according to claim 6 , wherein after the implantation, heat treatment is performed to replace some atoms of the site A or the site B with the implanted ions.

Images