JP4626480B2 - Power circuit - Google Patents

Description

  The present invention relates to a power supply circuit that stabilizes a voltage input to a load (for example, a microcomputer).

  Conventionally, it has been stable against loads that vary in power consumption over time, such as microcomputers that operate repeatedly in sleep (low power consumption) mode and wakeup (normal operation) mode (hereinafter referred to as microcomputers). A power supply circuit that supplies power is known.

  The microcomputer consumes less power in the sleep mode than in the wake-up mode. For this reason, if the power supplied in the wake-up mode is continuously supplied in the sleep mode, the power supplied in the wake-up mode is continuously applied to the power input terminal of the microcomputer. However, since the power consumption of the microcomputer in sleep mode is lower than that in the wake-up mode, the supplied power is surplus, and power exceeding the specified value is input to the microcomputer, destroying the microcomputer. There was a fear of being done.

  Therefore, as described above, a power supply circuit has been proposed in which when the power supply to the load fluctuates (for example, when the microcomputer shifts from the wake-up mode to the sleep mode), a voltage higher than a specified voltage is not applied to the microcomputer. (For example, refer to Patent Document 1). A conventional power supply circuit will be described below with reference to the drawings.

  FIG. 8 is a schematic circuit diagram of an ECU provided with a power supply circuit for inputting a specified voltage to the microcomputer. The ECU 400 is mounted on a vehicle, for example. As shown in FIG. 8, the ECU 400 is provided with an IC 40 having a power supply circuit 15, and + B power, which is a battery power supply, is input from an input terminal 21 provided in the IC 40 via a resistor R <b> 11. It has become.

  Outside the IC 40, + B power is input to the emitter of the pnp transistor Tr11 via the resistor R12, and the collector of the transistor Tr11 is connected to the voltage terminal 22 of the IC 40. The base of the transistor Tr11 is connected to the collector of the npn transistor Tr12 via the resistor R15. The emitter of the transistor Tr12 is connected to the ground 12, and the base of the transistor Tr12 is connected to the terminal 24 of the IC 40.

  The IC 40 includes a microcomputer 27 serving as a load, a voltage terminal 22 for monitoring a voltage applied to the microcomputer 27, and a voltage dividing circuit 29 that divides the voltage applied to the voltage terminal 22. The microcomputer 27 operates when an injection current I 0 is input from the input terminal 21 of the IC 40 via the diode D 1 and the power supply line 26. The voltage dividing circuit 29 connected to the power supply line 26 is configured by connecting resistors R21, R22, and R23 in series, and the voltage applied to the voltage terminal 22 is divided.

  In the voltage dividing circuit 29, the potential A1 between the resistor R22 and the resistor R23 is input to the non-inverting input terminal of the control amplifier 30 for controlling the voltage applied to the voltage terminal 22. A predetermined voltage is input to the inverting input terminal of the control amplifier 30 from a reference voltage source 31 (for example, 2 V). The output terminal of the control amplifier 30 is connected to the gate of the transistor Tr21 and the current sink circuit 41, respectively. The source of the transistor Tr21 is connected to the ground 28, and the drain is connected to the terminal 25 of the IC 40. This terminal 25 is clamped at the potential of the terminal 24. Further, the terminal 25 is connected to the + B power source via the resistor R13.

  The current sink circuit 41 is a circuit that flows an excessive current out of the current flowing into the voltage terminal 22 from the outside and releases it to the ground 28, and suppresses a rise in the voltage input to the voltage terminal 22, and a current sink control amplifier 42. And an N-channel MOS transistor 43.

  The output of the control amplifier 30 is input to the non-inverting input terminal of the current sink control amplifier 42 of the current sink circuit 41. The potential A2 between the resistors R21 and R22 in the voltage dividing circuit 29 is input to the inverting input terminal of the control amplifier 30. Further, the output terminal of the current sink control amplifier 42 is connected to the gate of the transistor 43, the drain of the transistor 43 is connected to the voltage terminal 22, and the source is connected to the ground 28. The above is the configuration of the conventional power supply circuit provided in the ECU 400.

  In the ECU 400 configured as described above, when the voltage at the voltage terminal 22 exceeds the specified value (5V), the potential A1 becomes higher than the voltage value (2V) of the reference voltage source 31, and therefore the control amplifier 30 outputs HI. As a result, the transistor Tr21 is turned on, so that the transistor Tr12 outside the IC 40 is turned off. Accordingly, the transistor Tr11 is turned off, and the supply of + B power to the voltage terminal 22 is stopped. When the voltage at the voltage terminal 22 falls below 5 V, the transistor Tr11 is turned on by the reverse operation described above, and + B power is supplied to the voltage terminal 22.

  In addition to the operation of supplying or stopping the + B power supply for the voltage at the voltage terminal 22 as described above, the operation for the injection current I0 flowing from the + B power supply into the input terminal 21 will be described. When the ECU 400 shifts to the sleep mode or wake-up mode of the microcomputer 27, first, when a voltage of, for example, 12V is input from the + B power supply to the input terminal 21 via the resistor R11, the microcomputer 27 is in the wake-up mode. Then, the injection current I0 is injected into the microcomputer 27 via the diode D1 and the power supply line 26. Thereby, the microcomputer 27 operates.

  When the microcomputer 27 shifts from the wake-up mode to the sleep mode, the microcomputer 27 does not operate, so that the injection current I0 flowing through the input terminal 21 and the diode D1 is lost and flows into the voltage terminal 22. As a result, the voltage at the voltage terminal 22 held at 5V increases.

  When the potential A1 becomes equal to or higher than the specified voltage (2V) in the voltage dividing circuit 29 as the voltage at the voltage terminal 22 increases, HI is output from the control amplifier 30 and this signal is input to the current sink control amplifier 42. Then, the output of the current sink control amplifier 42 becomes HI, a current flows through the gate of the transistor 43, and the transistor 43 is turned ON. As a result, the injected current I 0 that has flowed from the input terminal 21 to the voltage terminal 22 via the diode D 1 flows to the ground 28 via the transistor 43. Thus, it is possible to prevent the voltage at the voltage terminal 22 from rising due to the injected current I0 flowing into the voltage terminal 22.

When the microcomputer 27 shifts from the sleep mode to the wake-up mode, the transistor 43 is turned off by the reverse operation described above. As a result, the injection current I0 flows into the microcomputer 27 and is consumed, and the injection current I0 can be prevented from continuing to flow through the transistor 43 and the voltage at the voltage terminal 22 being lowered.
JP-A-2005-71320

  However, in the above conventional technique, the presence or absence of the injection current I 0 flowing into the voltage terminal 22 is sensed by the output voltage p 1 of the control amplifier 30. For this reason, at the time of entering or returning from the sleep mode in which the load current of the microcomputer 27 fluctuates rapidly, the drive capability of the control amplifier 30 is insufficient, and the rise of the power supply (overshoot) decreases due to a response delay, or A subduction (ripple) phenomenon occurs. Hereinafter, this will be described with reference to FIG.

  FIG. 9A is a diagram showing an output operation of the control amplifier 30 when the microcomputer 27 enters the sleep mode from the wake-up mode. In FIG. 9A, the output voltage p1 of the control amplifier 30 is shown in the lower stage, and the potential of the voltage terminal 22 is shown in the upper stage with respect to the time axis.

  When the microcomputer 27 is in the wake-up mode, as shown in the upper part of FIG. 9A, the voltage terminal 22 is maintained at a specified value (5V). At this time, as shown in the lower part of FIG. 9A, the output potential p1 of the control amplifier 30 is balanced with the voltage B (for example, 1 V) applied to the base of the transistor Tr21 and has the same value. In other words, the potential A2 is maintained at 2V, and the output of the control amplifier 30 is LOW. Therefore, the output of the current sink control amplifier 42 is also LOW, and the transistor 43 is OFF.

  When the microcomputer 27 shifts from the wake-up mode to the sleep mode, the current consumed by the microcomputer 27 is drastically reduced, so that the injected current I0 flows into the voltage terminal 22 and the potential of the voltage terminal 22 increases as described above. To do.

  However, in the voltage dividing circuit 29, the potential A2 does not immediately exceed the specified voltage (2V). This is because the phase compensation capacitor C12 for preventing this circuit from oscillating is connected to the voltage terminal 22, and the charge of the phase compensation capacitor C12 is accumulated by the injected current I0 flowing into the voltage terminal 22. Because it takes time to go.

  Therefore, as shown in the lower part of FIG. 9A, if the phase compensation capacitor C12 is not connected, the output potential p1 of the control amplifier 30, which is the potential B in the waveform indicated by the dotted line, exceeds the potential A2. Although the current sink control amplifier 42 operates immediately, in practice, it takes time to charge the phase compensation capacitor C12. For this reason, the operation of the current sink control amplifier 42 is delayed by the response delay time at the time of state transition.

  During this time, as shown in the upper part of FIG. 9A, since the current sink control amplifier 42 does not operate and the transistor 43 does not operate, the injected current I0 continues to flow to the voltage terminal 22, and the potential of the voltage terminal 22 is It will continue to rise above 5V. In this way, due to the response delay of the current sink control amplifier 42, a power supply overshoot occurs at the voltage terminal 22, and a voltage higher than a specified voltage may be applied to the microcomputer 27 and the microcomputer 27 may be destroyed. .

  FIG. 9B is a diagram showing the output operation of the control amplifier 30 when the microcomputer 27 returns from the sleep mode to the wake-up mode. In FIG. 9B, as in FIG. 9A, the output voltage p1 of the control amplifier 30 is shown in the lower stage and the potential of the voltage terminal 22 is shown in the upper stage with respect to the time axis.

  When the microcomputer 27 shifts from the sleep mode to the wake-up mode, the reverse phenomenon occurs. That is, when the microcomputer 27 is in the sleep mode, the output potential p1 of the control amplifier 30 is balanced to, for example, the potential A2. Therefore, the current sink control amplifier 42 operates, the transistor 43 is turned on, and a path through which the injected current I0 flows to the ground 12 through the transistor 43 is formed.

  When the microcomputer 27 shifts from the sleep mode to the wake-up mode, the injected current I0 flows into the microcomputer 27 and is consumed. However, as described above, the phase compensation capacitor C12 is in a charged state.

  Therefore, as shown in the lower part of FIG. 9B, if the phase compensation capacitor C12 is not connected, the output potential p1 of the control amplifier 30 drops from the potential A2 to the potential B during the time indicated by the dotted line, Although the sink control amplifier 42 operates immediately, it actually takes time to discharge the phase compensation capacitor C12. For this reason, the operation of the current sink control amplifier 42 is delayed by the response delay time at the time of state transition.

  During this time, as shown in the upper part of FIG. 9B, since the current sink control amplifier 42 does not become LOW and the transistor 43 remains ON, the current continues to flow to the ground 12 via the transistor 43, and the voltage The potential of the terminal 22 is less than 5V. In this way, due to the response delay of the current sink control amplifier 42, a power supply ripple (sinking) occurs at the voltage terminal 22, and the voltage applied to the microcomputer 27 becomes too low. Reset may occur, and the operation of the microcomputer 27 may be abnormal.

  9A and 9B, when the microcomputer 27 is in the sleep mode, the voltage terminal 22 is 5 V or higher. This is caused by the gain of the current sink control amplifier 42, and is a voltage value that does not cause a problem.

  The power overshoot and the power ripple as described above are caused by a response delay of the current sink control amplifier 42 because the output voltage p1 of the control amplifier 30 is sensed. In order to prevent the transistor 43 of the current sink circuit 41 and the transistor Tr11 for supplying or stopping the + B power supply from operating simultaneously, the movable region (the potential B and the potential A2 of the output potential p1 of the control amplifier 30) is prevented. A large interval is also a cause of a noticeable response delay during state transition.

  Therefore, in view of the above points, an object of the present invention is to reduce power supply overshoot and power supply ripple in a power supply circuit that stably supplies power to a load whose power consumed over time varies.

  In order to achieve the above object, in the present invention, when a current flows in the input path, the current sense circuit (34) detects that the current flows in the input path, and uses the detection result as a sense signal as a current sink circuit (32). When the current sink circuit (32) does not perform a sink operation according to the input sense signal, and no current flows in the input path, the current sense circuit (34) flows in the input path. And detecting the result of detection as a sense signal to the current sink circuit (32), and the current sink circuit (32) performs a sink operation in accordance with the input sense signal.

  In this way, the current flowing through the input path is detected by the current sense circuit, and the current sink circuit is operated based on the detection result of the current sense circuit. That is, the current sensing circuit controls the sink operation of the current sink circuit by directly detecting the current flowing through the input path as the current instead of the voltage corresponding to the current. As a result, when the current consumption of the load fluctuates, the detection result according to the presence or absence of current flowing in the input path can be output from the current sense circuit to the current sink circuit, which makes the control of the sink operation of the current sink circuit sensitive. It can be carried out.

  As described above, the operation delay of the current sink circuit can be reduced, so that when the current flows through the input path due to fluctuations in the current consumption of the load and the current is input to the voltage terminal, the sink operation of the current sink circuit is reduced. Since it can be stopped earlier, the ripple (sinking) phenomenon of the voltage at the voltage terminal caused by the current flowing from the voltage terminal to the current sink circuit can be suppressed. In addition, when current does not flow through the input path due to fluctuations in the current consumption of the load and no current is input into the voltage terminal, the sink operation of the current sink circuit can be performed faster, so the voltage terminal caused by the current flowing into the voltage terminal Voltage overshoot (lifting) can be suppressed.

  In this way, the voltage input to the voltage terminal can always be held at the specified voltage. Therefore, an unspecified voltage is not input to the load, the load can be prevented from being destroyed, and a malfunction of the load can be prevented.

In the present invention, the current sense circuit (34, 37) includes the first current mirror circuit (35) configured using the second transistor (Tr21), and the first transistor (Tr11) is turned OFF or ON . Thus, whether or not current flows in the input path is detected using the current mirror and the current flowing in the detection path when the second transistor (Tr21) is turned on or off.

Thus, the current sense circuit, the current flowing in the input path by OFF or ON of the first transistor (Tr11), using the current and the current mirror circuit flows through the output path by ON or OFF of the second transistor (Tr21) To detect. Thereby, it is possible to detect the presence or absence of a current flowing through the input path, that is, a current flowing into the voltage terminal. At this time, since the current flowing in the output path is detected by the current mirror circuit, the response delay with respect to the operation of the first transistor (Tr11) can be reduced.

  In the present invention, in the current sense circuit (34), when no current flows through the second transistor (Tr21), no current flows through the fifth transistor (Tr24) by the first current mirror circuit (35). A current flowing from the fourth transistor (Tr25) to the first resistor (R24) flows in, the potential at the connection point C rises, and the raised potential is output as a sense signal. Further, when a current flows through the second transistor (Tr21), a current flows through the fifth transistor (Tr24) by the first current mirror circuit (35), and a current flows out from the connection point C to the fifth transistor (Tr24). The potential of the point C is lowered, and the lowered potential is output as a sense signal.

  Thus, a current sense circuit is configured, and the current flowing through the second transistor (Tr21), that is, the current flowing through the fifth transistor (Tr24) and the reference current flowing through the first resistor (R24) are compared at the connection point C. The result is output as a sense signal. As a result, whether or not a current flows through the second transistor (Tr21) can be output as a sense signal earlier.

  The present invention is characterized in that the current flowing through the first resistor (R24) is set to be the maximum value of the variation of the current flowing through the output path.

  Thus, the current flowing through the first resistor (R24) is defined. As a result, malfunction of the current sink circuit (34) due to variations in the input voltage (for example, + B power supply) input to the first power supply line (11) can be prevented.

  In the present invention, the comparator (33) provided in the current sink circuit (32) outputs LOW to the gate electrode of the sixth transistor (Tr23) when the sense signal is larger than the comparison voltage, and the sixth transistor ( Tr23) is turned off to cut off the flow path to stop the sink operation of the sixth transistor (Tr23). When the sense signal is smaller than the comparison voltage, HI is output to the gate electrode of the sixth transistor (Tr23), The sixth transistor (Tr23) is turned on to perform a sink operation for passing a current to the ground (28) through the flow-in path.

  Thus, the current sink circuit (32) performs a sink operation based on the sense signal input from the current sense circuit (34). Since the sense signal is output to the current sink circuit (32) based on the current flowing through the transistor (T21), the current sink circuit (32) can be controlled more quickly. Thereby, the response delay of the current sink circuit (32) can be suppressed, and the voltage terminal overshoot and ripple phenomenon can be reduced.

  In the present invention, a seventh transistor (Tr31) is connected between the first power supply line (11) and the second transistor (Tr21) in the detection path, and the seventh transistor (Tr31) is connected to the first transistor (Tr31). It is provided in the detection path so that it is turned on when Tr11) is turned on and turned off when the first transistor (Tr11) is turned off, and the current sink circuit (32) includes a sixth transistor (Tr23). The transistor (Tr23) performs a sink operation when turned on in response to a sense signal output from the connection point C, and stops the sink operation when turned off in response to a sense signal output from the connection point C. Features.

  Thus, the current sink circuit (32) performs a sink operation based on the sense signal input from the current sense circuit (34). At this time, since the seventh transistor (Tr31) and the second transistor (Tr21) on the detection path operate in conjunction with the first transistor (Tr11), the current sense circuit (34) is connected to the first transistor (Tr11). Operation detection and sense signal output can be performed simultaneously. Thereby, the response delay of the current sink circuit (32) can be further suppressed, and the overshoot and ripple phenomenon of the voltage at the voltage terminal can be reduced.

  In the present invention, when no current flows through the second transistor (Tr21), the current stops flowing through the tenth transistor (Tr28), and the current flowing through the second resistor (R25) flows through the tenth transistor (Tr28). A current flows out from the point D, the potential at the connection point D decreases, and the decreased potential is output as a sense signal. When a current flows through the second transistor (Tr21), a current flows through the tenth transistor (Tr28), a current flows into the connection point D, the potential at the connection point D rises, and the increased potential is used as a sense signal. It is characterized by outputting.

  Thus, a current sense circuit is configured, and the current flowing through the second transistor (Tr21), that is, the current flowing through the fifth transistor (Tr24) and the reference current flowing through the second resistor (R25) are compared at the connection point D. The result is output as a sense signal. As a result, whether or not a current flows through the second transistor (Tr21) can be output as a sense signal earlier.

  The present invention is characterized in that the current flowing through the second resistor (R25) is set to be the maximum value of the variation of the current flowing through the output path.

  Thus, the current flowing through the second resistor (R25) is defined. Thereby, it is possible to prevent malfunction of the current sink circuit (37) due to variations in the input voltage (for example, + B power supply) input to the first power supply line (11).

  In the present invention, when the sixth transistor (Tr23) constituting the current sink circuit (32) is turned on according to the sense signal output from the connection point D, the sixth transistor (Tr23) is connected to the second power supply line (26) via the flow path. A sink operation is performed in which a current flows to the ground (28). When the sink operation is turned off according to the sense signal output from the connection point D, the sink operation is stopped.

  Thus, the current sink circuit (32) performs a sink operation based on the sense signal input from the current sense circuit (34). At this time, since the sixth transistor (Tr23) of the current sink circuit (32) is turned on or off by the sense signal output from the current sense circuit (34), the operation of the current sink circuit can be controlled earlier. Thereby, the response delay of the current sink circuit (32) can be suppressed, and the voltage terminal overshoot and ripple phenomenon can be reduced.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. In the following, the same components as those shown in FIG. FIG. 1 is a schematic circuit diagram of an ECU provided with a power supply circuit according to the first embodiment of the present invention. The ECU 100 shown in FIG. 1 is mounted on a vehicle, for example, and is used to perform desired control.

  As shown in FIG. 1, the ECU 100 includes an IC 20 that functions as a power supply circuit and has a constant pressure circuit 10 for maintaining a predetermined voltage. The constant pressure circuit 10 is for inputting a + B power supply (for example, 12 V) that is a battery voltage and inputting a predetermined voltage to an internal circuit of the IC 20.

  An external configuration of the IC 20 in the constant pressure circuit 10 will be described. First, the IC 20 is provided with five terminals of an input terminal 21, a voltage terminal 22, and terminals 23 to 25. Among these, the input terminal 21 is supplied with + B power, which is battery power, via a resistor R11. The path from the + B power source to the voltage terminal 22 corresponds to the input path of the present invention.

  Outside the IC 20, a resistor R 12 and a pnp transistor Tr 12 are connected in series between the power supply line 11 and the voltage terminal 22 of the IC 20, and a smoothing capacitor is connected between the voltage terminal 22 and the ground 12. C11 is connected, and a phase compensation capacitor C12 is connected between the voltage terminal 22 and the terminal 12. In the present embodiment, the power line 11 (the first power line of the present invention) is defined from the + B power source to the voltage terminal 22.

  Further, the terminals 24 and 25 of the IC 20 are connected inside the IC 20. Of these terminals 24 and 25, a resistor R13 is connected between the terminal 25 and the power supply line 11, and a capacitor C13 is connected between the terminal 25 and the ground 12. Resistors R14 and R15 and an npn transistor Tr13 are connected in series between the power supply line 11 and the ground 12, and the base of the transistor Tr13 is connected to the terminal 24. Each component outside the IC 20 is constituted by, for example, discrete parts.

  Next, the internal configuration of the IC 20 in the constant pressure circuit 10 will be described. First, a diode D <b> 1 is connected between the input terminal 21 and the voltage terminal 22 to prevent a reverse current flow. The terminal 22 is connected to a microcomputer 27 as a load via a power line 26 (second power line of the present invention). The microcomputer 27 executes a program for performing desired control in the wake-up (normal operation) mode, and enters the sleep (low power consumption) mode at a desired timing to reduce power consumption. The microcomputer 27 corresponds to the load of the present invention.

  A voltage dividing circuit 29 is connected between the voltage terminal 22 and the ground 28. The voltage dividing circuit 29 is configured by connecting resistors R21, R22, and R23 in series. The potential at the connection point between the resistors R22 and R23 is A1, and the potential at the connection point between the resistors R22 and R21. Is A2 (comparison voltage of the present invention, for example, 4.5 V). Among these, the connection point at the potential A1 is connected to the non-inverting input terminal of the control amplifier 30 as an operational amplifier. A reference voltage source is connected to the inverting input terminal of the control amplifier 30 so that a reference voltage (for example, 2 V) is applied.

  The control amplifier 30 outputs HI when the potential A1 exceeds the reference voltage of the reference voltage source 31, and the output terminal of the control amplifier 30 is the n-channel MOS transistor Tr21 (the second transistor of the present invention). Connected to the gate. The “HI” described above corresponds to a gate voltage at which the transistor Tr21 is turned on. Conversely, “LOW” corresponds to a gate voltage at which the transistor Tr21 is turned off. Therefore, each transistor used in this embodiment is turned ON or OFF when “HI” or “LOW” is input to the gate.

  In the present embodiment, the gate voltage of the transistor Tr21 is set to the potential B. That is, the potential B changes according to the output potential p1 of the control amplifier 30, and the transistor Tr21 is turned on or off. The transistor Tr21 has a drain connected to the terminals 24 and 25 and a source connected to the ground 28. The space between the power supply line 11 and the ground 28 corresponds to the detection path of the present invention.

  The output terminal of the control amplifier 30 is connected to the terminal 23 through the source and drain of the n-channel MOS transistor Tr22, and the gate of the transistor Tr22 is connected to a predetermined potential. The transistor Tr22 functions as a resistor and constitutes a phase compensation circuit together with the capacitor C12.

  Further, a current sink circuit 32 is connected between the power supply line 26 and the ground 28 (flow path of the present invention). The current sink circuit 32 is a circuit that suppresses an increase in the voltage at the voltage terminal 22 by flowing an excessive current out of the current flowing into the power supply line 26 from the outside of the IC 20 and releasing it to the ground 28. Such a current sink circuit 32 includes a current sink control amplifier 33 (comparator of the present invention) as an operational amplifier and an n-channel transistor Tr23 (sixth transistor of the present invention).

  Among these, the drain and source of the transistor Tr23 are connected to the power supply line 26 and the ground 28, respectively, and the gate is connected to the output terminal of the current sink control amplifier 33. Therefore, the transistor Tr23 is turned on or off according to the output of the current sink control amplifier 33.

  The potential A2 of the voltage dividing circuit 29 is input to the non-inverting input terminal of the current sink control amplifier 33, and the current sense circuit 34 is connected to the inverting input terminal. The current sense circuit 34 is a circuit that directly senses the current Isp flowing between the drain and source of the transistor Tr11 (the first transistor of the present invention) provided outside the IC 20 with the current. As will be described in detail later, when the voltage rise at the voltage terminal 22 occurs, the current Isp does not flow through the transistor Tr11. That is, the current sense circuit 34 detects the presence / absence of the current Isp using the current Is flowing through the transistor Tr21.

  Specifically, the current sense circuit 34 includes an n-channel MOS transistor Tr24 (the fifth transistor of the present invention), and the gate of the transistor Tr24 is connected to the transistor Tr21 (or the output terminal of the control amplifier 30). The source is connected to the ground 28. Thereby, the transistors Tr21 and Tr24 form a current mirror circuit 35 (first current mirror circuit of the present invention), and a current having the same value as the current Is flowing between the drain and source of the transistor Tr21 is between the drain and source of the transistor T24. It is supposed to flow through.

  The drain of the transistor Tr24 is connected to the inverting input terminal of the current sink circuit 32. The inverting input terminal of the current sink circuit 32 is also connected to the source of a p-channel MOS transistor Tr25 (the fourth transistor of the present invention), and the drain of the transistor Tr25 is connected to a predetermined potential.

  The gate of the transistor Tr25 is connected to the gate of a p-channel MOS transistor Tr26 (the third transistor of the present invention), and this gate is connected to the source of the transistor Tr26. The drain of the transistor Tr26 is connected to a predetermined potential, and the source is connected to the ground 28 via a resistor R24 (first resistor of the present invention). As a result, the transistors Tr25 and Tr26 constitute a current mirror circuit 36 (second current mirror circuit of the present invention), and a current having the same value as the current Irmax flowing through the resistor R24 flows between the drain and source of the transistor Tr25. ing.

  In the present embodiment, the value of the current flowing through the resistor R24 is the maximum value Irmax of the current Ir flowing through the resistor R13 provided outside the IC 20. This is because the current Ir flowing through the resistor R13 fluctuates due to the voltage value of the + B power supply or the resistor 13, and therefore the maximum value Irmax of the current Ir is monitored.

  Therefore, the current sense circuit 34 is a circuit for comparing the magnitude of the current Irmax flowing through the transistor Tr25 and the current Is flowing through the transistor Tr24, and the comparison result is the connection point C of the transistors Tr24 and Tr25. It is output as the potential C (sense signal of the present invention). The potential C is input to the inverting input terminal of the current sink control amplifier 33 of the current sink circuit 32.

  For example, when the current Irmax> the current Is, that is, when the transistor Tr21 is OFF, since the current does not flow to the transistor Tr24 side, the potential C becomes high and becomes HI, and the current sink control amplifier 33 outputs LOW. The transistor Tr23 is turned off. On the other hand, when the current Irmax <current Is, that is, when the transistor Tr21 is ON, since the current flows to the transistor Tr24 side, the potential C becomes low and becomes LOW, and the current sink control amplifier 33 outputs HI. Tr23 is turned on, current flows in, and escapes to the ground 28. The above is the circuit configuration of the ECU 100 including the constant pressure circuit 10 according to the present embodiment.

  Next, the operation of the constant pressure circuit 10 will be described. First, the operation when the potential of the voltage terminal 22 varies from the specified value (5 V) will be described. When the voltage at the voltage terminal 22 exceeds the specified value, the potential A1 of the voltage dividing circuit 29 increases accordingly. Thus, when the potential A1 exceeds the reference voltage of the reference voltage source 31, the control amplifier 30 outputs HI. When the control amplifier 30 outputs HI, a voltage is input to the gate of the transistor Tr21 to turn it ON, and a current Is flows between the drain and source of the transistor Tr21.

  Since the current flows from the + B power source through the path R13, the terminal 25, and the transistor Tr21, the current Ib flowing from the + B power source to the path R13, the terminals 25 and 24, and the transistor Tr12 does not flow, and the transistor Tr12 Turns off. As a result, no current flows between the base of the transistor Tr11, the resistor R15, and the emitter-collector of the transistor Tr12, and the transistor Tr11 is turned off.

  In this way, by preventing the current Isp from flowing from the + B power source to the path of the power supply line 11, the resistor R11, and the transistor Tr11, the supply of the + B power source to the voltage terminal 22 is stopped and the voltage rise at the voltage terminal 22 is stopped. .

  On the other hand, when the potential of the voltage terminal 22 falls below the specified value, the potential A1 of the voltage dividing circuit 29 decreases accordingly. As a result, the potential A1 falls below the reference voltage of the reference voltage source 31, and the control amplifier 30 outputs LOW. When the control amplifier 30 outputs LOW, no voltage is input to the gate of the transistor Tr21, the transistor Tr21 is turned off, and no current Is flows between the drain and the source.

  Then, outside the IC 20, a current flows from the + B power source through a path of the resistor R13, terminals 25 and 24, and the transistor Tr12. That is, the current Ib flows through the base of the transistor Tr12, and the transistor Tr12 is turned on. As a result, a current flows between the transistor Tr11, the resistor R15, and the collector-emitter of the transistor Tr12, turning on the transistor Tr11.

  Thus, the current Isp flows from the + B power source to the path of the power source line 11, the resistor 11, and the transistor Tr11, the + B power source is supplied to the voltage terminal 22, and the voltage drop at the voltage terminal 22 is stopped.

  In addition to such an operation of supplying or stopping the + B power supply to the voltage terminal 22, a case where the fluctuation of the potential of the voltage terminal 22 is reduced according to the operating state of the microcomputer 27 as a load, that is, the wake-up mode or the sleep mode. This will be described with reference to FIGS.

  First, the case where the microcomputer 27 shifts from the wake-up mode to the sleep mode will be described. FIG. 2A is a diagram showing the potential of the voltage terminal 22 (upper stage) and the output potential (lower stage) of the control amplifier 30 when the microcomputer 27 enters the sleep mode from the wake-up mode. FIG. 2B is a diagram showing the current Is flowing between the drain and source of the transistor Tr21 that changes according to the output operation of the control amplifier 30.

  In the ECU 100, when a voltage of, for example, 12V is input from the + B power source to the microcomputer 27 via the resistor R11, the terminal 21, and the power line 26, when the microcomputer 27 is in the wake-up mode, the injection current I0 is a diode from the + B power source. It is injected into the microcomputer 27 via D1 and the power line 26. The microcomputer 27 operates by consuming this injected current I0.

  When the microcomputer 27 shifts from the wake-up mode to the sleep mode, the microcomputer 27 does not operate, so that the injection current I0 is not consumed by the microcomputer 27. Thereby, the place of the injection current I0 flowing through the input terminal 21 and the diode D1 disappears, the injection current I0 flows into the voltage terminal 22, and the voltage of the voltage terminal 22 held at the specified value (5V) starts to rise. .

  That is, as shown in the upper part of FIG. 2A, when the potential of the voltage terminal 22 starts to rise, the current Is flowing between the drain and source of the transistor Tr21 rises as shown in FIG. 2B. Begin to.

  In this way, at the initial stage where the potential of the voltage terminal 22 starts to rise, the transistor Tr21 is turned off, so that the current Is flows through the transistor Tr24 and the transistor Tr24 of the current sense circuit 34 constituting the current mirror circuit 35. Absent. Therefore, in the current sense circuit 34, the current Irmax flowing through the transistor Tr25 by the current mirror circuit 36 becomes larger than the current Is (= 0) flowing through the transistor Tr24. For this reason, the connection point C absorbs the current Irmax, the potential C is increased, and HI is output. As a result, the current sink control amplifier 33 is turned off and the transistor Tr23 is also turned off.

  Then, as the voltage at the voltage terminal 22 rises, the potential A1 of the voltage dividing circuit 29 rises, so that the output potential p1 of the control amplifier 30 starts to rise. Accordingly, since the potential B rises, the gate voltage of the transistor Tr21 starts to rise, and eventually the transistor Tr21 is turned on, and the current Is flowing through the transistor Tr21 has the same value as the current Ir flowing through the resistor R13 outside the IC 20 become.

  At this time, as shown in FIG. 2B, the current Is flowing between the drain and the source also rises rapidly only by a slight increase in the gate voltage applied to the transistor Tr21. When the current Is becomes the same value as the current Ir, the current Ib flowing through the base of the transistor Tr12 becomes zero, and the transistors Tr11 and Tr12 are turned off.

  Thus, when the transistor Tr11 is turned off, the current Ir = current Is and the current Ib = 0, and the injected current I0 flows into the voltage terminal 22 even if the transistor Tr11 is turned off. For this reason, as shown in the lower part of FIG. 2A, the potential A1 of the voltage dividing circuit 29 also rises, and the output potential p1 of the control amplifier 30 continues to rise.

  Thereafter, in the current sense circuit 34, the current Is flows between the drain and source of the transistor Tr24 by the current mirror circuit 35. In the current sense circuit 34, the current Irmax flows between the drain and source of the transistor Tr25 by the current mirror circuit 36.

  Then, the current sensing circuit 34 compares the current Irmax with the current Is (= current Ir). As described above, when the current Is = current Ir, the current Is has not reached the current Irmax. However, since the voltage of the output potential p1 of the control amplifier 30 is monitored, when the injection current I0 flows into the voltage terminal 22, the output voltage p1 becomes + α (for example, as shown in the lower part of FIG. 2A). It can be assumed that the current Is increases virtually by increasing (approximately several tens of mV).

  That is, the output voltage p1 of the control amplifier 30 that is balanced with the gate voltage B of the transistor Tr21 increases as the current Is increases, and the current Irmax flows through the transistor Tr21, as shown in the lower part of FIG. Equilibrate to an assumed gate voltage B + α. Conventionally, since the output potential p1 of the control amplifier 30 was monitored as described above, it was necessary to wait until the output potential p1 balanced with the potential B increased by, for example, about 1 V. Since it is sufficient to wait until the output potential p1 rises from the potential B by + α (for example, 50 mV), the response delay that has been a problem in the past can be reduced.

  Note that while the current Is increases in this way, the potential of the voltage terminal 22 continues to increase as shown in the upper part of FIG.

  When the current Is rises as described above and the potential of the output potential p1 (= potential B) becomes B + α, the current Is exceeds the current Irmax and is connected as shown in FIG. A current is discharged from the point C, and the potential C decreases. As a result, LOW is output as the potential C at the connection point C.

  The potential C at the connection point C is input to the inverting input terminal of the current sink control amplifier 33 of the current sink circuit 32. Since the potential C is LOW, HI is output from the current sink control amplifier 33, and the transistor Tr23 is turned on. In this way, the injection current I0 that has lost its place due to the microcomputer 27 shifting to the sleep mode can flow into the current sink circuit 32 and escape to the ground 28.

  As a result, as shown in the upper part of FIG. 2A, the rise in the potential of the voltage terminal 22 can be stopped when the transistor Tr23 of the current sink circuit 32 is turned on. As described above, the rising of the voltage at the voltage terminal 22 is sensed by the current Isp of the transistor Tr11, that is, the current Isp is sensed directly by the current Ib, the current Ir, and the current Is to sink the current sink circuit 32. I am letting. In this way, the current sink control amplifier 33 is not operated using the output potential p1 of the control amplifier 30, but the current sink control amplifier 33 is operated using a current that reacts sensitively in the circuit path. The circuit 32 can be operated sensitively, and voltage overshoot generated at the voltage terminal 22 can be reduced.

  Note that the potential of the voltage terminal 22 when the microcomputer 27 enters the sleep mode is slightly higher than the predetermined value (5 V) as shown in the upper part of FIG. As described above, this occurs due to the gain of the current sink control amplifier 33 and is, for example, about several tens of mV, and is a voltage value that sufficiently satisfies the operation specified value of the microcomputer 27. Further, since the current sink control amplifier 33 of the current sink circuit 32 operates, the potential C drops to the potential A2 (specifically, a potential lower than the voltage A2).

  Next, a case where the fluctuation of the potential of the voltage terminal 22 when the microcomputer 27 shifts from the sleep mode to the wake-up mode will be described. In this case, the operation is the reverse of the above.

  FIG. 3A is a diagram showing the potential of the voltage terminal 22 (upper stage) and the output potential (lower stage) of the control amplifier 30 when the microcomputer 27 enters the wake-up mode from the sleep mode. FIG. 3B is a diagram showing the current Is flowing between the drain and source of the transistor Tr21 that changes according to the output operation of the control amplifier 30 when the microcomputer 27 enters the wake-up mode from the sleep mode. is there.

  First, when the microcomputer 27 shifts from the sleep mode to the wake-up mode, the microcomputer 27 starts to operate, so that the injection current I0 is consumed by the microcomputer 27. Further, since the current sink circuit 32 is also operating, a current flows from the voltage terminal 22 to the microcomputer 27 and the ground 28, and the voltage at the voltage terminal 22 starts to drop.

  As a result, the voltage A1 of the voltage dividing circuit 29 also decreases, and the output potential p1 of the control amplifier 30 also begins to decrease. That is, as shown in the upper part of FIG. 3A, the potential of the voltage terminal 22 starts to fall, and as shown in the lower part of FIG. 3B, the current Is flowing between the drain and source of the transistor Tr21. Is below the (virtual) current Irmax.

  At this time, the output voltage p1 of the control amplifier 30 balanced with the gate voltage B + α of the transistor Tr21 decreases as the current Is decreases as shown in the lower part of FIG. 3A, and the current Is flows through the transistor Tr21. Equilibrates to the gate voltage B when it disappears.

  As a result, in the current sense circuit 34, the potential at the connection point C is increased and HI is output from the connection point C. Therefore, the output of the current sink control amplifier 33 of the current sink circuit 32 becomes LOW, and the transistor Tr21 is turned off. become.

  As shown in FIG. 3B, at this time, the current Is is lower than the current Irmax. However, since the current Is is virtually larger than the current Ir, the transistor Is has a current Is. Is flowing. Therefore, the base current Ib of the transistor Tr12 is zero.

  When the current Is flowing through the transistor Tr21 becomes the same value as the current Ir, the base current Ib begins to flow through the transistor Tr12, turning on the transistor Tr12 and turning on the transistor Tr11. Thereafter, since a sufficient current flows through the transistor Tr12, the transistor Tr11 is turned on and the + B power source is input to the voltage terminal 22.

  As described above, it is possible to prevent the injection current I0 from being consumed and the voltage at the voltage terminal 22 from being lowered due to the microcomputer 27 being in the operating state, and the potential at the voltage terminal 22 is lower than the specified value. It is possible to input the + B power supply to the voltage terminal 22 by previously turning on the transistor Tr11.

  As described above, the present embodiment is characterized in that the current flowing through the input path is detected by the current sense circuit 34 and the current sink circuit 32 is operated based on the detection result of the current sense circuit 34. That is, the current sensing circuit 32 controls the sink operation of the current sink circuit 32 by directly detecting the current flowing through the input path as the current instead of the voltage corresponding to the current. As a result, when the current consumption of the load fluctuates, the detection result corresponding to the presence or absence of the current flowing through the input path can be output from the current sense circuit 34 to the current sink circuit 32, and the sink operation of the current sink circuit 32 is controlled. Can be done sensitively.

  As described above, the delay in the operation of the current sink circuit 32 can be reduced, so that when the current flows through the input path due to fluctuations in the current consumption of the load and the current is input to the voltage terminal, the sink of the current sink circuit 32 Since the operation can be stopped earlier, the ripple (sinking) phenomenon of the voltage at the voltage terminal 22 caused by the current flowing from the voltage terminal 22 to the current sink circuit 32 can be suppressed. Further, when no current flows into the input path due to fluctuations in the current consumption of the load and no current is input to the voltage terminal 22, the sink operation of the current sink circuit 32 can be performed earlier, so that the current flowing into the voltage terminal 22 The overshoot (lifting) of the voltage at the voltage terminal 22 that occurs can be suppressed.

  In this way, the voltage input to the voltage terminal 22 can always be held at the specified voltage. Therefore, an unspecified voltage is not input to the microcomputer 27 as a load, so that the microcomputer 27 can be prevented from being destroyed, and malfunction of the microcomputer 27 can be prevented.

(Second Embodiment)
In the present embodiment, only different parts from the first embodiment will be described. In the present embodiment, the current sink control amplifier 33 is omitted from the current sink circuit 32 used in the first embodiment, and the transistor Tr23 is directly controlled.

  FIG. 4 is a schematic circuit diagram of an ECU provided with a power supply circuit according to the second embodiment of the present invention. As shown in this figure, the drain and the source of the transistor Tr23 are connected between the power line 26 and the ground 28 in the IC 20 provided in the ECU 200. The gate of the transistor Tr23 is connected to a current sense circuit 37 described later. Therefore, the transistor Tr23 is turned on or off according to the output of the current sense circuit 37, and the transistor Tr23 and the ground 28 constitute the current sink circuit 32.

  The current sense circuit 37 is provided with a transistor Tr24, and the transistor Tr24 and the transistor Tr21 constitute a current mirror circuit 35. A current having the same value as the current Is flowing between the drain and source of the transistor Tr21 flows between the drain and source of the transistor T24.

  The drain of the transistor Tr24 is connected to the source of a p-channel MOS transistor Tr27, and the drain of the transistor Tr27 is connected to a predetermined voltage. The gate of the transistor Tr27 is connected to the gate of a p-channel MOS transistor Tr28 (the tenth transistor of the present invention), and this gate is connected to the source of the transistor Tr27. Thus, the transistors Tr27 and Tr28 constitute a current mirror circuit 38 (fourth current mirror circuit of the present invention).

  Further, the drain and source of an n-channel MOS transistor Tr29 (the ninth transistor of the present invention) are connected between the source of the transistor Tr28 and the ground 28. In this embodiment, the junction point between the source of the transistor Tr28 and the drain of the transistor Tr29 is D, and the potential at the junction point D is the potential D. This potential D is output from the current sense circuit 37 and input to the gate of the transistor Tr23.

  The gate of the transistor Tr29 is connected to the gate of an n-channel MOS transistor Tr30 (the eighth transistor of the present invention), and this gate is connected to the drain of the transistor Tr30. As a result, the transistors Tr29 and Tr30 constitute a current mirror circuit 39 (third current mirror circuit of the present invention). The transistor Tr30 has a source connected to the ground 28, and a drain connected to a predetermined voltage via a resistor R25 (second resistor of the present invention).

  In the present embodiment, the current flowing through the resistor R25 is Irmax. The current Irmax flowing through the resistor R25 flows between the drain and source of the transistor Tr29 by the current mirror circuit 39. On the other hand, the current Is flowing in the transistor Tr21 flows between the drain and source of the transistor Tr28 by the current mirror circuits 35 and 38.

  That is, in the current sense circuit 37, when the current Irmax> the current Is, that is, when the transistor Tr21 is OFF, the current Is does not flow to the transistor Tr28. LOW, and the transistor Tr23 is turned OFF. On the other hand, when the current Irmax <current Is, that is, when the transistor Tr21 is ON, since the current flows into the connection point D, the potential D becomes high and becomes HI, and the transistor Tr23 becomes ON and the injection current I0 flows. Escape to the ground 28. The above is the circuit configuration of the ECU 200 including the constant pressure circuit 10 according to the present embodiment.

  In the ECU 200 including the constant pressure circuit 10, when the microcomputer 27 shifts from the wake-up mode to the sleep mode, as described above, the potential A1 rises and the control amplifier 30 operates to turn on the transistor Tr21. Outside the IC 20, the transistors Tr 11 and Tr 12 are turned off to stop supplying + B power to the voltage terminal 22.

  When the transistor Tr21 is turned on as described above, a current Is (= current Ir) flows between the drain and source of the transistor Tr21. Accordingly, in the current sense circuit 37, the current Is flows through the transistor Tr28 by the current mirror circuits 35 and 38. Similarly, in the current sense circuit 37, the current Irmax flows through the transistor Tr29 by the current mirror circuit 39.

  As described above, as the output potential p1 of the control amplifier 30 increases, when the current flowing through the transistor Tr29 also virtually increases and exceeds the current Irmax, HI is output from the connection point D as the potential D. As a result, the transistor Tr23 is turned on and the injection current I0 flowing into the voltage terminal 22 is released to the ground 28. In this way, it is possible to prevent the power supply overshoot from being caused by the potential of the voltage terminal 22 rising due to the injected current I0 when the microcomputer 27 enters the three-modeless mode.

  Further, when the microcomputer 27 shifts from the sleep mode to the wake-up mode, the power consumption of the microcomputer 27 increases as described above, but since the injected current I0 is released to the ground 28 via the transistor Tr23, the voltage terminal 22 Voltage drop occurs.

  When the voltage at the voltage terminal 22 decreases in this way, the output potential p1 of the control amplifier 30 becomes LOW, so that the current Is does not flow between the drain and source of the transistor Tr21. Accordingly, in the current sense circuit 37, the current Is does not flow to the transistor Tr28 and the current is discharged from the connection point D, so that LOW is output from the connection point D as the potential D. As a result, the transistor Tr23 is turned off so that the injection current I0 is not released to the ground 28. In this way, it is possible to prevent the microcomputer 27 from shifting to the wake-up mode and increasing the power consumption, and sucking the injected current I0 to reduce the potential at the voltage terminal 22 and cause a ripple phenomenon.

  As described above, also in this embodiment, since the current flowing in the transistor Tr21 is used to control the ON or OFF of the transistor Tr23 for releasing the injection current I0 to the ground 28, the power consumption of the microcomputer 27 varies. In this case, ON / OFF of the transistor Tr23 can be quickly controlled. Therefore, it is possible to prevent the power terminal overshoot or ripple phenomenon of the voltage terminal 22 from occurring.

  Further, in this embodiment, since the current sink control amplifier 33 used in the first embodiment is eliminated, the circuit configuration inside the IC 20 in the constant pressure circuit 10 can be simplified, and current consumption can be reduced. it can. Further, since the gain of the system is reduced by not using the current sink control amplifier 33, the feedback gain when the transistor Tr23 is in the sink operation state can be reduced and the power oscillation can be suppressed. Can be improved.

(Third embodiment)
In the present embodiment, only portions different from the first and second embodiments will be described. FIG. 5 is a schematic circuit diagram of an ECU provided with a power supply circuit according to the third embodiment of the present invention. As shown in FIG. 5, the IC 20 provided in the ECU 300 is provided with four terminals of an input terminal 21, a voltage terminal 22, and terminals 23 and 25.

  Outside the IC 20, a resistor R 12 and a transistor Tr 12 are connected in series between the power supply line 11 and the voltage terminal 22, and a phase compensation capacitor C 12 is connected between the terminal 23 and the ground 12. ing. A startup diode D2 and a current limiting resistor R26 are connected in series between the voltage terminal 22 and the terminal 25.

  The start-up diode D2 functions as a start-up for turning on the transistor Tr11 by forcibly inputting a voltage to the voltage terminal 22 to start the control amplifier 30 when the + B power source is connected to the ECU 300. . Therefore, the diode D <b> 2 is connected between the resistor R <b> 26 and the voltage terminal 22 so that the current flows in the voltage terminal 22.

  Further, a pnp transistor Tr31 (seventh transistor of the present invention) and a current limiting resistor R27 are connected between the power supply line 11 and the gate of the transistor Tr11. Specifically, the emitter of the transistor Tr31 is connected to the power supply line 11, and the collector of the transistor Tr31 is connected to the resistor R27. A voltage relaxation Zener diode D3 is connected between the gate of the transistor Tr31 and the resistor R26. The diode D3 is for relaxing the voltage applied to the terminal 25 of the IC 20. Each component outside the IC 20 is constituted by, for example, discrete parts.

  Further, inside the IC 20, the current sense circuit 34 shown in the first embodiment is provided. In the present embodiment, the current flowing through the resistor R24 is Ir0, and the potential C at the junction C between the transistor Tr25 and the transistor Tr24 is input to the gate of the transistor Tr23 that operates as a sink function. In the present embodiment, a current sink circuit 32 is configured by the transistor Tr23 and the ground 28, as in the second embodiment.

  The reference voltage of the reference voltage source 31 is input to the non-inverting input terminal of the control amplifier 30, and the potential A1 of the voltage dividing circuit 20 is input to the inverting input terminal of the control amplifier 30. The circuit configuration of the ECU 300 including the constant pressure circuit 10 according to the present embodiment has been described above.

  Next, an operation for suppressing the voltage fluctuation of the voltage terminal 22 in accordance with the operation state of the microcomputer 27 will be described with reference to FIGS.

  First, the case where the microcomputer 27 shifts from the wake-up mode to the sleep mode will be described. FIG. 6 shows the potential of the voltage terminal 22 (upper stage), the output potential p1 (middle stage) of the control amplifier 30, and the current Is (lower stage) flowing through the transistor Tr21 when the microcomputer 27 enters the sleep mode from the wakeup mode. It is a figure.

  When the microcomputer 27 is in the wake-up mode, the potential A1 of the voltage dividing circuit 29 is set to be higher than the reference voltage of the reference voltage source 31. Therefore, when the potential A1 is input to the control amplifier 30, the control amplifier 30 Outputs HI. Then, the transistors Tr21 and Tr24 are turned ON, and a current Is flows from the + B power source to the transistor Tr24 via the power supply line 11, the transistor Tr31, the diode D3, and the resistor R26.

  As a result, the current Is flows through the transistor Tr24 by the current mirror circuit 35 of the current sense circuit 34. On the other hand, the current Ir0 flows to the transistor Tr25 by the current mirror circuit 36, but the current Is flows to the transistor Tr24, so that the current is discharged from the connection point C, and LOW is output as the potential C from the connection point C. . Therefore, the transistor Tr23 is OFF and the sink function is stopped.

  Further, since the transistors Tr21 and Tr31 are turned on, the transistor Tr11 is also turned on, the current Isp flows through the transistor Tr11, and the current is supplied to the voltage terminal 22. Thereby, the voltage drop of the voltage terminal 22 is suppressed by operating the microcomputer 27.

  Then, as shown in the upper part of FIG. 6, when the microcomputer 27 shifts from the wake-up mode to the sleep mode, the microcomputer 27 stops operating, and thus the voltage at the voltage terminal 22 starts to rise as described above. As the voltage at the voltage terminal 22 rises in this way, the potential A1 of the voltage dividing circuit 29 rises, so that the output potential p1 of the control amplifier 30 starts to drop as shown in the middle stage of FIG.

  When the output voltage p1 starts to decrease in this way, the gate voltage of the transistor Tr21 starts to decrease, and as shown in the lower part of FIG. 6, the current Is flowing between the drain and source of the transistor Tr21 decreases rapidly. Then, the transistor Tr21 is turned off. At this time, the output voltage p1 of the control amplifier 30 that is balanced with the gate voltage B of the transistor Tr21 decreases as the current Is decreases, as shown in the middle stage of FIG. 6, and the gate voltage B when the transistor Tr21 is turned off. Equilibrate to α ′.

  As the transistor Tr21 is turned off, the transistor Tr11 is also turned off, the current Isp stops flowing, and no current is input to the voltage terminal 22. At the moment when the transistor Tr11 is turned off, in the current sense circuit 34, the current Ir0 flows to the transistor Tr25 by the current mirror circuit 36, and the current Is does not flow to the transistor Tr24 by the current mirror circuit 35. Therefore, since the current Ir0 flows into the connection point C and the voltage rises, the HI voltage C is output from the current sense circuit 34 as shown in the middle stage of FIG.

  Since the voltage C indicating HI output from the current sense circuit 34 is input to the transistor Tr23, the transistor Tr23 is turned on, and the transistor Tr23 performs a sink operation. In this way, the injection current I0 that has lost its place due to the microcomputer 27 entering the sleep mode can be released to the ground 28.

  As described above, in the present embodiment, the transistor Tr23 can be turned on by the current sense circuit 34 at the moment when the current Is flowing through the transistor Tr21 stops flowing. Therefore, the transistor Tr23 is sinked in a shorter time than the above embodiments. It can be operated.

  Next, a case where the fluctuation of the potential of the voltage terminal 22 when the microcomputer 27 shifts from the sleep mode to the wake-up mode will be described. In this case, the operation is the reverse of the above.

  FIG. 7 shows the potential of the voltage terminal 22 (upper stage), the output potential of the control amplifier 30 (middle stage), and the current Is (lower stage) flowing through the transistor Tr21 when the microcomputer 27 enters the wake-up mode from the sleep mode. FIG.

  As described above, when the microcomputer 27 is in the sleep mode, as described above, the transistor Tr23 is turned on and is in a sink operation state. Then, as shown in the upper part of FIG. 7, when the microcomputer 27 shifts to the wake-up mode, the injection current I0 is consumed by the microcomputer 27 even though the transistor Tr23 is performing the sink operation, The potential at the terminal 22 begins to drop.

  As a result, the potential A1 of the voltage dividing circuit 29 decreases, so that the output potential p1 of the control amplifier 30 begins to increase as shown in the middle stage of FIG. As a result, the gate voltage of the transistor Tr21 begins to rise, and as shown in the lower part of FIG. 7, the current Is flowing between the drain and source of the transistor Tr21 increases rapidly, and the transistor Tr21 is turned on. At this time, the output voltage p1 of the control amplifier 30 that has been balanced with the gate voltage B-α ′ of the transistor Tr21 that has been turned off increases as the current Is increases, as shown in the middle stage of FIG. The gate voltage B when the Tr21 is turned on is balanced.

  As the transistor Tr21 is turned on, the transistor Tr11 is also turned on, the current Isp flows through the transistor Tr11, and the current is input to the voltage terminal 22. Further, at the moment when the transistor Tr11 is turned on, in the current sense circuit 34, the current Is flows through the transistor Tr24 by the current mirror circuit 35. Since the current Is is larger than the current Ir0, the current Ir0 is discharged from the connection point C, and the voltage C at the connection point C decreases. For this reason, as shown in the middle stage of FIG. 7, a LOW voltage C is output from the current sense circuit 34.

  The transistor Tr23 is turned on by the voltage C indicating LOW output from the current sense circuit 34, and the sink operation of the transistor Tr23 is stopped. In this way, it is possible to prevent the potential of the voltage terminal 22 from dropping due to the injection current I0 being consumed by the microcomputer 27 due to the microcomputer 27 entering the wake-up mode.

  As described above, in the present embodiment, Is = 0 can be fixed as the voltage rise condition of the voltage terminal 22, and the current Irmax shown in each of the above embodiments is compared with the comparison current Ir0 flowing through the transistors Tr25 and Tr26. Therefore, it is not necessary to set a margin in consideration of variations in the large current Ir (lifting condition Is = Ir).

  For this reason, since the voltage rise at the voltage terminal 22 and the timing of the transition of the transistor Tr23 to the sink operation can be performed simultaneously, the transition to the sink operation can be made more sensitive, and the response delay of the sink operation can be further reduced. That is, the sink operation of the transistor Tr23 can be stopped when the current Is flows through the transistor Tr21, and the transistor Tr23 can be operated when the current Is stops flowing. In this way, the power supply overshoot and ripple phenomenon of the voltage terminal 22 can be reduced.

(Other embodiments)
The power supply circuit shown in each of the above embodiments is not limited to the ECUs 100 to 300, and can be employed in a system in which the specified voltage fluctuates according to the power consumption of the load.

  Moreover, you may implement what combined said each embodiment.

It is a schematic circuit diagram of ECU provided with the power supply circuit which concerns on 1st Embodiment of this invention. (A) is a diagram showing the voltage terminal potential (upper stage) and the output of the control amplifier (lower stage) when the microcomputer enters the sleep mode from the wake-up mode, and (b) shows the output operation of the control amplifier according to the output operation It is the figure which showed the electric current Is which flows between the drain-source of the transistor which changes. (A) is a diagram showing the voltage terminal potential (upper stage) and the control amplifier output potential (lower stage) when the microcomputer enters the wake-up mode from the sleep mode, and (b) shows the output operation of the control amplifier. It is the figure which showed the electric current Is which flows between the drain-source of the transistor Tr which changes according to it. It is a schematic circuit diagram of ECU provided with the power supply circuit which concerns on 2nd Embodiment of this invention. It is a schematic circuit diagram of ECU provided with the power supply circuit which concerns on 3rd Embodiment of this invention. It is the figure which each showed the electric potential of the voltage terminal (upper stage), the output potential p1 (middle stage), and the current Is (lower stage) of the control amplifier when the microcomputer enters the sleep mode from the wakeup mode. It is the figure which showed the electric potential of the voltage terminal (upper stage), the output potential (middle stage) of the control amplifier, and the current Is (lower stage) when the microcomputer enters the wake-up mode from the sleep mode. It is a schematic circuit diagram of a conventional ECU provided with a power supply circuit for inputting a specified voltage to a microcomputer. (A) is a diagram showing an output operation of the control amplifier when the microcomputer enters the sleep mode from the wakeup mode, and (b) is an output of the control amplifier when the microcomputer returns from the sleep mode to the wakeup mode. It is the figure which showed operation | movement.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Constant pressure circuit 11, 26 ... Power supply line, 20 ... IC, 27 ... Load (microcomputer), 29 ... Voltage dividing circuit, 32 ... Current sink circuit, 34, 37 ... Current sense circuit.

Claims (8)

A specified voltage set based on the input voltage input to the first power supply line (11) is generated at the voltage terminal (22), and the second power supply line (26) connected to the voltage terminal (22) is provided. The specified voltage is input to the load (27) via
When a voltage input to the voltage terminal (22) exceeds the specified voltage according to a change in current consumption of the load, a current is supplied to the voltage terminal (22) via the first power supply line (11). Assuming that the flow path is an input path, the voltage terminal (22) is stopped from rising by preventing current from flowing into the voltage terminal (22) via the input path, and the voltage terminal (22). A constant pressure circuit (10) for stopping a decrease in the potential of the voltage terminal (22) by allowing a current to flow into the voltage terminal (22) via the input path when the voltage of the voltage terminal is lower than the specified voltage. In the provided power supply circuit,
In the constant pressure circuit,
A current sense circuit (34, 37) for directly detecting whether or not a current flows into the voltage terminal (22) via the input path by a current flowing through the input path and outputting the detection result as a sense signal; ,
Of the current flowing into the second power supply line (26) in response to the sense signal input from the current sense circuit (34), an excessive current flowing into the second power supply line in accordance with the consumption current of the load A current sink circuit (32) that performs a sink operation to flow into the ground (28).
When a current flows through the input path, the current sense circuit (34) detects that a current flows through the input path and outputs the detection result as a sense signal to the current sink circuit (32). The sink circuit (32) does not perform the sink operation according to the input sense signal,
When no current flows in the input path, the current sense circuit (34) detects that no current flows in the input path, and outputs the detection result to the current sink circuit (32) as a sense signal, The current sink circuit (32) is adapted to perform the sink operation according to the input sense signal .
A first transistor (Tr11) is connected to the input path, and when the first transistor (Tr11) is turned on, a current flows through the input path, and the first power line (11) and the ground (28). The second transistor (Tr21) is connected to the detection path formed between the current sensing circuit and the current sensing circuit (34) when the second transistor (Tr21) is turned on. Current flows through the output path for outputting the sense signal to
The input path so that the first transistor (Tr11) is turned off when the second transistor (Tr21) is turned on, and the first transistor (Tr11) is turned on when the second transistor (Tr21) is turned off. The detection path is configured for
The current sense circuit (34, 37) includes a first current mirror circuit (35) configured by using the second transistor (Tr21), and the first transistor (Tr11) is turned OFF or ON. Thus, whether the current flows in the input path is detected by using the current flowing in the detection path and the first current mirror circuit (35) by turning on or off the second transistor (Tr21). power supply circuit, characterized in that it it. The current sense circuit (34) includes a path connecting the first resistor (R24) and the third transistor (Tr26), and a fourth transistor (Tr25) connected in pairs with the third transistor (Tr26). ) And a first current mirror circuit (35) constituted by a fifth transistor (Tr24) connected in pairs with the second transistor (Tr21). And the current flowing through the first resistor (R24) is caused to flow through the fourth transistor (Tr25) by the second current mirror circuit (36).
If the connection point between the fifth transistor (Tr24) and the fourth transistor (Tr25) is C,
When no current flows through the second transistor (Tr21), no current flows through the fifth transistor (Tr24) by the first current mirror circuit (35), and the fourth transistor (Tr25) is connected to the connection point C. A current flowing through the first resistor (R24) flows in and the potential at the connection point C increases, and the increased potential is output as a sense signal.
When a current flows through the second transistor (Tr21), a current flows through the fifth transistor (Tr24) by the first current mirror circuit (35), and a current flows from the connection point C to the fifth transistor (Tr24). 2. The power supply circuit according to claim 1 , wherein the power supply circuit is configured to output the lowered potential as a sense signal while flowing out and decreasing the potential at the connection point C. The power supply circuit according to claim 2 , wherein the current flowing through the first resistor (R24) is set so as to be a maximum value of variation in the current flowing through the output path. The current sink circuit (32)
A sixth transistor (Tr23) connected between the second power line (26) and the ground (28) to form a flow path;
A comparator (33) that compares the comparison voltage (A2) according to the rise or fall of the voltage of the voltage terminal with a sense signal input from the current sense circuit and outputs the result; When the sense signal is larger than the comparison voltage, the device (33) outputs LOW to the gate electrode of the sixth transistor (Tr23), turns off the sixth transistor (Tr23), and disconnects the flow path. Then, the sink operation of the sixth transistor (Tr23) is stopped, and when the sense signal is smaller than the comparison voltage, HI is output to the gate electrode of the sixth transistor (Tr23), and the sixth transistor (Tr23) ) Is turned on, and a sink operation is performed in which a current flows to the ground (28) via the flow path. The power supply circuit according to claim 2 or 3 . A seventh transistor (Tr31) is connected between the first power supply line (11) and the second transistor (Tr21) on the detection path, and the seventh transistor (Tr31) is connected to the first transistor. (Tr11) is provided on the detection path so as to be turned on when the transistor is turned on and turned off when the first transistor (Tr11) is turned off.
The current sink circuit (32) includes a sixth transistor (Tr23) connected between the second power supply line (26) and the ground (28) to form a flow path, and the sixth transistor (Tr23). ) Is connected to the connection point C,
When the sixth transistor (Tr23) is turned on in response to a sense signal output from the connection point C, a current flows from the second power supply line (26) to the ground (28) via the flow-in path. 3. The sink operation according to claim 2 , wherein when the sink operation is performed and turned off according to the sense signal output from the connection point C, the sink operation is stopped by cutting the flow path. Power supply circuit. The current sense circuit (37) includes a path connected to the second resistor (R25) and the eighth transistor (Tr30), and a ninth transistor (Tr29) connected in pairs with the eighth transistor (Tr30). And a fourth current formed by a tenth transistor (Tr28) connected in a pair with a transistor (Tr27) connected to the fifth transistor (Tr24). A mirror circuit (38),
The current flowing through the second resistor (R25) flows to the tenth transistor (Tr28) by the third current mirror circuit (39), and the current flowing through the second transistor (Tr21) flows to the first current mirror circuit (35). ) And the fourth current mirror circuit (38) to flow to the tenth transistor (Tr28),
When the connection point between the tenth transistor (Tr28) and the ninth transistor (Tr29) is D,
When no current flows through the second transistor (Tr21), no current flows through the tenth transistor (Tr28) by the first current mirror circuit (35) and the fourth current mirror circuit (38). When a current flowing through the resistor (R25) flows to the tenth transistor (Tr28) via the third current mirror circuit (39), a current flows out from the connection point D, and the potential at the connection point D decreases. , Output the lowered potential as a sense signal,
When a current flows through the second transistor (Tr21), a current flows through the tenth transistor (Tr28) by the first current mirror circuit (35) and the fourth current mirror circuit (38), and the current flows through the connection point D. a power supply circuit according to claim 1, the potential at the node D flows current increases, characterized in that it is an increased potential to output as the sense signal. The power supply circuit according to claim 6 , wherein the current flowing through the second resistor (R25) is set to have a maximum value of variation in the current flowing through the output path. The current sink circuit (32) includes a sixth transistor (Tr23) connected between the second power supply line (26) and the ground (28) to form a flow path,
A gate electrode of the sixth transistor (Tr23) is connected to the connection point D;
When the sixth transistor (Tr23) is turned on in response to a sense signal output from the connection point D, a current flows from the second power supply line (26) to the ground (28) via the flow-in path. It performs sync operation, when the OFF in response to the sense signal output from the connection point D, that is adapted to stop the sink operation by cutting the pouring path in claim 6 or 7, characterized in The power supply circuit described.

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