JP4625368B2 - Optical signal processing circuit - Google Patents

Description

  The present invention relates to an optical signal processing circuit, and more specifically, serial-parallel conversion for converting an asynchronous burst serial optical signal into a plurality of electrical signals, parallel-serial conversion for converting parallel electrical signals into serial optical signals, The present invention also relates to an optical signal processing circuit that performs optical label conversion processing in optical packet communication.

  In recent years, with the explosive increase in data communication represented by the Internet, there has been an increasing demand for high-speed optical signals. Conventionally, an optical signal is converted into an electric signal by a light receiving element and processed by an electronic circuit in the state of the electric signal. However, it has become a problem to process an optical signal having a bit rate of 10 Gbps or more by an electronic circuit in the state of an electric signal. For example, in optical packet communication, a network device such as a router has a function of decoding the address information contained in the label of the optical packet to determine an output port, in order to avoid collision between optical packets, A buffer memory function that delays by an arbitrary time is required. Conventionally, since the label recognition function and the memory function are configured by a silicon LSI, the operation speed is limited to 1 Gbps or less. Therefore, it is difficult to realize a label recognition function and a memory function for a high-speed optical packet signal of 10 Gbps or more in a silicon-based electronic circuit.

  Thus, high-speed optical packet signals are converted into a plurality of low-speed electric signals (electrical serial-parallel conversion) and processed by a silicon-based electronic circuit. In this method, an optical signal is converted into an electric signal by an O / E (optical / electrical) receiving circuit including a light receiving element, and the electric signal is processed by an InP or GaAs high-speed electronic circuit. The high-speed electronic circuit extracts a clock signal from the converted electric signal by an electric clock signal generator, and converts the converted electric signal into a plurality of low-speed electric signals using the electric clock signal. The electric signal subjected to the electric serial-parallel conversion is subjected to a label recognition function or the like by a silicon-based electronic circuit.

  However, this method is considered to have a limit of a bit rate of about 40 Gbps because the generation of the electric clock signal and the electric serial-parallel conversion all depend on the electronic circuit. In addition, the electric serial-parallel conversion sequentially divides the converted electric signal at a half speed (for example, 40 GHz → 20 GHz →... → several 100 MHz), and thus requires a large number of stages of frequency dividing circuits. As the number of stages of the frequency divider increases, clock extraction and phase control in each stage must be performed with high accuracy. Furthermore, the high-speed electronic circuit has a problem that the power consumption is very large as compared with a silicon-based electronic circuit.

  A conventional clock extraction circuit locks an oscillation frequency of a VCO (Voltage Control Oscillator) by controlling feedback by a PLL (Phase Locked Loop). Therefore, a clock cannot be instantaneously extracted from an optical packet signal input in an asynchronous burst.

  On the other hand, with respect to electrical serial-parallel conversion, several studies have been conducted on a method of performing serial-parallel conversion with an optical signal. As one of the methods, a method is known in which a high-speed optical signal is branched into a plurality of signals, and each high-speed optical signal is converted into a low-speed optical signal using an optical-optical switch. For example, when an optical signal of 100 Gbps is converted into 10 optical signals of 10 Gbps, 10 optical-optical switches are used. As other optical serial-parallel conversion methods, a method using a plurality of surface-emitting second harmonic generation, a method using an excitonic giant nonlinear effect, a method using a hologram, and the like are known.

  However, the conventional optical serial-parallel conversion method has a problem that the apparatus scale is large and the power consumption is large because the optical-optical switch is used by the number of branches. The conventional method using surface-emitting second-order harmonic generation has a problem that it is extremely inefficient and has a very large loss because it uses a non-resonant optical nonlinear effect. Further, the conventional method using the exciton giant nonlinear effect has a problem that the nonlinear medium needs to be cooled to the liquid helium temperature in order to obtain a large nonlinear effect. Furthermore, since the conventional method using a hologram uses the diffraction effect, there is a problem that the loss is extremely large. Therefore, all of the conventional optical serial-parallel conversion methods require a running cost, are inefficient, and have a problem that it is very difficult to maintain stable performance over a long period of time.

  In order to solve the above-described problems, an ultrafast surface-type optical-optical switch using a low-temperature grown Be-doped strained InGaAs / InAlAs multiple quantum well has been developed, and an all-optical serial-parallel converter has been realized (for example, Non-Patent Document 1). However, the all-optical serial-parallel converter has a drawback in that it is expensive because it requires a high-speed planar waveguide circuit and a high-density light-receiving element array. In order to realize a label recognition function using a CMOS processor which is a silicon-based electronic circuit, together with an all-optical serial-parallel converter, an output interface for converting a parallel electric signal into a serial optical signal Since a parallel-serial converter is separately required, it is difficult to reduce the size of the entire system.

R. Takahashi et al., “1-Tb / s 16-b All-Optical Serial-to-Parallel Conversion Using a Surface-Reflection Optical Switch”, IEEE Photonics Tech. Lett., Vol.15, no.2, p .287-289, 2003 T. Nakahara et al., “Time-Domain 16-bit Label Swapping and Self-Routing of 40-Gb / s Burst Optical Packets”, IEEE Photonics Tech. Lett., Vol.16, no.9, p, 2153- 2155, 2004 K. Takahata et al., “3.3ps electrical pulse generation from a discharge-based metal-semiconductor-metal based”, Electronics Lett., Vol.41, no.1, p.38-40, 2005

  As described above, in order to process an asynchronous high-speed optical packet signal using a silicon-based electronic circuit, a serial-parallel converter and a parallel-serial converter are required as an input / output interface. Hereinafter, a specific example will be described using a label exchanger.

  FIG. 1 shows a configuration of a conventional label exchanger. In the label exchanger 10, an all-optical serial-parallel converter 12, a PD array 13, a CMOS processing circuit 14, and an electro-optical parallel-serial converter 15 are connected in cascade. The single optical pulse generator 11 is capable of receiving asynchronous burst packets, and is connected to the all-optical serial-parallel converter 12 and the electro-optical parallel-serial converter 15, respectively. A trigger pulse is supplied (see, for example, Non-Patent Document 2).

  Part of the input N-bit optical label signal L is input to the single optical pulse generator 11 and converted into a single optical pulse that is accurately synchronized with the optical label signal. The optical label signal L is spatially separated in parallel in the all-optical serial-parallel converter 12 using a single optical pulse as a control pulse. Each separated bit is converted into a low-speed electric signal by the PD array 13 and then sent to the CMOS processing circuit 14. The CMOS circuit extracts the address information of the input label L, replaces it with a new label L ′, and outputs it to the electro-optical parallel-serial converter 15 as a parallel electric signal. The parallel electric signal is output again as an optical label signal L ′ by the electric-optical parallel-serial converter 15.

  According to this configuration, since the label recognition function is executed by the CMOS processing circuit without using a high-speed electronic circuit, the speed is extremely high and the power consumption is low. However, since optical technology is introduced as an input / output interface, it is necessary to mount an all-optical serial-parallel converter and an electro-optical parallel-serial converter, which means that the circuit scale is large and the cost is high. There was a problem.

  SUMMARY OF THE INVENTION A first object of the present invention is to provide a serial-parallel converter and a parallel-serial converter that can cope with asynchronous high-speed optical packet signals, are small in size and low in cost, and have low power consumption. .

  In addition, the second object of the present invention is to enable bidirectional operation of serial-parallel conversion (SPC) and parallel-serial conversion (PSC) with a single element, so that optical signal processing such as an optical label switch is performed. An object of the present invention is to provide an optical signal processing circuit capable of reducing the size and cost of the entire system.

In order to achieve the above object, according to the present invention, an optical signal processing circuit according to claim 1 includes a transmission line for propagating an N-bit input serial electric signal input from the outside, and a parallel transmission line. The N-bit output serial electrical signal is input to the transmission line, sampled and held, or output to the outside via the transmission line. And N photo-trigger type transistor circuits that output different one-bit electric signals constituting the signal to the transmission line, each photo-trigger type transistor circuit comprising: (a) a drain terminal on the transmission line a transistor but which is connected connected, a hold capacitor connected to the source terminal of (b) the transistor, (c) said transistor An MSM-PD connected to the gate terminal for outputting an electric pulse; and (d) a reset transistor connected to the source terminal of the transistor for charging the hold capacitor with the specific 1-bit electric signal; e) a buffer circuit connected to the source terminal of the transistor and outputting the charge of the hold capacitor as an electric signal; and (f) connected to an input of the MSM-PD and outputting the electric pulse from the MSM-PD. includes an input resistor and a charging capacitor for the transistor is in OFF, and said bias is applied to the charging capacitor a state where the charging capacitor is charged, the serial to the MSM-PD - parallel converter When use (for SPC) optical pulse Ru is irradiated, the electrical pulses from said MSM-PD Is output, the transistor is turned on , and one specific bit corresponding to the optical pulse for SPC out of the N-bit input serial electric signal input to the transmission line is transferred to the hold capacitor via the transistor. is sampled and held, is output from the buffer circuit as one of the electrical signals that constitute the output parallel electrical signals of N bits, wherein the transistor is in OFF, and the hold capacitor is charged by the reset transistor, and externally et input when N-bit input parallel electrical signals the optical trigger type on the electrical signal inputted to the input resistance of the transistor circuit thus the charging capacitor of the the state of being charged, parallel to the MSM-PD - serial converter When use (for PSC) optical pulse Ru is irradiated, Said transistor is turned ON is output by the electrical pulses from the MSM-PD, an electric signal of said particular one bit corresponding to an electrical signal inputted to the optical trigger type transistor circuit, via the transistor from said hold capacitor by outputting to the transmission line Te, wherein together with the input serial electric signal of N bits is input from the outside to the transmission line, in synchronization with the input serial electric signal of the N bits of the input serial electric signal of the N-bit When the N optical trigger transistor circuits are sequentially irradiated with the SPC optical pulse having a time difference corresponding to the bit interval, each bit of the N-bit input serial electrical signal is converted to the N optical pulses. respectively stored in the hold capacitor of the trigger type transistor circuit, the N-bit output parameter Output as Le electrical signal, with each bit of the input parallel electrical signals of the N bits are input to each of the N optical trigger type transistor circuit, the time difference corresponding to the bit interval of the input serial electric signal of the N-bit When the N optical trigger transistor circuits are sequentially irradiated with the optical pulses for PSC provided with the PSC, a specific 1-bit electric signal input to each optical trigger transistor circuit is transmitted from the hold capacitor to the The N-bit output serial electric signal having the same information as the N- bit input parallel electric signal is output to the transmission line and output to the transmission line.

2. An optical label switching circuit using the optical signal processing circuit according to claim 1 , wherein an N-bit optical signal is input, and a single SPC trigger light pulse and a predetermined delay with respect to the SPC trigger light pulse are provided. A single optical pulse generator for generating a single PSC trigger light pulse given time, and the SPC trigger light pulse and the PSC trigger light pulse supplied from the single optical pulse generator, Light that is branched into N optical pulses, and is output as N optical pulses for SPC and N optical pulses for PSC by giving each optical pulse a time difference corresponding to the bit interval of the optical signal. a branch delay circuit receives the optical signal of the N bits, into serial electric signal of N bits, the PD for output to the transmission line, the charge of each of the hold capacitor N For as Tsu bets output parallel electrical signals, from new and CMOS processing circuit for supplying to each said charging capacitor as an input parallel electrical signals of N bits, said single PSC for triggering light pulse, said N-bit of the optical multiplexing circuit for generating an optical pulse train of N bits corresponding to the bit interval of the optical signal, said by each bit of the serial electric signal of the N bits propagated through the transmission line, the N output from the optical multiplexing circuit characterized in that it further comprises an optical modulator that modulates bits for each bit of the optical pulse train, respectively.

  As described above, according to the present invention, parallel conversion of a high-speed optical signal and serial conversion of a parallel electric signal can be performed with an extremely simple configuration in which N optical trigger transistor circuits including MSM-PD are integrated. It can be realized by one optical signal processing circuit.

  In addition, according to the present invention, by applying the optical signal processing circuit to a label switch in optical packet communication, the input / output interface with the CMOS processing circuit is integrated into one. Cost reduction is possible.

  Furthermore, according to the present invention, most of the transistor circuit is designed by a high impedance circuit, so that the power consumption can be extremely reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 2 shows a configuration of a label exchanger according to an embodiment of the present invention. The label exchanger 20 performs serial-parallel conversion on the optical label signal L input via the PD 21 and transmits it as a parallel electric signal to the CMOS processing circuit 23, and the new label L ′ converted in the CMOS processing circuit 23 is transmitted. An OCTA (Optically Clocked Transistor Array) 22 that performs parallel-serial conversion and outputs the result to the optical modulator 24 is provided. That is, the OCTA 22 can perform serial-parallel conversion and parallel-serial conversion bidirectional operations. The single optical pulse generator 25 can receive asynchronous burst packets, and is connected to the OCTA 22 via the optical branching delay circuit 26 and connected to the optical modulator 24 via the optical multiplexing circuit 27. An SPC trigger pulse and a PSC trigger pulse are supplied.

  FIG. 3 shows an SPC operation in OCTA according to an embodiment of the present invention. In the OCTA 22, a plurality of optical trigger transistor circuits 31 a to 31 c are arranged on the transmission line 32. The optical trigger transistor circuit 31 a includes a high-speed photoelectric converter 33 including an input resistor 34 having a high resistance value, a charging capacitor 35, and an MSM-PD (Metal-Semiconductor-Metal PD) 36. The output of the MSM-PD 36 is connected to the gate terminal of a transistor 37 for capturing an input signal via resistors 38 and 39 for adjusting the output bias. A drain terminal of the transistor 37 is connected to the transmission line 32, and a hold capacitor 40 for charging an input signal and a reset transistor 41 for resetting the charge of the capacitor are connected to the source terminal. Further, a buffer circuit 42 is connected to the source terminal of the transistor 37 in order to extract the voltage of the hold capacitor 40 to the outside.

  The SPC operation in OCTA 22 will be described. The input N-bit optical label signal L is converted into an electric signal in the PD 21 and then input to a transmission line 32 in which N optical trigger transistor circuits 31 are attached in parallel. In each photo-trigger type transistor circuit 31, when the MSM-PD 36 is irradiated with a light pulse, the electric pulse generated by the MSM-PD 36 is input to the gate terminal of the transistor 37, turning on the transistor 37. At this time, one specific bit of the N bits of the serial electric signal propagating on the transmission line 32 is charged to the hold capacitor 40 via the transistor 37. Similarly, the N optical trigger transistor circuits 31 sample-hold each bit of the serial electrical signal, thereby performing a parallel conversion of the serially input electrical signal.

The operation of the MSM-PD 36 will be described in detail. First, the bias voltage V _MSM of the MSM-PD 36 is set to “High”, and the charging capacitor 35 is charged. Thereafter, when the MSM-PD 36 is irradiated with a light pulse, the charge of the charging capacitor 35 is discharged at a high speed, so that an electric pulse is generated. When a direct current voltage is applied to one electrode of the MSM-PD 36 to irradiate a light pulse, the hole mobility is extremely slow, so that the electrical pulse rises sharply, but a tail that is very slow occurs at the fall. Therefore, by inserting a large input resistor 34 and a charging capacitor 35 on the bias side, an extremely high-speed electric pulse can be generated without being affected by slow holes (for example, see Non-Patent Document 3). ). In the experiments so far, the response of the MSM-PD 36 is about 100 ps only by applying a DC voltage, but it can be increased to 3.3 ps by inserting the input resistor 34 and the charging capacitor 35. It has been confirmed.

Next, the sample hold of the input electric signal will be described in detail. By setting the output bias V _trans by the resistors 38 and 39 so that the transistor 37 is turned off in a state where the MSM-PD 36 is not irradiated with an optical pulse, an electric pulse is generated from the MSM-PD 36. The transistor 37 is turned on only for a certain time. At this time, an electrical signal propagating on the transmission line 32 is charged in the hold capacitor 40. V _{rst of the} reset transistor 41 is set to a negative voltage value so that the charged charge does not leak. An optical pulse in which a time difference corresponding to the bit interval of the input signal is provided to the MSM-PD 36 of the N optical trigger transistor circuits 31 (output from the single optical pulse generator 25 as will be described later with reference to FIG. 5). The SPC trigger pulse is branched by the optical branch delay circuit 26.) By sequentially irradiating, each bit of the N-bit input electric signal is stored in the hold capacitor 40 of the respective optical trigger transistor circuit 31. .

  The charge charged in the hold capacitor 40 is output to the CMOS processing circuit 23 through the buffer circuit 42. In this manner, a high-speed sample-and-hold operation, that is, an SPC operation can be realized by a very simple and low power consumption circuit.

  The parallel-converted electrical signal is taken into the CMOS processing circuit 23 and stored as data in a RAM (Random Access Memory), or processing such as extraction of label address information is performed. The CMOS processing circuit 23 reads the stored data, exchanges labels, and outputs a new label to the OCTA 22 as an N-bit parallel electric signal.

FIG. 4 shows a PSC operation in OCTA according to an embodiment of the present invention. First, V _rst is set to “High” and the hold capacitor 40 is charged. Each of the N-bit parallel electric signals output from the CMOS processing circuit 23 is input as a bias signal of the MSM-PD 36 of the respective light trigger type transistor circuit 31. At this time, when the MSM-PD 36 is irradiated with a light pulse, if the input data is “1”, an electric pulse is generated, the transistor 37 is turned on, and the charge charged in the hold capacitor 40 is discharged. The discharged charge is output on the transmission line 22 as an electric pulse. When the input data is “0”, no electric pulse is generated, so that the transistor 37 remains OFF.

  Accordingly, when N MSM-PDs 36 are irradiated one after another with a certain time difference, a serial electric pulse train having the same information as the parallel electric signal input from the CMOS processing circuit 23 is output on the transmission line 22 and PSC. Operation can be realized. If the optical modulator 24 is driven by the output N-bit serial electric signal to modulate the N-bit optical pulse train, a serial-converted optical signal can be obtained.

  Note that a PIN type light receiving element exists as means for generating a high-speed electric pulse for opening and closing a transistor. However, even if the bias voltage is “0”, PIN-PD is not suitable for PSC operation because an electrical pulse is output when irradiated with a light pulse. In the present embodiment, a charge / discharge type MSM-PD biased by electric charge is used instead of the conventional MSM-PD biased by a DC voltage, so that an extremely high speed operation is possible. In addition, MSM-PD is easy to manufacture and can realize cost reduction.

  With reference to FIG. 5, the operation | movement which reads an old optical label in the label exchanger concerning one Embodiment of this invention is demonstrated. The configuration of the label exchanger shown in FIG. 2 and the SPC operation shown in FIG. 3 will be described together. The input optical label signal L is branched, and one is converted into an electrical signal by the PD 21 and sent onto the transmission line 32 of the OCTA 22. The other is converted into a single light pulse by a single light pulse generator 25.

  The single optical pulse generator 25 supplies an SPC trigger pulse and a PSC trigger pulse. After the delay time T is given, the PSC trigger pulse is combined with the SPC trigger pulse. The SPC trigger pulse and the PSC trigger pulse are branched into N optical pulses in the optical branch delay circuit 26. The optical branch delay circuit 26 gives a delay of an integer multiple of the bit interval τ of the input optical label signal to each of the N SPC trigger pulses ((n−1) τ, n = 1 to N), Supply to OCTA22.

The bias voltage V _MSM of the MSM-PD 36 of the OCTA 22 is set to “High”, the charging capacitor 35 is charged, and the V _{rst of the} reset transistor 41 is set to a negative voltage value. At this time, when the SPC optical trigger pulse is irradiated to the MSM-PD 36, the electric signal sent to the transmission line 32 is sampled and held one bit at a time by the transistor 37 of the optical trigger transistor circuit 31, and the hold capacitor 40 is charged. The charge charged in the hold capacitor 40 is output to the CMOS processing circuit 23 through the buffer circuit 42, and the old optical label of the input optical label signal L is read.

With reference to FIG. 6, the operation | movement which outputs a new optical label in the label exchanger concerning one Embodiment of this invention is demonstrated. The CMOS processing circuit 23 recognizes the address of the old optical label within time T, calculates a new label, and outputs it again as a parallel electric signal. The parallel electric signal is output as a bias signal of each MSM-PD 36 of the optical trigger transistor circuit 31. The gate terminal voltage V _rst of the reset transistor 41 is set to “High”, and the hold capacitor 40 is charged.

  As described above, the PSC trigger pulse is branched into N optical pulses in the optical branch delay circuit 26 after the delay time T is given. Each of the N PSC trigger pulses is given a delay that is an integral multiple of the bit interval τ of the input optical label signal ((n−1) τ, n = 1 to N). When the optical trigger pulse for PSC is irradiated to each MSM-PD 36, the electrical signal output from the CMOS processing circuit 23 is converted into a serial electrical signal having the same bit rate as the input optical label signal, and transmitted to the OCTA 22 It is sent onto the track 32.

  The PSC optical trigger pulse output from the single optical pulse generator 25 is converted into an N-bit optical pulse train by the 1: N optical multiplexing circuit 26. In the electroabsorption type or Mach-Zehnder type optical modulator 24, the N-bit optical pulse train is modulated by the electrical signal output from the OCTA 22, and the optical label signal L 'is output as a new optical label.

  According to this embodiment, the OCTA 22 in which N transistor gate arrays are integrated on the transmission line 22 is extremely small, and most of the circuit is designed with high impedance. In addition, bidirectional conversion operations such as serial-parallel conversion and parallel-serial conversion are possible. Therefore, the power consumption is extremely small, and the cost of the entire system can be reduced.

It is a block diagram which shows the structure of the conventional label exchanger. It is a block diagram which shows the structure of the label exchanger concerning one Embodiment of this invention. It is a figure for demonstrating the SPC operation | movement in OCTA concerning one Embodiment of this invention. It is a figure for demonstrating the PSC operation | movement in OCTA concerning one Embodiment of this invention. It is a figure for demonstrating the operation | movement which reads an old optical label in the label exchanger concerning one Embodiment of this invention. It is a figure for demonstrating the operation | movement which outputs a new optical label in the label exchanger concerning one Embodiment of this invention.

Explanation of symbols

20 Label changer 21 PD
22 OCTA
23 CMOS processing circuit 24 Optical modulator 25 Single optical pulse generator 26 Optical branch delay circuit 27 Optical multiplexing circuit 31 Optical trigger type transistor circuit 32 Transmission line 33 High-speed photoelectric converter 34 Input resistance 35 Charging capacitor 36 MSM-PD
37 Transistor 38, 39 Resistance 40 Hold capacitor 41 Reset transistor 42 Buffer circuit

Claims (2)

A transmission line for propagating an N-bit input serial electrical signal input from the outside;
N bits connected to the transmission line in parallel and input from the transmission line and sample and hold specific one bit different from the N-bit input serial electrical signal, or output to the outside through the transmission line. N photo-trigger type transistor circuits for outputting different one-bit electric signals constituting the output serial electric signal of bits to the transmission line,
Each photo-trigger transistor circuit
(A) a transistor having a drain terminal connected to the transmission line and connected;
(B) a hold capacitor connected to the source terminal of the transistor ;
(C) MSM-PD connected to the gate terminal of the transistor and outputting an electric pulse;
(D) a reset transistor connected to the source terminal of the transistor for charging the hold capacitor with the specific 1-bit electrical signal;
(E) a buffer circuit connected to the source terminal of the transistor and outputting the charge of the hold capacitor as an electrical signal;
(F) connected to an input of the MSM-PD, and includes an input resistor and a charging capacitor for outputting the electric pulse from the MSM-PD ;
The transistor is in OFF, and the state where the bias is applied to the charging capacitor the charging capacitor is charged, the serial to the MSM-PD - for parallel conversion (for SPC) when the light pulse is Ru is irradiated the transistor is turned oN is the electrical pulses output from the MSM-PD, one specific bit corresponding to the SPC light pulse of the input serial electric signal of the N bits inputted to the transmission line, Sampled and held by the hold capacitor through the transistor, and output from the buffer circuit as one of the electric signals constituting an N-bit output parallel electric signal ,
Electricity said transistor is in OFF, and the reset transistor the hold capacitor is charged by and inputted to the input resistance of the optical trigger type transistor circuit of the externally et the entered N bits of the input parallel electrical signals when the state signal therefore said charging capacitor is charged, the on MSM-PD parallel - the serial conversion (for PSC) optical pulse Ru is irradiated, is the electrical pulses output from the MSM-PD wherein transistor is turned oN, an electric signal of said particular one bit corresponding to an electrical signal inputted to the optical trigger type transistor circuit, by outputting to the transmission line from the hold capacitor through the transistor,
SPC input serial electric signal of the N bits is input from the outside to the transmission line, and a time difference corresponding to the bit interval of the input serial electric signal of the N bits in synchronization with the input serial electric signal of the N-bit When the N optical trigger transistor circuits are sequentially irradiated with the optical pulse for use, each bit of the N-bit input serial electric signal is respectively applied to the hold capacitors of the N optical trigger transistor circuits. stored, and outputs as an output a parallel electric signal of the N bits,
Each bit of the N- bit input parallel electrical signal is input to each of the N optical trigger transistor circuits, and a PSC optical pulse having a time difference corresponding to the bit interval of the N-bit input serial electrical signal When the N light trigger transistor circuits are sequentially irradiated, a specific 1-bit electric signal input to each light trigger transistor circuit is output from the hold capacitor to the transmission line, and An optical signal processing circuit, wherein the N-bit output serial electrical signal having the same information as the N- bit input parallel electrical signal is output to the transmission line. An optical label switching circuit using the optical signal processing circuit according to claim 1 ,
Single optical pulse generation for inputting an N-bit optical signal and generating a single SPC trigger optical pulse and a single PSC trigger optical pulse given a predetermined delay time to the SPC trigger optical pulse And
The SPC trigger optical pulse and the PSC trigger optical pulse supplied from the single optical pulse generator are each branched into N optical pulses, and each optical pulse corresponds to the bit interval of the optical signal. An optical branch delay circuit that gives a time difference and outputs N optical pulses for SPC and N optical pulses for PSC;
PD for inputting the N-bit optical signal, converting it to an N-bit serial electric signal, and outputting it to the transmission line;
A CMOS processing circuit that processes the charge of each of the hold capacitors as an N- bit output parallel electrical signal and supplies it as an N- bit input parallel electrical signal to each of the charging capacitors;
An optical multiplexing circuit that generates an N-bit optical pulse train corresponding to a bit interval of the N-bit optical signal from the single PSC trigger optical pulse;
Wherein the respective bits of the serial electric signal of the N bits of the transmission line and propagated, further comprising an optical modulator that modulates each bit of the optical pulse train of the N-bit output from the optical multiplexing circuit, respectively Optical label exchange circuit.

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