JP5922277B1 - Series / parallel converter - Google Patents

Abstract

A level difference between a high level and a low level of a converted signal obtained by converting an electric pulse is enhanced. In a transistor T1, one of a drain terminal and a source terminal is connected to a transmission line TL1, and a gate pulse is input to a gate terminal. The capacitor C1 has one terminal connected to the other of the drain terminal and the source terminal of the transistor T1, and the other terminal grounded. In the register R1, one terminal is connected to the other of the drain terminal and the source terminal of the transistor T1, and the DC voltage Vchrg is supplied to the other terminal. A gate pulse is input in synchronization with the electric pulse propagating through the transmission line TL1, and a voltage corresponding to high and low of the electric pulse is held in the capacitor C1. [Selection] Figure 1

Description

  The present invention relates to a serial / parallel converter that outputs a conversion signal of an NRZ (Non Return to Zero) type output waveform based on the concept of charge transfer.

  High-speed electric pulses are serial / parallel converted by holding the corresponding voltage levels for a predetermined time and converting them into electric signals. This makes it possible to interface the high-speed electric pulse with an electric circuit that operates at a low speed, for example, a circuit that could not directly process such a high-speed electric pulse without conversion.

  The execution of signal processing by a low-speed circuit is very excellent in terms of energy efficiency, and serial / parallel conversion is an important factor for promoting energy-efficient operation. Furthermore, when the pulse width of the high-speed electric pulse is very narrow, it is very difficult to find a reliable means for directly processing this, and therefore serial / parallel conversion is indispensable.

In this regard, the inventors of the present application are particularly interested in interface connection between, for example, a bit of a high-speed burst mode optical packet of 25 Gbps or more and a low-speed CMOS circuit with high energy efficiency. Such processing is called packet buffering, and is the basis for enabling optical packet switching (OPS).
Packet buffering is strongly demanded for other reasons, and is used to resolve conflicts between colliding optical packets. It is also used to provide networking functions.
In addition, packet buffering includes packets that belong to a specific OPS domain and use a specific modulation format and transmission rules, and other communication domains that employ transmission rules and formats such as OPS / Ethernet conversion. It is also essential for the interface connection.

  In a common approach, an optical packet is converted into an electrical signal (electric pulse) by an ultrafast photodetector that supports burst mode operation, that is, operation can begin as soon as the optical packet arrives. The electrical pulses output from the photodetector are typically coupled to a serial / parallel converter via a transmission line so that sufficient bandwidth is available for transmission of the received high speed signal.

  FIG. 19 shows a basic configuration of the serial / parallel converter. As shown in the figure, an output (electric pulse) from the photodetector is propagated along a transmission line TL including N serial / parallel conversion channels CH01 to CHN. Each channel CH01-CHN is used sequentially in time to convert N consecutive bits (electrical pulses) propagated along the transmission line TL, and each channel CH01-CHN is used for every N + 1 bits. By repeatedly using it, all bits included in the optical packet can be converted. The output from each channel CH01-CHN is interfaced to the subsequent low speed circuit of interest.

(Demand for efficient methods to perform serial / parallel conversion using NRZ output waveforms)
Several schemes have already been proposed for performing serial / parallel conversion of high-speed electrical pulses. However, with conventional techniques, the waveform resulting from the converted bits does not directly take a non-return to zero (NRZ) pattern.
In the case of an output having an NRZ type waveform, the same voltage level is maintained as a result of the serial / parallel conversion until the serial / parallel conversion is completed and the next conversion is performed. There is an important technical significance that maintaining the same signal level for a long time means reducing the frequency component. Such an NRZ type waveform is a signal in which the speed or frequency component is minimized, and is an optimal pattern for directly coupling the converted bit and the subsequent low-speed circuit.

One technique for generating an output (converted signal) with an NRZ-type waveform is to install a comparator at the output of a serial / parallel converter that outputs a return-to-zero (RZ) type output signal. By changing the threshold value of the comparator, the time of the generated pulse can be adjusted.
However, in practice, the serial / parallel converter is constituted not only by a single conversion channel but also by a number of conversion channels. Therefore, if an off-chip comparator that operates at a relatively high speed of about 1 Gbps, for example, is installed in each conversion channel, the energy consumption of the entire module is clearly increased.
In contrast, by integrating an on-chip comparator in each conversion channel, the threshold for each conversion channel should be provided independently using a separate set of bias sources. However, this is hardly feasible when considering a large number of conversion channels.

Salah Ibrahim, Hiroshi Ishikawa, Tatsushi Nakahara, and Ryo Takahashi, "A novel optoelectronic serial-to-parallel converter for 25-Gbps burst-mode optical packets" OPTICS EXPRESS, 2013, Vol.22, No.1, p157-165

(Conventional sample-and-hold scheme for performing serial / parallel conversion)
Sample and hold (S & H) schemes are often used to perform serial / parallel conversion of fast electrical pulses. The basic configuration of the S & H scheme is shown in FIG. In the case of a high-speed electric pulse flow that is propagated along the transmission line TL1 and takes into account a specific electric pulse for conversion, it is fundamental to obtain a charge in the capacitor C1 that varies according to the voltage level of the specific electric pulse. Become a concept. This is performed by turning on the normally-off transistor T1 that connects the capacitor C1 and the transmission line TL1 for a short time in the presence of the pulse.

When the voltage level of the high-speed electrical pulse is high, the transistor terminal connected to the transmission line TL1 functions as the drain terminal d, the transistor terminal connected to the capacitor C1 functions as the source terminal s, and current flows from the drain to the source. Flows toward the capacitor C1.
On the other hand, when the voltage level of the high-speed electrical pulse is low, the transistor terminal connected to the transmission line TL1 functions as the source terminal s, and the transistor terminal connected to the capacitor C1 functions as the drain terminal d and exists in the capacitor C1. The electric charge to be discharged is discharged to the transmission line TL1.

  The distinction between sampled high and low level electrical pulses is made more effective by increasing the pure charge difference at capacitor C1. However, the problem is that the charge generated by this processing scheme is inherently limited.

An equivalent circuit relating to the charging process is shown in FIG. In the figure, RTL1 is the characteristic impedance of the transmission circuit TL1, RT1 is the resistance of the transistor T1, and VTL1 is the voltage of the transmission line.
Here, a part of the electric pulse is dispersed in the characteristic impedance RTL1 of the transmission line TL1, and thus the amount of charge generated by the capacitor C1 is limited. Furthermore, since the transistor T1 connecting the transmission line TL1 and the capacitor C1 is opened only for a part of the pulse, and is not affected by the preceding pulse or the subsequent pulse, the charge inflow time becomes shorter as the pulse time decreases. Become. In other words, the charge generated by the S & H scheme is reduced when the line speed is high.

The present invention provides a serial / parallel converter capable of achieving the following objects in view of the above-described conventional technology.
(1) To realize an efficient method for performing serial / parallel conversion for high-speed electric pulses in burst mode.
(2) Ensure that the signal generated by serial / parallel conversion takes an NRZ pattern.
(3) To realize a serial / parallel conversion circuit that can directly drive a low-speed circuit with a load resistor.

The conversion channel of the serial / parallel converter of the first invention of the present application that solves the above problems is as follows.
A transistor in which one of a drain terminal and a source terminal is connected to a transmission line through which a series of electric pulses propagates, and a gate pulse synchronized with the electric pulse is input to the gate terminal;
A conversion signal charging capacitor having one terminal connected to the other of the drain terminal or the source terminal of the transistor and the other terminal grounded;
A resistor having one terminal connected to the other of the drain terminal or the source terminal of the transistor and a DC voltage supplied to the other terminal;
An amplification / uniformization circuit that amplifies and equalizes the voltage of the conversion signal charging capacitor and outputs it as a conversion signal;
It is characterized by having.

Conversion channel serial / parallel converter of the present Application the second invention also,
A first transistor in which one of a drain terminal and a source terminal is connected to a transmission line through which a series of electric pulses propagates, and a gate pulse synchronized with the electric pulse is input to the gate terminal;
A charge securing capacitor in which one terminal is connected to the other of the drain terminal or the source terminal of the first transistor and the other terminal is grounded;
A resistor having one terminal connected to the other of the drain terminal or the source terminal of the first transistor and a DC voltage supplied to the other terminal;
A second transistor in which one of a drain terminal or a source terminal is connected to the other of the drain terminal or the source terminal of the first transistor, and a gate pulse synchronized with the electric pulse is input to the gate terminal;
A conversion signal charging capacitor having one terminal connected to the other of the drain terminal or the source terminal of the second transistor and the other terminal grounded;
It is characterized by having.

Conversion channel serial / parallel converter of the present Application the third invention also
The second invention of the present application is characterized by comprising an electric amplifier inserted between the charge securing capacitor and the second transistor.

The conversion channel of the serial / parallel converter of the fourth invention of the present application is:
The second or third aspect of the present invention is characterized in that it has an amplification / uniformization circuit that amplifies and equalizes the voltage of the conversion signal charging capacitor and outputs it as a converted signal.
Conversion channel serial / parallel converter of the present patent application the fifth invention also
In any one of the first to fourth inventions of the present application, a trigger circuit for generating the gate pulse is provided.

Conversion channel serial / parallel converter of the present Application sixth invention also
5th invention of this application WHEREIN: The said trigger circuit has MSM-PD which produces | generates an electrical trigger pulse, if the optical trigger pulse synchronized with the said serial electrical pulse is input,
The electrical trigger pulse output from the MSM-PD is the gate pulse.

The serial / parallel converter of the present Application seventh invention,
A plurality of conversion channels according to any one of the first to sixth inventions of the present application are connected to the transmission line in parallel.

The serial / parallel converter of the present Application eighth invention,
A conversion channel according to any one of the first to sixth inventions connected to the first transmission line;
A conversion channel according to any one of the first to sixth inventions connected to the second transmission line;
A trigger circuit for commonly sending a gate pulse to the conversion channel connected to the first transmission line and the conversion channel connected to the second transmission line;
It is characterized by having.

  According to the present invention, a high-speed electric pulse propagating through a transmission line can be serial / parallel converted to obtain a converted signal having an NRZ output waveform.

The block diagram which shows the conversion channel of the serial / parallel converter which concerns on Example 1 of this invention. FIG. 3 is a circuit diagram illustrating an equivalent circuit of a conversion channel according to the first embodiment. The block diagram which shows the conversion channel of the serial / parallel converter which concerns on Example 2 of this invention. The operation state figure which shows the operation state of the conversion channel of Example 2. FIG. The block diagram which shows the conversion channel of the serial / parallel converter which concerns on Example 3 of this invention. The block diagram which shows the more concrete conversion channel of the serial / parallel converter which concerns on Example 3 of this invention. FIG. 6 is a waveform diagram showing a gate pulse applied to a first transistor in Example 3. In Example 3, the wave form diagram which shows the voltage of the 1st capacitor. In Example 3, it is a wave form diagram which shows the output of an inverter amplifier. In Example 3, it is a wave form diagram which shows the gate pulse applied to the 2nd transistor. In Example 3, the wave form diagram which shows the pulse formed with the 2nd capacitor. The block diagram which shows the conversion channel of the serial / parallel converter which concerns on Example 4 of this invention. The block diagram which shows a DB-MSMPD trigger circuit. The block diagram which shows the conversion channel of the serial / parallel converter which concerns on Example 4 of this invention. The block diagram which shows the more concrete conversion channel of the serial / parallel converter which concerns on Example 4 of this invention. The block diagram which shows the more concrete conversion channel of the serial / parallel converter which concerns on Example 4 of this invention. The block diagram which models and shows a field programmable gate array. The block diagram which shows the conversion channel of the serial / parallel converter which concerns on Example 5 of this invention. FIG. 10 is a waveform diagram illustrating converted bits (converted signals) in the fifth embodiment. FIG. 10 is a waveform diagram illustrating converted bits (converted signals) in the fifth embodiment. FIG. 10 is a waveform diagram illustrating converted bits (converted signals) in the fifth embodiment. The block diagram which shows the conversion channel of the serial / parallel converter which concerns on Example 6 of this invention. The block diagram which shows the serial / parallel converter which concerns on Example 7 of this invention. The block diagram which shows another serial / parallel converter which concerns on Example 7 of this invention. The block diagram which shows the basic composition of a serial / parallel converter. The block diagram which shows the basic composition of a sample hold scheme. The circuit diagram which shows the equivalent circuit of a sample hold scheme.

  Hereinafter, a serial / parallel converter according to the present invention and a conversion channel used for the serial / parallel converter will be described in detail based on examples.

[Example 1]
(Changed discharge or hold scheme to perform serial / parallel conversion)
The purpose of this scheme (Example 1: see FIG. 1) is to differentiate these differences so that the pure difference in charge between the high and low voltage levels of the fast electrical pulse at capacitor C1 can be more efficiently distinguished. It is to strengthen.

In this new scheme, it is ensured that the charge of the capacitor C1 is full before starting the conversion of the fast electrical pulse, the basic concept is to discharge the charge from the capacitor C1 to the transmission line TL1, or That is, the charge is held in the capacitor C1 without discharging the charge.
Hereinafter, this scheme is called a discharge or hold (D-or-H) scheme, and the circuit used is shown in FIG. In the example of FIG. 1, the capacitor C1 functions as a conversion signal charging capacitor.

FIG. 1 shows one conversion channel of the serial / parallel converter according to the first embodiment. In this example, one terminal of the transistor T1 is attached to the transmission line TL1, and one terminal of the capacitor C1 and one terminal of the resistor R1 are attached to the other terminal of the transistor T1. The other terminal of the capacitor C1 is grounded, and the DC voltage Vchrg is supplied to the other terminal of the resistor R1.
The time constant (R1 · C1) specified by the capacitance of the capacitor C1 and the resistance value of the resistor R1 is selected between the capacitor C1 and a sufficient time after the bit conversion is completed and before the next bit conversion is performed. The capacitance of the capacitor C1 and the resistance value of the resistor R1 are set so as to ensure that the charge is completely recharged.

  Normally, transistor T1 is turned off by having a gate terminal g to which a DC low voltage is supplied, and upon arrival of the fast electrical pulse, a short gate pulse is added to the DC voltage already present at the gate terminal g. . Here, the transistor terminal connected to the transmission line TL1 functions as the source terminal s, and the other terminal connected to the RC circuit functions as the drain terminal d. Whether to turn on the transistor T1 is determined by the voltage difference Vgs between the gate terminal and the source terminal.

When the level of the high-speed electric pulse propagating through the transmission line TL1 is low, the voltage of the gate pulse is sufficiently higher than the voltage of the transmission line TL1 so that the transistor T1 is turned on and the charge of the capacitor C1 is discharged to the transmission line TL1. Should be high.
On the other hand, when the level of the high-speed electrical pulse propagating through the transmission line TL1 is high, the gate pulse is not sufficient to turn on the transistor T1, and the charge of the capacitor C1 does not change. That is, because the charge is retained, this scheme is eligible as a discharge or retention scheme.

  An equivalent circuit for the discharge process is shown in FIG. Here, the resistance value of the resistor R1 is selected to be sufficiently higher than the characteristic impedance (1/2) RTL1 of the transmission line TL1. When the electrical pulse propagating through the transmission line TL1 is at a low level, discharging of the capacitor C1 is started when the transistor T1 is turned on, and at the same time, a charging current is supplied from the resistor R1 to the capacitor C1. However, since the resistance of the resistor R1 is selected to be high, the charging current flowing through the resistor R1 is kept low. That is, the value is very low until a clear voltage drop occurs in the capacitor C1. Therefore, by appropriately selecting the resistance value of the resistor R1 and forcibly turning on the transistor T1 at the same time, it is possible to sufficiently discharge the capacitor C1. The upper limit of the resistance value of the resistor R1 is set so that the charge of the capacitor C1 is recovered before the next bit conversion is performed by sufficiently suppressing the value with respect to the time constants R1 and C1.

  Compared to the S & H scheme, the D-or-H scheme can effectively increase the pure difference in charge in the capacitor (conversion signal charging capacitor) C1. This is because the capacitor C1 is efficiently discharged to a low resistance or held unchanged. In addition, by appropriately increasing the DC voltage value Vchrg, the voltage difference Vds between the drain and source terminals of the transistor T1 is sufficient regardless of fluctuations that may occur for electrical pulses at low voltage levels. Can be large. For this reason, a sufficient current flow is always ensured for a low voltage level electrical pulse in the transmission line TL1 and within a short on-time of the transistor T1. Such a feature enables an efficient serial / parallel conversion operation even at a high line speed.

[Example 2]
(Concept of charge transfer to perform serial / parallel conversion using NRZ waveform)
The purpose of this circuit (Example 2: see FIG. 3) is to perform serial / parallel conversion from high-speed electrical pulses to electrical signals using corresponding voltage levels and NRZ type waveforms. When performing serial / parallel conversion, based on the level of the bit to be converted (fast electrical pulse), the circuit output voltage will be high or low, taking into account the conversion of the bit stream divided equally in time, By holding an output corresponding to a specific bit that is not changed until the next bit conversion, an NRZ waveform is generated.

  To enable serial / parallel conversion using NRZ-type output waveforms, the D-or-H scheme and the controlled charge transfer between the two capacitors C1, C2 that are normally disconnected are: Propose an operating mechanism. These capacitors C1, C2 are temporarily connected only at the moment of bit conversion, and when disconnected again, the state of one capacitor C2 has already changed according to the level of the converted bit.

  The basic circuit configuration of the new operation mechanism is shown in FIG. In FIG. 3, the capacitor C2 functions as a conversion signal charging capacitor, and the capacitor C1 functions as a charge securing capacitor.

The basic circuit of the second embodiment (see FIG. 3) is the same as that of the D-or-H scheme shown in FIG. 1, except that a capacitor C2 attached via a normally-off transistor T2 is added.
That is, in one conversion channel of the serial / parallel converter according to the second embodiment, one terminal of the transistor T1 is attached to the transmission line TL1, and one terminal of the capacitor C1 and one terminal of the resistor R1 are connected to the transistor. It is attached to the other terminal of T1. Furthermore, one terminal of the capacitor C2 is attached to the other terminal of the transistor T1 via the transistor T2. That is, one terminal of the transistor T2 is connected to the other terminal of the transistor T1, and the other terminal of the transistor T2 is connected to one terminal of the capacitor C2.
The other terminals of the capacitors C1 and C2 are grounded, and the DC voltage Vchrg is supplied to the other terminal of the resistor R1.

Capacitor C1 is necessary to secure a sufficient amount of charge before the start of bit (high-speed electrical pulse) conversion. When the bit reaches transmission line TL1, the gate terminals of both transistor T1 and transistor T2 are connected. At the same time, a short gate pulse is applied in addition to the existing DC bias that keeps both transistors normally off.
The gate pulse applied to the gate terminal of transistor T2 must be sufficient to turn on the terminal, and the gate pulse applied to the gate terminal of transistor T1 is present at a low voltage level on transmission line TL1. In other words, the terminal can be turned on only when the voltage level of the bit is low.

  One of the following two operation scenarios is executed on the basis of the voltage level of the bit in the transmission line TL1. This operation scenario will be described with reference to FIGS. 4 (a) and 4 (b).

When the voltage level of the bit (high-speed electric pulse) is high, the transistor T1 is not turned on as shown in FIG. This is because the voltage difference Vgs between the gate and source terminals of the transistor T1 is smaller than the threshold voltage of the transistor T1. Therefore, the capacitor C1 remains disconnected from the transmission line TL1, and the existing charge is held.
However, at the same time, the transistor T2 is turned on by the gate pulse applied to the gate terminal of the transistor T2, and the capacitor C1 and the capacitor C2 are temporarily connected. The terminal of the transistor T2 connected to the capacitor C1 functions as the drain terminal d, the other terminal of the transistor T2 connected to the capacitor C2 functions as the source terminal s, and charges are sent from the capacitor C1 to the capacitor C2. When the application of the gate pulse to the gate terminal of the transistor T2 is completed, the two capacitors C1 and C2 return to the normal disconnected state, so that the charge sent to the capacitor C2 remains unchanged until the next bit conversion is performed. It is kept as it is.

On the other hand, when the voltage level of the bit (high-speed electric pulse) is low, the voltage difference Vgs between the gate and source terminals of the transistor T1 is the threshold voltage of the transistor T1, as shown in FIG. Since it becomes much larger, the transistor T1 is turned on. The terminal of the transistor T1 connected to the transmission line TL1 functions as the source terminal s, and the other terminal of the transistor T1 connected to the capacitor C1 functions as the drain terminal d.
At the same time, the transistor T2 is turned on by the gate pulse applied to the gate terminal of the transistor T2, and the capacitor C1 and the capacitor C2 are connected to each other. Therefore, the two capacitors C1 and C2 connect the available path to the transmission line TL1 via the transistor T1, where both capacitors C1 and C2 are discharged. When the application of the gate pulse to the gate terminal of the transistor T2 is completed, the two capacitors C1 and C2 return to a normal disconnection state, and the capacitor C2 has already been discharged, so there is no change until the next bit is converted The low voltage level is maintained.

Therefore, the following points can be emphasized as excellent operation for both operation scenarios determined by the voltage level of the converted bit.
(1) The state of the capacitor (conversion signal charge capacitor) C2 changes only according to the level of the converted bit. That is, the level of the voltage level that occurs as a result of the capacitor C2 changes based only on the voltage level of the converted bit.
(2) After the state of the capacitor C2 changes according to the converted bit, the state remains unchanged until the next conversion is performed. Therefore, the voltage level of the capacitor (conversion signal charging capacitor) C2 is used. To generate a non-zero return (NRZ) waveform.

[Example 3]
(Improved circuit configuration for serial / parallel conversion using NRZ waveform)
The purpose of this configuration (Embodiment 3: see FIG. 5) is to improve the difference in voltage level generated in the capacitor (converted signal charge capacitor) C2 for different levels of the converted bits.

  As shown in the basic configuration of FIG. 3, the transistor T2 is a transistor responsible for charge transfer between the two capacitors C1 and C2. When the converted bit is high, the drain terminal and the source terminal of the transistor T2 are terminals connected to the capacitor C1 and the capacitor C2, respectively. On the other hand, when the converted bit is low, the reverse is true, and the drain terminal and the source terminal of the transistor T2 are terminals connected to the capacitor C2 and the capacitor C1, respectively. In either case, the voltage difference Vds between the drain and source terminals of the transistor T2 must be large enough to allow sufficient current to flow during a short on-time.

From the viewpoint of charge transfer between the two capacitors C1 and C2, the optimum value of the DC voltage Vchrg is selected so that the difference in voltage level of the capacitor C2 is maximized. The need for such optimization can be explained as follows.
For example, when a large value is selected for the DC voltage Vchrg and a high-level bit is converted, the capacitor C2 is easily charged and the voltage level is increased. On the other hand, when a low-level bit is converted, it is not preferable to select a large value for the DC voltage Vchrg. The reason for this is that in order for the capacitor C2 to discharge sufficiently, the voltage of the capacitor C1 must also be lowered below a certain voltage level, and this low voltage level when the initial DC voltage Vchrg of the capacitor C1 is high. This is because it becomes more difficult to reach this level.

  Therefore, it should be noted that the new operating mechanism combines the two processes. In one process, the capacitors C1 and C2 are selectively discharged to the transmission line TL1 based on the voltage level of the converted bit. In the other process, charge transfer is performed between the two capacitors in both directions from the capacitor C1 to the capacitor C2 and from the capacitor C2 to the capacitor C1. Both processes are directly determined by the same parameter DC voltage Vchrg, making it more difficult to optimize each other.

  Therefore, in the improved circuit (Embodiment 3) shown in FIG. 5, an electric amplifier Am is inserted between the capacitor C1 and the transistor T2. Thereby, it is possible to generate a difference between the voltage level of the signal emitted to the transmission line TL1 and the voltage level of the signal that determines the charge transfer to the capacitor C2. Therefore, by making both the underlying processes independent, both processes can be optimized more efficiently.

  An implementation of the improved circuit is shown in FIG. Here, an inverter amplifier Ainv is used to increase the voltage difference at the inverter output. The inverter amplifier Ainv is configured by connecting a resistor Rinv1 and a transistor Tinv1 in series. One end of the capacitor C1 is connected to the gate terminal of the transistor Tinv1, and the connection point between the resistor Rinv1 and the transistor Tinv1 is connected to one end of the transistor T2.

  The measurement data in the circuit of FIG. 6 are shown in FIGS. 7A to 7E. Note that the measurement results correspond to performing serial / parallel conversion to a 25-Gbps signal at a ratio of 1:16. In addition, the ripple that may occur in the measurement is due to the influence of the measurement probe.

A series of electrical pulses are propagated along the transmission line TL1 and converted by applying the gate pulses shown in FIGS. 7A and 7D to the gate terminals of the transistors T1 and T2, respectively. Here, the pattern confirmed by the circuit takes the form [011011011011011 ...].
As shown in FIG. 7B, the voltage of the capacitor C1 decreases when the electric pulse is at a low level and is held when the electric pulse is at a high level. The output of the inverter amplifier Ainv is shown in FIG. 7C. Here, a large voltage difference between the low output and the high output is realized. FIG. 7E shows the NRZ waveform of the voltage at the capacitor C2. A small spike superimposed on the NRZ waveform is generated by a pulse supplied through the gate of the ultrafast transistor used and can be completely removed from the final output of the circuit, as will be shown later.

[Example 4]
(Exact time trigger provided by MSM-PD trigger circuit based on discharge)
The following requirements must be satisfied regarding the gate pulse to be applied to the gate terminals of the transistors T1 and T2 so that specific bit conversion can be performed. This will be described with reference to FIG. In the fourth embodiment shown in FIG. 8, the trigger circuit 10 generates a gate pulse synchronized with the converted high-speed electric pulse (bit), and inputs the gate pulse to the gate terminals of the transistors T1 and T2.
(1) The gate pulse should be accurately synchronized with the relevant bit in time.
(2) As for the gate pulse applied to the gate terminal of the transistor T1, maintaining a sufficient amplitude with a narrow pulse width is a main requirement for proper bit selection.
(3) It is not important to maintain a narrow pulse width for the gate pulse applied to the gate terminal of the transistor T2, but sufficient pulse amplitude is required to keep the transistor T2 always on. That is, it is necessary to have a sufficient voltage difference every time a pulse is applied.

  With respect to the initial requirements for time synchronization, the use of optoelectronic circuits that convert optical triggers into electrical triggers greatly improves control over time. This is because the electrical pulse is likely to disappear due to a long delay, whereas the delay of the optical pulse can be controlled very accurately.

  Among various methods, as a specific example of the trigger circuit 10, a circuit that converts a light trigger into an electric trigger using a metal semiconductor metal (MSM) photodetector is examined. Here, a discharge-based (DB) MSM-PD trigger circuit is configured to generate a narrow electrical pulse each time a light trigger pulse is applied. Such a circuit allows iterative processing in a short time, i.e. it can provide an appropriate electrical pulse each time it is triggered, even if the time is divided into less than 1 nanosecond.

A DB-MSMPD trigger circuit 11 shown in FIG. 9 includes an RC circuit composed of a resistor Rin to which a DC input voltage Vinput is input and a capacitor Cin, and an MSM-PD (Metal Semiconductor Metal) having one terminal connected to the RC circuit. Photo Detector) 11a and two parallel registers R _bias connected to the other terminal of MSM-PD 11a.
One of the two parallel resistors R _bias is grounded, and the other parallel resistor R _bias is connected to the bias voltage Vbias. Further, by keeping the bias voltage Vbias low, the controlled transistor T1 (or T2) is set to a normally-off mode.

By applying an optical trigger pulse P having sufficient energy to the MSM-PD 11a of the DB-MSMPD trigger circuit 11, sufficient carriers (carriers) are generated in the MSM-PD 11a, which functions as a low resistance capacitor. Charges can be stored _in C _in and discharged quickly with a resistor R _bias . Also, by selecting the time constant R _in C _in to be longer than R _bias C _in , the capacitor C _in can be used up _in a short time, and recharging takes a relatively long time, thus generating a narrow electrical pulse. The DB-MSMPD trigger circuit 11 can change the combination of design parameters to generate electric pulses with different conditions.

  In addition, by optimizing these parameters, electrical pulses can be generated repeatedly with sufficient amplitude and reasonably narrow pulse width without the need to fully recharge the capacitor Cin for circuit optimization. As shown in Non-Patent Document 1, a short time of 640-ps has already been demonstrated.

  Two separate DB-MSMPD trigger circuits can be used to drive transistor T1 and transistor T2 independently, but this requires two separate light pulses, which only occupy the circuit's own space It also means that energy consumption will increase.

As shown in FIG. 10, a single DB-MSM trigger circuit 11 can drive the transistors T1 and T2 simultaneously. Compared to driving the gate terminal of one transistor, the electric capacity of the gate applied to the trigger circuit is doubled, thereby affecting the shape of the electric trigger.
Note that in the example of FIG. 10, a capacitor C3 is inserted to facilitate charge transfer to the capacitor C2 by ensuring that sufficient stored charge corresponding to the voltage level generated by the inverter amplifier Ainv is available. . In addition, an amplifier A1 for amplifying the electrical trigger sent to the transistor T2 is provided.
Further, an amplification / uniformization circuit 20 is provided that amplifies and equalizes the voltage (NRZ type signal waveform) of the capacitor C2 and sends the amplified voltage to the low-speed device 30.
In the first to third embodiments, an amplification / uniformization circuit may be provided.

  The inverter amplifier Ainv is configured by connecting a resistor Rinv1 and a transistor Tinv1 in series. One end of the capacitor C1 is connected to the gate terminal of the transistor Tinv1, and the connection point between the resistor Rinv1 and the transistor Tinv1 is connected to one end of the transistor T2. The high voltage Vinv1_high for amplification is input to one end of the resistor Rinv1, and the low voltage Vinv1_low for amplification is input to the other end of the transistor Tinv1.

  FIG. 11 shows another method in which the transistor T1 and the transistor T2 are simultaneously driven by one MSM-PD trigger circuit. Here, a positive pulse generated at one terminal of the MSM-PD 11a is used to drive the gate of the transistor T1, and a negative pulse generated at the other terminal of the MSM-PD 11a is inverted by the amplifier A1. Amplified and used to drive the gate of transistor T2.

As a specific example of the amplifier A1 shown in FIG. 11, an inverter amplifier A2 as shown in FIG. 12 can be adopted. The inverter amplifier A2 includes a transistor T21, a resistor R22, and a resistor R23. A high voltage Vtrig_high for triggering is input to one end of the resistor R22, and a low voltage Vtrig_low for triggering is input to the other end of the transistor T21.
The trigger bias voltage Vtrig_bias is input to R23.
In FIG. 12, C10 represents a capacitor.

  Normally, the amplification process slightly increases the width of the generated electrical pulse, but maintaining a very narrow pulse width is not an important factor in driving the gate of transistor T2, so the sufficient voltage difference Vgs is reduced. It should be noted that the benefits of amplification that can be guaranteed without disadvantages are enormous. The gate pulses input to the gate terminals of the transistors T1 and T2 are shown in FIGS. 7A and 7D, respectively.

[Example 5]
(Amplification and equalization of circuit output)
The output generated as a result of performing serial / parallel conversion is characterized by the fact that the bit is much faster before the conversion is performed, so it is supplied to a low speed circuit that could not operate directly on the bit. Is intended. Therefore, it is necessary to supply the generated output to the subsequent low-speed circuit after the serial / parallel conversion is processed normally. The supply of the conversion result to the subsequent circuit can be divided into voltage level amplification and adjustment processes as shown in the amplification / uniformization circuit 20 of FIG. In other words, it can be rephrased as a necessary signal change so that an output signal can be provided in a form suitable for a subsequent low-speed circuit (low-speed device).

Here, in general, a specific CMOS circuit that is a field programmable gate array (FPGA) is specifically assumed as a low-speed circuit (low-speed device). Such a low speed circuit can be modeled as a load resistance. This load resistor is equipped with two terminals labeled as terminals “a” and “b”, as shown in FIG.
Based on the polarity of the terminals “a” and “b”, a high voltage or low voltage level can be detected by the CMOS circuit. For example, if the voltage of “a” exceeds the voltage of “b” having a certain voltage tolerance, a high signal is detected, and conversely, the voltage “b” has a certain voltage tolerance “a”. If the voltage is exceeded, a low signal is detected. In general, such two-terminal signaling is called LVDS signaling. The same effect can be obtained by changing only the voltage at one terminal and keeping the voltage at the other terminal fixed.

  As shown in FIG. 13B, the output of the serial / parallel conversion circuit 50 is used to drive the voltage “a” according to the level of the converted bit with the voltage “b” fixed. Is done. For high voltage level converted bits, the required tolerance will cause the voltage on “a” to rise above the voltage on “b”. On the other hand, for a converted bit at a low voltage level, the voltage of “a” is reduced below the voltage of “b” due to the required tolerance.

A specific circuit corresponding to this is shown in FIG.
The amplifying / uniformizing circuit 21 shown in FIG. 14 includes transistors T211, T212 and resistors R211, R212. The input high voltage Vinv2g_high is input to one end of the resistor R211, the input low voltage Vinv2_low is input to the other end of the transistor T211, and the output high voltage Vout_high is input to one end of the transistor T212. An output low voltage Vout_low is input to the other end of R212.
The amplification / uniformization circuit 21 amplifies and equalizes the voltage of the capacitor C2 so as to match the characteristics of the low-speed device 31, and sends the converted signal to the low-speed device 31.
In FIG. 14, 31 indicates a low-speed device, and C10 indicates a capacitor.

  Circuits similar to the amplification / uniformization circuit 21 of FIG. 14 are assembled, and circuit outputs measured for various combinations of converted bits (converted signals) are shown in FIGS. 15A to 15C. The circuit outputs shown in FIGS. 15A to 15C correspond to the voltage level of the capacitor C2 shown in FIG. 7E, and the spike already existing in the voltage of the capacitor C2 has an effect of not affecting the final circuit output.

[Example 6]
(Several conversion channels driven by the same light trigger)
In the sixth embodiment shown in FIG. 16, the conversion channel CH11 is connected to the transmission line TL1, and the conversion channel CH21 is connected to the transmission line TL2. The optical trigger pulse P is input to the MSMPD 11 a of the DB-MSMPD trigger circuit 11. When the optical trigger pulse P is input to the MSMPD 11a, an electric pulse (gate pulse) output from one end of the MSMPD 11a is input to the gate of the transistor T1 of the conversion channel CH11 and to the gate of the transistor T1 of the conversion channel CH21. Entered. At the same time, the electric pulse (gate pulse) output from the other end of the MSMPD 11a is input to the gate of the transistor T2 of the conversion channel CH11 via the capacitor C11 and the amplifier A1, and the gate of the transistor T2 of the conversion channel CH21. Is input.

  That is, in the sixth embodiment, two different conversion channels CH11 and CH21 share the same trigger circuit 11, and by applying one optical trigger pulse P to the shared MSM-PD 11a, the two conversion channels CH11, CH21 can be used to convert two synchronized bits propagated on separate transmission lines TL1, TL2.

[Example 7]
(Configuration of full series / parallel converter)
An example (Example 7) of the configuration of the serial / parallel converter is as shown in FIG. In the example of FIG. 17, the conversion channels having the configuration shown in FIG. 14 are adopted as the conversion channels C11, C12... C1N, and the optical trigger pulses P1, P2,.・ ・ PN is entered.
The plurality of conversion channels C11, C12... C1N are in parallel and are sequentially connected to the transmission line TL1.

A serial electric pulse propagates through the transmission line TL1. Between the optical trigger pulses P1, P2,... PN, a time difference corresponding to the bit interval of the electric pulse (serial electric pulse) propagating through the transmission line TL1 is sequentially set. Therefore, when the first electric pulse arrives at the conversion channel C11, the optical trigger pulse P1 is input to the MSMPD of the conversion channel C11, the conversion signal is output from the conversion channel C11, and the second electric pulse is converted. The optical trigger pulse P2 is input to the MSMPD of the conversion channel C12 when it arrives at the channel C12, the conversion signal is output from the conversion channel C12, and the optical trigger pulse when the Nth electric pulse arrives at the conversion channel C1N PN is input to MSMPD of conversion channel C1N, and a conversion signal is output from conversion channel C1N.
In this way, the converted signals from the respective conversion channels C11, C12... C1N become NRZ parallel (parallel) signals.

  Another example of the configuration of the serial / parallel converter is as shown in FIG. In the example of FIG. 18, the conversion channels having the configuration shown in FIG. 16 are adopted as the conversion channels C11, C21, C12, C22,..., C1N, C2N, and paired conversion channels C11, C21, C12 , C22,..., C1N, C2N are input with optical trigger pulses P1, P2,.

In the example shown in FIG. 18, the electric pulse (serial electric pulse) propagating through the transmission line TL1, the electric pulse (serial electric pulse) propagating through the transmission line TL2, and the optical trigger pulses P1, P2,. ing.
Therefore, the electrical pulses propagating through the transmission line TL1 are converted by the conversion channels C11, C12... C1N to obtain NRZ-format parallel signals, and the electric pulses propagating through the transmission line TL2 are converted into the respective conversion channels C21, Conversion by C22... C2N can obtain a parallel signal in NRZ format.

  The present invention can be applied to a serial / parallel converter that performs serial / parallel conversion on an electric pulse (serial signal) propagating through a transmission line and outputs a converted signal (parallel signal).

10 Trigger circuit 11 DB-MSMPD Trigger circuit 11a MSMPD
20, 21 Amplification and equalization circuit 30, 31 Low speed device 50 Series / parallel conversion circuit
TL, TL1, TL2 transmission line
C1, C2 capacitors
T1 transistor
R1 register
Am electric amplifier
Ainv inverter amplifier
A1 amplifier
A2 Inverter amplifier
P Optical trigger pulse

Claims (8)

A transistor in which one of a drain terminal and a source terminal is connected to a transmission line through which a series of electric pulses propagates, and a gate pulse synchronized with the electric pulse is input to the gate terminal;
A conversion signal charging capacitor having one terminal connected to the other of the drain terminal or the source terminal of the transistor and the other terminal grounded;
A resistor having one terminal connected to the other of the drain terminal or the source terminal of the transistor and a DC voltage supplied to the other terminal;
An amplification / uniformization circuit that amplifies and equalizes the voltage of the conversion signal charging capacitor and outputs it as a conversion signal;
A conversion channel of a serial / parallel converter characterized by comprising: A first transistor in which one of a drain terminal and a source terminal is connected to a transmission line through which a series of electric pulses propagates, and a gate pulse synchronized with the electric pulse is input to the gate terminal;
A charge securing capacitor in which one terminal is connected to the other of the drain terminal or the source terminal of the first transistor and the other terminal is grounded;
A resistor having one terminal connected to the other of the drain terminal or the source terminal of the first transistor and a DC voltage supplied to the other terminal;
A second transistor in which one of a drain terminal or a source terminal is connected to the other of the drain terminal or the source terminal of the first transistor, and a gate pulse synchronized with the electric pulse is input to the gate terminal;
A conversion signal charging capacitor having one terminal connected to the other of the drain terminal or the source terminal of the second transistor and the other terminal grounded;
A conversion channel of a serial / parallel converter characterized by comprising: In claim 2,
A conversion channel of a serial / parallel converter, comprising an electric amplifier inserted between the charge securing capacitor and the second transistor. In claim 2 or claim 3,
A conversion channel of a serial / parallel converter, comprising an amplification / uniformization circuit for amplifying and equalizing the voltage of the capacitor for charging the conversion signal and outputting it as a conversion signal. In any one of Claims 1-4 ,
A conversion channel of a serial / parallel converter, comprising a trigger circuit for generating the gate pulse. In claim 5 ,
The trigger circuit has an MSM-PD that generates an electrical trigger pulse when an optical trigger pulse synchronized with the serial electrical pulse is input;
A conversion channel of a serial / parallel converter, wherein the electrical trigger pulse output from the MSM-PD is the gate pulse.   A serial / parallel converter, wherein a plurality of conversion channels according to any one of claims 1 to 6 are connected in parallel to the transmission line. A conversion channel according to any one of claims 1 to 6 connected to a first transmission line;
A conversion channel according to any one of claims 1 to 6 connected to a second transmission line;
A trigger circuit for commonly sending a gate pulse to the conversion channel connected to the first transmission line and the conversion channel connected to the second transmission line;
A serial / parallel converter characterized by comprising:

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