JP5945027B1 - Pulse generation circuit - Google Patents

Abstract

An electric pulse having a narrower pulse width and a larger amplitude is generated while suppressing energy of an optical pulse. A pulse generation circuit (2) according to the present invention includes an optoelectronic circuit (11) for generating an electrical signal in response to an incident optical pulse, and a first main electrode connected to a first fixed potential (Vh). A first resistance (RL) connected between the first transistor (TR1) and the second main electrode of the first transistor and a second fixed potential (Vsrc1) lower than the first fixed potential; A second transistor (TR2) having an electrode connected to the second main electrode of the first transistor and a second main electrode connected to a third fixed potential (TR2) equal to or lower than the second fixed potential; and a drive circuit (20). The drive circuit is characterized in that, when an electrical signal is generated by the optoelectronic circuit, the first transistor is turned on and then the second transistor is turned on. [Selection] Figure 3

Description

  The present invention relates to a pulse generation circuit for generating a pulse for driving a transistor, for example, a high-speed electric pulse serial / parallel converter or a pulse for driving a transistor of a parallel / serial converter used in communication using an optical packet. The present invention relates to a pulse generation circuit that generates a signal using a photodetector.

  In recent years, data processing of ultra-high-speed bits is becoming an essential technology in a wide range of fields. In particular, in the field of optical communication, in order to cope with an increase in communication traffic, communication using optical packets with ultra-high-speed bits exceeding several tens of Gbit seconds is being adopted, and high-speed data processing corresponding to that is required. It has become to.

  However, in such ultra-high-speed bit data communication, although the most reliable means for performing data processing is still an electronic circuit, due to physical factors such as power consumption and power dissipation, The processing speed of electronic circuits is limited. For this reason, when the communication speed of data communication of ultra-high-speed bits exceeds the operation upper limit speed of the electronic circuit, it is necessary to match the data communication speed with the operation speed of the electronic circuit.

  Specifically, as shown in FIG. 10, after converting a high-speed optical signal into a serial electrical signal, the serial electrical signal is converted into a parallel electrical signal and input to an electronic circuit, and the electronic circuit It is necessary to convert the processed parallel electric signal into a serial electric signal and convert it into a high-speed optical signal again.

  More specifically, by performing 1-to-N serial / parallel conversion processing of ultra-high-speed bit data for each predetermined group, the time of each single bit in the group increases N times, and ultra-high-speed bits Is converted into data having a speed that can be processed by a low-speed electronic circuit in the subsequent stage. In addition, low-speed data is converted back to ultra-high-speed bit data by performing N-to-1 parallel / serial conversion processing on the data that has been processed by the electronic circuit. With these processes, data communication between the energy efficient low-speed electronic circuit and the ultrahigh-speed bit optical communication network can be performed for each bit.

  Here, as an example of a serial / parallel converter and a parallel / serial converter, a serial / parallel converter and a parallel / parallel converter used for optical communication by optical packet switching (OPS) that performs optical switching in units of packets. The serial converter will be described.

  First, an optical communication scheme based on optical packet switching will be briefly described. In optical communication based on optical packet switching, data (information) is transmitted in packet units (optical packets) composed of ultra high-speed bits. Optical packets are transmitted in a burst mode, and no signal is transmitted between two consecutive packets. The optical packet is equipped with a packet label (optical label) mainly composed of a group of bits in which the packet destination and the packet characteristics (packet level priority etc.) are defined. Each node of the optical packet switching network transfers the optical packet to the destination specified by the information in the packet label while holding the payload of the optical packet in the optical domain.

  In optical communication by optical packet switching, processing for updating the packet label of an optical packet is performed by an OPS label processor. Since this OPS label processor is constituted by an energy efficient electronic circuit, it is necessary to convert the packet label of the optical packet into low-speed bit data that can be processed by the OPS label processor and then input it to the OPS label processor. At that time, a serial / parallel converter is used. Further, the packet label updated by the OPS label processor is exchanged with a packet label before being processed, and is transmitted again as an optical packet. At that time, a parallel / serial converter is required.

  In optical communication using optical packet switching, a serial / parallel converter and a parallel / serial converter are also required for packet buffering. Note that packet buffering is performed, for example, to enable upper networking functions such as avoiding contention between competing optical packets, provisioning of packet reproducibility and quality of service (QoS), and packet multicasting. . In addition, packet buffering includes a packet belonging to a specific OPS domain having a specific modulation format and communication rule, and another communication domain based on a different communication rule and modulation format such as OPS / Ethernet (registered trademark) conversion. The role as an interface between them is also important.

These serial / parallel converters and parallel / serial converters are mainly used to realize energy-efficient processing, and therefore generally require low power consumption. For example, in optical communication using optical packet switching, the serial / parallel converter and the parallel / serial converter need to be configured to support burst mode operation in order to reduce power consumption and increase efficiency. That is, serial / parallel converters and parallel / serial converters used for optical communication are required to maintain a normally-off mode when no operation is required and to immediately switch to an operating state when a trigger is input. The
The configuration of the serial / parallel converter and the parallel / serial converter used for optical communication by optical packet switching will be described below.

FIG. 11 is a diagram showing a basic configuration of an optical communication system by optical packet switching using a serial / parallel converter.
In the optical communication system 900 shown in FIG. 11, the transmitted optical packet is converted into an electrical signal by an ultrahigh-speed photodetector (not shown) that supports burst mode operation. The electrical signal converted by the photodetector is output to a transmission line (communication line) TL0 configured to obtain a sufficient bandwidth for transmitting a high-speed signal. To the transmission line TL0, n (n is an integer of 2 or more) conversion channels CH1 to CHn of the serial / parallel converter 9 are connected in parallel, and an electric signal output from the photodetector to the transmission line TL0. Is input to each of the conversion channels CH1 to CHn. Each of the conversion channels CH1 to CHn operates continuously in time. As a result, N consecutive bits (data) propagating along the transmission line TL0 are sequentially taken into the conversion channels CH1 to CHn. By repeatedly taking in the data sequentially performed by the conversion channels CH1 to CHn for each (N + 1) bits, all bits (serial data) included in the optical packet can be converted into parallel data.

  The data for n channels converted by the conversion channels CH1 to CHn of the serial / parallel converter 9 is input to the low-speed electronic circuit 91 at the subsequent stage and buffered. The buffered data is input to an n-channel parallel / serial converter (not shown) for re-conversion into ultrafast optical packets. The n-channel parallel / serial converter operates each channel continuously in time, so that each buffered bit (parallel data) is sequentially output sequentially and converted into serial data. The Bits (data) output from each conversion channel of the parallel / serial converter are propagated along a shared transmission line (communication line), and an optical packet is regenerated.

  As shown in FIG. 11, each of the conversion channels CH1 to CHn of the serial / parallel converter 9 is a normally-off transistor (hereinafter referred to as “a”) connected between a common transmission line TL0 and a low-speed electronic circuit 91. Also referred to as “main transistor”.) TR0. The parallel / serial converter also has similar transistors. In the case of a serial / parallel converter, when the main transistor TR0 is turned on, bits to be converted are taken from data propagating through the common transmission line TL0 and input to the low-speed electronic circuit 91. In the case of the parallel / serial converter, when the main transistor is turned on, the data (bit) output from the low-speed electronic circuit 91 is released and output to the common transmission line.

  In optical communication by optical packet switching, the time for turning on the main transistor needs to be shorter than the time (pulse width) of one bit for both the serial / parallel converter and the parallel / serial converter. Therefore, it is necessary to supply an electric pulse having a sufficiently large amplitude with a short pulse width to the control electrode (gate) of the main transistor accurately synchronized with the timing at which the serial / parallel conversion process or the parallel / serial conversion process is performed. There is. Hereinafter, an electric pulse supplied to the gate electrode to drive the main transistor is referred to as a “gate pulse”.

  As shown in FIG. 11, the serial / parallel converter and the parallel / serial converter generate a gate pulse by a pulse generation circuit (hereinafter also referred to as “master gate circuit”) 90, and use the gate pulse as a main transistor. Supply.

  The master gate circuit 90 has an optoelectronic circuit (light trigger circuit) that converts a light trigger to an electrical trigger in order to generate a gate pulse that meets strict time synchronization requirements. Thereby, the precision of the timing which performs a conversion process can be improved significantly. This is due to the fact that electrical pulses tend to disappear with delay, whereas optical pulse delay can be controlled very accurately.

  A master gate circuit using such an optical trigger circuit is disclosed in Non-Patent Document 1 and Non-Patent Document 2, for example. Non-Patent Document 1 uses a photodetector having a metal-semiconductor-metal structure (hereinafter referred to as “MSM-PD”), and has an input resistance at one output terminal of the MSM-PD. An optical trigger circuit having a configuration in which a charge holding capacitor is connected is disclosed. Non-Patent Document 2 discloses a serial / parallel converter that drives a main transistor by a gate pulse generated by a master gate circuit including an optical trigger circuit disclosed in Non-Patent Document 1.

Here, the configuration and operation principle of the conventional master gate circuit disclosed in Non-Patent Document 2 will be described.
FIG. 12 is a diagram showing a configuration of a conventional master gate circuit.
In the master gate circuit 90 shown in the figure, the MSM-PD 91 has two terminals for outputting an electrical signal generated in response to the light detection signal. One terminal of the MSM-PD is connected to an RC circuit including an input resistor Rin and a capacitor Cin to which a DC input voltage Vinput is supplied, and the other terminal of the MSM-PD 91 is connected to a control terminal (gate) of the main transistor. In addition to being connected, it is connected to a node to which two resistors Rbias arranged between the bias voltage Vbias and the reference voltage (ground voltage) are connected. By keeping the bias voltage Vbias low, the transistor TR0 is set to a normally-off mode.

  The MSM-PD 91 has a planar structure that can be easily integrated with other circuit components. When an optical trigger pulse is incident on the MSM-PD 91, an electric pulse 92 having a narrow pulse width is generated from the MSM-PD 91, and the electric pulse 92 is output from the other terminal of the MSM-PD 91, and a gate pulse is applied to the gate of the main transistor TR0. Is entered as According to the master gate circuit 90, since it is possible to perform repeated processing in a short time, an appropriate gate pulse can be generated even when an optical trigger is output at a time interval of less than 1 nanosecond. it can.

  By irradiating the MSM-PD91 with a light trigger pulse having sufficient energy, the MSM-PD91 generates a sufficient carrier, which functions as a low resistance. As a result, electric charge can be accumulated in the capacitor Cin and discharged quickly via the resistor Rbias. Specifically, by setting a value longer than (Rbias × Cin) as the time constant (Rin × Cin), the capacitor Cin is discharged in a short time, and a relatively long time is required for recharging. Thereby, an electric pulse (gate pulse) 92 having a narrow pulse width can be generated, and an electric pulse having different conditions can be generated by adjusting a circuit constant (design parameter) in the master gate circuit 90. . Furthermore, by optimizing these design parameters, it is possible to repeatedly generate electrical pulses with sufficient amplitude and moderately narrow pulse width. Also, in this case, it is not necessary to fully recharge Cin for circuit optimization. For example, as shown in Non-Patent Document 2 described above, it has been demonstrated that the master gate circuit 90 can generate a gate pulse with a short time of 640 ps.

“3.3ps electrical pulse generation from a discharge-based metal-semiconductor-metal functions”, K. Takahara, R. Takahashi, T. Nakahara, H. Takenouchi and H. Suzuki, ELECTRONICS LETTERS 6th January 2005 Vol. 41 No. 1 . “A novel optoelectronic serial-to-parallel converter for 25-Gbps burst-mode optical packets”, Salah Ibrahim, Hiroshi Ishikawa, Tatsushi Nakahara, and Ryo Takahashi, OPTICS EXPRESS Vol.22, No. 1, 13th January 2014.

  According to the conventional master gate circuit 90, as shown in FIG. 12, an electric pulse 92 having a short rise time can be generated. However, the waveform at the time of falling of the electric pulse 92 is a relatively long tail-like waveform that starts at a high speed and then gradually decelerates, and it is difficult to say that the falling time of the electric pulse 92 is short.

  Therefore, conventionally, in order to realize a short on-time of the main transistor, the upper part (beneficial amplitude) 900 of the waveform of the electric pulse is used as the gate pulse of the main transistor, and the remaining part 901 of the waveform is removed. It was. Specifically, by adjusting the bias voltage Vbias, the DC level of the electric pulse 92 is adjusted so that the undesired portion 901 of the electric pulse 92 is lower than the threshold voltage of the main transistor, and a part of the electric pulse 92 is adjusted. Only was used as a gate pulse to drive the main transistor. Therefore, the conventional master gate circuit has a problem that the useful amplitude of the electric pulse generated in the MSM-PD 91 is limited.

  In order to increase the useful amplitude of the electrical pulse, it is necessary to increase the energy of the light trigger pulse. However, in the serial / parallel converter and the parallel / serial converter described above, it is necessary to make the optical trigger pulse incident on the MSM-PD of each conversion channel every time conversion processing is performed. As a result, the energy efficiency of the entire optical communication system is reduced.

  On the other hand, it is not easy to increase the useful amplitude of an electrical pulse that can be used as a gate pulse without increasing the energy of the light trigger pulse. This is because the amplitude of the optical trigger pulse applied to the MSM-PD and the pulse width of the electric pulse generated from the MSM-PD 91 are in a trade-off relationship. For example, by increasing the value of the bias resistor Rbias, the amplitude of the electrical pulse can be maintained while suppressing the amplitude of the optical trigger pulse and reducing the optical trigger energy, but at the same time the pulse width of the electrical pulse is reduced. There is a problem of growing. In this case, by adjusting the bias voltage Vbias and readjusting the DC level of the electric pulse, a portion having a small pulse width in the electric pulse can be used as a gate pulse. As the resistance Rbias increases, it slows down, reducing the useful amplitude of the electrical pulse that can be used as a gate pulse.

  As a method for increasing the useful amplitude of an electric pulse that can be used as a gate pulse without increasing the energy of the light trigger pulse, for example, increasing the reactivity of MSM-PD or another type having high reactivity. It is conceivable to employ a photo detector (PD). However, in order to realize these methods, a manufacturing process that is finally different from the new PD configuration is required, resulting in an increase in manufacturing cost. Even if the MSM-PD reactivity is improved and an integrated PD with high reactivity can be realized, the above-mentioned trade-off problem in the master gate circuit remains unresolved, and the electric pulse still remains. It remains the same that only a part can be used as a gate pulse.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an electric circuit having a narrow pulse width and a large amplitude while suppressing the energy of an optical pulse in a pulse generation circuit using a photodetector. It is to be able to generate pulses.

  The pulse generation circuit (1-4) according to the present invention includes an optoelectronic circuit (11) that generates an electric signal in response to an incident light pulse, and a first main electrode connected to a first fixed potential (Vh). A first transistor (TR1), a load resistor (RL) connected between the second main electrode of the first transistor and a second fixed potential (Vsrc1 = GND) lower than the first fixed potential; An electric signal is generated by the optoelectronic circuit with the second transistor (TR2) having an electrode connected to the first transistor second main electrode and the second main electrode connected to a third fixed potential (TR2) equal to or lower than the second fixed potential. If not, the first transistor and the second transistor are turned off, and when the electrical signal is generated by the optoelectronic circuit, the first transistor and the second transistor are turned on based on the generated electrical signal. It is thereby a driving circuit (10-40), the drive circuit, when to turn on the first transistor and the second transistor, and wherein turning on the second transistor after turning on the first transistor.

  In the pulse generation circuit (2), the drive circuit (20) generates the first drive signal (Vsrc1) generated by superimposing the electric signal generated by the optoelectronic circuit on the first bias voltage, and the control electrode of the first transistor. A first drive signal generation circuit (21) to be supplied to the second drive signal (VEP2) generated by superimposing an electric signal generated by the optoelectronic circuit on a second bias voltage lower than the first bias voltage. And a second drive signal generation circuit (22) that supplies the two-transistor control electrode.

  In the pulse generation circuit (2), the optoelectronic circuit has two terminals, the photodetector (110) that outputs an electrical signal generated according to the incident optical pulse from the terminal, and the other of the photodetectors. The input resistor (Rin) connected between the terminal (P2) of the pixel and the input fixed potential (Vin), and the input capacitor (Cin) connected between the other terminal of the photodetector and the second fixed potential. The first drive signal generation circuit superimposes the electric signal output from one terminal (P1) of the photodetector on the first bias voltage and outputs the first signal to the control electrode of the first transistor. The second drive signal generation circuit includes a circuit (111), a second output circuit (14) that superimposes an electrical signal output from the other terminal (P2) of the photodetector on a DC voltage, and outputs a second output circuit (14). Output from 2nd output circuit to 2 bias voltage The polarity of the electrical signal may comprise an inverter circuit to the control electrode of the second transistor by inverting (13) was.

  In the pulse generation circuit (2), the optoelectronic circuit has two terminals, a photodetector (110) that outputs an electrical signal generated according to the incident optical pulse from the terminal, and photodetection to a DC voltage. Connected between the first output circuit (111) that superimposes and outputs the electrical signal output from one terminal (P1) of the detector, and the other terminal (P2) of the photodetector and the input fixed potential An input resistor (Rin); and an input capacitor (Cin) connected between the other terminal of the photodetector and the second fixed potential. Including a buffer circuit (12) that superimposes an electric signal output from one output circuit and outputs the signal to the control electrode of the first transistor, and the second drive signal generation circuit outputs a DC voltage from the other terminal of the photodetector. Superimposed electrical signal And an inverter circuit (13) that superimposes a signal obtained by inverting the polarity of the electrical signal output from the second output circuit on the second bias voltage and supplies the signal to the control electrode of the second transistor. And may be included.

  In the pulse generation circuit (3), the optoelectronic circuit has two terminals, a photodetector (110) that outputs an electrical signal generated according to the incident optical pulse from the terminal, and photodetection to a DC voltage. A first output circuit (111) that superimposes and outputs an electrical signal output from one terminal of the detector, and an input resistor (Rin) connected between the other terminal of the photodetector and the input fixed potential And an input capacitor (Cin) connected between the other terminal of the photodetector and the second fixed potential, and the drive circuit controls the electric signal output from the first output circuit to the first transistor. A first buffer circuit (12) for supplying the electrodes, a second output circuit (14) for outputting an electric signal output from the other terminal of the photodetector on a DC voltage, and an output from the second output circuit The second electrical signal A second buffer circuit (16) for supplying a second main electrode of the second transistor, a DC voltage (Vb8) is supplied to the control electrode of the second transistor, and the second main electrode of the second transistor is supplied from the second buffer circuit. The DC level of the signal (VEP2) supplied to may be lower than the second fixed potential (Vsrc1).

  In the pulse generation circuit (1), the optoelectronic circuit has two terminals, the photodetector (110) that outputs an electrical signal generated according to the incident optical pulse from the terminal, and the DC voltage A first output circuit (111) that superimposes and outputs an electrical signal output from one terminal of the photodetector, and an input resistor (Rin) connected between the other terminal of the photodetector and an input fixed potential ) And an input capacitor (Cin) connected between the other terminal of the photodetector and the second fixed potential, and the drive circuit receives the electric signal output from the first output circuit of the first transistor. From the first buffer circuit (12) for supplying the control electrode, the second output circuit (14) for superimposing the electric signal output from the other terminal of the photodetector on the DC voltage, and the second output circuit Delay the output electrical signal An output delay circuit (15), an inverter circuit to the control electrode of the second transistor by reversing the polarity of the electric signal output from the delay circuit (16) may contain.

  The pulse generation circuit (4) includes a plurality of sets of first transistors (TR1A, TR1B), second transistors (TR2A, TR2B), and load resistors (RL), and the drive circuit (40) is generated by an optoelectronic circuit. Each set of the first transistor and the second transistor may be driven based on the single electric signal.

  In the pulse generation circuit (4), the optoelectronic circuit has two terminals, a photodetector (110) that outputs an electrical signal generated according to the incident optical pulse from the terminal, and photodetection to a DC voltage. A first output circuit (111) that superimposes and outputs an electrical signal output from one terminal of the detector, and an input resistor (Rin) connected between the other terminal of the photodetector and the input fixed potential And an input capacitor (Cin) connected between the other terminal of the photodetector and the second fixed potential, and the drive circuit outputs the electrical signal output from the first output circuit to each of the first transistors. A first buffer circuit (12) for supplying the control electrode, a second output circuit (14) for superposing and outputting an electric signal output from the other terminal of the photodetector on the DC voltage, and for each second transistor Correspondingly provided, second output And a second buffer circuit (16A, 16B) for supplying an electric signal output from the path to the second main electrode of the corresponding second transistor, and a DC voltage (Vb8) is applied to the control electrode of each second transistor. And the DC level of the signal supplied from the second buffer circuit to the second main electrode of each second transistor may be lower than the second fixed potential.

  In the above description, as an example, constituent elements on the drawing corresponding to the constituent elements of the invention are represented by reference numerals with parentheses.

  According to the present invention, an electric pulse having a narrow pulse width and a large amplitude can be generated while suppressing the energy of an optical pulse in a pulse generation circuit using a photodetector.

FIG. 1 is a diagram illustrating a configuration of a data converter using a master gate circuit according to the first embodiment. FIG. 2 is a diagram showing a comparative example of the gate pulse by the master gate circuit according to the first embodiment and the gate pulse by the conventional master gate circuit. FIG. 3 is a diagram illustrating a configuration of a data converter using the master gate circuit according to the second embodiment. FIG. 4 is a diagram for explaining the operation of each transistor when the same voltage is applied to the gate electrodes of the two transistors. FIG. 5 is a diagram for explaining the operation of each transistor when different voltages are applied to the gate electrodes of the two transistors. FIG. 6A is a diagram illustrating a specific circuit configuration of the master gate circuit according to the second embodiment. FIG. 6B is a diagram showing a more specific circuit configuration of the master gate circuit shown in FIG. 6A. FIG. 7A is a diagram showing another specific circuit configuration of the master gate circuit according to Embodiment 2. FIG. 7B is a diagram showing a more specific circuit configuration of the master gate circuit shown in FIG. 7A. FIG. 8A is a diagram illustrating a specific circuit configuration of the master gate circuit according to the third embodiment. FIG. 8B is a diagram showing a more specific circuit configuration of the master gate circuit shown in FIG. 8A. FIG. 9 is a diagram showing a specific circuit configuration of the master gate circuit according to the fourth embodiment. FIG. 10 is a diagram for explaining data conversion between a high-speed optical communication network and a low-speed electronic circuit. FIG. 11 is a diagram showing a basic configuration of an optical communication system by optical packet switching using a serial / parallel converter. FIG. 12 is a diagram showing a configuration of a conventional master gate circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<< Embodiment 1 >>
FIG. 1 is a diagram showing a configuration of a data converter using a master gate circuit according to an embodiment of the present invention.
A data converter 101 shown in the figure is a functional unit constituting a serial / parallel converter or a parallel / serial converter in an optical communication system based on optical packet switching, for example. Specifically, the data converter 101 propagates a transmission line (communication line) TL1 and converts a high-speed serial signal converted from an optical signal (optical packet) into an electrical signal by an ultra-high-speed photodetector, a multi-bit parallel signal. In a serial / parallel converter that converts the signal into a low-speed electronic circuit 8 and supplies it to the low-speed electronic circuit 8, or a parallel / serial converter that converts a multi-bit parallel signal output from the electronic circuit 8 into a serial signal and supplies it to the transmission line TL1 This is a circuit constituting a conversion channel for 1 bit.

  As shown in FIG. 1, the data converter 101 includes a master gate circuit 1 and a main transistor TR0. For example, in the case of an n-bit serial / parallel converter (or parallel / serial converter), n sets of master gate circuits 1 and main transistors TR0 are provided, and n main transistors TR0 are connected in parallel to the transmission line TL1. Is done.

  The main transistor TR0 is, for example, a HEMT (High Electron Mobility Transistor), one main electrode (for example, drain electrode) is connected to the transmission line TL1, and the other main electrode (for example, source electrode) is connected to the electronic circuit 8. .

  The master gate circuit 1 is a circuit that generates an electric pulse (gate pulse) VG for driving the gate of the main transistor TR0 based on the irradiated light pulse. The gate pulse VG is supplied to the gate electrode of the main transistor TR0.

  The master gate circuit 1 according to the first embodiment has a narrow pulse width and a large amplitude by turning on two transistors TR1 and TR2 connected in series with a time difference according to the incidence of an optical pulse. A gate pulse is generated. Hereinafter, the master gate circuit 1 will be described in detail.

  As shown in FIG. 1, the master gate circuit 1 includes transistors TR <b> 1 and TR <b> 2, a resistor RL, an optoelectronic circuit 11, and a drive circuit 1.

The transistors TR1 and TR2 are, for example, HEMTs. The transistors TR1 and TR2 are connected in series between a fixed potential (for example, power supply voltage) Vh and a fixed potential Vsrc2 lower than the fixed potential Vh, and a node to which the transistors TR1 and TR2 are connected is a main transistor TR0. Connected to the gate electrode. Specifically, in the transistor TR1, the drain electrode as the first main electrode is connected to a fixed potential (for example, power supply voltage) Vh, and the source electrode as the second main electrode is connected to the gate electrode of the main transistor TR0. . In the transistor TR2, the drain electrode as the first main electrode is connected to the gate electrode of the main transistor TR0 and the source electrode of the transistor TR1, and the source electrode as the second main electrode is connected to the fixed potential Vsrc2.
In the following description, the case where all the transistors including the transistors TR1 and TR2 are HEMTs will be described as an example, but the present invention is not limited to this.

  The resistor RL has one end connected to the gate electrode of the main transistor TR0 and the other end connected to the ground potential GND.

  Here, the relationship between the fixed potentials Vh and Vsrc2 and the ground voltage GND is Vsrc2 ≦ GND <Vh.

  The optoelectronic circuit 11 is a circuit that generates an electrical signal in accordance with an incident light pulse. For example, as shown in FIG. 1, the optoelectronic circuit 11 includes a photodetector 110, an output circuit 111, a resistor Rin, and a capacitor Cin.

The photodetector 110 is an element that has two terminals P1 and P2 and outputs an electrical signal generated according to an incident light pulse from the terminal. The photodetector 110 is, for example, the above-described MSM-PD. Hereinafter, the photodetector 110 is referred to as MSM-PD110.
When the MSM-PD 110 is irradiated with an optical pulse serving as an optical trigger, an electric pulse is generated from one terminal P1 of the MSM-PD 110, and another electric pulse having a polarity opposite to that of the electric pulse is generated from the other terminal P2. Generated. For example, when the MSM-PD 110 is irradiated with an optical pulse, an electric pulse having a positive polarity corresponding to the pulse width of the optical pulse irradiated from the terminal P1 is output, and according to the pulse width of the optical pulse irradiated from the terminal P2. A negative polarity electrical pulse is output.

  The output circuit 111 is a circuit that superimposes and outputs an electric signal output from the terminal P1 of the MSM-PD 110 on a direct current (DC) voltage. For example, the output circuit 111 includes a resistor Rb1 and a resistor Rb2 connected in series between the bias potential Vb1 and the ground potential GND. As a result, the voltage between the bias potential Vb1 and the ground potential GND is divided by the resistance ratio of the resistors Rb1 and Rb2, and the electric signal (AC component) output from the terminal P1 of the MSM-PD 110 to the divided voltage. ) Are superimposed and output.

  The input resistor Rin has one terminal connected to the input bias potential Vin and the other terminal connected to the terminal P2 of the MSM-PD110. The input capacitor Cin has one terminal connected to the terminal P2 of the MSM-PD 110 and the other terminal connected to the ground potential GND.

  The drive circuit 10 is a circuit that drives the transistors TR1 and TR2 based on the electrical signal generated by the optoelectronic circuit 11. Specifically, the drive circuit 10 turns off the transistor TR1 and the transistor TR2 when the electrical signal is not generated by the optoelectronic circuit 11, and generates the electrical signal when the electrical signal is generated by the optoelectronic circuit 11. Based on the above, the transistors TR1 and TR2 are turned on. When the transistor TR1 and the transistor TR2 are turned on, the drive circuit 10 first turns on the transistor TR1 and then turns on the transistor TR2.

  As shown in FIG. 1, the drive circuit 10 includes, for example, a buffer circuit 12, an output circuit 14, a delay circuit 15, and an inverter circuit 13.

  The buffer circuit 12 is a circuit that supplies the electrical signal output from the terminal P1 of the MSM-PD 110 in the optoelectronic circuit 11, that is, the electrical signal output from the output circuit 111, to the gate electrode of the transistor TR1.

  The output circuit 14 is a circuit that superimposes the electrical signal output from the terminal P2 of the MSM-PD 110 on the DC voltage and outputs the superimposed signal. The output circuit 14 includes, for example, a capacitor C1 and a resistor Rb3. One end of the capacitor C1 is connected to the terminal P2 of the MSM-PD 110, and the other end is connected to one end of the resistor Rb3. The other end of the resistor Rb3 is connected to the fixed potential Vb2. According to this, the AC component of the electrical signal output from the terminal P2 of the MSM-PD 110 is detected by capacitive coupling of the capacitor C1, and the detected electrical signal is superimposed on the DC voltage based on the fixed potential Vb2 and output. .

  The delay circuit 15 is a circuit that delays and outputs the electric signal output from the terminal P2 of the MSM-PD 110, that is, the electric signal output from the output circuit 14. The delay circuit 15 is not particularly limited as long as it is a circuit that generates a necessary delay time ΔT. For example, a circuit in which a necessary number of inverters, buffer circuits, and the like are connected in series may be used, or the wiring length between the node to which the capacitor C1 and the resistor Rb3 are connected and the input terminal of the subsequent inverter circuit 13 is adjusted. It may be a circuit.

  The inverter circuit 13 is a circuit that inverts the polarity of the electrical signal output from the delay circuit 15 and supplies it to the gate electrode of the transistor T2.

  When the master gate circuit 1 having the above circuit configuration is irradiated with an optical pulse, an electric signal (positive polarity) is generated from the terminal P1 of the MSM-PD 110, and a drive signal Vg1 corresponding to the electric signal is applied to the gate electrode of the transistor TR1. Supplied. In addition, an electric signal (negative polarity) is generated from the terminal P2 of the MSM-PD 110, and a driving signal Vgs2 (positive polarity) obtained by inverting the polarity of the electric signal is supplied to the gate electrode of the transistor TR2 later than the driving signal Vg1. Is done.

  When the drive signal Vg1 is supplied to the gate electrode of the transistor TR1, the transistor TR1 is turned on, and a current flows from the fixed potential Vh via the transistor TR1. At this time, since the transistor TR2 is off (normally off), the current flowing out from the fixed potential Vh via the transistor TR1 flows into the resistor RL. As a result, the gate pulse VG rises sharply.

  When the drive signal Vg2 is supplied to the gate electrode of the transistor TR2 after the delay time ΔT has elapsed, the transistor TR2 is turned on, and a current path is formed between the gate electrode of the main transistor TR0 and the fixed potential Vsrc2. Thereby, the current flowing out of the transistor TR1 flows into the fixed potential Vsrc2 via the transistor TR2. At this time, the operating conditions such as the fixed potential Vsrc2 and the size of the transistor TR2 are adjusted so that the current flowing out of the transistor TR1 flows into the transistor TR2 without flowing through the resistor RL. It can be sharply lowered to a voltage level (for example, 0 V).

  Also, by designing the buffer circuit 12 and the inverter circuit 13 so that the signal delay time by the buffer circuit 12 and the signal delay time by the inverter circuit 13 are equal, the time interval between the drive signal Vg1 and the drive signal Vg2, That is, the delay circuit 15 determines the delay time ΔT between the timing when the transistor TR1 is turned on and the timing when the transistor TR2 is turned on.

FIG. 2 is a diagram showing a comparative example of the gate pulse by the master gate circuit according to the first embodiment and the gate pulse by the conventional master gate circuit.
FIG. 4A shows the waveform of the gate pulse generated by the above-described conventional master gate circuit 90. Further, (b) of the figure shows the waveform of the gate pulse generated by the master gate circuit 1 according to the present embodiment.

  As described above, the gate pulse generated by the conventional master gate circuit 90 has a steep rising waveform but a relatively slow falling waveform. Therefore, as shown in FIG. 2A, the amplitude Vw0 effective for driving the main transistor TR0 is reduced and the pulse width Tp0 is increased.

  On the other hand, the gate pulse VG generated by the master gate circuit 1 according to the present embodiment has a steep rising waveform and falling waveform as shown in FIG. Compared to the gate pulse by the master gate circuit 90, the effective amplitude Vw1 can be increased, and the pulse width Tp1 can be narrowed.

  As described above, according to the master gate circuit according to the first embodiment, since the gate pulse is generated by turning on two transistors connected in series with a time difference, the falling waveform is the same as in the conventional master gate circuit. However, it is possible to generate a steep gate pulse with a rising waveform and a falling waveform instead of a gentle gate pulse. According to this, it is not necessary to increase the energy of the light pulse irradiated to the photodetector (MSM-PD) in order to increase the effective amplitude as the gate pulse. That is, according to the master gate circuit of this embodiment, it is possible to generate a gate pulse with a narrow pulse width and a large effective amplitude while suppressing the energy of the optical pulse.

  Further, in the optical communication system 900 using the optical packet switching shown in FIG. 11 described above, each master transistor TR0 is driven by applying the master gate circuit 1 according to the first embodiment instead of the conventional master gate circuit 90. Since the energy of the optical pulse necessary for generating the gate pulse to be generated can be suppressed, the energy efficiency of the entire optical communication system can be improved.

<< Embodiment 2 >>
As described above, in the master gate circuit 1 according to the first embodiment, the delay circuit 15 shifts the turn-on timing (delay time ΔT) of the two transistors TR1 and TR2 for driving the main transistor TR0. As described above, when the delay time ΔT is realized by adjusting the wiring length, for example, in order to obtain the delay time ΔT of 1 ps, an approximate wiring length of 80 μm is required, and the final circuit size becomes very large. In addition, when obtaining a delay time ΔT of 10 ps or more, the wiring length becomes too long and the electric signal propagating through the wiring disappears (dissipates), so that a realizable delay time is limited. Therefore, when the timings at which the two transistors TR1 and TR2 are turned on are shifted by the delay circuit 15 as in the master gate circuit 1 according to the first embodiment, the delay time that can be set is limited, and the circuit scale increases. there is a possibility.

  The master gate circuit according to the second embodiment does not generate the delay time ΔT by the delay circuit as described above, but generates the delay time ΔT by making the bias states of the two transistors TR1 and TR2 different. is there.

FIG. 3 is a diagram illustrating a configuration of a data converter using the master gate circuit according to the second embodiment.
Similar to the data converter 101 according to the first embodiment, the data converter 102 shown in the figure is a 1-bit unit in a serial / parallel converter or a parallel / serial converter of an optical communication system using optical packet switching. It is a circuit constituting a conversion channel.

  As shown in FIG. 3, the data converter 102 includes a master gate circuit 2 and a main transistor TR0. In the master gate circuit 2 according to the second embodiment, the same components as those in the master gate circuit 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

The master gate circuit 2 includes transistors TR1 and TR2, a resistor RL, an optoelectronic circuit 11, and a drive circuit 20.
The drive circuit 20 includes two drive signal generation circuits 21 and 22.

  The drive signal generation circuit 21 is a circuit that generates the drive signal VEP1 by superimposing the electrical signal generated by the optoelectronic circuit 11 on the first bias voltage and supplies the drive signal VEP1 to the gate electrode of the transistor TR1.

  The drive signal generation circuit 22 is a circuit that generates the drive signal VEP2 by superimposing the electric signal generated by the optoelectronic circuit 11 on a second bias voltage lower than the first bias voltage, and supplies the drive signal VEP2 to the gate electrode of the transistor TR2. is there.

  The drive signal VEP1 generated by the drive signal generation circuit 21 and the drive signal VEP2 generated by the drive signal generation circuit 22 are different voltages. That is, in the master gate circuit 2, different voltages are applied to the gate electrodes of the two transistors TR1 and TR2.

  According to the master gate circuit 2, as in the master gate circuit 1 according to the first embodiment, a gate pulse having a narrow pulse width and a large effective amplitude can be generated. Hereinafter, the master gate circuit 2 will be described in detail.

Here, before describing the operation principle of the master gate circuit 2 according to the second embodiment, first, as a comparative example, consider the case where the same voltage is applied to the gate electrodes of two transistors.
FIG. 4 is a diagram for explaining the operation of each transistor when the same voltage is applied to the gate electrodes of the two transistors.
In FIG. 4, when the transistors TR1 and TR2 have the same size and the same threshold voltage Vth and the source electrodes of the two transistors TR1 and TR2 are connected to different potentials, the same voltage is applied to the gate electrodes of the transistors TR1 and TR2. The timing when the transistors TR1 and TR2 are turned on is shown.

  Specifically, the source electrode of the transistor TR1 is connected to the fixed potential Vsrc1, the drain electrode of the transistor TR1 is connected to the fixed potential Vh, and the voltage VEP is applied to the gate electrode of the transistor TR1. Further, the source electrode of the transistor TR2 is connected to the fixed potential Vsrc2, the drain electrode of the transistor TR2 is connected to the fixed potential Vh, and the voltage VEP is applied to the gate electrode of the transistor TR2. Here, Vsrc1 <Vsrc2.

  The timing at which each transistor TR1, TR2 is turned on is determined by the gate-source voltage Vgs between the gate electrode and the source electrode of each transistor and the threshold voltage Vth. For example, when the voltage VEP is increased in proportion to time, since Vsrc1 <Vsrc2, first, the transistor TR1 is turned on at time t1 when the gate-source voltage Vgs of the transistor TR1 exceeds the threshold voltage Vth. Thereafter, at time t2 when the gate-source voltage Vgs of the transistor TR2 exceeds the threshold voltage Vth, the transistor TR2 is turned on.

  When the target time difference (ΔT) between the turn-on times of the two transistors is small, it is necessary to make the rising waveform of the electric pulse applied to the gate electrodes of the transistors TR1 and TR2 as steep as possible. According to this, the voltage supplied to the gate electrode of the transistor TR1 that is turned on first increases sufficiently, and the transistor TR1 can be turned on with a margin before the other transistor TR2 reaches the turn-on time.

In this way, by making the potentials of the source electrodes of the two transistors TR1 and TR2 different and applying a common voltage VEP to the respective gate electrodes, the transistors TR1 and TR2 can be provided without providing the delay circuit 15. The timing to turn on can be shifted.
However, in the case of FIG. 4, the transistors TR1 and TR2 cannot be turned on in this order unless Vsrc1 <Vsrc2. Therefore, if the principle of FIG. 4 is applied to the master gate circuit of FIG. 3, the voltage (Vsrc2) of the source electrode of the transistor TR2 becomes larger than the voltage (Vsrc1) of one end of the resistor RL. There is a limit to shortening the fall time.
Therefore, in the master gate circuit 2 according to the second embodiment, the source voltage of each of the transistors TR1 and TR2 is not applied by applying different voltages to the gate electrodes of the two transistors TR1 and TR2, but by applying different voltages. The voltage of the electrode is set to satisfy Vsrc1 ≧ Vsrc2.

FIG. 5 is a diagram for explaining the operation of each transistor when different voltages are applied to the gate electrodes of the two transistors.
In FIG. 5, the transistors TR1 and TR2 have the same size and threshold voltage Vth, the source electrodes of the two transistors TR1 and TR2 are connected to different potentials, and different voltages are applied to the gate electrodes of the transistors TR1 and TR2. The timing at which each transistor TR1, TR2 is turned on is shown.

  For example, the source electrode of the transistor TR1 is connected to the fixed potential Vsrc1, the drain electrode of the transistor TR1 is connected to the fixed potential Vh, and the voltage VEP1 is applied to the gate electrode of the transistor TR1. In addition, the source electrode of the transistor TR2 is connected to the fixed potential Vsrc2, the drain electrode of the transistor TR2 is connected to the fixed potential Vh, and the voltage VEP2 is applied to the gate electrode of the transistor TR2. Here, as shown in FIG. 5, Vsrc1> Vsrc2, and the direct current (DC) level of the voltage VEP1 is larger than the DC level of the voltage VEP2.

  In this case, as shown in FIG. 5, when the voltages VEP1 and VEP2 are increased in proportion to time, first, the transistor TR1 is turned on at time t1 when the voltage Vgs of the transistor TR1 exceeds the threshold voltage Vth. . Thereafter, at time t2 when the voltage Vgs of the transistor TR2 exceeds the threshold voltage Vth, the transistor TR2 is turned on.

  In this manner, by applying the voltages VEP1 and VEP2 having different DC levels to the respective gate electrodes of the two transistors TR1 and TR2 in the master gate circuit 2, the delay circuit 15 is not provided and the transistors TR1 and TR2 are not provided. The timing to turn on can be shifted. Also, according to this, unlike the case where the same voltage is applied to the gate electrode (see FIG. 4), Vsrc1> Vsrc2 can be satisfied, so that in FIG. 3, the transistor is more than the voltage at one end of the resistor (Vsrc1). The voltage (Vsrc2) of the source electrode of TR2 can be reduced, and the fall of the gate pulse VG can be sufficiently advanced. In general, if the DC potential difference between the DC level of the voltage VEP2 and the fixed potential Vsrc2 is equal, the delay time ΔT does not change even if the values of the voltage VEP2 and the fixed potential Vsrc2 are changed. The state can be easily adjusted. That is, the value of the fixed potential Vsrc2 can be freely set to satisfy other circuit design requirements. As described above, the voltages VEP1 and VEP2 do not need to be the same voltage, but both voltages VEP1 and VEP2 need to have sufficiently steep slopes and amplitudes.

Next, a specific operation of the master gate circuit 2 based on the operation principle shown in FIG. 5 will be described.
First, in a state where the MSM-PD 110 before time t1 in FIG. 5 is not irradiated with an optical pulse, the DC level of the drive signal VEP2 generated by the drive signal generation circuit 22 is the drive generated by the drive signal generation circuit 21. It is lower than the DC level of the signal VEP1. At this time, since the two transistors TR1 and TR2 are normally off and no current flows through the resistor RL, the source terminal of the transistor TR1 is grounded (Vsrc1 = GND).

  Next, when the MSM-PD 110 is irradiated with an optical pulse, the drive signal generation circuits 21 and 22 generate drive signals VEP1 and VEP2, respectively. At this time, since the DC level of VEP1 is higher than the DC level of VEP2 as described above, first, the transistor TR1 is turned on at time t1 when the drive signal VEP1 becomes the threshold value Vth of the transistor TR1. At this time, the transistor TR2 remains normally off. When the transistor TR1 is turned on, a current flows from the fixed potential Vh to the resistor RL via the transistor TR1. Thereby, as shown in FIG. 5, the output voltage (gate voltage VG) increases rapidly.

  Next, at time t2 when the drive signal VEP2 rises and reaches the threshold value Vth of the transistor TR2, the transistor TR2 is turned on. As a result, the current flowing from the fixed potential Vh via the transistor TR1 flows into the fixed ionization Vsrc2 via the transistor TR2. That is, the current of the transistor TR1 is canceled by the current of the transistor TR2. As a result, the gate voltage VG rapidly decreases as shown in FIG.

  As shown in FIG. 5, in order to generate an appropriate gate pulse VG, it is necessary to appropriately determine the DC level of VEP2 and the fixed potential Vsrc2. Specifically, as the first condition, the delay time ΔT between the turn-on time of the transistor T1 and the turn-on time of the transistor T2 is appropriate so that an accurate rise time of the gate pulse VG by the resistor RL can be obtained. Thus, it is necessary to determine the DC level of VEP2 and the fixed potential Vsrc2. As a second condition, in order to cancel the current of the transistor TR1, it is necessary to determine the DC level of the VEP2 and the fixed potential Vsrc2 so that an appropriate current flows through the transistor TR2 when the transistor TR2 is turned on. By defining the DC level of VEP2 and the fixed potential Vsrc2 so as to satisfy these two conditions, the amplitude is reduced to “0 V (GND)” and the pulse width of the transistor having the same pulse width is used. It is possible to generate a gate pulse VG that is approximately twice ΔT ″.

Next, a specific circuit configuration example of the master gate circuit 2 according to the second embodiment is shown below.
FIG. 6A is a diagram illustrating a specific circuit configuration of the master gate circuit 2 according to the second embodiment. FIG. 6B is a diagram showing a more specific circuit configuration of the master gate circuit shown in FIG. 6A.
As shown in FIG. 6A, the output circuit 111 in the optoelectronic circuit 11 is used as the drive signal generation circuit 21, and the drive signal generation circuit 22 is realized by the output circuit 14 and the inverter circuit 13.

  As shown in FIG. 6B, the inverter circuit 13 can be realized by, for example, a resistor Rb4 and a transistor TR3. One end of the resistor Rb4 is connected to the fixed potential Vb4, and the other end is connected to the gate electrode of the transistor TR2. The gate electrode of the transistor TR3 is connected to a node to which the capacitor C1 and the resistor Rb3 are connected, the source electrode of the transistor TR3 is connected to the fixed potential Vb5, and the drain electrode of the transistor TR3 is connected to the gate electrode of the transistor TR2. The

  Here, the values of the fixed potentials Vb1, Vb2, Vb4, Vb5, the resistor Rb4, and the like are adjusted so that the drive signals VEP1, VEP2 satisfy the above-described relationship of FIG.

6A and 6B, the electrical signal output from the terminal P1 of the MSM-PD 110 in the optoelectronic circuit 11 is supplied to the gate electrode of the transistor TR1 as the drive signal VEP1 through the output circuit 111, and the optoelectronic circuit 11 The polarity of the electric signal output from the terminal P2 of the MSM-PD110 is inverted by the inverter circuit 13 and supplied to the gate electrode of the transistor TR2 as the drive signal VEP2.
Accordingly, the timing at which the transistor TR1 is turned on and the timing at which the transistor TR2 is turned on can be shifted, so that a gate pulse having a narrow pulse width and a large effective amplitude can be generated.

FIG. 7A is a diagram showing another specific circuit configuration of the master gate circuit 2 according to the second embodiment. FIG. 7B is a diagram showing a more specific circuit configuration of the master gate circuit shown in FIG. 7A.
As shown in FIG. 7A, the drive signal generation circuit 21 is realized by the buffer circuit 12, and the drive signal generation circuit 22 is realized by the output circuit 14 and the inverter circuit 13.
As shown in FIG. 7B, the buffer circuit 12 can be realized by, for example, a resistor Rb5 and a transistor TR4. One end of the resistor Rb5 is connected to the fixed potential Vb6, and the other end is connected to the gate electrode of the transistor TR1. The gate electrode of the transistor TR4 is connected to a node to which the resistors Rb1 and Rb2 are connected, the drain electrode of the transistor TR4 is connected to the fixed potential Vb3, and the source electrode of the transistor TR3 is connected to the gate electrode of the transistor TR1. The

  Here, the values of the fixed potentials Vb1, Vb2, Vb3, Vb4, Vb5, the resistor Rb4, the resistor Rb5, and the like are adjusted so that the drive signals VEP1, VEP2 satisfy the above-described relationship of FIG.

7A and 7B, the electrical signal output from the terminal P1 of the MSM-PD 110 in the optoelectronic circuit 11 is supplied to the gate electrode of the transistor TR1 as the drive signal VEP1 through the buffer circuit 12, and the optoelectronic circuit 11, the polarity of the electric signal output from the terminal P2 of the MSM-PD 110 is inverted by the inverter circuit 13 and supplied to the gate electrode of the transistor TR2 as the drive signal VEP2.
6A and 6B, the timing at which the transistor TR1 is turned on and the timing at which the transistor TR2 is turned on can be shifted, so that a gate pulse with a narrow pulse width and a large effective amplitude can be generated. . Further, according to the circuits of FIGS. 7A and 7B, since not only the inverter circuit 13 but also the buffer circuit 12 is provided, the relative generated between the drive signal VEP1 and the drive signal VEP2 as compared with the case where only the inverter circuit 13 is provided. Delay can be reduced. Thereby, it becomes possible to realize a gate pulse having a pulse width of less than 10 ps.

  As described above, according to the master gate circuit 2 according to the second embodiment, similarly to the master gate circuit 1 according to the first embodiment, the gate has a narrow pulse width and a large effective amplitude while suppressing the energy of the optical pulse. Pulses can be generated.

  Further, since there is no need to provide the delay circuit 15 in order to provide the delay time ΔT unlike the master gate circuit 1 according to the first embodiment, the delay time can be easily set while suppressing an increase in circuit scale. .

<< Embodiment 3 >>
FIG. 8A is a diagram illustrating a specific circuit configuration of the master gate circuit according to the third embodiment.
FIG. 8B is a diagram showing a more specific circuit configuration of the master gate circuit shown in FIG. 8A.
The master gate circuit 3 according to Embodiment 3 does not change the voltage of the gate electrode of the transistor TR2, but generates the gate pulse VG by changing the voltage of the source electrode of the transistor TR2. 2 is the same as the master gate circuit 2 in other points.

  8A and 8B, the master gate circuit 3 includes an output circuit 14 and buffer circuits 12 and 16 in addition to the transistors TR1 and TR2, the resistor RL, and the optoelectronic circuit 11. In the master gate circuit 3 according to the third embodiment, the same components as those in the master gate circuits 1 and 2 according to the first and second embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. .

  As shown in FIG. 8B, the buffer circuit 16 can be realized by a resistor Rb6 and a transistor TR5, for example. One end of the resistor Rb6 is connected to the fixed potential Vb5, and the other end is connected to the source electrode of the transistor TR2. The gate electrode of the transistor TR5 is connected to a node to which the resistor Rb3 and the capacitor C1 are connected, the drain electrode of the transistor TR5 is connected to the fixed potential Vb7, and the source electrode of the transistor TR5 is connected to the source electrode of the transistor TR2. The The gate electrode of the transistor TR2 is connected to the fixed potential Vb8.

  8A and 8B, as in the master gate circuit 2 according to the second embodiment, the electric signal output from the terminal P1 of the MSM-PD 110 in the optoelectronic circuit 11 is driven via the buffer circuit 12. The signal VEP1 is supplied to the gate electrode of the transistor TR1. On the other hand, the electrical signal output from the terminal P2 of the MSM-PD 110 in the optoelectronic circuit 11 is supplied to the source electrode of the transistor TR2 as the drive signal VEP2 via the buffer circuit 16. This makes it possible to minimize the delay time between the drive signal VEP1 and the drive signal VEP2.

  In this case, the constants of the fixed potentials Vb5 and Vb7, the resistor Rb6, and the transistor TR5 are set so that the DC level of the drive signal VEP2 supplied to the source electrode of the transistor TR2 is smaller than the fixed voltage Vsrc1. Further, the potential difference between the fixed potential Vb8 and the DC level of the drive signal VEP2 supplied to the source electrode of the transistor TR2 is the difference between the fixed potential Vsrc2 in FIG. 5 and the drive signal (VEP2) supplied to the gate electrode of the transistor TR2. This is the same as the difference from the DC level.

  According to this, similarly to the master gate circuit 2 according to the second embodiment, the timing at which the transistor TR1 is turned on and the timing at which the transistor TR2 is turned on can be shifted, so that the pulse width is narrow and the effective amplitude is large. A gate pulse VG can be generated.

  In the circuits of FIGS. 8A and 8B, when the transistor TR2 is turned on, a current flows from the transistor TR2 via the resistor Rb6. Therefore, in order to generate a gate pulse VG having a narrow pulse width, the resistance value of the resistor Rb6 is set. It needs to be smaller.

<< Embodiment 4 >>
FIG. 9 is a diagram showing a specific circuit configuration of the master gate circuit according to the fourth embodiment.
The master gate circuit 4 shown in the figure is different from the master gate circuit according to the first to third embodiments in that two gate pulses are generated based on one optical pulse, and the other points are the same as in the embodiment. 1-3.

  Specifically, the master gate circuit 4 has M sets of transistors TR1, transistors TR2, and resistors RL for driving M (M is an integer of 2 or more) main transistors TR0. The master gate circuit 4 includes an optoelectronic circuit 11 and a drive circuit 40. The drive circuit 40 generates drive signals VEP1 and VEP2 for driving each pair of transistors TR1 and TR2 based on one electrical signal generated by the optoelectronic circuit 11.

  As the drive circuit 40, a circuit based on any of the drive circuits 10 to 30 according to the first to third embodiments described above can be exemplified. For example, FIG. 9 illustrates a drive circuit 40 based on the drive circuit 30.

  As shown in FIG. 9, the drive circuit 40 includes a buffer circuit 12, an output circuit 14, and buffer circuits 16A and 16B. FIG. 9 shows an example of the master gate circuit 4 when M = 2.

  The buffer circuit 12 supplies the electric signal output from the output circuit 111 to the gate electrodes of the transistors TR1A and TR1B as the drive signal VEP1.

  The output circuit 14 superimposes the electric signal output from the terminal P2 of the MSM-PD 110 on the fixed potential Vb2, and supplies the electric signal to the buffer circuits 16A and 16B, respectively.

  The buffer circuits 16A and 16B are provided corresponding to the respective transistors TR2, and supply the electric signal output from the output circuit 14 to the source electrodes of the corresponding transistors TR2A and TR2B. A fixed potential voltage VEP2 is supplied to the gate electrodes of the transistors TR2A and TR2B. The buffer circuits 16A and 16B have a circuit configuration similar to that of the buffer circuit 16, for example.

  According to the master gate circuit 4 of FIG. 9, the electric signal output from the terminal P1 of the MSM-PD 110 in the optoelectronic circuit 11 is supplied to the gate electrodes of the transistors TR1A and TR1B via the buffer circuit 12. On the other hand, the electrical signal output from the terminal P2 of the MSM-PD 110 in the optoelectronic circuit 11 is supplied to the source electrodes of the transistors TR2A and TR2B via the buffer circuits 16A and 16B, respectively.

  According to this, it is possible to generate the gate pulses VGA and VGB supplied to the respective main transistors TR0 by irradiating the optoelectronic circuit 11 with one light pulse, and to set the pulse widths of the gate pulses VGA and VGB, respectively. The narrow and effective amplitude can be increased. According to this, for example, conversion processing (serial / parallel conversion processing or parallel / serial conversion processing) for two types of transmission lines (communication lines) TL1 and TL2 can be realized by irradiation with one light pulse. That is, according to the master gate circuit according to the fourth embodiment, the energy of the light pulse can be further reduced.

  Although the invention made by the present inventors has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. Yes.

  For example, in the fourth embodiment, the case where M = 2 is illustrated. However, the present invention is not limited to this, and a master gate circuit that generates M gate pulses VG is also realized when M ≧ 3. Can do.

  In the fourth embodiment, the drive circuit 40 based on the drive circuit 30 is illustrated as the drive circuit 40 (see FIG. 9). However, the present invention is not limited to this, and the drive circuit 40 is replaced with the first and second embodiments. The drive circuits 10 and 20 can be configured as a base. For example, the drive circuit 40 can be realized based on the drive circuit 20 shown in FIGS. 7A and 7B. Specifically, in FIG. 9, the source electrodes of the transistors TR2A and TR2B are connected to the fixed potential Vsrc2 (<Vsrc1), and the buffer circuits 16A and 16B are replaced with the inverter circuits 13, respectively. Are supplied to the gate electrodes of the corresponding transistors TR2A and TR2B. According to this, as in the case of the fourth embodiment (FIG. 9), the energy of the light pulse can be further reduced.

  1, 2, 3, 4 ... Master gate circuit, 8 ... Electronic circuit, TR0, TR0A, TR0B ... Main transistor, 101 ... Data converter, TR1, TR2, TR1A, TR1B, TR2A, TR2B ... Transistor, 10, 20, 30, 40 ... Drive circuit, 11 ... Optoelectronic circuit, 12 ... Buffer circuit, 13 ... Inverter circuit, 14,111 ... Output circuit, 15 ... Delay circuit, RL, Rb1, Rb2, Rb3, Rb4, Rb5, Rb6 ... Resistance, Rin: input resistance, Cin: input capacitor, C1: capacitor, 110: MSM-PD, P1, P2: terminals of MSM-PD, Vg1, Vg2, VEP1, VEP2: drive signal, VG, VG1, VG2: gate pulse, Vh, Vsrc1, Vsrc2, Vb1, Vb2, Vb3, Vb4, Vb5, Vb6, Vb7, V 8 ... fixed potential, GND ... ground potential, TL1, TL2 ... transmission line.

Claims (8)

An optoelectronic circuit that generates an electrical signal in response to an incident light pulse;
A first transistor having a first main electrode connected to a first fixed potential;
A resistor connected between a second main electrode of the first transistor and a second fixed potential lower than the first fixed potential;
A second transistor having a first main electrode connected to the first transistor second main electrode and a second main electrode connected to a third fixed potential equal to or lower than the second fixed potential;
When the electrical signal is not generated by the optoelectronic circuit, the first transistor and the second transistor are turned off, and when the electrical signal is generated by the optoelectronic circuit, the first signal is generated based on the generated electrical signal. A driving circuit for turning on one transistor and the second transistor,
The drive circuit turns on the second transistor after turning on the first transistor when turning on the first transistor and the second transistor. The pulse generation circuit according to claim 1,
The drive circuit is
A first drive signal generation circuit for supplying a first drive signal generated by superimposing an electric signal generated by the optoelectronic circuit to a first bias voltage to a control electrode of the first transistor;
A second drive signal generation circuit for supplying a second drive signal generated by superimposing an electric signal generated by the optoelectronic circuit to a second bias voltage lower than the first bias voltage to the control electrode of the second transistor And a pulse generation circuit characterized by comprising: The pulse generation circuit according to claim 2,
The optoelectronic circuit is:
A photodetector having two terminals and outputting an electrical signal generated in response to an incident light pulse from the terminal;
An input resistor connected between the other terminal of the photodetector and an input fixed potential;
An input capacitor connected between the other terminal of the photodetector and the second fixed potential;
The first drive signal generation circuit includes:
A first output circuit that superimposes an electrical signal output from one terminal of the photodetector on the first bias voltage and outputs the superimposed signal to a control electrode of the first transistor;
The second drive signal generation circuit includes:
A second output circuit that superimposes and outputs an electric signal output from the other terminal of the photodetector on a DC voltage;
An inverter circuit for inverting the polarity of the electrical signal output from the second output circuit to the second bias voltage and supplying the inverted signal to the control electrode of the second transistor. The pulse generation circuit according to claim 2,
The optoelectronic circuit is:
A photodetector having two terminals and outputting an electrical signal generated in response to an incident light pulse from the terminal;
A first output circuit that superimposes and outputs an electric signal output from one terminal of the photodetector on a DC voltage;
An input resistor connected between the other terminal of the photodetector and an input fixed potential;
An input capacitor connected between the other terminal of the photodetector and the second fixed potential;
The first drive signal generation circuit includes:
A buffer circuit that superimposes the electrical signal output from the first output circuit on the first bias voltage and outputs the superimposed signal to the control electrode of the first transistor;
The second drive signal generation circuit includes:
A second output circuit that superimposes and outputs an electric signal output from the other terminal of the photodetector on a DC voltage;
An inverter circuit that superimposes a signal obtained by inverting the polarity of the electric signal output from the second output circuit on the second bias voltage and supplies the signal to the control electrode of the second transistor. Generation circuit. The pulse generation circuit according to claim 1,
The optoelectronic circuit is:
A photodetector having two terminals and outputting an electrical signal generated in response to an incident light pulse from the terminal;
A first output circuit that superimposes and outputs an electric signal output from one terminal of the photodetector on a DC voltage;
An input resistor connected between the other terminal of the photodetector and an input fixed potential;
An input capacitor connected between the other terminal of the photodetector and the second fixed potential;
The drive circuit is
A first buffer circuit for supplying an electric signal output from the first output circuit to a control electrode of the first transistor;
A second output circuit that superimposes and outputs an electric signal output from the other terminal of the photodetector on a DC voltage;
A second buffer circuit for supplying an electric signal output from the second output circuit to a second main electrode of a second transistor;
A DC voltage is supplied to the control electrode of the second transistor,
The pulse generation circuit, wherein a DC level of a signal supplied from the second buffer circuit to the second main electrode of the second transistor is lower than the second fixed potential. The pulse generation circuit according to claim 1,
The optoelectronic circuit is:
A photodetector having two terminals and outputting an electrical signal generated in response to an incident light pulse from the terminal;
A first output circuit that superimposes and outputs an electric signal output from one terminal of the photodetector on a DC voltage;
An input resistor connected between the other terminal of the photodetector and an input fixed potential;
An input capacitor connected between the other terminal of the photodetector and the second fixed potential;
The drive circuit is
A first buffer circuit for supplying an electric signal output from the first output circuit to a control electrode of the first transistor;
A second output circuit that superimposes and outputs an electric signal output from the other terminal of the photodetector on a DC voltage;
A delay circuit that delays and outputs the electrical signal output from the second output circuit;
An inverter circuit that inverts the polarity of the electrical signal output from the delay circuit and supplies the inverted signal to the control electrode of the second transistor. The pulse generation circuit according to claim 1,
A plurality of sets of the first transistor, the second transistor, and the resistor;
The pulse generation circuit, wherein the drive circuit drives each pair of the first transistor and the second transistor based on the one electric signal generated by the optoelectronic circuit. The pulse generation circuit according to claim 7,
The optoelectronic circuit is:
A photodetector having two terminals and outputting an electrical signal generated in response to an incident light pulse from the terminal;
A first output circuit that superimposes and outputs an electric signal output from one terminal of the photodetector on a DC voltage;
An input resistor connected between the other terminal of the photodetector and an input fixed potential;
An input capacitor connected between the other terminal of the photodetector and the second fixed potential;
The drive circuit is
A first buffer circuit for supplying an electric signal output from the first output circuit to a control electrode of each of the first transistors;
A second output circuit that superimposes and outputs an electric signal output from the other terminal of the photodetector on a DC voltage;
A second buffer circuit provided corresponding to each of the second transistors and supplying an electric signal output from the second output circuit to a second main electrode of the corresponding second transistor;
A DC voltage is supplied to the control electrode of each of the second transistors,
The pulse generation circuit, wherein a DC level of a signal supplied from the second buffer circuit to the second main electrode of each of the second transistors is lower than the second fixed potential.