JP4624890B2 - Circuit design method and simulation system - Google Patents

Description

  The present invention relates to a circuit design method for an integrated circuit, and more particularly to a circuit design method and a simulation system for changing the configuration of an input transistor so as to avoid a negative delay without inserting a buffer.

  Conventionally, with the miniaturization of semiconductor integrated circuits, it has become important to increase the operation speed. In order to perform the operation at high speed, the delay time in the wiring path has been measured in the conventional integrated circuit design. In addition, simulation software has been developed that supports circuit design that automatically performs circuit changes or wiring changes based on the measurement result of the delay time.

  For example, there has been proposed a semiconductor device design method in which correction is performed to shorten the delay time for a wiring path having a delay time exceeding a predetermined value (Patent Document 1).

Further, the level transition time of each of the data signal and clock signal supplied to each flip-flop is extracted from the design data timing verification result, and the timing for the flip-flop timing design standard is matched to the difference of each level transition time. An automatic circuit design method has been proposed in which characteristics are optimized to prevent malfunction due to a transition time difference caused by deterioration of data signal and clock signal waveforms (Patent Document 2).
Japanese Patent Laid-Open No. 9-319775 Japanese Patent Laid-Open No. 10-91661

  However, with the miniaturization of the semiconductor integrated circuit, the gate length is shortened, the power supply voltage can be lowered, and the threshold voltage (Vth) of the transistor is lowered by the reduced voltage, so that the circuit operation is also accelerated. On the other hand, if the waveform input to the circuit is rounded, the output changes before the input signal swings sufficiently, resulting in a negative delay time, making it difficult to accurately represent the circuit delay time. There was a case.

  The above prior art does not consider a case where the delay time of the circuit due to the negative delay time cannot be expressed accurately, and therefore does not provide a solution. Therefore, in order to solve the negative delay time due to the rounding of the input waveform, a cell (for example, a gate circuit) is inserted and lengthened as in the past so that the input waveform has no round. I tried to avoid wiring. However, with this method, it is necessary to re-execute layout processing and verify delay time and the like in accordance with the arrangement and wiring of the inserted cell. At this time, a new error may be detected, and an increase in gate size (an increase in arrangement area and an increase in power supply) due to the insertion of a cell is caused.

  Accordingly, an object of the present invention is to provide a circuit design method and a simulation system that can change the threshold voltage of an input-side transistor so as to eliminate a negative delay time.

To solve the above problems, the disclosed technology is a simulation system for performing based on the arrangement and the wiring design of a plurality of cells in the circuit in the circuit information including the information of each cell by a computer, the parameters of the cell One of a plurality of parameter value tables prepared for each value and storing a value indicating a positive / negative delay time corresponding to a combination of an input slew value and a load value of an input side circuit of the cell is stored in the circuit information. First table specifying means for specifying based on the parameter value of the cell in the cell, and the first table specifying based on the input through value and load value of the input side circuit calculated based on the circuit information First table position specifying means for specifying a table position on the parameter value table specified by the means, and parameters specified by the first table specifying means. By sequentially referring to the same table position as the table position specified by the first table position specifying means in each parameter value table other than the parameter value table in the order of increasing parameter values, the referenced delay time Parameter value acquisition means for acquiring a parameter value when changing from positive to negative or from negative to positive, and a circuit configuration for changing the parameter value of the cell of the circuit information to the parameter value acquired in the parameter value acquisition means And changing means .

  In such a circuit design method, it is possible to change the threshold voltage of the input-side transistor so as to eliminate the negative delay time without performing buffer insertion.

  In addition, in order to solve the above-described problem, a simulation system for designing a circuit by a computer, wherein the threshold voltage of the input circuit is increased by changing the configuration of the input circuit in the circuit exhibiting a negative delay time. It is configured to have a changing means and a second changing means for lowering the threshold voltage of the input circuit by changing the ion implantation amount of the input circuit in the circuit showing the positive delay time.

  In such a simulation system, the negative delay time is avoided and the circuit configuration is changed so as to reduce the positive delay time, and the positive delay time is shortened by changing the ion implantation amount of the input circuit. Is possible. Therefore, the difference between the minimum delay time and the maximum delay time of the data signal timing and the clock signal timing in the timing verification can be made substantially equal.

  As means for solving the above-mentioned problems, the present invention may be a computer-readable storage medium storing a program for causing a computer to execute the above procedure, and a computer-executable program.

  The present invention can change the circuit configuration so as to shorten the positive delay time by changing the ion implantation amount of the input transistor, and to avoid the negative delay time and reduce the positive delay time. Become. Therefore, the difference between the minimum delay time and the maximum delay time of the data signal timing and the clock signal timing in the timing verification can be made substantially equal. Further, an increase in circuit scale and an increase in power supply due to repeated insertion of a circuit such as a buffer can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  A simulation system that realizes the circuit design method according to the present invention is a computer device and has a hardware configuration as shown in FIG. FIG. 1 is a diagram illustrating a hardware configuration of a simulation system according to an embodiment of the present invention.

  In FIG. 1, a simulation system 100 is a device controlled by a computer, and includes a CPU (Central Processing Unit) 11, a memory unit 12, a display unit 13, an output unit 14, an input unit 15, and a communication unit. 16, a storage device 17, and a driver 18, which are connected to the system bus B.

  The CPU 11 controls the simulation system 100 according to a program stored in the memory unit 12. The memory unit 12 includes a RAM (Random Access Memory), a ROM (Read-Only Memory), and the like, and is obtained by a program executed by the CPU 11, data necessary for processing by the CPU 11, and processing by the CPU 11. Stored data. A part of the memory unit 12 is allocated as a work area used for processing by the CPU 11.

  The display unit 13 displays various information required under the control of the CPU 11. The output unit 14 has a printer or the like, and is used for outputting various types of information in accordance with instructions from the user. The input unit 15 includes a mouse, a keyboard, and the like, and is used by a user to input various information necessary for the simulation system 100 to perform processing.

  The communication unit 16 is a device for controlling communication with the PC 3 when the simulation system 100 is connected to, for example, a PC (personal computer) via the network 2 such as the Internet or a LAN (Local Area Network). is there. By configuring the network in this way, the PC user can use the processing in the timing adjustment method according to the present invention.

  The storage device 17 is composed of, for example, a hard disk unit, and stores data such as programs for executing various processes.

Program that implements processing in the circuit design method performed by the simulation system 100 is a program for performing cell layout of the logic circuit, for example, by CD-ROM (Compact Disk Read- Only Memory) storage medium 19 such as a The simulation system 100 is provided. That is, when the storage medium 19 storing the program is set in the driver 18, the driver 18 reads the program from the storage medium 19, and the read program is installed in the storage device 17 via the system bus B. . When the program is activated, the CPU 11 starts its processing according to the program installed in the storage device 17.

  The medium for storing the program is not limited to a CD-ROM, and any medium that can be read by a computer may be used. The program for realizing the processing according to the present invention may be downloaded via the network by the communication unit 16 and installed in the storage device 17. Further, when the simulation system 100 has an interface such as a USB (Universal Serial Bus) for connecting to the outside, the program may be read from an external storage medium by USB connection.

  An outline of the circuit design process executed by the CPU 11 of the simulation system 100 will be described with reference to FIG. FIG. 2 is a diagram for explaining the outline of the circuit design process.

  In FIG. 2, when the time required for the input waveform to reach a predetermined height (hereinafter referred to as input slew) exceeds the limit value in the wiring and arranged gate circuit 2, this gate is displayed. Circuit 2 is detected as an error.

  In the present invention, the negative delay time is avoided by changing the configuration of the input-side transistor (hereinafter referred to as the input transistor) of the gate circuit 2 in which an error that does not satisfy the limit value is detected. The positive delay time can be shortened by changing the ion implantation amount of the input transistor. Further, the threshold voltage Vth changes according to the change of the ion implantation amount, and the threshold voltage Vth is improved.

  Further, by changing the configuration of the input transistor so as to avoid the negative delay time, the delay time in the timing verification can be verified more accurately. Further, the threshold voltage Vth changes according to the change in the configuration of the input transistor, and the threshold voltage Vth is improved.

  Further, by changing the ion implantation amount of the input transistor to shorten the positive delay time, and avoiding the negative delay time and reducing the positive delay time, the timing of the data signal and the clock signal in the timing verification can be reduced. It is possible to adjust so that the difference between the minimum delay time and the maximum delay time is substantially equal and can be suppressed within a fixed clock cycle.

  Conventionally, when the input waveform is rounded, the circuit delay increases, so a slew limit (upper limit value of the input slew) is provided, and a buffer is inserted between elements that do not satisfy the slew limit to perform waveform shaping. However, such extra buffer insertion can be eliminated.

  Therefore, an increase in circuit scale and an increase in power supply due to repeated insertion of circuits such as buffers can be suppressed.

  Next, circuit design processing according to the present invention will be described in detail with reference to FIGS.

  FIG. 3 is a flowchart for explaining the outline of the circuit design process. In FIG. 3, the CPU 11 of the simulation system 100 performs a process of placing cells on the substrate (step S <b> 11). And the process which wires between the arrange | positioned cells is performed (step S12). Thereafter, RC extraction is performed on the integrated circuit in which a plurality of cells are arranged and wiring processing to each cell is performed (step S13). The result of steps S11 to S12 is stored in the layout circuit information table 34 as layout circuit information relating to the laid out circuit each time.

  The CPU 11 calculates a delay time for each predetermined wiring path, and outputs the result as a delay calculation result 30 to the storage area (step S14). Here, the input through is calculated from the wiring resistance component.

  The CPU 11 acquires through information regarding the input through from the delay calculation result 30 and refers to the through limit 32 based on the design order of the input waveform, thereby determining whether the input through of the laid-out cell satisfies the through limit 32. Is checked (step S15). When checking the slew limit in this way, in order to process a circuit that satisfies the slew limit as much as possible as an error, for example, a circuit that is 1 to 2% below the slew limit is detected as an error. Therefore, the circuit detected as an error includes a circuit showing a positive delay time.

  If the through limit 32 is satisfied, timing verification is performed by referring to the delay calculation result 30 (step S16).

  On the other hand, if the input through does not satisfy the through limit 32, circuit information relating to the circuit in which the error is detected is acquired from the layout circuit information table 34 (step S17).

  Next, based on the slew information, the slope of the input slew obtained from the required waveform height of the input waveform and the input slew indicating the time required to reach the height is determined as the required waveform height of the output waveform. It is determined whether or not the inclination of the output slew obtained by the output slew indicating the time required up to the height is larger (step S18). For example, the slope per unit time until the input signal on the input transistor side reaches the threshold voltage Vth is calculated as the slope of the input through. Similarly, the output through slope is also calculated.

  In step S18, when the slope of the input slew is equal to or smaller than the slope of the output slew, since the delay is not a negative delay, the circuit operation itself is further slowed if the configuration of the input transistor is changed. The circuit information is changed by changing the threshold voltage Vth by adjusting the amount of ion implantation to reduce the delay time (step S19). Thereafter, the CPU 11 returns to step S12 and repeats the same processing as described above based on the changed circuit information.

  In step S18, if the slope of the input slew is larger than the slope of the output slew, a negative delay occurs. Therefore, the CPU 11 changes the threshold voltage Vth by changing the configuration of the input transistor and performs processing to avoid the negative delay. Then, the circuit information is changed (step S20). Thereafter, the CPU 11 returns to step S12 and repeats the same processing as described above based on the changed circuit information.

  Next, the ion implantation amount changing process executed in step S19 of FIG. 3 will be described. FIG. 4 is a flowchart for explaining the ion implantation amount changing process. In FIG. 4, the threshold voltage conversion table 41 based on the ion implantation amount and the transistor variable information 51 based on the ion implantation amount are referred to by the CPU 11. Further, the threshold voltage conversion table 41 based on the ion implantation amount and the transistor variable information 51 based on the ion implantation amount are stored, for example, in the storage device 17 of FIG.

  The threshold voltage conversion table 41 based on the ion implantation amount is composed of a plurality of tables, and a table is prepared for each predetermined implantation amount of the ion implantation amounts 1 to p in order of increasing ion implantation amount. In this case, the threshold voltage Vth decreases in the order of the ion implantation amount 1 to p in order of increasing ion implantation amount.

  For example, in the table for the ion implantation amount 1, the through values from the through 11 to the through 1n are set in each row in the order in which the slope of the input through increases, and the load 11 to the load 1m in each column in the order of increasing the load. It is a matrix in which load values are set. In this table, the sign of the delay is shown by the through value and the load value when the ion implantation amount is 1. Since the through value and the load value are individually set in the table for each ion implantation amount 1 to p, the table position on the table is specified, and the delay is made by referring to the following table in order from the current table. Can be verified as changing from positive to negative or from negative to positive.

  The transistor variable information 51 based on the ion implantation amount indicates transistor information 51-1 to 51-p corresponding to the ion implantation amounts 1 to p of the threshold voltage variable table 41 based on the ion implantation amount. The transistor information 51-1 to 51 -p is detailed information related to the corresponding ion implantation amounts 1 to p, and includes, for example, information that is referred to in the manufacturing process when indicating the ion implantation amount.

  The CPU 11 specifies a table corresponding to the ion implantation amount shown in the circuit information acquired in step S17 of FIG. 3 from the threshold voltage conversion table 41 based on the ion implantation amount (step S191). For example, when the ion implantation amount 1 is indicated by the circuit information, a table for the ion implantation amount 1 is specified.

  The CPU 11 specifies the table position from the through information referenced in step S15 by the through (inclination of input through) at the time of error detection and the load (step S192). When the table for the ion implantation amount 1 is specified and the through 1i and the load 11 are indicated in the through information, the line number “i” specified by the through 1i and the load 11 is The table position is specified by the combination with the column number “1”.

  The CPU 11 refers to the tables in the order of increasing ion implantation amount from the table specified in step S191 until the delay changes from positive to negative at the same table position (step S193). That is, in the table for the ion implantation amount 1 specified in step S191, the delay is positive at the table position by the row number “i” and the column number “1”. In the order of the tables for 3,..., The delay state at the table position with the same row number “i” and column number “1” is checked, and the table in which the delay state first changes to negative is referred to. . With reference to the last table for the ion implantation amount p, the processing in step S193 is terminated.

  Then, the CPU 11 first determines whether there is a table whose delay is from positive to negative (step S194). When there is no table in which the delay becomes positive to negative, that is, when the table for the ion implantation amount p is referred to but the delay remains positive and does not change, the CPU 11 ends the ion implantation amount changing process. .

  On the other hand, when there is a table in which the delay is positive to negative, transistor information corresponding to the ion implantation amount that becomes a positive delay immediately before the negative delay is obtained from the transistor variable information 51 based on the ion implantation amount ( Step S195). For example, when a negative delay is changed in the table for the ion implantation amount 4, the ion implantation amount 3 is acquired as the ion implantation amount, and the transistor information 51-3 corresponding to the ion implantation amount 3 is set as the ion implantation amount. Obtained from the transistor variable information 51 based thereon.

  The CPU 11 changes the layout circuit information table 34 by setting the acquired transistor information as error circuit information (step S196), and ends the ion implantation amount changing process. In this case, the transistor information 51-3 regarding the ion implantation amount 3 is set in the circuit information, and the designation of the ion implantation amount in the manufacturing process is changed from the ion implantation amount 1 to the ion implantation amount 3. Alternatively, the through and the load may be acquired from the table position specified in step S192 of the table for the ion implantation amount specified in step S195, and these may be combined and set in the circuit information.

  Next, the input transistor configuration change process executed in step S20 of FIG. 3 will be described. FIG. 5 is a flowchart for explaining the input transistor configuration change processing. In FIG. 5, the threshold voltage variable table 42 based on the parameter value for each parameter and the transistor variable information 52 based on the parameter value for each parameter are referred to by the CPU 11. Further, the threshold voltage variable table 42 based on the parameter value and the transistor variable information 52 based on the parameter value are stored, for example, in the storage device 17 of FIG.

  The threshold voltage variable table 42 based on parameter values is composed of a plurality of tables for each parameter such as gate length, gate width, S / D (source / drain) width, and the like. A table is prepared for each predetermined value from 1 to p. In this case, the threshold voltage Vth of the input transistor increases in order according to parameter values 1 to p in which the parameter value increases.

  For example, in the threshold voltage variable table 42 based on the gate length value, a table is prepared for each of the predetermined gate length values 1 to p, and the parameters and parameter values 1 to p are read as the gate length and the gate length value. be able to. The same applies to the gate width and S / D width. Regarding the S / D width, the threshold voltage variable table 42 may be prepared for each of the source width and the drain width, or the threshold voltage variable table 42 may be prepared for each combination of the source width and the drain width. .

  For example, in the table for the parameter value 1, through values from through 11 to through 1n are set in each row in the order in which the slope of input through increases, and loads from load 11 to load 1m in each column in order of increasing load. A matrix in which values are set. In this table, the sign of the delay is indicated by the through value and the load value when the parameter value is 1. Since the through value and load value are individually set in the table for each parameter value 1 to p, the table position on the table is specified, and the delay is reduced by referring to the subsequent tables in order from the current table. The state of changing from positive to negative or from negative to positive can be verified.

  The transistor variable information 52 based on the parameter value indicates transistor information 52-1 to 52 -p corresponding to the parameter values 1 to p of the threshold voltage variable table 42 based on the parameter value. The transistor information 52-1 to 52-p is detailed information related to the corresponding parameter values 1 to p, and includes, for example, information that is referred to in the manufacturing process when the parameter value is indicated.

  The transistor variable information 52 is also prepared for each parameter such as a gate length, a gate width, and an S / D (source / drain) width, similarly to the threshold voltage variable table 42 based on the parameter value. That is, in the transistor variable information 52 based on the gate length value, transistor information 52-1 to 52 -p is prepared corresponding to a predetermined gate length value 1 to p, and parameters and parameter values 1 to p are set. It can be read as gate length and gate length value. The same applies to the gate width and S / D width. Regarding the S / D width, the transistor variable information 52 may be prepared for each of the source width and the drain width, or the transistor variable information 52 may be prepared for each combination of the source width and the drain width.

  The CPU 11 determines a parameter to be changed based on the restriction of the error circuit configuration and the presence or absence of table reference (step S201). For example, in a layout in which the gate width of the input transistor is limited, first, the gate length is determined as a parameter. On the other hand, in a layout with no restriction on the gate width, first, the gate width is determined as a parameter. Further, when the gate length and the gate width already refer to the corresponding threshold voltage table 42, the S / D width is determined as a parameter. In this case, when the threshold voltage table 42 corresponding to the S / D width has already been referred to, the process result in step S201 cannot be determined as a parameter.

  Then, the CPU 11 determines whether or not the parameter has been determined by the process in step S201 (step S202). If the parameter cannot be determined, the CPU 11 proceeds to step S210 in which a buffer is inserted to avoid a negative delay. On the other hand, if the parameter can be determined, a threshold voltage variable table corresponding to the determined parameter to be changed (gate length, gate width, or S / D width) is acquired (step S203). For example, when the parameter for determining the gate length is determined, the threshold voltage variable table 42 based on the gate length value is acquired.

  Next, the CPU 11 specifies a table corresponding to the parameter value indicated in the circuit information acquired in step S17 of FIG. 3 from the threshold voltage variable table 42 based on the parameter value (step S204). When the parameter value (gate length value) of the circuit information is the parameter value 1 (gate length value 1), the table for the parameter value 1 is specified.

  The CPU 11 specifies the table position from the through information referred in step S15 by the through (inclination of input through) at the time of error detection and the load (step S204). When the table for the parameter value 1 is specified and the through information indicates the through 1i and the load 11, the row number “i” and the column specified by the through 1i and the load 11 are specified. The table position is specified by the combination with the number “1”.

  The CPU 11 refers to the tables in the order of increasing parameter values from the table specified in step S204 until the delay changes from positive to negative at the same table position (step S206). That is, in the table for the parameter value 1 specified in step S207, the delay is negative at the table position by the row number “i” and the column number “1”. In the order of the tables for..., The delay state at the table position by the same row number “i” and the column number “1” is checked, and the table in which the delay state first changes to negative is referred to. With reference to the table for the last parameter value p, the process in step S206 is terminated.

  Then, the CPU 11 first determines whether or not there is a table whose delay is changed from negative to positive (step S207). If there is no table in which the delay changes from negative to positive, that is, if the table for the parameter value p is referred to but the delay remains negative and does not change, the CPU 11 returns to step S201 to change other parameters. The same processing as described above is performed with the parameters.

  On the other hand, when there is a table in which the delay first becomes negative to positive, transistor information corresponding to the parameter value of the table is acquired from the transistor variable information 52 based on the parameter value (step S208). For example, when the parameter value 3 is changed to a positive delay in the table for the parameter value 3, the transistor information 52-3 corresponding to the parameter value 3 is acquired from the transistor variable information 52 based on the parameter value. When the gate length value 3 corresponds to the parameter value 3, transistor information 52-3 including information referred to in the manufacturing process for obtaining the gate length value 3 is acquired.

  The CPU 11 changes the layout circuit information table 34 by setting the acquired transistor information as error circuit information (step S209), and ends the input transistor configuration change processing. In this case, the transistor information 52-3 regarding the parameter value 3 is set in the circuit information, and the parameter value 1 (buffer length value 1) is changed to the parameter value 3 (buffer length value 3). Alternatively, the through and load may be acquired from the table position specified in step S205 of the table for the parameter value specified in step S208, and these may be combined and set in the circuit information.

  On the other hand, when determining in step S202 that the parameter could not be determined, the CPU 11 executes processing for inserting a buffer and adds the generated circuit information to the layout circuit information table 34 (step S210). . Then, the CPU 11 ends the input transistor configuration change process. Thus, since the buffer is inserted when there is no changeable parameter, the number of times the buffer is used can be reduced.

  From the above, by performing the ion implantation amount changing process in step S19 and the input and transistor configuration changing process in step S20 shown in FIG. 3, the ion implantation amount of the input transistor is changed to shorten the positive delay time, In addition, by avoiding the negative delay time and reducing the positive delay time, the difference between the minimum delay time and the maximum delay time of the data signal timing and the clock signal timing in the timing verification can be made substantially equal. It becomes. That is, the threshold voltage Vth can be changed so that the difference between the minimum delay time and the maximum delay time is substantially equal.

  Therefore, an increase in circuit scale and an increase in power supply due to repeated insertion of circuits such as buffers can be suppressed.

  The above-described simulation system 100 according to the present invention is applied to a CAD (Computer Aided Design) system or the like.

Regarding the above description, the following items are further disclosed.
(Appendix 1)
In a circuit design method in which a computer performs circuit design, the computer includes:
By referring to a plurality of parameter value tables indicating the positive and negative delay times in accordance with the slope of the input slew and the load for each parameter value of the input circuit constituting the circuit, the circuit showing the negative delay time becomes a positive delay time. Parameter value acquisition procedure to acquire the parameter value when changing to
A circuit design changing method for executing a circuit configuration change procedure for changing the configuration of the input circuit in the circuit using the acquired parameter value.
(Appendix 2)
The computer is
Performing a through slope determination procedure for determining whether the input through slope of the circuit is greater than or equal to the output through slope;
The circuit design method according to appendix 1, wherein the parameter value acquisition procedure and the circuit configuration change procedure are validated when the slope of the input through is equal to or greater than the slope of the output through.
(Appendix 3)
The computer is
When the slope of the input slew is smaller than the slope of the output slew, a plurality of ion implantation amount tables showing the positive / negative of the delay time depending on the slope of the input through and the load for each ion implantation amount to the input circuit constituting the circuit By referring to an ion implantation amount acquisition procedure for acquiring an ion implantation amount indicating a positive delay time when changing from a positive delay time to a negative delay time,
3. The circuit design method according to appendix 2, wherein an ion implantation amount designation changing procedure for changing designation of an ion implantation amount to the input circuit in the circuit is executed using the acquired ion implantation amount.
(Appendix 4)
The through inclination determination procedure includes:
A first slope calculation procedure for calculating a slope per unit time until an input signal of an input circuit in the circuit reaches a threshold voltage as the slope of the input through;
The circuit according to appendix 2 or 3, further comprising a second slope calculation procedure for calculating a slope per unit time until an output signal of an output circuit in the circuit reaches a threshold voltage as the slope of the output through. Design method.
(Appendix 5)
The circuit design method according to any one of appendices 1 to 4, wherein the parameter value acquired by the parameter value acquisition procedure increases a threshold voltage of the input circuit.
(Appendix 6)
A simulation system for designing a circuit by a computer,
First changing means for increasing the threshold voltage of the input circuit by changing the configuration of the input circuit in the circuit exhibiting a negative delay time;
A simulation system comprising: second changing means for lowering a threshold voltage of the input circuit by changing an ion implantation amount of the input circuit in the circuit exhibiting a positive delay time.
(Appendix 7)
The first changing means includes
By referring to a plurality of parameter value tables indicating the positive and negative delay times in accordance with the slope of the input slew and the load for each parameter value of the input circuit constituting the circuit, the circuit showing the negative delay time becomes a positive delay time. Parameter value acquisition means for acquiring a parameter value when changing to
The simulation system according to claim 6, further comprising circuit configuration changing means for changing the configuration of the input circuit in the circuit using the acquired parameter value.
(Appendix 8)
The second changing means includes
The delay time from positive to negative is changed by referring to a plurality of ion implantation amount tables indicating the positive / negative of the delay time by the slope of the input through and the load for each ion implantation amount to the input circuit constituting the circuit in a predetermined order. An ion implantation amount acquisition means for acquiring an ion implantation amount indicating a positive delay time, and
The simulation system according to appendix 6 or 7, further comprising ion implantation amount designation changing means for changing designation of an ion implantation amount to the input circuit in the circuit using the acquired ion implantation amount.
(Appendix 9)
A simulation system for designing a circuit by a computer,
A plurality of parameter value tables indicating the positive and negative of the delay time with the slope of the input through and the load for each parameter value of the input circuit constituting the circuit,
Parameter value acquisition means for acquiring a parameter value when a circuit showing a negative delay time is changed to a positive delay time by referring to the parameter value table in a predetermined order;
A simulation system comprising circuit configuration changing means for changing the configuration of the input circuit in the circuit using the acquired parameter value.
(Appendix 10)
A computer-readable storage medium storing a program for causing a computer to perform circuit design processing,
By referring to a plurality of parameter value tables indicating the positive and negative delay times in accordance with the slope of the input slew and the load for each parameter value of the input circuit constituting the circuit, the circuit showing the negative delay time becomes a positive delay time. Parameter value acquisition procedure to acquire the parameter value when changing to
A computer-readable storage medium storing a program for executing a circuit configuration change procedure for changing a configuration of the input circuit in the circuit using the acquired parameter value.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

It is a figure which shows the hardware constitutions of the simulation system which concerns on one Example of this invention. It is a figure for demonstrating the outline | summary of a circuit design process. It is a flowchart figure for demonstrating the outline | summary of a circuit design process. It is a flowchart for demonstrating ion implantation amount change processing. It is a flowchart for demonstrating an input transistor structure change process.

Explanation of symbols

11 CPU
DESCRIPTION OF SYMBOLS 12 Memory unit 13 Display unit 14 Output unit 15 Input unit 16 Communication unit 17 Storage device 18 Driver 19 Storage medium 100 Simulation system

Claims (4)

In a circuit design method in which a computer performs design of arrangement and wiring of a plurality of cells in a circuit based on circuit information including information on each cell , the computer includes:
One of a plurality of parameter value tables prepared for each parameter value of the cell and storing a value indicating a positive / negative delay time corresponding to a combination of an input slew value and a load value of an input side circuit of the cell. A first table specifying procedure for specifying based on a parameter value of a cell in the circuit information;
A first table for specifying a table position on the parameter value table specified in the first table specifying procedure based on the input slew value and the load value of the input side circuit calculated based on the circuit information A location procedure;
The table position identical to the table position specified in the first table position specifying procedure in each parameter value table other than the parameter value table specified in the first table specifying procedure is sequentially increased in order of increasing parameter values. A parameter value acquisition procedure for acquiring a parameter value when the reference delay time changes from positive to negative or from negative to positive by referring;
A circuit design change procedure for executing a circuit configuration change procedure for changing a parameter value of the cell of the circuit information to a parameter value acquired in the parameter value acquisition procedure . The computer is
A plurality of ion implantation amount tables prepared for each ion implantation amount of the input side circuit of the cell and storing values indicating positive and negative delay times corresponding to combinations of input through values and load values of the input side circuit A second table specifying procedure for specifying one of them based on an ion implantation amount in the circuit information;
A second table position specifying procedure for specifying a table position on the ion implantation table specified in the second table specifying procedure based on an input slew value and a load value calculated based on the circuit information;
The same table position as that specified in the second table position specifying procedure of each ion implantation table other than the ion implantation table specified in the second table specifying procedure is sequentially increased in order of increasing ion implantation amount. An ion implantation amount identifying procedure for identifying an ion implantation amount that exhibits a positive delay time immediately before the reference delay time changes from positive to negative by referring to;
The circuit design method according to claim 1 , wherein an ion implantation amount designation changing procedure for changing the ion implantation amount of the circuit information to the ion implantation amount specified in the ion implantation amount specifying procedure is executed . A simulation system for performing placement and wiring design of a plurality of cells in a circuit based on circuit information including information on each cell by a computer ,
One of a plurality of parameter value tables prepared for each parameter value of the cell and storing a value indicating a positive / negative delay time corresponding to a combination of an input slew value and a load value of an input side circuit of the cell. First table specifying means for specifying based on a parameter value of a cell in the circuit information;
A first table for specifying a table position on the parameter value table specified by the first table specifying means based on the input through value and load value of the input side circuit calculated based on the circuit information Positioning means;
The table position identical to the table position specified by the first table position specifying means in each parameter value table other than the parameter value table specified by the first table specifying means is sequentially increased in order of increasing parameter values. Parameter value acquisition means for acquiring a parameter value when the referenced delay time changes from positive to negative or from negative to positive by referring;
A simulation system comprising circuit configuration changing means for changing a parameter value of the cell of the circuit information to a parameter value acquired by the parameter value acquiring means . A plurality of ion implantation amount tables prepared for each ion implantation amount of the input side circuit of the cell and storing values indicating positive and negative delay times corresponding to combinations of input through values and load values of the input side circuit Second table specifying means for specifying one of them based on an ion implantation amount in the circuit information;
Second table position specifying means for specifying the table position on the ion implantation table specified by the second table specifying means based on the input slew value and the load value calculated based on the circuit information;
The table positions identical to the table positions specified by the second table position specifying means of each ion implantation table other than the ion implantation table specified by the second table specifying means are sequentially increased in order of increasing ion implantation amount. An ion implantation amount specifying means for specifying an ion implantation amount indicating a positive delay time immediately before the reference delay time changes from positive to negative by referring to;
4. The simulation system according to claim 3, further comprising ion implantation amount designation changing means for changing the ion implantation amount of the circuit information to an ion implantation amount specified by the ion implantation amount specifying means.

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