JP4621424B2 - Programmable logic circuit and wiring structure of programmable logic circuit - Google Patents

Description

  The present invention relates to a programmable logic circuit and a wiring structure of a programmable logic circuit that can realize logic circuit elements having various functions by changing a program by a user.

  In recent years, programmable logic circuits such as a programmable logic device (PLD) and a field programmable gate array (FPGA) have been rapidly spread because a user can realize various functions by a program. A programmable logic circuit is generally composed of an interconnection network having a plurality of switch blocks that can be changed in connection and a plurality of logic blocks that can be connected via the interconnection network.

  Regarding the interconnection network, Freeman's FPGA interconnection network technology has been proposed (Patent Document 1). In summary, this technique builds an FPGA interconnect network using short wiring segments and flexible switch connections.

  Carter has also proposed a technique for eliminating switch blocks between adjacent logical blocks by adding a direct connection path between adjacent logical blocks in addition to Freeman's interconnection network ( Patent Document 2). This can reduce the delay of adjacent logical blocks somewhat.

  Leon et al. Have proposed a technique in which a direct path is provided between adjacent four-way logic blocks, and a switch block is used to connect them to a wide-area interconnection network (Patent Document 3).

  On the other hand, Green et al., In addition to the proposals by Freeman and Carter, perform wiring across two or more logical blocks that are longer than singles connecting adjacent basic cells, such as doubles, quads, etc. An interconnection network having a long horizontal wiring segment and a vertical wiring segment is proposed (Patent Document 4). As a result, wiring having a long path can be connected with a small number of switch blocks, and the delay on the signal system path can be reduced. Programmable logic circuits based on these proposals have been commercialized as Xilinx FPGA XC4000 series by Xilinx, USA.

Lady et al. Have proposed a technique for reducing the delay of a signal path between any two logical blocks by hierarchizing an interconnection network (Patent Document 5). In summary, the number of switch blocks intervening between logical blocks across groups can be reduced by combining multiple stages of interconnection network within a group of logical blocks and interconnection network between groups. It is. Programmable logic circuits based on this proposal have been commercialized as the CPLD FLEX series of Altera Corp., USA.
US Reissue Patent No. 34363 U.S. Pat. No. 4,642,487 US Pat. No. 5,537,057 US Pat. No. 5,077,729 US Pat. No. 5,883,526

  However, in the conventionally proposed technique (invention) as described above, since the connection is always made via a switch block (a switch for selectively switching the connection relationship) in the horizontal direction or the vertical direction, the same wiring is used. The connection between two basic cells (or between switch blocks) that do not exist on the track cannot be connected without passing through at least one switch block. In addition, since the wiring types are limited, it is necessary to combine a plurality of wiring types even in the same direction. As a result, the number of switches in the signal path increases.

  On the other hand, a technique of using a long line in which the wiring length is extended to the end in the horizontal direction (row direction) or the vertical direction (column direction) has been proposed. Unlike the wiring tracks such as singles, doubles, and quads, this long line can be connected in the same direction (only in the row direction or only in the column direction) without using a switch block. However, when this wiring is used, there is a fatal problem that an unusable wiring track is generated at the end.

  As described above, in the conventionally proposed programmable logic circuit having a connection-changeable interconnection network, since the number of switch blocks affects the delay in the signal path, attempts have been made to reduce the number. However, no technology that can achieve a sufficient effect has been proposed yet. In addition, the conventional programmable logic circuit having a regular wiring structure has a problem that 80 to 90% of the chip area is a wiring area, and the wiring usage rate is low.

  The present invention has been made in view of such problems, and its object is to reduce the number of switch blocks used in the signal path of the interconnection network, thereby reducing signal transmission and computation delays. It is an object of the present invention to provide a programmable logic circuit and a programmable logic circuit wiring structure capable of improving the wiring utilization rate and reducing the chip area.

  In the first programmable logic circuit of the present invention, a plurality of basic cells having logic blocks for performing a logical operation are arranged in a matrix, and have a wiring track connecting the basic cells. In a programmable logic circuit having a switch block in which all or a part of basic cells determine a connection relationship with a basic cell other than itself according to connection information, the wiring tracks are arranged in the matrix form Wiring is performed to form a small world network as a network connecting a plurality of basic cells.

  The wiring structure of the first programmable logic circuit according to the present invention includes a plurality of basic cells having logic blocks for performing a logical operation arranged in a matrix, and has a wiring track connecting the basic cells. In the wiring structure of a programmable logic circuit having a switch block in which all or a part of the plurality of basic cells determine a connection relationship with a basic cell other than itself according to connection information, the wiring track is The wiring is made so as to form a small world network as a network connecting a plurality of basic cells arranged in a matrix.

  That is, in the first programmable logic circuit of the present invention or the wiring structure thereof, the wiring tracks are wired so as to form a small world network as a network connecting a plurality of basic cells arranged in a matrix. Any two basic cells can be connected by passing through a small number of switch blocks.

  In the second programmable logic circuit of the present invention, a plurality of basic cells having logic blocks for performing logical operations are arranged in a matrix, and each of the basic cells is regularly arranged with respect to the basic cells other than itself. In a programmable logic circuit having a basic cell having a switch block that has a wiring track connected in a simple connection relationship and has a switch block that determines a connection relationship with a basic cell other than itself according to connection information. A shortcut wiring track is provided in which a part of a network composed of regularly connected wiring tracks is replaced with a wiring that directly connects basic cells randomly selected with a predetermined probability.

  The wiring structure of the second programmable logic circuit according to the present invention includes a plurality of basic cells each having a logic block for performing a logical operation arranged in a matrix, and has a wiring track for connecting the basic cells. In a wiring structure of a programmable logic circuit having a basic cell having a switch block that determines a connection relationship with a basic cell other than itself according to given connection information, the wiring tracks are arranged in the matrix form. In addition, wiring is performed so as to form a small world network as a network connecting a plurality of basic cells.

  That is, in the second programmable logic circuit or the wiring structure thereof according to the present invention, a part of the network composed of regularly connected wiring tracks is replaced with wiring that directly connects basic cells randomly selected with a predetermined probability. Since the shortcut wiring track is provided, any two basic cells can be connected to each other through a small number of switch blocks by connecting via the shortcut wiring track.

  The second programmable logic circuit or its wiring structure according to the present invention is more specifically described in detail. The number of basic cells provided with the switch block is M, and the regular connection relation per basic cell. If the number of wiring tracks provided for N is N and the predetermined probability is p, two of the M basic cells are selected at random, and the two selected basic cells are connected to each other. By providing the shortcut wiring track along the shortest Manhattan route between the two times p × N times to construct a network including the shortcut wiring track, A world network can be configured.

  According to the programmable logic circuit of the present invention or the wiring structure of the programmable logic circuit, first, wiring tracks are wired so as to form a small world network as a network connecting a plurality of basic cells arranged in a matrix. Thus, it is possible to connect any two basic cells with only a small number of switch blocks, thereby reducing signal transmission and computation delay. Second, since a part of the network composed of regularly connected wiring tracks is replaced with a wiring that directly connects the basic cells randomly selected with a predetermined probability, a shortcut wiring track is provided. By connecting via the shortcut wiring track, it is possible to connect any two basic cells with only a small number of switch blocks, thereby reducing signal transmission and computation delays. Can be made.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 schematically shows a configuration of a main part of a programmable logic circuit according to an embodiment of the present invention. FIG. 2 schematically shows the configuration of the main part of the basic cell. In addition, in order to avoid complication, illustration and detailed description of the controller etc. for performing connection control of a switch block were abbreviate | omitted.

  This programmable logic circuit includes a basic cell 1, and regular wiring tracks 2 and irregular shortcut wiring tracks 3 that connect adjacent basic cells 1 constituting a wiring network as main parts. .

  The basic cell 1 is an individual logic cell constituting the basic cell groups 111 to 177 arranged in a matrix (matrix array) on one semiconductor substrate in the programmable logic circuit. This basic cell 1 includes a logic block 11 that performs an N-bit input logic operation, a switch block 12 that selectively connects the wiring track 2 or the shortcut wiring track 3 to the logic block 11 in the basic cell 1, A connection block 13 for mediating the connection between the block 11 and the switch block 12 and a controller (not shown) for controlling the connection of the switch block 12 are included.

(Logical block)
The logic block 11 which is the most main part of the basic cell 1 as a logic cell is a block that performs logic processing based on an input signal, and is a LUT (Look Up Table) or FF (Flip- Flop) and the like. The input / output signal terminals of the logic block 11 are joined to the connection block 13.

(Switch block)
The switch block 12 is provided at each position where the horizontal (row direction) wiring track 211 and the vertical (column direction) wiring track 212 intersect, for example, between horizontal wirings or according to a control signal. It is set so that the connection state between the wirings or the combination of the horizontal wiring and the vertical wiring can be switched and the connection state can be maintained.

  Information about the connection relationship of the switch block 12 set with the logic block 11 via the wiring track 2 or the shortcut wiring 3 is stored in a configuration memory (not shown) or the like. It is possible to program based on the programmed configuration data. This connection relationship is controlled by supplying connection information to the switch block 12 from a controller (not shown).

(Connection block)
One connection terminal of the connection block 13 is connected to the switch block 12 in its own basic cell 1, and the other connection terminal is connected to the other basic terminal via at least one of the wiring track 2 and the shortcut wiring track 3. It is connected to the switch block 12 of the cell 1 (at least one basic cell 1 outside the own basic cell 1), and the other terminal is also connected to the logic block 11 in the own basic cell 1. Yes. An input signal transmitted from an external basic cell 1 (not shown in FIG. 2) is input to the logic block 11 in the basic cell 1 focused in FIG. Conversely, the output signal from the basic cell 1 is transmitted to the external basic cell 1. Therefore, this connection block 13 is for making a signal exchange connection between its own basic cell 1 and the external basic cell 1.

(Wiring track)
The wiring track 2 and the shortcut wiring track 3 are wirings for connecting the basic cells 1 to form a desired circuit. Generally, as the regular wiring track 2, a plurality of types of wirings (singles, doubles, quads, long lines) having a prescribed length are arranged in the horizontal direction (211) and the vertical direction (212), respectively.

  More specifically, as an example of the regular wiring track 2, as shown in FIG. 4, between the adjacent basic cells 1 (for example, between the basic cell 111 and the basic cell 112 in FIG. A wiring (Singles 201) for connecting the most basic and small units (between one switch block) as between 111 and the basic cell 121 (for example, between the basic cells 111) Between two switch blocks (such as between the basic cell 111 and the basic cell 131) and between the basic cell 113 and the basic cell 131 without using the switch block 12 (doubles 202). Between the basic cells 1 (for example, between the four switch blocks such as between the basic cell 111 and the basic cell 115 or between the basic cell 111 and the basic cell 151). Directly connected to the wiring (Kuwazzu 203), and the like wiring for connecting between the adjacent basic cells 1 at a position spaced over long distances (long line 204) without using the. The long line 204 connects between two basic cells 1 on either a horizontal direction (also referred to as a row direction or an x direction) or a vertical direction (also referred to as a column direction or a y direction). . These wiring tracks 2 (201, 202, 203, 204) are regularly provided for each basic cell in the conventional general programmable logic circuit.

  In the programmable logic circuit according to the present embodiment, in addition to the regular wiring track 2 as described above, the shortcut wiring track 3 that is intentionally broken and configured to form a small world network is connected to all wiring. It is provided in the network at a predetermined rate (with a probability described later). By this shortcut wiring track 3, two basic cells 1 at a distant position are directly connected in a bypass manner in both the x direction and the y direction (the switch block 12 at the intersection of the x direction and the y direction is connected). The connection relationship by the small world network can be configured without going through all the switch blocks 12 in between.

(Small World Network)
Here, the basic principle of the small world network will be described. As schematically shown in FIG. 3, a random network (B) having no regularity in connection between all nodes 330, a regular network (A) in which all nodes 330 are regularly connected, and the intermediate There are three types of networks: small world network (C) in which only the connections between nodes 330 are not partly regularly linked (anomalous). In the regular network (A), the connection cost (the amount and density of connections) is low because of a completely regular connection structure. For example, when connecting distant nodes 330, a large number of links (connections) are connected between them. Therefore, the average distance between arbitrary nodes 330 (the average value obtained by dividing the total distance of connections between all nodes 330 by the number of connections) is large. Further, in the random network (B), the long distance nodes 330 are directly connected to each other by breaking the regular wiring regularity in the regular network (A) for all the nodes 330. Therefore, the average distance between arbitrary nodes 330 is determined. Is small, but has a high connection cost due to the structure having a large number of links at random. However, the small mold network (C) is different from the above two types of networks (A; regular) and (B; random), and breaks the complete regularity as in the regular network (A). The connection structure is partly anomalous, so it is also different from a completely random connection structure as in the random network (B). As a result, in the small world network (C), long-distance nodes are directly connected by an irregular link (connection), and the connection cost (the cost for establishing a link required for connection) can be reduced. And the distance between arbitrary nodes can be made small. Further, in the small mold world network (C), by optimizing the connection structure as described above, the average distance between any two nodes can be shortened to approximate a random network.

  That is, when the above is summarized, when an attempt is made to construct a random network, the amount (distance and density) of links (connections) increases compared to the case of a regular network. On the other hand, in a regular network, the average distance of connection becomes large. However, according to the small world network, by providing a small amount of shortcut links, the average distance of connection between any two nodes can be reduced to the same level as a random network. In addition, since only a small amount of link is required, the connection cost does not increase or is small compared to the regular network. As a result, the connection cost can be reduced to almost the same as that of the random network. The small world network has such a very effective advantage. Therefore, the advantage of such a small world network is used for a programmable logic circuit. In other words, the “node” in the above description based on the discrete mathematical model is the basic cell 1 (more specifically, the internal switch block 12), and the “link (or connection)” is the wiring track 2. As a basic principle, by adopting a wiring structure based on the small world network as schematically described in such a model, it is more than a conventional programmable logic circuit having a completely regular wiring structure. The wiring cost can be reduced, and therefore the occupation ratio of the wiring area in the chip area can be reduced, and the average wiring distance between any two basic cells can be set to a random network wiring structure. An excellent programmable logic circuit can be realized that can be made shorter than in the case of a logic circuit, and therefore can reduce signal transmission and operation delays.

(Numericalization of small world network)
The small world network can be numerically characterized by the shortest average path length L, the cluster coefficient C, and the number of nodes n. That is, in the small world network, n is large, L is close to the random network, and C is extremely large compared to the random network. Therefore, by constructing a wiring network having the shortcut wiring track 3 conforming to the small world network in a programmable logic circuit having a large number of basic cells 1, the shortest average path length L becomes close to a random network, and regular The average wiring length can be shortened as compared with the case of only the wiring track 2, and the wiring cost performance can be made extremely higher than that of the case of only the regular wiring track 2.

(Average path length L)
The shortest average path length L in the programmable logic circuit according to the present embodiment is an average of the distance Lij between any basic cells 1. Here, Lij is a wiring length necessary for connecting the basic cell 1i and the basic cell 1j in the shortest distance. By calculating their average, the shortest average path length Li for the basic cell 1i can be obtained. Therefore, the shortest average path length L of the network can be calculated by obtaining L for all the basic cells 1 and averaging them.

(Small world network connection method)
Next, a method for constructing a wiring network conforming to the small world network will be described. First, consider a regular network in which all the wiring of the switch block 12 of each basic cell 1 is a regular wiring track 2. FIG. 5 shows a configuration of a main part of a conventional general regular network logic circuit in which all wirings are regular wiring tracks.

  The basic cells 1 (111 to 177) are arranged in a so-called matrix. Each basic cell 1 can be connected to an adjacent basic cell 1 using internal wiring. Here, “adjacent” means an arrangement relationship in which the basic cells 1 are adjacent to each other without interposing other basic cells 1.

  For example, in FIG. 5, the basic cell 162 is adjacent to a total of four basic cells 1 of the basic cells 161, 163, 152, and 172. In this case, the basic cell 162 is connected to the adjacent basic cells 161, 163, 152, 172 via the wiring tracks 2 (261, 263, 252, 272), respectively.

  A small world network is constructed by replacing a part of the wiring network having only the regular wiring track 2 as described above with the shortcut wiring track 3. Here, in the wiring network having the conventional regular wiring track 2 as described above, the switch block 12 of each basic cell 1 is connected to the switch blocks 12 other than itself by N singles 201. To do. In addition, the number of switch blocks 12 included in the wiring network is M, and the probability of switching is p.

  First, as a first step, two switch blocks 12 are randomly selected from the M switch blocks 12 (in other words, the basic cell 1) in the wiring network having the regular wiring tracks 2 described above.

  Next, as a second step, the wires of the singles 201 are connected together along a route (shortest Manhattan route) that is the shortest Manhattan distance between the two selected switch blocks 12, and a switch in the middle is connected. It is assumed that one shortcut wiring track 3 is directly connected without substantially passing through the block 12.

By performing the operations of the first step and the second step p × N times, it is possible to construct a wiring network in which regular wiring tracks 2 and irregular shortcut wiring tracks 3 are mixed. .

(Shortest Manhattan route)
Here, the above shortest Manhattan distance means that a certain basic cell 1a (the position in the matrix is (x1, y1)) and the basic cell 1b (the position in the matrix is (x2, y2)). The distance between the two points is expressed as | x1-x2 | + | y1-y2 |. A route that takes such a distance is called a shortest Manhattan route.

(Program storage method)
An FPGA (Field Programmable Gate Array) generally includes a plurality of logic cells that can be programmed with functions and wiring that can be programmed to connect the logic cells. The main part is configured (not shown). Program information of logic cells and wiring in each basic cell of such an FPGA is stored by a memory such as a static random access memory (SRAM) built in the FPGA or a state of a fuse. The The circuit function of the logic cell is determined according to the contents of the connected memory and the state of the fuse. Also, the wiring program is executed by determining the state of the switch of the wiring network according to the contents of the memory and the state of the fuse.

  When program information is stored in a rewritable memory element such as an SRAM, it can be reprogrammed (program rewriting) by rewriting the memory contents. On the other hand, when program information is stored according to the state of the fuse, it is not possible to re-program it once it has been programmed.

  It goes without saying that such a program storage method can also be used in the programmable logic circuit according to the present embodiment.

  Next, the operation of the programmable logic circuit according to the present embodiment will be described focusing on the operation of the small world network including the shortcut wiring track 3 in particular.

(Operation of small world network)
As shown in FIG. 1, when a signal path from the basic cell 172 to the basic cell 137 is formed by a program, first, the basic cell 172 is connected to the basic cell 136 via the shortcut wiring track 301. By going through the shortcut wiring track 301, all of the seven basic cells 173, 174, 175, 176, 166, 156, and 146 in the course of the route do not go through the switch block 12. During this time, the switch cell 12 is “bypassed” or “shortcut”, and the basic cell 172 and the basic cell 136 are directly connected. At this time, it is important for the operation of the programmable logic circuit according to the present embodiment that the switch block 12 of the basic cell 176 located at the intersection of the path in the x direction and the path in the y direction is not used. The basic cell 136 is connected to the basic cell 137 by selecting connection by the singles wiring track 236 by the switch block 12 of its own.

  Thus, in the programmable logic circuit according to the present embodiment, when the signal path from the basic cell 172 to the basic cell 137 is formed by the program, it is used by (via use) the shortcut wiring track 301. The number of switch blocks 12 to be performed can be extremely small, such as one switch block 12 in the basic cell 136.

  The shortcut wiring track 302 that directly connects the basic cell 151 and the basic cell 135 and the shortcut wiring track 303 that directly connects the basic cell 113 and the basic cell 145 are similar to the shortcut wiring track 301 described above. As a result, the number of switch blocks 12 used in the path can be extremely small.

  On the other hand, as a comparative example, in a programmable logic circuit having only a conventional general regular wiring track 2 as shown in FIG. 5, the signal path from the basic cell 172 to the basic cell 137 is programmed by the program as described above. Consider the case of forming. In the case where the wiring network is configured only from the singles wiring track 2 without the doubles or the like, the signal path from the basic cell 172 to the basic cell 137 is the basic cell 173, 174, 175, 176, A total of seven switch blocks 12 of 166, 156, and 146 are used (used), and the number thereof is extremely large.

  Even if the basic cell 172 to the basic cell 176 can be connected by the quad wiring track 270, the three switch blocks 12 between them are not used (by “bypassing”), and the basic cell 172 is changed to the basic cell. 176 can be directly connected to the base cell 176, but when the connection path is changed from the horizontal direction (x direction) to the vertical direction (y direction) in the basic cell 176, the switch block 12 of the basic cell 176 is used, A connection in the vertical direction (y direction, in other words, from the basic cell 176 to the basic cell 136) must be selected. The basic cell 176 is directly connected to the basic cell 136 via the quad wiring track 271. At this time, the switch cell 12 of the basic cell 176 is used to select the quad wiring track 271 and the basic cell 136. The switch block 12 must be used to select a connection to the basic cell 137. Therefore, in this case, at least two switch blocks 12 are used in total.

  As another example, consider a case where the basic cell 162 and the basic cell 137 are connected. In the programmable logic circuit according to the present embodiment, the basic cell 162 is temporarily connected to the adjacent basic cell 172, and the basic cell 136 is connected via the shortcut wiring track 301 using the switch block 12 of the basic cell 172. Connecting. In the basic cell 136, the singles wiring track 236 is selected using its own switch block 12 and connected to the basic cell 137. In this way, the basic cell 162 and the basic cell 137 can be connected by using a total of two switch blocks 12 including the basic cell 172 and the basic cell 136 in the course of the route.

  On the other hand, in the case of the conventional general programmable logic circuit shown in FIG. 5 having only the regular wiring tracks 2 of singles, doubles, quads, and global, the basic cell 162 passes through the quads wiring track 272. The basic cell 166 is connected to the adjacent basic cell 156 through the singles wiring track 201 by using its own switch block 12. At this time, the switch block 12 of the basic cell 156 is used. In the basic cell 156, the doubles wiring track 202 is selected and connected to the basic cell 136 using its own switch block 12. In the basic cell 136, the singles wiring track 236 is selected and connected to the basic cell 137 using its own switch block 12. In this way, the basic cell 162 and the basic cell 137 can be connected by using a total of three switch blocks 12 in the middle of the route, but the number of switch blocks 12 in this case is three. The number is one more than that of the programmable logic circuit according to the present embodiment.

  Thus, according to the programmable logic circuit according to the present embodiment, the number of switch blocks used in the signal path is reduced by optimizing the wiring network in the programmable logic circuit in accordance with the small world network. As a result, signal transmission and computation delay can be reduced.

  If the wiring method includes the shortcut wiring track 3 capable of constructing a wiring network in which L is close to a random network and C is an extremely large network compared to the random network, Other than the wiring method strictly conforming to such a small world network, it can be applied as the programmable logic circuit of the present invention or the wiring structure thereof.

  That is, the shortcut wiring track 3 is provided with a wiring that directly connects the two basic cells 1 existing in positions separated in both the row direction and the column direction without going through the switch block 12. Thus, for example, between the basic cell 122 and the basic cell 166, without optimizing the probability p to a numerical value that can realize the optimization of the average distance, or without necessarily selecting the basic cell 1 completely at random. The appropriate number of shortcut wiring tracks 3 that connect two basic cells 1 that exist at positions separated in both the row direction and the column direction, such as the connection of, are mixed in the wiring network. You may do it. Even if this is done, there is a high probability that the effect will be less than that of the wiring method strictly following the small world network as described above, but it is still sufficiently effective compared to the conventional wiring structure. In particular, the number of switch blocks used can be reduced, and the average wiring distance can be reduced and the wiring efficiency can be improved.

  It goes without saying that the switch block 12 of the basic cell 1 in which the regular wiring track 2 is replaced with the shortcut wiring track 3 may be omitted for the switch relating to the replaced wiring track 2. This is because the switch of the wiring replaced with the shortcut wiring track 3 is bypassed (or shortcut) by the shortcut wiring track 3 and is not used, and can be omitted.

  In addition, the wiring network including the shortcut wiring track 3 is formed in accordance with the request of the customer (user) in a so-called ASIC (Application Specific Integrated Circuit) landing process (the wiring structure is built in hardware). Etc. are also possible. That is, a method for forming a wiring structure in accordance with the small world network as described above corresponding to the customer's required function is prepared in advance by preparing a general gate array as a so-called base wafer. Thus, a wiring network including the shortcut wiring track 3 may be formed.

  In addition, it goes without saying that the present invention is not limited to the above-described embodiment, and various modifications can be made.

  For example, the present invention can be applied to a programmable logic circuit such as an FPGA that can realize logic circuit elements having various functions by changing a program by a user and a wiring structure of the programmable logic circuit.

It is the figure which represented typically the structure of the principal part of the programmable logic circuit which concerns on one embodiment of this invention. It is the figure which represented typically the structure of the principal part of the basic cell in the programmable logic circuit shown in FIG. It is a figure showing the basic concept of a small world network. It is a figure showing an example of the kind of regular wiring track. It is the figure which represented typically the structure and wiring network of the principal part of the conventional common programmable logic circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Basic cell, 2 ... Wiring track, 3 ... Shortcut wiring track, 11 ... Logic block, 12 ... Switch block, 13 ... Connection block

Claims (6)

A plurality of basic cells having logic blocks for performing a logical operation are arranged in a matrix and have wiring tracks connecting the basic cells, and all or a part of the plurality of basic cells is other than itself In a programmable logic circuit having a switch block that determines a connection relationship with a basic cell in accordance with given connection information,
The programmable logic circuit, wherein the wiring track is wired so as to form a small world network as a network connecting the plurality of basic cells arranged in a matrix. A plurality of basic cells having logical blocks for performing logical operations are arranged in a matrix, and each of the basic cells has a wiring track connected to a basic cell other than itself in a regular connection relationship. In a programmable logic circuit having a basic cell with a switch block that determines a connection relationship with a basic cell other than itself according to given connection information,
Programmable, comprising a shortcut wiring track in which a part of the network composed of regularly connected wiring tracks is replaced with a wiring directly connecting basic cells randomly selected with a predetermined probability Logic circuit. When the number of basic cells having the switch block is M, the number of wiring tracks provided for the regular connection relation per basic cell is N, and the predetermined probability is p. Selecting two of the M basic cells at random, and providing the shortcut wiring track along the shortest Manhattan path between the two selected basic cells p × N times The programmable logic circuit according to claim 2, wherein a network including the shortcut wiring track is constructed. A plurality of basic cells having logic blocks for performing a logical operation are arranged in a matrix and have wiring tracks connecting the basic cells, and all or a part of the plurality of basic cells is other than itself In the wiring structure of the programmable logic circuit having a switch block that determines the connection relationship with the basic cell according to the given connection information,
A wiring structure of a programmable logic circuit, wherein the wiring track is wired to form a small world network as a network connecting a plurality of basic cells arranged in a matrix. A plurality of basic cells having logical blocks for performing logical operations are arranged in a matrix, and each of the basic cells has a wiring track connected to a basic cell other than itself in a regular connection relationship. In a wiring structure of a programmable logic circuit having a basic cell with a switch block that is determined according to connection information given a connection relationship with a basic cell other than itself,
A programmable logic comprising a shortcut wiring track by replacing a part of a network composed of the regularly connected wiring tracks with a wiring that directly connects basic cells randomly selected with a predetermined probability. Circuit wiring structure. When the number of basic cells having the switch block is M, the number of wiring tracks provided for the regular connection relation per basic cell is N, and the predetermined probability is p. Selecting two of the M basic cells at random, and providing the shortcut wiring track along the shortest Manhattan path between the two selected basic cells p × N times The wiring structure of the programmable logic circuit according to claim 5 , wherein a network including the shortcut wiring track is constructed.

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