JP2008047708A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can cut standby power consumption in a structured ASIC. <P>SOLUTION: The circuit has a circuit column of M (M is an integer of 2 or more) columns, and a program column of (M-1) columns having a lookup table (LUT) structure which uniquely decides arbitrary input logic. The program column is disposed between circuit columns, and before redundancy, it has a structure connected to a circuit column adjacent to a first side. When a prescribed circuit column is defective, a program column wherein a defective circuit column is arranged one by one from the program column positioned in the first side is subjected to cell arrangement by a column shift redundant method connected to the circuit column adjacent to a second side. Each circuit 220 has a structure which can supply power for each constituent element, and a constituent element unnecessary for circuit operation is separated from a power supply in the circuit 220. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a plurality of modules whose functions can be substituted for each other.

  In recent years, in semiconductor integrated circuits, processing dimensions have been miniaturized and circuit configurations have been increased in scale, resulting in a serious decrease in yield due to manufacturing defects. Therefore, a method has been proposed in which a redundant circuit is provided in advance in a part of the entire circuit, and the defective portion is replaced with the redundant circuit so that the entire semiconductor chip does not become a defective product.

  For example, in the logic circuit data generation method of FPGA (field programmable gate array) described in Patent Document 1, the necessity of failure avoidance is determined from failure information and logic information, and if necessary, the function of the failure portion is determined as an empty portion. Change the logical information to substitute.

  In the semiconductor device described in Patent Document 2, data transfer between a plurality of circuit modules is performed by memory map type addressing. An ID code is assigned to each circuit module, and the failed circuit module is replaced with a redundant circuit module by operating the ID code to control the data transfer destination.

  A structured ASIC (Structured ASIC) is known as a semiconductor integrated circuit configured by combining a plurality of circuit cells serving as basic structural units.

  A structured ASIC is an IC that uses a circuit cell having a coarser grain structure than a basic gate such as a NAND circuit as the minimum structural unit of a circuit.

  For example, Non-Patent Document 1 is a typical paper on the basic logical structural unit of the structured ASIC. In this paper, a basic structural unit is configured using a three-input lookup table (hereinafter abbreviated as “LUT”), a scan flip-flop, two three-input NAND circuits, and seven buffers. A performance comparison with the standard cell system has been studied, and it has been reported that although the area is increased by about 40 to 68%, almost the same performance can be obtained with respect to the delay.

  Patent Document 3 proposes a logic cell in which a NAND circuit is connected to the input of the LUT. Patent Document 4 proposes a logic cell configured using two three-input LUTs, two-input LUTs, and flip-flops.

  Unlike a field programmable gate array (FPGA), a structured ASIC can configure a circuit having a desired function by mask routing that customizes a part of wiring according to the application. Reconfigurable wiring structure in FPGA is very wasteful, but by replacing it with mask routing, it is possible to develop a circuit that is less wasteful than FPGA, but less wasteful than FPGA. There is a merit.

Japanese Patent No. 3491579 Japanese Patent No. 3192220 K. Y. Tong et al., “Regular logic fabrics for a via patterned gate array (VPGA)”, IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE (USA), p. 53-56 US Pat. No. 6,236,229 US Pat. No. 6,580,289

  The technology described above has the following disadvantages.

  In the FPGA described in Patent Document 1, when a basic cell that is a basic structural unit of a logic circuit is out of order, the wiring route is changed so as to bypass it. There are various types of bypass wiring for avoiding a failure, depending on the state of occurrence of the failure, and it is difficult to predict what wiring route will be changed. For this reason, it is difficult to set a clear delay margin that can satisfy the desired delay condition even if any of the basic cells fails. It is necessary to anticipate.

  In the semiconductor device described in Patent Document 2, there is a possibility that the length of the data transfer distance between the circuit modules will vary greatly depending on the state of occurrence of the defect. It is necessary to specify the operation of each module assuming the maximum distance. Therefore, it is necessary to allow for a considerably large delay margin at the design stage, and it is difficult to optimize the performance of the entire system.

Further, in the structured ASIC, leakage current in cells not related to circuit operation is wasted as DC characteristics of the circuit, so it is desirable to delete it as much as possible.
However, in a structured ASIC using a look-up table, for example, when a so-called shift type redundancy system is adopted, the activated circuit changes depending on the presence or absence of a shift. In addition, power consumption during standby increases.

  According to the present invention, even if a defect occurs in a part of the circuit, it is possible to relieve the defect so that the entire circuit can operate normally, and it is possible to reduce the change in signal delay accompanying the defect relief. Another object of the present invention is to provide a semiconductor integrated circuit capable of reducing standby power consumption in a structured ASIC.

  A semiconductor integrated circuit according to an aspect of the present invention has M (M is an integer of 2 or more) columns of circuit units and a lookup table (LUT) structure that uniquely determines an arbitrary input logic (M-1) column. The program part sequence is arranged between the circuit part sequences, and is connected to a circuit unit sequence adjacent to the first side before redundancy, and has a predetermined circuit. If there is a defect in the partial row, the program portion row in which the defective circuit portion row is sequentially arranged from the program portion row located on the first side is connected to the adjacent circuit portion row on the second side. Cell arrangement is performed in a redundant manner, and each of the circuit units has a structure capable of supplying power to each component element. In the circuit unit, component elements unnecessary for circuit operation are separated from a power source.

  Preferably, when the LUTs on both sides are not used at the stage where the cell arrangement is completed, the entire circuit unit is disconnected from the power source.

  Preferably, when only one LUT is used at the stage where the cell arrangement is completed, only the components necessary for selecting data of the LUT being used are connected to the power source, and the other configurations The element is disconnected from the power source.

  Preferably, when the LUTs on both sides are used at the stage where the cell arrangement is completed, only the components necessary for data selection of the LUTs on both sides are connected to the power source, and the other components are disconnected from the power source. ing.

According to the present invention, in the structured ASIC, power supply to components such as an inactive gate and a single transistor unnecessary for circuit operation can be stopped, and power consumption during standby can be reduced.
In addition, since a plurality of modules connected to the same input / output unit can be arranged so that the difference in distance from the input / output unit becomes small, the input / output unit and the module The change in signal delay that occurs when the connection is switched can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the present embodiment, the basic concept and configuration of the so-called column shift redundancy method will be described with reference to FIGS. 1 to 5, and then the structure and power consumption of a repairable structured ASIC (RS-ASIC). The reduction structure will be described with reference to FIGS.

FIG. 1 is a diagram showing an example of the configuration of a semiconductor integrated circuit employing a column shift redundancy system according to an embodiment of the present invention.
The semiconductor integrated circuit according to the present embodiment includes modules M11 to M19, M21 to M29, M31 to M39, M41 to M49, a general circuit block 100, and a module selection unit 50, for example, as shown in FIG.

  Modules M11 to M19, M21 to M29, M31 to M39, and M41 to M49 are arranged in a matrix of 4 rows and 9 columns, for example. Here, if 'k' is an integer from 1 to 4 and 'n' is an integer from 1 to 9, the module Mkn belongs to the kth row and the nth column.

The module Mkn is a circuit whose function is set according to input function setting data, that is, a programmable circuit.
The circuit configuration and functions of the module Mkn are arbitrary. For example, a circuit having an arithmetic / processing function such as a DSP (digital signal processor) or a circuit that performs a simple logical operation may be included. As the latter circuit, for example, one of a plurality of bit data of function setting data is selected in accordance with at least a part of a signal input from an input / output unit (described later), and the selected bit data or its logical inversion is selected. A selector SEL (FIG. 2) for outputting data to the input / output unit may be used.

  The module Mkn is not limited to a digital circuit, and may be an analog circuit capable of setting functions according to function setting data.

  Modules belonging to the same row can substitute each other's functions when the input function setting data is the same. That is, when the same function setting data is input to the modules Mk1 to Mk9 belonging to the kth row, the functions of these modules are equivalent.

  The modules Mk1 to Mk9 belonging to the same row may all have the same circuit configuration, and if the function can be replaced when the same function setting data is input, a part of the circuit configuration is different. A module having the same may be included.

  The general circuit block 100 includes input / output units P11 to P18, P21 to P28, P31 to 38, and P41 for exchanging signals with the modules M11 to M19, M21 to M29, M31 to M39, and M41 to M49. ~ P48, and executes predetermined processing in cooperation with these modules. The circuit configuration and function of the general circuit block 100 are arbitrary, and may be, for example, only wiring.

  The input / output units P11 to P18, P21 to P28, P31 to 38, and P41 to P48 are arranged in a matrix of 4 rows and 8 columns. Here, if 'i' is an integer from 1 to 8, the input / output unit Pki belongs to the k-th row and the i-th column.

  Each of the input / output units P11 to P18, P21 to P28, P31 to 38, and P41 to P48 outputs at least one signal to one module and inputs at least one signal generated in the one module. In FIG. 1, the symbol “I / O” indicates a signal exchanged between the input / output unit and the module in addition to the function setting data described later.

The input / output units Pk1 to Pk8 belonging to the same row may all input / output the same combination of signals, or may include different types of input / output units that input / output different combinations of signals. good.
For example, when the module Mkn has three output terminals, those that input signals from all three output terminals, those that input signals from only one output terminal, and the like are in the input / output units Pk1 to Pk8. It may be mixed.

  Further, the input / output unit Pki has a data holding unit PD that holds the above-described function setting data. When the input / output unit Pki is connected to one module by the module selection unit 50 described later, the data holding unit PD provided in the input / output unit Pki holds the function held by the connected module. Enter the setting data.

  The data holding unit PD only needs to hold at least data, and its configuration is arbitrary.

For example, the data holding unit PD may be a circuit that generates fixed data configured using wiring such as vias.
In this case, the data holding unit PD can be configured using a plurality of wirings LA (first wiring), a plurality of wirings LB (second wiring), and a plurality of wirings LC (third wiring).
The wiring LA is a wiring for transmitting each bit data of the function setting data to the connection destination module.
The wiring LB is a wiring that transmits predetermined bit data. For example, wiring for transmitting bit data ('1', '0') of a constant value such as a power supply line or a ground line, or wiring for transmitting bit data set to an arbitrary value by a circuit included in the general circuit block 100 Etc. are included.
The wiring LC is a wiring that connects any one of the plurality of wirings LB to each of the plurality of wirings LA.

  For example, the first wiring LA is formed in one metal wiring layer ML1, and the second wiring LB is formed in the metal wiring layer ML2 above the metal wiring layer ML1. In this case, the third wiring LC includes a via penetrating between the two metal wiring layers (ML1, ML2).

  As described above, when the data holding unit PD is configured using the wiring, the function setting data held in the data holding unit PD cannot be changed after the semiconductor integrated circuit is manufactured.

On the other hand, the data holding unit PD is configured by using storage elements that can rewrite stored data at least once, such as various static random access memories (SRAMs), read only memories (ROMs), flip-flops, and nonvolatile memories. You may do it.
When a storage element is used for the data holding unit PD, the function setting data held in the data holding unit PD can be rewritten even after the semiconductor integrated circuit is manufactured.

FIG. 2 is a diagram illustrating a configuration example of the input / output unit and the module.
The data holding unit PD provided in the input / output unit Pki holds, for example, 4-bit function setting data (FD0,..., FD3), and this function is added to the module Mki connected by the module selection unit 50 described later. Enter the setting data. The input / output unit Pki outputs a 2-bit signal (IN0, IN1) to the module Mki via the module selection unit 50, and also outputs a 1-bit signal (OUT) from the module Mki via the module selection unit 50. input.
The module Mki has, for example, a selector SEL, and one bit data corresponding to the signals IN0 and IN1 from the bit data (FD0,..., FD3) of the function setting data input from the data holding unit PD. Is output to the input / output unit Pki as a signal OUT.

  In the example of FIG. 2, the data holding unit PD and the selector SEL constitute a lookup table with two inputs and one output. In the semiconductor integrated circuit according to the present embodiment, for example, as shown in FIG. 2, the data holding unit and the selector which are components of the lookup table are separated, and the data holding unit is provided inside the input / output unit. Each selector is arranged.

  The module selection unit 50 selects a 4-row, 8-column module obtained by removing one column from the above-described 4-row, 9-column module according to a control signal supplied from a control unit (not shown), and the selected four rows The 8-column module and the above-described 4-row 8-column input / output unit are connected one-to-one. In this case, the module selection unit 50 connects one module selected according to the control signal from two modules belonging to the same row to each of the input / output units belonging to the same row. That is, the module selection unit 50 selects one of the module Mki or the module Mk (i + 1) belonging to the kth row according to the control signal, and connects this to the input / output unit Pki on the kth row.

  For example, the module selection unit 50 excludes a column including a failed module (a specific column provided for redundancy when there is no failed module) according to a control signal supplied from a control unit (not shown). A module of 4 rows and 8 columns is selected.

  If there is no failed module, for example, as shown in FIG. 1, the module Mki and the input / output unit Pki are connected one-to-one, and the modules M19 to M49 belonging to the ninth column are disconnected from all the input / output units. . In the following, a module row that is disconnected from the input / output unit in a normal state where there is no faulty module may be referred to as a redundant column.

FIG. 3 is a diagram showing an example of defect relief in the semiconductor integrated circuit shown in FIG. 1, and shows a connection state between the input / output unit and the module when the module M22 is out of order.
When the module 22 is out of order, the control unit (not shown) separates the second row of modules M12 to M42 including the module 22 from the second row of input / output units P12 to P42. The input / output units P12 to P42 in the second column are connected to the modules M13 to M43 in the third column instead of the modules M12 to M42 in the second column, and the input / output units P21 to P22 in the third column are connected to the third column. Are connected to the modules M14 to M44 in the fourth row instead of the modules M13 to M43. In this way, the connection destination of each input / output unit shifts in the direction of the redundant column (9th column) in order, so that the 4 × 8 input / output unit and the 4 × 8 module excluding the second column and 1 The pair M1 is connected to repair the defect of the module M22.

FIGS. 4 and 5 are diagrams illustrating how the input direction of the function setting data is changed in accordance with defect repair. The lower side of the diagram illustrates an example of a cross section of the semiconductor integrated circuit illustrated in FIG. ing.
When there is no defective module (FIG. 4), the data holding unit PD of each input / output unit inputs the function setting data to the selector SEL of the module located on the left side of the drawing. On the other hand, when a defective module exists (FIG. 5), the data holding unit PD of each input / output unit on the right side of the column including the defective module is set to the function setting data in the selector SEL of the module located on the right side of the figure. Enter. As a result, the function of each module on the right side of the column including the defective module is shifted to the right as a whole as compared with that before performing defect repair.

The basic concept and configuration of the column shift redundancy system has been described above.
A structure of a repairable structured ASIC (Repairable Structured ASIC (RS-ASIC)) employing the column shift redundancy method according to the present embodiment and a structure for reducing power consumption will be described below with reference to FIGS.

  FIG. 6 is a diagram showing a basic configuration of a repairable structured ASIC (RS-ASIC) according to the present embodiment.

As shown in FIG. 6, the RS-ASIC 200 of the present embodiment includes a plurality (5 in the example of FIG. 6) of cell units 201 to 205 and one redundant cell unit 206.
The redundant cell unit 260 corresponds to the redundant column described above.

  In the RS-ASIC 200 of the present embodiment, a lookup table (Look Up Table (LUT)) and a flip-flop (Flip Flop (FF)) are used for each of the cell units 201 to 205 in forming a random logic circuit. Structured ASIC method is adopted.

The LUT is a circuit capable of realizing all logics that can be configured with N inputs by programming arbitrary data.
In a PLA (Programmable Logic Array) such as an FPGA or the semiconductor integrated circuit 100 shown in FIG. 1 described above, this programming generally uses a storage device such as a RAM. Here, a hard wired logic is targeted. Therefore, it will be realized by contact via (VIA).
Further, since the occurrence of a defective portion is unpredictable, it is necessary to electrically avoid the defective portion in order to perform redundant relief for a chip that has completed all the manufacturing processes.
Therefore, in the present embodiment, the LUT is defined as a “program part” 210 by contact and a circuit part “AFE (Adaptive Functional Element)” 220 for reading out the data, and the defect of the circuit part is relieved. .

Accordingly, each of the cell units 201 to 205 includes a plurality of circuit units (AFE) 220, a program unit (LUT) 210 corresponding thereto, a plurality of FFs 230, and a plurality of FF pins corresponding thereto. ing.
The redundant cell unit 206 includes a plurality of circuit units (AFE) 220, a plurality of FFs 230, and a plurality of FF pins 240 corresponding thereto.

Each of the cell units 201 to 205 includes a plurality of circuit units (AFE) 220 and a corresponding program unit (LUT) 210, and input / output to the circuit unit (AFE) 220 is a program unit (LUT). This is done through the 210 area.
The cell unit 201 in FIG. 6 includes a circuit unit (AFE) column 2011 and a program unit (LUT) column 2012.
The cell unit 202 in FIG. 6 includes a circuit unit (AFE) column 2021 and a program unit (LUT) column 2022.
The cell unit 203 in FIG. 6 includes a circuit unit (AFE) column 2031 and a program unit (LUT) column 2032.
The cell unit 204 in FIG. 6 includes a circuit unit (AFE) column 2041 and a program unit (LUT) column 2042.
The cell unit 205 in FIG. 6 includes a circuit unit (AFE) column 2051 and a program unit (LUT) column 2052.
The redundant cell 206 in FIG. 6 has a circuit portion (AFE) column 2061.

  In the present embodiment, M = 6 circuit arrangement rows and (M−1) = 5 program arrangement rows are arranged, and cell arrangement is performed by adopting a column shift redundancy system for this configuration. Do.

FIG. 7 is a diagram illustrating a wiring layout example when there is no defect (defect) in each of the cell units 201 to 205.
FIG. 8 is a diagram showing a case where the cell portion 203 has a defect (defect), and FIG. 9 is a diagram showing a wiring layout example when the cell portion 203 has a defect (defect).

When there is no defect (defect) in the chip, the data programmed in the LUT 210 is selected by the AFE 220 on the left side as viewed from the LUT 210, and the output value is determined.
However, if there is a failure in the circuit in the chip, the LUT 210 connected to the failure circuit unit (AFE) separates the failure circuit row and avoids the M failure as shown in FIGS. Connected to the circuit.
By performing the same processing on all the circuits on the right side when this operation is viewed from the defective circuit row, it is possible to avoid the defective circuit.

In the example of FIG. 8 and FIG. 9, since the circuit part (AFE) 220 of the cell part 203 has a defect (defect), the program part (LUT) column 2032 of the cell part 203 of FIG. It is connected to the circuit part (AFE) row 2041 of the cell part 204 located.
The program unit (LUT) column 2042 of the cell unit 204 in FIG. 6 is connected to the circuit unit (AFE) column 2051 of the cell unit 205 located on the right side in FIG.
The program unit (LUT) column 2052 of the cell unit 205 in FIG. 6 is connected to the circuit unit (AFE) column 1061 of the redundant cell 206 located on the right side in FIG.
In this way, after redundancy replacement, the cell unit 203 forms the post-redundancy cell 203A including the circuit unit (AFE) column 2031.
A cell portion 204A is formed by the program portion (LUT) row 2032 and the circuit portion (AFE) row 2041, and a cell portion 205A is formed by the program portion (LUT) row 2042 and the circuit portion (AFE) row 2051. The program part (LUT) column 2052 and the circuit part (AFE) column 2061 form a cell unit 206A.

7 and 9 show circuit cross-sectional structures and wiring examples.
As shown in the figure, the circuit part (AFE) and wiring are all connected through contacts on the program part (LUT), and connected to the circuit part (AFE) via the switch mechanism. For this reason, there is no change in the upper layer wiring path before and after the redundancy processing.

  Then, the RS-ASIC 200 adopting the column shift redundancy method of this embodiment waits by deleting the power supply to components such as an inactive gate and a single transistor unnecessary for circuit operation using the following steps. It is configured to reduce leakage current that sometimes flows.

FIG. 10 is a diagram for explaining a first example of reducing the leakage current that flows during standby according to the present embodiment.
FIG. 11 is a diagram for explaining a second example of reducing the leakage current flowing during standby according to the present embodiment.
FIG. 12 is a diagram for explaining a third example for reducing the leakage current that flows during standby according to the present embodiment.

10 to 12, the circuit unit (AFE) 220 includes two-input one-output multiplexers 211 to 214 arranged in the first stage, two-input one-output multiplexers 215 and 216 arranged in the next stage, and It consists of a 2-input 1-output multiplexer 217 arranged in the final stage.
The first stage multiplexers 211 to 214 select and output input data according to the signal A.
The next stage multiplexers 215 and 216 select and output the input data according to the signal B.
The final stage multiplexer 217 selects and outputs the output Q according to the signal C.

  10 to 12, the circuit unit (AFE) 220-n is connected to the program unit (LUT) 210-n by the switch SW2, and the circuit unit (AFE) 220-n + 1 is connected to the program unit (by the switch SW4. LUT) 210-n + 1, and circuit unit (AFE) 220-n + 2 is connected to program unit (LUT) 210-n + 2 by switch SW6.

When the LUTs on both sides are not used as viewed from the decoder at the stage where the cell placement is completed (when Filler Cell is placed), as shown in FIG. 10, the power supply line (VDD) or GND) and remove from the power supply.
In the example of FIG. 10, the contact connected to the power supply line for the entire circuit portion (AFE) 220-n + 1 is excluded and disconnected from the power supply.

When only one LUT is used as viewed from the decoder at the stage where cell placement is completed, power is supplied only to the gates necessary to select the data of the LUT being used, as shown in FIG. Disconnect the other gates from the power supply.
In the example shown in FIG. 11, when an output Q obtained by inverting the input signal A is obtained, the contact connected to the power supply line (VDD or GND) to the multiplexers 212 to 214 and 216 is excluded and disconnected from the power supply.

When the LUTs on both sides as viewed from the decoder are used at the stage where the cell arrangement is completed, power is supplied only to the gates necessary for data selection of the LUTs on both sides as shown in FIG. Disconnect from the power source.
In the example shown in FIG. 12, when the output Q is obtained by ANDing the input signals A and B, the contact connected to the power supply line (VDD or GND) to the multiplexers 213, 214, and 216 is excluded and disconnected from the power supply. .

  By executing the above steps, it is possible to turn off the power of circuits that are not used after realizing all circuit operations regardless of the presence or absence of circuit defects.

As described above, in the structured ASIC, it is possible to reduce the leakage current of the circuit by turning off the power of the circuit unnecessary for the actual operation (cutting the connection with the power supply).
Further, by not connecting the connection line with the power source in the unnecessary circuit portion, even if a failure of the power supply short mode that normally cannot be saved occurs, if the failure is in the unnecessary circuit portion, it can be made a good product without any problem.

As described above, according to the semiconductor integrated circuit shown in FIG. 1, a module of 4 rows and 8 columns is selected by removing one column from a module of 4 rows and 9 columns, and this selected 4 rows and 8 columns module is selected. The module and the 4 × 8 input / output unit are connected in a one-to-one relationship. Further, one module selected from two modules belonging to the same row is connected to each of the input / output units belonging to the same row.
Thereby, two modules (Mki, Mk (i + 1)) connected to the same input / output unit Pki can be arranged so that the difference in distance from the input / output unit Pki is small. For example, as shown in FIG. 1, by arranging eight input / output units (Pk1 to Pk8) in each row at equal intervals, two modules (Mki, Mk ( i + 1)) can be arranged.
By reducing the difference in the distance between the input / output unit and the module, the difference in the wiring length connecting the two can be reduced. Therefore, it is possible to reduce the change in signal delay that occurs when the connection between the module and the input / output unit is switched along with the defect relief.

  Further, since it is possible to accurately predict how much the signal delay changes due to defect relief based on the positional relationship between the modules Mki and Mk (i + 1) and the input / output unit Pki, for example, as described above Compared to the case where accurate prediction is difficult as in Patent Document 1, it is possible to estimate the delay margin smaller. Thereby, a circuit operating at high speed can be realized.

Further, according to the semiconductor integrated circuit shown in FIG. 1, since it is possible to relieve defects with a simple circuit configuration in which one of two modules is selected and connected to one input / output unit, an increase in the number of circuits and an extra circuit are possible. Generation of power consumption can be minimized.
Since a circuit that can be designed and manufactured by a conventional general method can be used for a switch circuit used for switching connection, a control unit, and a storage unit for holding defect information, a defect relief function is provided. The increase in cost can be suppressed to a minute.

In addition, according to the semiconductor integrated circuit shown in FIG. 1, each input / output unit is provided with a data holding unit PD for holding function setting data, and the function setting data held in the data holding unit PD is the module selection unit. Are input to each module. The function of each module is set according to input function setting data.
As a result, even if a module connected to one input / output unit is switched for defect relief, the module connected to the one input / output unit is changed to function setting data held in the data holding unit PD. It can be set to a certain function according to.

When the connection between the input / output unit and the module is switched along with defect repair, the function of each module needs to be changed according to the input / output unit of the connection destination. Therefore, if the data holding unit PD is provided inside the module, the function setting data of the data holding unit PD must be rewritten according to the input / output unit of the connection destination when defect repair is performed. Don't be. In order to realize this, for example, there is a method of configuring the data holding unit PD with a rewritable storage element, a method of fixing the wiring of the data holding unit PD by an electron beam apparatus after inspecting the module for defects, or the like. Conceivable.
However, in the method of configuring the data holding unit PD using a rewritable storage element, the circuit configuration is significantly more complicated than the method of fixing the wiring by a via or the like, resulting in an increase in circuit area and an increase in failure rate. There is a disadvantage. In addition, the method of fixing the wiring of the data holding unit PD with an electron beam apparatus or the like has a disadvantage that a conventional general production line cannot be used and a disadvantage that production efficiency is lowered.
On the other hand, according to the semiconductor integrated circuit shown in FIG. 1, even if the connection between the input / output unit and the module is switched, there is no need to change the function setting data held in the data holding unit PD. The part PD can be configured by fixed wiring. Therefore, it is possible to avoid the disadvantages described above in the method using a rewritable memory element and the method of fixing wiring using an electron beam apparatus or the like.

  Furthermore, since it is not necessary to add a circuit to the general circuit block 100 in order to repair the defect, it is possible to use the conventional circuit as it is, and the design burden by providing the defect repair function is reduced. Can be reduced.

  In addition, the structure in which the modules are regularly arranged makes it easier to optimize the wiring interval and the element characteristics, etc., so that the increase in circuit area and the variation in circuit characteristics are suppressed compared to the structure in which the modules are randomly arranged. Can do.

  Moreover, according to the semiconductor integrated circuit shown in FIG. 1, since the connection state between the input / output unit and the module can be collectively controlled for each column, the connection state with the input / output unit can be independently set for each module. Compared to control, the number of control signals can be greatly reduced, and the circuit configuration of the control unit can be simplified.

  Further, when a failure is inspected, it is only necessary to inspect the presence or absence of a failure for each column, so that the inspection time can be shortened as compared with the case where each module is inspected.

  Furthermore, when writing fault module information using a storage element such as a fuse inside a semiconductor integrated circuit, it is only necessary to write information about the presence or absence of a fault for each column. Can be shortened.

  In the semiconductor integrated circuit according to the present embodiment, when a faulty module exists, all modules belonging to the same column as this are disconnected from the input / output unit, so that a normal module is also wasted. Therefore, when the failure occurrence probability is high, the number of modules that are wasted tends to increase. However, when the probability of failure is not so high or when there are a large number of relatively small modules, in order to achieve the same yield compared to the method of controlling the connection state for each module The required circuit area can be reduced.

  In the semiconductor integrated circuit shown in FIG. 1, the input / output units (Pk1 to Pk8) in the same row are arranged on a straight line. However, they may be arranged on a curved line or a meandering line, for example. , May be arranged in a zigzag manner. If the input / output units Pk1 to Pk8 are arranged at equal intervals on any line, the two modules (Mki, Mk (i + 1)) are arranged so that the distance from the input / output unit Pki is equal to each other. It is possible to arrange.

  In the embodiment described above, modules and input / output units are arranged in a matrix, but the present invention is not limited to this. For example, the number of rows in the matrix described above may be one. In this case, the modules and input / output units may be arranged along one straight line, may be arranged along an arbitrary line such as a curve or a meander line, or may be arranged in a zigzag shape. good.

  All of the semiconductor integrated circuits described above may be formed on the same semiconductor chip, or may be divided into a plurality of semiconductor chips by using a technique such as SIP (system in package).

It is a figure showing an example of composition of a semiconductor integrated circuit concerning an embodiment. It is a figure which shows the structural example of an input / output part and a module. FIG. 2 is a diagram showing an example of defect relief in the semiconductor integrated circuit shown in FIG. 1. It is a 1st figure for demonstrating a mode that the input direction of function setting data changes with defect relief. It is the 2nd figure for demonstrating a mode that the input direction of function setting data changes with defect relief. It is a figure which shows the fundamental structure of the repairable structured ASIC (Repairable Structured ASIC (RS-ASIC)) which concerns on this embodiment. FIG. 7 is a diagram illustrating a wiring layout example when there is no defect (defect) in each cell portion of FIG. 6. It is a figure which shows the case where there exists a defect (defect) in the cell part 203 of FIG. FIG. 7 is a diagram showing a wiring layout example when there is a defect (defect) in the cell unit 203 of FIG. 6. It is a figure for demonstrating the 1st example which reduces the leakage current which flows at the time of standby concerning this embodiment. It is a figure for demonstrating the 2nd example which reduces the leakage current which flows at the time of standby concerning this embodiment. It is a figure for demonstrating the 3rd example which reduces the leakage current which flows at the time of standby concerning this embodiment.

Explanation of symbols

50 ... Module selection unit, 100 ... General circuit block, PD ... Data holding unit, SEL ... Selector, M11-M19, M21-M29, M31-M39, M41-M49 ... Module, P11-P18, P21-P28, P31-38, P41-P48 ... I / O unit, 200 ... Repairable Structured ASIC (RS-ASIC), 201-205 ... Cell unit, 206 .. Redundant cells, 203A ... Redundant cells, 204A to 206A ... Cell part, 210 ... Program part (LUT), 220 ... Circuit part (AFE), 230 ... Flip-flop (FF) ), 2011-2061... Circuit portion (AFE) row, 2012-2052... Program portion (LUT) row.

Claims (4)

M (M is an integer greater than or equal to 2) columns of circuit sections;
(M-1) columns of program parts having a look-up table (LUT) structure that uniquely determines an arbitrary input logic,
The program part sequence is arranged between the circuit part sequences, and before redundancy, has a structure connected to the circuit unit sequence adjacent to the first side,
When there is a defect in a predetermined circuit part sequence, the program part sequence in which the defective circuit part sequence is sequentially arranged from the program unit sequence located on the first side is connected to the circuit unit sequence adjacent to the second side. Cell placement is performed by the column shift redundancy method,
Each of the circuit units has a structure capable of supplying power for each component,
In the above circuit portion, a semiconductor integrated circuit in which components unnecessary for circuit operation are separated from a power source. The semiconductor integrated circuit according to claim 1, wherein, when the cell arrangement is completed, when the LUTs on both sides are not used, the entire circuit unit is disconnected from the power source. When only one LUT is used at the stage where the cell arrangement is completed, only the components necessary for selecting the data of the LUT being used are connected to the power source, and the other components are connected from the power source. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is separated. When the LUTs on both sides are used at the stage where the cell arrangement is completed, only the constituent elements necessary for data selection of the LUTs on both sides are connected to the power source, and the other constituent elements are disconnected from the power source. 2. The semiconductor integrated circuit according to 1.

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