JP2009038105A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, which can reduce a variation of a signal delay accompanied with a relief measure of failure, while it is possible to relieve a failure and to normally operate a whole circuit even if the failure occurs in a part of a circuit, and is also suitable for a redundancy system of an LUT with many inputs, and can actualize an optimal architecture in a structured ASIC. <P>SOLUTION: Interface sequences 203-1 to 203-5 are arranged between circuit sequences, and have a structure connected with the circuit sequences adjacent to a primary side before a redundancy. If a predetermined circuit sequence has any failure, with respect to the interface sequences arranged one by one from the interface sequence in which the failure circuit sequence is located in the primary side, a cell portion is arranged by a column shift redundancy system connected with the circuit sequences adjacent to a secondary side. A programming of plural data before and after the redundancy is carried out in a programming portion of the LUT which actualizes a logic of a circuit portion. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a plurality of modules whose functions can be substituted for each other.

  In recent years, in semiconductor integrated circuits, processing dimensions have been miniaturized and circuit configurations have been increased in scale, resulting in a serious decrease in yield due to manufacturing defects. Therefore, a method has been proposed in which a redundant circuit is provided in advance in a part of the entire circuit, and the defective portion is replaced with the redundant circuit so that the entire semiconductor chip does not become a defective product.

  For example, in the logic circuit data generation method of FPGA (field programmable gate array) described in Patent Document 1, the necessity of failure avoidance is determined from failure information and logic information, and if necessary, the function of the failure portion is determined as an empty portion. Change the logical information to substitute.

  In the semiconductor device described in Patent Document 2, data transfer between a plurality of circuit modules is performed by memory map type addressing. An ID code is assigned to each circuit module, and the failed circuit module is replaced with a redundant circuit module by operating the ID code to control the data transfer destination.

  A structured ASIC (Structured ASIC) is known as a semiconductor integrated circuit configured by combining a plurality of circuit cells serving as basic structural units.

  A structured ASIC is an IC that uses a circuit cell having a coarser grain structure than a basic gate such as a NAND circuit as the minimum structural unit of a circuit.

  For example, Non-Patent Document 1 is a typical paper on the basic logical structural unit of the structured ASIC. In this paper, a basic structural unit is configured using a three-input lookup table (hereinafter abbreviated as “LUT”), a scan flip-flop, two three-input NAND circuits, and seven buffers. A performance comparison with the standard cell system has been studied, and it has been reported that although the area is increased by about 40 to 68%, almost the same performance can be obtained with respect to the delay.

  Patent Document 3 proposes a logic cell in which a NAND circuit is connected to the input of the LUT. Patent Document 4 proposes a logic cell configured using two three-input LUTs, two-input LUTs, and flip-flops.

  Unlike a field programmable gate array (FPGA), a structured ASIC can configure a circuit having a desired function by mask routing that customizes a part of wiring according to the application. Reconfigurable wiring structure in FPGA is very wasteful, but by replacing it with mask routing, it is possible to develop a circuit that is less wasteful than FPGA, but less wasteful than FPGA. There is a merit.

Japanese Patent No. 3491579 Japanese Patent No. 3192220 K. Y. Tong et al., “Regular logic fabrics for a via patterned gate array (VPGA)”, IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE (USA), p. 53-56 US Pat. No. 6,236,229 US Pat. No. 6,580,289

  The technology described above has the following disadvantages.

  In the FPGA described in Patent Document 1, when a basic cell that is a basic structural unit of a logic circuit is out of order, the wiring route is changed so as to bypass it. There are various types of bypass wiring for avoiding a failure, depending on the state of occurrence of the failure, and it is difficult to predict what wiring route will be changed. For this reason, it is difficult to set a clear delay margin that can satisfy the desired delay condition even if any of the basic cells fails. It is necessary to anticipate.

  In the semiconductor device described in Patent Document 2, there is a possibility that the length of the data transfer distance between the circuit modules will vary greatly depending on the state of occurrence of the defect. It is necessary to specify the operation of each module assuming the maximum distance. Therefore, it is necessary to allow for a considerably large delay margin at the design stage, and it is difficult to optimize the performance of the entire system.

  In a structured ASIC using an FPGA macro cell, since the LUT and the flip-flop (FF) are included in the cell, the number ratio between the LUT and the FF is not always optimal for the circuit architecture.

Further, for example, it is conceivable that the LUT is divided into a “program unit” and a “decoder unit” so that only the decoder unit is relieved.
However, in this case, since the program part is basically only a contact, it is a redundancy system for the purpose of substantially repairing the transistor part. Since the number of selectors is two (the number of transistors is four), it is not suitable as a redundancy system for an LUT having a large number of inputs.

  According to the present invention, even if a defect occurs in a part of the circuit, it is possible to relieve the defect so that the entire circuit can operate normally, and it is possible to reduce the change in signal delay accompanying the defect relief. An object of the present invention is to provide a semiconductor integrated circuit that is suitable for an LUT redundancy system having a large number of inputs and that can realize an optimum architecture in a structured ASIC.

  A semiconductor integrated circuit according to an aspect of the present invention includes M (M is an integer of 2 or more) columns of circuit units, and an interface unit column that uniquely determines an arbitrary input / output logic. , Arranged between the circuit unit rows, and before redundancy, has a structure connected to the circuit unit row adjacent to the first side. When a predetermined circuit unit row is defective, the defective circuit portion row is In the interface unit sequence sequentially arranged from the interface unit sequence located on the 1 side, the cell units are arranged by the column shift redundancy system connected to the circuit unit sequence adjacent to the second side, and the logic of the circuit unit In the look-up table (LUT) programming unit that realizes the above, a plurality of data before and after redundancy are programmed.

  Preferably, programming is completed by using contacts in the programming section and connecting to different power sources.

  Preferably, the programming unit includes memory cells and completes programming by connecting to different power sources.

  Preferably, redundancy of circuit blocks having different physical sizes is performed using the same redundancy address.

According to the present invention, an optimum architecture can be realized in a structured ASIC, which is suitable for a redundant system of LUTs having a large number of inputs.
In addition, since a plurality of modules connected to the same input / output unit can be arranged so that the difference in distance from the input / output unit becomes small, the input / output unit and the module The change in signal delay that occurs when the connection is switched can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the present embodiment, the basic concept and configuration of the so-called column shift redundancy method will be described with reference to FIGS. 1 to 5, and then a structured ASIC (Repairable Structured ASIC (RS-ASIC)) which is a feature of the present embodiment. The structure, arrangement, specific circuit configuration, etc. will be described.

FIG. 1 is a diagram showing an example of the configuration of a semiconductor integrated circuit employing a column shift redundancy system according to an embodiment of the present invention.
The semiconductor integrated circuit according to the present embodiment includes modules M11 to M19, M21 to M29, M31 to M39, M41 to M49, a general circuit block 100, and a module selection unit 50, for example, as shown in FIG.

  Modules M11 to M19, M21 to M29, M31 to M39, and M41 to M49 are arranged in a matrix of 4 rows and 9 columns, for example. Here, if 'k' is an integer from 1 to 4 and 'n' is an integer from 1 to 9, the module Mkn belongs to the kth row and the nth column.

The module Mkn is a circuit whose function is set according to input function setting data, that is, a programmable circuit.
The circuit configuration and functions of the module Mkn are arbitrary. For example, a circuit having an arithmetic / processing function such as a DSP (digital signal processor) or a circuit that performs a simple logical operation may be included. As the latter circuit, for example, one of a plurality of bit data of function setting data is selected in accordance with at least a part of a signal input from an input / output unit (described later), and the selected bit data or its logical inversion is selected. A selector SEL (FIG. 2) for outputting data to the input / output unit may be used.

  The module Mkn is not limited to a digital circuit, and may be an analog circuit capable of setting functions according to function setting data.

  Modules belonging to the same row can substitute each other's functions when the input function setting data is the same. That is, when the same function setting data is input to the modules Mk1 to Mk9 belonging to the kth row, the functions of these modules are equivalent.

  The modules Mk1 to Mk9 belonging to the same row may all have the same circuit configuration, and if the function can be replaced when the same function setting data is input, a part of the circuit configuration is different. A module having the same may be included.

  The general circuit block 100 includes input / output units P11 to P18, P21 to P28, P31 to 38, and P41 for exchanging signals with the modules M11 to M19, M21 to M29, M31 to M39, and M41 to M49. ~ P48, and executes predetermined processing in cooperation with these modules. The circuit configuration and function of the general circuit block 100 are arbitrary, and may be, for example, only wiring.

  The input / output units P11 to P18, P21 to P28, P31 to 38, and P41 to P48 are arranged in a matrix of 4 rows and 8 columns. Here, if 'i' is an integer from 1 to 8, the input / output unit Pki belongs to the k-th row and the i-th column.

  Each of the input / output units P11 to P18, P21 to P28, P31 to 38, and P41 to P48 outputs at least one signal to one module and inputs at least one signal generated in the one module. In FIG. 1, the symbol “I / O” indicates a signal exchanged between the input / output unit and the module in addition to the function setting data described later.

The input / output units Pk1 to Pk8 belonging to the same row may all input / output the same combination of signals, or may include different types of input / output units that input / output different combinations of signals. good.
For example, when the module Mkn has three output terminals, those that input signals from all three output terminals, those that input signals from only one output terminal, and the like are in the input / output units Pk1 to Pk8. It may be mixed.

  Further, the input / output unit Pki has a data holding unit PD that holds the above-described function setting data. The data holding unit PD can be formed by a programmable device, for example. When the input / output unit Pki is connected to one module by the module selection unit 50 described later, the data holding unit PD provided in the input / output unit Pki holds the function held by the connected module. Enter the setting data.

  The data holding unit PD only needs to hold at least data, and its configuration is arbitrary.

For example, the data holding unit PD may be a circuit that generates fixed data configured using wiring such as vias.
In this case, the data holding unit PD can be configured using a plurality of wirings LA (first wiring), a plurality of wirings LB (second wiring), and a plurality of wirings LC (third wiring).
The wiring LA is a wiring for transmitting each bit data of the function setting data to the connection destination module.
The wiring LB is a wiring that transmits predetermined bit data. For example, wiring for transmitting bit data ('1', '0') of a constant value such as a power supply line or a ground line, or wiring for transmitting bit data set to an arbitrary value by a circuit included in the general circuit block 100 Etc. are included.
The wiring LC is a wiring that connects any one of the plurality of wirings LB to each of the plurality of wirings LA.

  For example, the first wiring LA is formed in one metal wiring layer ML1, and the second wiring LB is formed in the metal wiring layer ML2 above the metal wiring layer ML1. In this case, the third wiring LC includes a via penetrating between the two metal wiring layers (ML1, ML2).

  As described above, when the data holding unit PD is configured using the wiring, the function setting data held in the data holding unit PD cannot be changed after the semiconductor integrated circuit is manufactured.

On the other hand, the data holding unit PD is configured by using storage elements that can rewrite stored data at least once, such as various static random access memories (SRAMs), read only memories (ROMs), flip-flops, and nonvolatile memories. You may do it.
When a storage element is used for the data holding unit PD, the function setting data held in the data holding unit PD can be rewritten even after the semiconductor integrated circuit is manufactured.

FIG. 2 is a diagram illustrating a configuration example of the input / output unit and the module.
The data holding unit PD provided in the input / output unit Pki holds, for example, 4-bit function setting data (FD0,..., FD3), and this function is added to the module Mki connected by the module selection unit 50 described later. Enter the setting data. The input / output unit Pki outputs a 2-bit signal (IN0, IN1) to the module Mki via the module selection unit 50, and also outputs a 1-bit signal (OUT) from the module Mki via the module selection unit 50. input.
The module Mki has, for example, a selector SEL, and one bit data corresponding to the signals IN0 and IN1 from the bit data (FD0,..., FD3) of the function setting data input from the data holding unit PD. Is output to the input / output unit Pki as a signal OUT.

In the example of FIG. 2, the data holding unit PD and the selector SEL constitute a lookup table with two inputs and one output. In the semiconductor integrated circuit according to the present embodiment, for example, as shown in FIG. 2, the data holding unit and the selector which are components of the lookup table are separated, and the data holding unit is provided inside the input / output unit. Each selector is arranged.
The data holding unit PD and the selector SEL form a combinational circuit.

  The module selection unit 50 selects a 4-row, 8-column module obtained by removing one column from the above-described 4-row, 9-column module in accordance with a control signal supplied from a control unit (not shown), and selects the selected four rows The 8-column module and the above-described 4-row 8-column input / output unit are connected one-to-one. In this case, the module selection unit 50 connects one module selected according to the control signal from two modules belonging to the same row to each of the input / output units belonging to the same row. That is, the module selection unit 50 selects one of the module Mki or the module Mk (i + 1) belonging to the kth row according to the control signal, and connects this to the input / output unit Pki on the kth row.

  For example, the module selection unit 50 excludes a column including a failed module (a specific column provided for redundancy when there is no failed module) according to a control signal supplied from a control unit (not shown). A module of 4 rows and 8 columns is selected.

  If there is no failed module, for example, as shown in FIG. 1, the module Mki and the input / output unit Pki are connected one-to-one, and the modules M19 to M49 belonging to the ninth column are disconnected from all the input / output units. . In the following, a module row that is disconnected from the input / output unit in a normal state where there is no faulty module may be referred to as a redundant column.

FIG. 3 is a diagram showing an example of defect relief in the semiconductor integrated circuit shown in FIG. 1, and shows a connection state between the input / output unit and the module when the module M22 is out of order.
When the module M22 is out of order, the control unit (not shown) disconnects the second row of modules M12 to M42 including the module M22 and the second row of input / output units P12 to P42. The input / output units P12 to P42 in the second column are connected to the modules M13 to M43 in the third column instead of the modules M12 to M42 in the second column, and the input / output units P21 to P22 in the third column are connected to the third column. Are connected to the modules M14 to M44 in the fourth row instead of the modules M13 to M43. In this way, the connection destination of each input / output unit shifts in the direction of the redundant column (9th column) in order, so that the 4 × 8 input / output unit and the 4 × 8 module excluding the second column and 1 The pair M1 is connected to repair the defect of the module M22.

FIGS. 4 and 5 are diagrams illustrating how the input direction of the function setting data is changed in accordance with defect repair. The lower side of the diagram illustrates an example of a cross section of the semiconductor integrated circuit illustrated in FIG. ing.
When there is no defective module (FIG. 4), the data holding unit PD of each input / output unit inputs the function setting data to the selector SEL of the module located on the left side of the drawing. On the other hand, when there is a defective module (FIG. 5), the data holding unit PD of each input / output unit on the right side of the column including the defective module functions as a selector SEL of the module located on the right side of the figure. Enter the setting data. As a result, the function of each module on the right side of the column including the defective module is shifted to the right as a whole as compared with that before performing defect repair.

The basic concept and configuration of the column shift redundancy system has been described above.
Hereinafter, a redundant circuit for remedying a defect that occurs during production of a random logic circuit using an LUT (Look Up Table) according to the present embodiment will be described.
In the present embodiment, basically, in a structured ASIC having a redundancy function, a plurality of data before and after redundancy are programmed by a programming unit of an LUT that realizes logic.
In this case, it is possible to use a contact (VIA) in the programming unit and connect to a different power source to complete the programming.
It is also possible to use a memory cell in the programming unit and connect to a different power source to complete the programming.
In addition, redundancy of circuit blocks having different physical sizes can be realized using the same redundancy address.
Hereinafter, these configurations will be described with reference to the drawings.

  FIG. 6 is a diagram showing a redundant basic configuration in the structured ASIC using the multi-input LUT according to the present embodiment.

As shown in FIG. 6, the structured ASIC 200 of this embodiment includes a plurality of m (m = 5 in the example of FIG. 6) cell units 201-1 to 201-5 and one redundant cell unit 202.
The redundant cell unit 202 corresponds to the redundant column described above.
The cell units 201-1 to 201-5 and the redundant cell unit 202 have a structure in which LUTs for realizing random logic are arranged in a lattice pattern, and write interfaces 203-1 to 203- for accessing the LUT between the LUTs. 5, input / output pins TIL, TIR, TOL, and TOR are arranged.
The input / output pins are connected to the input / output ports of the LUTs on both sides via switches SWIL, SWIR, SWOL, SWOR.

  When the manufactured chip has no defect, as in the case described above, as shown in FIG. 7, all the switches SWIL, SWIR, SWOL, SWOR are connected to either the left or right side (FIG. 7). Then, the redundant cell unit 202 of the LUT block (right side in the figure) at the right end in the figure is not used.

Next, when there is a repairable defect in the manufactured chip, for example, as shown in FIG. 8, when there is a defect in the third circuit block from the right in the figure, the cell parts 201 from the left to the third are shown. The input / output pins TI and TO of the write interfaces 203-1 to 203-3 that form the interface sections -1 to 201-3 are connected to the left LUT in the same manner as in the initial state, as in FIG. The redundant switch is controlled as follows.
However, if there is a defect in the 4th block from the left, connecting the 4th input / output pin from the left to the 4th block from the left will cause a malfunction in the circuit. The connection relationship of the input / output pins TIL and TOL to the left is canceled and the input / output pins TIL and TOL are connected to the right input / output pins TIR and TOR.
Therefore, access to the defective part is prohibited by connecting the blocks after the fourth block to the right LUT.

Next, a case where the physical sizes of circuit blocks to be redundant are different will be described.
As shown in FIG. 9, when a plurality of circuit blocks having different sizes are made redundant as in the relationship between the LUT and the flip-flop FF, the redundancy is performed in exactly the same manner as the redundancy method using only the LUT described above. Can be realized.
For example, assume that the size of the LUT is four times as large as the FF in the example of FIG. In this case, in the address for controlling redundancy, the FF is controlled by an address excluding all bits of the address, and the LUT is controlled by an address excluding the lower 2 bits. Then, the point at which the LUT shifts is every four address shifts of the FF.

  Next, a description will be given of a configuration in which programming is completed by using memory cells in the programming unit and connecting to different power sources.

  FIG. 10 is a diagram showing an example in which the programming unit of the LUT according to the present embodiment is configured by a memory circuit.

  As shown in FIG. 10, the memory circuit 300 includes a memory cell array 310 in which memory cells MC are arranged in a matrix, a sense amplifier group 320 including a plurality of sense amplifiers 321, a row decoder 330, and word line changeover switches 341-1. A switch group 340 including 341-n and a column selector 350 are included. In FIG. 10, the column decoder is omitted.

For example, as shown in FIG. 11, memory cell MC includes SRAM cells including p-channel MOS (PMOS) PT1, PT2, and n-channel MOS (NMOS) NT1, NT2, and two storage nodes ND1, ND2 are respectively provided. The bit pairs BL0, BLB0, BL1, BLB1,... Wired corresponding to each column are connected via an access transistor ACT made up of an NMOS transistor.
Access transistors ACT arranged in the same row are connected to word lines WL0, WR0, WL1, WR1, WL2, WR2, WL3, WR3,.
Access transistors ACT connected to memory cells MC in adjacent rows are selectively switched by word line changeover switches 341-0 to 341-n. In other words, the left word line WL and the right word line WR are selectively connected to the row decoder 330 and driven by the switches 341-0 to 341-n.

In this case, “MC1” in the figure is a memory cell accessed when the left side is selected by the redundant shift circuit (in the above example, before redundancy relief), and “MC2” is the case where the right side is selected by the redundant shift circuit To the memory cell (in the above example, after redundancy relief).
The memory cell MC1 stores data required when the left side is selected as viewed from the input / output pin, and the memory cell MC2 stores data when selected from the right side.

  FIG. 12 is a diagram illustrating another example in which the programming unit of the LUT according to the present embodiment is configured by a memory circuit.

In this example, a contact type memory cell is used as shown in FIG.
In this example, the sources of the two access transistors ACTL1 of each cell are connected to the bit line BL through contacts, and the drain side is open, for example (or connected to a power supply). The drain of ACTL2 is connected to the bit line BLB through a contact, the source side is connected to a reference potential (for example, ground potential) GND, and the gates of both transistors ACTL1 and ACTL2 are connected to WL.
Further, the source of two access transistors ACTR1 of each cell adjacent to the right side in the figure is connected to the bit line BL, and the drain side is connected to the ground potential GND through a contact. The drain of ACTR2 is connected to the bit line BLB, and the source side is open, for example (or connected to the power supply). The gates of both transistors ACTR1, ACTR2 are connected to WR.

When a 6-input LUT is configured by adopting the above configuration, for example, an increase in area can be suppressed as compared with the configuration of a 3-input LUT without adopting it.
Therefore, the present embodiment is most suitable for the redundancy system in the structured ASIC using the LUT having a large number of inputs.

As described above, according to the semiconductor integrated circuit shown in FIG. 1, a module of 4 rows and 8 columns is selected by removing one column from a module of 4 rows and 9 columns, and this selected 4 rows and 8 columns module is selected. The module and the 4 × 8 input / output unit are connected in a one-to-one relationship. Further, one module selected from two modules belonging to the same row is connected to each of the input / output units belonging to the same row.
Thereby, two modules (Mki, Mk (i + 1)) connected to the same input / output unit Pki can be arranged so that the difference in distance from the input / output unit Pki is small. For example, as shown in FIG. 1, by arranging eight input / output units (Pk1 to Pk8) in each row at equal intervals, two modules (Mki, Mk ( i + 1)) can be arranged.
By reducing the difference in the distance between the input / output unit and the module, the difference in the wiring length connecting the two can be reduced. Therefore, it is possible to reduce the change in signal delay that occurs when the connection between the module and the input / output unit is switched along with the defect relief.

  Further, since it is possible to accurately predict how much the signal delay changes due to defect relief based on the positional relationship between the modules Mki and Mk (i + 1) and the input / output unit Pki, for example, as described above Compared to the case where accurate prediction is difficult as in Patent Document 1, it is possible to estimate the delay margin smaller. Thereby, a circuit operating at high speed can be realized.

Further, according to the semiconductor integrated circuit shown in FIG. 1, since it is possible to relieve defects with a simple circuit configuration in which one of two modules is selected and connected to one input / output unit, the number of circuits can be increased or increased. Generation of power consumption can be minimized.
Since a circuit that can be designed and manufactured by a conventional general method can be used for a switch circuit used for switching connection, a control unit, and a storage unit for holding defect information, a defect relief function is provided. The increase in cost can be suppressed to a minute.

In addition, according to the semiconductor integrated circuit shown in FIG. 1, each input / output unit is provided with a data holding unit PD for holding function setting data, and the function setting data held in the data holding unit PD is the module selection unit. Are input to each module. The function of each module is set according to input function setting data.
As a result, even if a module connected to one input / output unit is switched for defect relief, the module connected to the one input / output unit is changed to function setting data held in the data holding unit PD. It can be set to a certain function according to.

When the connection between the input / output unit and the module is switched along with defect repair, the function of each module needs to be changed according to the input / output unit of the connection destination. Therefore, if the data holding unit PD is provided inside the module, the function setting data of the data holding unit PD must be rewritten according to the input / output unit of the connection destination when defect repair is performed. Don't be. In order to realize this, for example, there is a method of configuring the data holding unit PD with a rewritable storage element, a method of fixing the wiring of the data holding unit PD by an electron beam apparatus after inspecting the module for defects, or the like. Conceivable.
However, in the method of configuring the data holding unit PD using a rewritable storage element, the circuit configuration is significantly more complicated than the method of fixing the wiring by a via or the like, resulting in an increase in circuit area and an increase in failure rate. There is a disadvantage. In addition, the method of fixing the wiring of the data holding unit PD with an electron beam apparatus or the like has a disadvantage that a conventional general production line cannot be used and a disadvantage that production efficiency is lowered.
On the other hand, according to the semiconductor integrated circuit shown in FIG. 1, even if the connection between the input / output unit and the module is switched, there is no need to change the function setting data held in the data holding unit PD. The part PD can be configured by fixed wiring. Therefore, it is possible to avoid the disadvantages described above in the method using a rewritable memory element and the method of fixing wiring using an electron beam apparatus or the like.

  Furthermore, since it is not necessary to add a circuit to the general circuit block 100 in order to repair the defect, it is possible to use the conventional circuit as it is, and the design burden by providing the defect repair function is reduced. Can be reduced.

  In addition, the structure in which the modules are regularly arranged makes it easy to optimize the wiring interval and element characteristics, etc., so that the increase in circuit area and the variation in circuit characteristics are suppressed compared to the structure in which the modules are randomly arranged. Can do.

  Moreover, according to the semiconductor integrated circuit shown in FIG. 1, since the connection state between the input / output unit and the module can be collectively controlled for each column, the connection state with the input / output unit can be independently set for each module. Compared to control, the number of control signals can be greatly reduced, and the circuit configuration of the control unit can be simplified.

  Further, when a failure is inspected, it is only necessary to inspect the presence or absence of a failure for each column, so that the inspection time can be shortened as compared with the case where each module is inspected.

  Furthermore, when writing fault module information using a storage element such as a fuse inside a semiconductor integrated circuit, it is only necessary to write information about the presence or absence of a fault for each column. Can be shortened.

  In the semiconductor integrated circuit according to the present embodiment, when a faulty module exists, all modules belonging to the same column as this are disconnected from the input / output unit, so that a normal module is also wasted. Therefore, when the failure occurrence probability is high, the number of modules that are wasted tends to increase. However, if the failure probability is not very high or if there are a large number of relatively small modules, in order to achieve the same yield compared to the method of controlling the connection state for each module Necessary circuit area can be reduced.

  In the semiconductor integrated circuit shown in FIG. 1, the input / output units (Pk1 to Pk8) in the same row are arranged on a straight line. However, they may be arranged on a curved line or a meandering line, for example. , May be arranged in a zigzag manner. If the input / output units Pk1 to Pk8 are arranged at equal intervals on any line, the two modules (Mki, Mk (i + 1)) are arranged so that the distance from the input / output unit Pki is equal to each other. It is possible to arrange.

  In the embodiment described above, modules and input / output units are arranged in a matrix, but the present invention is not limited to this. For example, the number of rows in the matrix described above may be one. In this case, the modules and input / output units may be arranged along one straight line, may be arranged along an arbitrary line such as a curve or a meander line, or may be arranged in a zigzag shape. good.

  All of the semiconductor integrated circuits described above may be formed on the same semiconductor chip, or may be divided into a plurality of semiconductor chips by using a technique such as SIP (system in package).

It is a figure showing an example of composition of a semiconductor integrated circuit concerning an embodiment. It is a figure which shows the structural example of an input / output part and a module. FIG. 2 is a diagram showing an example of defect relief in the semiconductor integrated circuit shown in FIG. 1. It is a 1st figure for demonstrating a mode that the input direction of function setting data changes with defect relief. It is the 2nd figure for demonstrating a mode that the input direction of function setting data changes with defect relief. It is a figure which shows the redundant basic composition in structured ASIC using the multi-input LUT which concerns on this embodiment. FIG. 7 is a diagram illustrating a wiring layout example when there is no defect (defect) in each cell portion of FIG. 6. It is a figure which shows the case where there exists a defect (defect) in the cell part of FIG. It is a figure for demonstrating the case where the physical size of the circuit block used as redundancy object differs. It is a figure which shows an example which comprised the programming part of LUT which concerns on this embodiment with the memory circuit. It is a figure which shows the structural example of a SRAM cell. It is a figure which shows the other example which comprised the programming part of LUT which concerns on this embodiment with the memory circuit. It is a figure which shows the structural example of a contact-type memory cell.

Explanation of symbols

  50 ... Module selection unit, 100 ... General circuit block, PD ... Data holding unit, SEL ... Selector, M11-M19, M21-M29, M31-M39, M41-M49 ... Module, P11 to P18, P21 to P28, P31 to 38, P41 to P48 ... I / O unit, 200 ... structured ASIC, 201-1 to 201-5 ... cell unit, 202 ... redundant cell unit, 300, 300A ... memory circuit, 310 ... memory cell array, 320 ... sense amplifier sense amplifier group, 330 ... row decoder, 340 ... switch group, 350 ... column selector.

Claims (4)

M (M is an integer greater than or equal to 2) columns of circuit sections;
An interface part sequence that uniquely determines an arbitrary input / output logic, and
The interface unit row is arranged between the circuit unit rows, and before redundancy, has a structure connected to a circuit unit row adjacent to the first side,
When there is a defect in a predetermined circuit section row, the interface section row in which the defective circuit section row is sequentially arranged from the interface section row located on the first side is connected to the circuit section row adjacent on the second side. The cell part is arranged by the column shift redundancy method,
A semiconductor integrated circuit for programming a plurality of data before and after redundancy in a programming unit of a look-up table (LUT) that realizes logic of a circuit unit. The semiconductor integrated circuit according to claim 1, wherein programming is completed by using a contact in the programming unit and connecting to a different power source. The semiconductor integrated circuit according to claim 1, wherein the programming unit includes a memory cell and completes programming by connecting to a different power source. The semiconductor integrated circuit according to claim 1, wherein redundancy of circuit blocks having different physical sizes is performed using the same redundancy address.

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