JP4614129B2 - Network load tester - Google Patents

Description

  The present invention relates to a load tester for a network that can keep the instantaneous transmission rate constant.

  In a network such as Ethernet (registered trademark), a load test is performed by continuously transmitting transmission frames having different frame lengths. Ethernet (registered trademark) stipulates that an IFG (Inter Frame Gap) having a minimum length is provided between transmission frames.

  FIG. 6 shows the configuration of a load tester for performing such a network load test. In FIG. 6, the timing generation unit 10 includes a frame counter 11 and an IFG counter 12, and outputs a frame trigger signal and an IFG trigger signal.

  The frame counter 11 includes four counters 11a to 11d. These counters 11a to 11d operate in order. Since four counters are built in, this load tester can generate four types of transmission frames having different frame lengths.

  The counters 11a to 11d are counted up by a clock from a clock generator (not shown), and when the count value reaches a predetermined set value, a frame trigger signal is output to the frame generation unit 20 and the IFG counter 12, and resets itself. The IFG counter 12 starts counting up when a frame trigger signal is input, resets itself when reaching a predetermined set value, and outputs the IFG trigger signal to the counters 11 a to 11 d and the frame generation unit 20. Reset itself. In response to the IFG trigger signal, the next counter starts counting up.

The set value of the IFG counter 12 is determined based on the following expression (1) so that the average value of the transmission rate (= transmission frame length / (transmission frame length + IFG length)) is constant.
Setting value = ((F1 + F2 + F3 + F4) / 4) × (100−A) / A (1)
F1, F2, F3, and F4 are set values (transmission frame length) of the counters 11a to 11d, respectively, and A is a transmission rate (% unit).

  Next, the operations of the timing generator 10 and the frame generator 20 will be described with reference to FIG. 2, (A) to (D) are operations of the counters 11a to 11d, (E) is an operation of the IFG counter 12, and (F) is an output of the frame generation unit 20, respectively.

  The counter 11a starts counting up from time t1, and at the same time, the frame generation unit 20 generates and outputs a transmission frame using frame data (destination address, transmission source address, data, payload, etc.) output by the frame data unit 30. To do. When the counter 11a counts up at time t2, a frame trigger signal is output. When this frame trigger signal is input, the frame generation unit 20 stops generating a transmission frame and continuously outputs IFG (data “0”). When the IFG trigger signal is output at time t3, the counter 11b starts counting up, and the frame generation unit 20 stops outputting the IFG and generates a transmission frame again.

  Similarly, a frame trigger signal is output at time t4, and the frame generation unit 20 stops generating a transmission frame and outputs an IFG. Since the IFG trigger signal is output at time t5, output of the IFG is stopped and transmission frame generation is resumed. Thereafter, in the same manner, the counters 11c and 11d sequentially count up, and the generation of the transmission frame and the output of the IFG are repeated alternately.

  Patent Document 1 describes an invention of a timing generation circuit used in ATM (Asyncronous Transfer Mode). The configuration of this timing generation circuit is shown in FIG. In ATM, a plurality of fixed bit rates are set, and data must be transmitted to the ATM network at a cell gap period determined for each of these fixed bit rates. In order to generate the period of the cell gap, a clock having a predetermined frequency is counted, and a timing pulse is output every time the counted value reaches a specified value. However, in order to satisfy the specified cell gap accuracy, clocks in the order of gigahertz must be counted. There was a problem that the circuit scale increased.

Therefore, the output of the 28-bit adder is stored in the latch 42 in synchronization with the 2 MHz clock, and the operation of adding the output of this latch and the initial value by the 28-bit adder 41 is repeated, and the overflow of the 28-bit adder 41 is repeated. The signal is a cell generation trigger pulse. By doing so, it is possible to cope with various bit rates by using a clock having a low frequency of 2 MHz only by changing the initial value.
JP 2003-289323 A

However, such timing generation circuits and load testers have the following problems. The network load tester shown in FIG. 6 can set the average transmission rate to a desired value by using (1). However, if the IFG length is _FIFG , the transmission rates of the transmission frames are F1 / _FIFG , F2 / _FIFG , F3 / _FIFG , and F4 / _FIFG , respectively. Since F1 to F4 are different from each other, there is a problem that the transmission rate of each transmission frame is not constant.

  Further, the timing generation circuit described in Patent Document 1 requires a 28-bit adder and a latch in order to obtain a cell gap period with a predetermined accuracy, and there is a problem when the circuit scale increases.

  Accordingly, an object of the present invention is to provide a network load tester capable of making the transmission rate constant in units of transmission frames.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
A network load tester that performs a load test on a network that exchanges information by alternately transmitting transmission frames and interframe gaps,
A frame length and a transmission rate of the transmission frame are input, a ratio calculation unit that calculates and outputs a ratio between the IFG length that is the length of the interframe gap and the frame length from these input values;
A frame counter that outputs a frame trigger signal when the clock signal is counted by a value equal to the frame length after the IFG trigger signal is input;
When the IFG trigger signal is input, the output value of the ratio calculation unit is accumulated in synchronization with the clock signal, and when the frame trigger signal is input, a fixed value is accumulated in synchronization with the clock signal. An accumulation part to calculate,
A comparator that compares a value accumulated by the accumulation unit with a predetermined value, and outputs the IFG trigger signal when the accumulated value is smaller than the predetermined value;
A frame generation unit that starts transmission of a transmission frame when the IFG trigger signal is input and starts output of an inter-frame gap when the frame trigger signal is input. The transmission rate can be made constant even instantaneously.

The invention according to claim 2
A network load tester that performs a load test on a network that exchanges information by alternately transmitting transmission frames and interframe gaps,
A ratio calculation unit that receives the IFG length and the transmission rate that are the length of the interframe gap, calculates the ratio of the frame length that is the length of the transmission frame and the IFG length from these input values, and outputs the ratio.
An IFG counter that outputs an IFG trigger signal when the clock signal is counted by a value equal to the IFG length after a frame trigger signal is input;
When the frame trigger signal is input, the output value of the ratio calculation unit is accumulated in synchronization with the clock signal, and when the IFG trigger signal is input, a fixed value is accumulated in synchronization with the clock signal. An accumulation part to calculate,
A comparator that compares a value accumulated by the accumulation unit with a predetermined value, and outputs the frame trigger signal when the accumulated value is smaller than the predetermined value;
A frame generation unit that starts transmission of a transmission frame when the IFG trigger signal is input and starts output of an inter-frame gap when the frame trigger signal is input. The transmission rate can be made constant even instantaneously.

The invention according to claim 3 is the invention according to claim 1 or 2,
The accumulation unit accumulates an integer part and a fraction part of the ratio calculated by the ratio calculation unit and sets the fixed value to -1. The configuration can be simplified.

As is apparent from the above description, the present invention has the following effects.
According to the first, second, and third aspects of the present invention, the ratio of the two lengths is accumulated while the frame for setting the length is transmitted among the two frames of the transmission frame and the interframe gap. A fixed value is accumulated during transmission of a frame for which the length is not set, and when the accumulated value falls below a predetermined value, switching to transmission of a frame for setting the length is performed.

  Depending on the length of the frame for which the length is set, the length of the frame for which the length is not set is adjusted, so that not only the average transmission rate but also the instantaneous transmission rate can be made constant. There is an effect. In addition, since the bit length of the adder can be shortened, there is an effect that the circuit scale can be reduced.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a network load tester according to the present invention. In addition, the same code | symbol is attached | subjected to the same element as FIG. 6, and description is abbreviate | omitted. In FIG. 1, reference numeral 50 denotes a timing generation unit, which includes a ratio calculation unit 51, a frame counter register 52, a frame counter 53, a fixed register 54, a ratio register 55, a switch 56, an adder 57, an addition register 58, and a comparator 59. Then, the frame trigger signal and the IFG trigger signal are output to the frame generator 20.

The ratio calculation unit 51 acquires the frame length and transmission rate of the frame to be transmitted from the frame data unit 30, and calculates the ratio of the IFG length to the transmission frame length using the following equation (2). A is a frame transmission rate expressed in%.
IFG length ratio = (100−A) / A (2)
The frame counter register 52 stores the frame length acquired by the ratio calculation unit 51.

  The fixed register 54 stores the value -1, and the ratio register 55 stores the ratio of the IFG length calculated by the ratio calculator 51 according to the above equation (2). This ratio is stored separately in an integer part and a decimal part. Although the number of digits of the decimal part stored is arbitrary, the accuracy of the transmission rate can be increased as the number of digits increases.

  The value stored in the fixed register 54 is input to the A side of the switch 56, and the value stored in the ratio register 55 is input to the B side. The switch 56 selects and outputs these values. The adder 57 adds the value selected by the switch 56 and the value of the addition register 58 and outputs the result. The addition register 58 holds the value added by the adder 57. The comparator 59 compares the value of the addition register 58 with a predetermined set value, and outputs an IFG trigger signal, which is the comparison result, to the frame counter 53 and the switch 56.

  The adder 57 and the addition register 58 constitute an accumulator. When the IFG trigger signal is input, the switch 56 thereafter inputs the output of the ratio register 55 to this accumulator, and when the frame trigger signal is input, the value of the fixed register 54 is thereafter input to the accumulator. Plays the role of typing.

  Next, the operation of this embodiment will be described with reference to the flowchart of FIG. Note that a series of steps from steps (A-4) to (A-6) and steps (A-11) to (A-12) are executed in synchronization with the same clock. In FIG. 2, first, in step (A-1), the frame length is set in the frame counter register 52, the addition register 58 is cleared to zero, and the initial setting for setting the switch 56 to the B side is performed.

  Next, in step (A-2), the ratio of the IFG length calculated by the ratio calculation unit 51 using the equation (2) from the transmission rate is set in the ratio register 55. This ratio is stored separately in an integer part and a decimal part. In step (A-3), the frame length stored in the frame counter register 52 is set in the frame counter 53.

  Next, in step (A-4), the frame counter 53 is counted down, and in step (A-5), the value stored in the ratio register 55 is added to the value in the addition register 58 and stored in the addition register 58. This addition is performed separately for the integer part and the fractional part. In step (A-6), it is checked whether the count value of the frame counter 53 is 0. If not, the process returns to step (A-4). That is, the value of the ratio register 55 is added to the addition register 58 in synchronization with the clock until the value of the frame counter 53 becomes zero.

  When the value of the frame counter 53 becomes 0, a frame trigger signal is output in step (A-7). When this frame trigger signal is input, the frame generation unit 20 interrupts output of the transmission frame and starts output of IFG. In step (A-8), it is checked whether a frame stop interrupt has occurred. If it has occurred, frame transmission is stopped.

  If no frame interrupt has occurred, the switch 56 is switched to the A side in step (A-10). Actually, the switch 56 is switched to the A side when a frame trigger signal is input. As a result, the value stored in the fixed register 54, that is, −1 is input to the adder 57.

  Next, in step (A-11), the output of the adder 57 is latched in the addition register 58. Since the value of the addition register 58 and -1 (value stored in the fixed register 54) are input to the adder 57, the output of the adder 57 is latched in the addition register 58 in synchronization with the clock. The addition register 58 can be decremented in synchronization with the clock.

  In step (A-12), the comparator 59 determines whether or not the value stored in the addition register 58 is smaller than 1, and if smaller, outputs an IFG trigger signal. The switch 56 is switched to the B side, and the addition register 58 is cleared to zero. And it returns to a process (A-3). When the IFG trigger signal is input, the frame generation unit 20 interrupts the output of the IFG and starts outputting the transmission frame.

  By doing so, the IFG length is controlled to the length of the ratio set in the ratio register 55 for each transmission frame, so that the transmission rate can be made constant even instantaneously. In addition, since the ratio between the IFG length and the frame length is divided into an integer part and a fraction part and set in the ratio register 55, and the adder 57 adds the integer part and the fraction part separately, the data can be accurately obtained with a short data length. The transmission rate can be made constant.

  Next, the operation of this embodiment will be described in more detail with reference to FIG. The frame transmission rate was 62.5%. The ratio register 55 stores 0.6 calculated by the equation (2).

  FIG. 3A shows a clock, which operates in synchronization with both rising and falling of this clock. (B) is a frame trigger signal, and (C) is a count value of the frame counter 53. The frame counter 53 decrements in synchronization with the rise and fall of the clock. (D) is the stored value of the integer part of the addition register 58, (E) is the stored value of the decimal part, (F) is the IFG trigger signal, and (G) is the transmission signal that is the output of the frame generating unit 20.

  FIG. 3 starts from a state in which a transmission frame is output. The adder 57 adds the value (= 0.6) stored in the ratio register 55 to the addition register 58 in synchronization with the rise and fall of the clock. When the decimal part becomes 10 or more, a carry is generated.

  Since the value of the decimal part becomes 12 at time t1, a carry occurs, the integer part increases by 1, and the decimal part becomes 2. At time t2, the value of the frame counter 53 becomes 0 and a frame trigger signal is generated. Therefore, the frame generation unit 20 interrupts the output of the transmission frame and starts outputting the IFG. The switch 55 is switched to the A side. Thereafter, the addition register 58 is decremented by one.

  Since the value of the addition register 58 becomes smaller than 1 at time t3, an IFG trigger signal is output. Therefore, the frame length is set in the frame counter 53, and the frame generation unit 20 interrupts the IFG output and starts frame transmission. Further, since the switch 55 is switched to the B side, the stored value of the addition register 58 is increased by the value (= 0.6) stored in the ratio register 55. This series of operations continues until a frame stop interrupt occurs.

  FIG. 4 shows the calculation result of the transmission rate according to this embodiment. The set value of the transmission rate was 62.5%. 5A shows the IFG length in the conventional example (FIG. 5), FIG. 5B shows the same instantaneous transmission rate, FIG. 5C shows the calculated IFG length in FIG. 1 embodiment, FIG. 5D shows the actual IFG length, E) is the instantaneous transmission rate.

  As shown in (A), in the conventional example, even if the frame length changes, the IFG length is constant at 385 bytes. Therefore, as shown in (B), when the frame length is changed between 69 and 1518 bytes, the average transmission rate is 62.476%, which is close to the set value, but the instantaneous transmission rate is 15%. 198 to 79.768%.

  In contrast, in the embodiment of FIG. 1, the IFG length also changes according to the frame length. (C) is a calculated value of the IFG length that keeps the instantaneous transmission rate constant (= 62.5%). Actually, since the IFG length can take only an integer value, the value after the decimal point is rounded down as shown in (D). The instantaneous transmission rate when the IFG length is shown in (E). From this figure, even if the frame length is changed from 69 to 1518 bytes, the instantaneous transmission rate changes only at most 0.2%.

  In this embodiment, the integer part and fraction part of the ratio of IFG length to frame length are stored in the ratio register 55 and the addition register. However, the ratio may be multiplied by n to store only the integer part. Good. In this case, −n is stored in the fixed register 54. In the IFG output period (period from t2 to t3 in FIG. 3), n is subtracted from the stored value of the addition register 58.

  FIG. 5 shows another embodiment of the present invention. In this embodiment, an IFG length is set, and a transmission frame having a length corresponding to the IFG length is output. In addition, the same code | symbol is attached | subjected to the same element as FIG. 1, and description is abbreviate | omitted.

In FIG. 5, 60 is a timing generator. The ratio calculation unit 61 acquires the IFG length and the transmission rate from the frame data unit 30, and calculates the ratio of the transmission frame length to the IFG length using the following equation (3). A is a frame transmission rate expressed in%.
Transmission frame length ratio = A / (100−A) (3)
The IFG counter register 62 stores the IFG length acquired by the ratio calculation unit 51.

  The operation is almost the same as the flowchart in FIG. In the IFG counter 63, the IFG length stored in the IFG counter register 62 is set. The set value is counted down, and the transmission frame length ratio set in the ratio register 55 is added to the addition register 58 at the same time.

  When the IFG counter reaches 0, an IFG trigger signal is output. The frame generation unit 20 stops outputting the IFG with this IFG trigger signal and starts outputting the transmission frame. Further, the value (−1) of the fixed register 54 is subtracted from the value of the addition register 58.

  When the value of the addition register 58 becomes smaller than 1, a frame trigger signal is generated. The frame generation unit 20 stops outputting the transmission frame by this frame trigger signal and starts outputting IFG. These series of operations are continued until a frame stop interrupt occurs.

  In this embodiment as well, as in the embodiment of FIG. 1, the ratio may be stored or added separately for the integer part and the decimal part, or may be stored and added by multiplying by n. In this case, the fixed register 54 may store a value of −n.

  Further, the frame counter 53 of FIG. 1 embodiment and the IFG counter 63 of FIG. 5 embodiment first set the length, decrement in synchronization with the clock signal, and when it becomes zero, the frame trigger signal (IFG trigger) However, other configurations may be used such as first clearing to zero, incrementing in synchronization with the clock signal, and outputting a trigger signal when a value corresponding to the length is reached. The point is that the frame trigger signal (IFG trigger signal) may be output when the clock corresponding to the set length is counted after the IFG trigger signal (frame trigger signal) is input.

It is a block diagram which shows one Example of this invention. It is a flowchart for demonstrating operation | movement of one Example of this invention. It is a time chart for demonstrating operation | movement of one Example of this invention. It is a table | surface which shows the effect of this invention. It is a block diagram of the other Example of this invention. It is a block diagram of the conventional network load tester. It is a time chart for demonstrating operation | movement of the conventional network load tester. It is a block diagram of the conventional timing generation circuit.

Explanation of symbols

20 Frame generation unit 30 Frame data unit 50, 60 Timing generation unit 51, 61 Ratio calculation unit 52 Frame counter register 53 Frame counter 54 Fixed register 55 Ratio register 56 Switch 57 Adder 58 Addition register 59 Comparator 62 IFG counter register 63 IFG counter

Claims (3)

A network load tester that performs a load test on a network that exchanges information by alternately transmitting transmission frames and interframe gaps,
A frame length and a transmission rate of the transmission frame are input, a ratio calculation unit that calculates and outputs a ratio between the IFG length that is the length of the interframe gap and the frame length from these input values;
A frame counter that outputs a frame trigger signal when the clock signal is counted by a value equal to the frame length after the IFG trigger signal is input;
When the IFG trigger signal is input, the output value of the ratio calculation unit is accumulated in synchronization with the clock signal. When the frame trigger signal is input, a fixed value is accumulated in synchronization with the clock signal. An accumulation part to calculate,
A comparator that compares a value accumulated by the accumulation unit with a predetermined value, and outputs the IFG trigger signal when the accumulated value is smaller than the predetermined value;
A network load comprising: a frame generation unit that starts output of a transmission frame when the IFG trigger signal is input and starts output of an interframe gap when the frame trigger signal is input Tester. A network load tester that performs a load test on a network that exchanges information by alternately transmitting transmission frames and interframe gaps,
A ratio calculation unit that receives the IFG length and the transmission rate that are the length of the interframe gap, calculates the ratio of the frame length that is the length of the transmission frame and the IFG length from these input values, and outputs the ratio.
An IFG counter that outputs an IFG trigger signal when the clock signal is counted by a value equal to the IFG length after a frame trigger signal is input;
When the frame trigger signal is input, the output value of the ratio calculation unit is accumulated in synchronization with the clock signal, and when the IFG trigger signal is input, a fixed value is accumulated in synchronization with the clock signal. An accumulation part to calculate,
A comparator that compares a value accumulated by the accumulation unit with a predetermined value, and outputs the frame trigger signal when the accumulated value is smaller than the predetermined value;
A network load comprising: a frame generation unit that starts output of a transmission frame when the IFG trigger signal is input and starts output of an interframe gap when the frame trigger signal is input Tester. 3. The accumulation unit according to claim 1, wherein an integral part and a fraction part of the ratio calculated by the ratio calculation unit are divided and accumulated, and the fixed value is set to -1. The network load tester described in 1.

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