JP4609977B2 - Digital transmitter, digital receiver, data scramble method, data descramble method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital transmission device, a digital reception device, a data scrambling method, and a data descrambling method for avoiding a data error due to erroneous detection of a symbol synchronization position when data is a continuation of a specific symbol pattern over a long period of time. It is about.
[0002]
[Prior art]
When dealing with an increase in demand for mobile communications using a limited frequency band, there is a need to increase the frequency utilization efficiency. The most efficient means is QAM (Quadrature Amplitude Modulation).
[0003]
When QAM is used for mobile communications, it is necessary to deal with envelope and phase changes due to fading fluctuations. As a coping method, for example, “Transmission path distortion compensation method” disclosed in Japanese Patent Publication No. 6-1908 and Reference 1: Electronic Information Communication Society Journal B-II Vol. J72-B-II No. 1 pp7-15, January 1989, Sanbe et al. Proposed "16QAM fading distortion compensation system for land mobile communications". This proposed method is a pilot symbol interpolation synchronous detection method that measures fading distortion from known pilot symbols inserted at regular intervals and estimates and compensates for fading distortion of all pilot symbols by interpolating the time series. . In this case, the target modulation scheme is often 16QAM.
[0004]
Here, a known pilot symbol inserted at a constant interval will be described. FIG. 4 is a diagram illustrating an example of a frame configuration using a PSI (Pilot Symbol Insertion) method. As shown in FIG. 4, one frame is composed of one symbol of pilot symbol PS and 16 symbols of data to be transmitted.
[0005]
Further, in connection with the above proposed scheme, Reference 2: IEICE Technical Report RCS92-106 (1993-1), Sanbe et al., “16QAM / TDMA scheme symbol timing recovery scheme” has been proposed. The MAM (Maximum Amplitude Method) used here is a synchronization establishment method in which a symbol indicating the maximum amplitude is a synchronization position.
[0006]
Here, mapping of symbols used for MAM will be described. Here, mapping refers to arranging one symbol on a coordinate plane composed of an I-phase component and a Q-phase component. FIG. 5 is a diagram illustrating an example of mapping positions corresponding to known pilot symbols. In FIG. 5, the horizontal axis represents the I-phase component, and the vertical axis represents the Q-phase component. As shown in FIG. 5, the pilot symbol mapping PS is arranged so that both the I-phase component and the Q-phase component have positive maximum values.
[0007]
Reference 2 confirms by simulation results that good characteristics can be obtained when the frame length is several tens of symbols and the number of oversamples is 32 times in MAM.
[0008]
However, the synchronization establishment method based on MAM detects the synchronization position for data in which the maximum amplitude appears in the same frame period as the pilot symbol due to the property that the mapping position of the pilot symbol is arranged in the symbol of the maximum amplitude. There is a problem of making mistakes.
[0009]
Here, the above-described problem will be described with a specific example. FIG. 6 is a diagram showing mapping of symbols in 16QAM. The horizontal axis in FIG. 6 represents the I-phase component, and the vertical axis represents the Q-phase component. Here, one symbol is obtained by dividing data into 4 bits, and the contents of 4 bits are arranged according to FIG.
[0010]
For example, the pilot symbol is periodically arranged at the position of the symbol “0000” in FIG. 6 and transmitted. When the power in each symbol of the frame is averaged over the long term during reception, symbols with peaks appear gradually. In MAM, a symbol having this peak is determined to be a pilot symbol and set as a synchronization position.
[0011]
However, if any specific symbol of “0000”, “0100”, “1000”, and “1100” having the maximum amplitude in FIG. 6 is present in the data and this specific symbol appears in the frame period, it is not a pilot symbol. A peak will also occur.
[0012]
FIG. 7 is a diagram illustrating an example of a result of long-term averaging of symbol power in a frame period. The upper part of FIG. 7 is a symbol string having the same configuration as that of FIG. The lower part of FIG. 7 is a time axis waveform obtained by averaging the power of the upper symbol string in the frame period over a long period, and has a length of one frame.
[0013]
As shown in the upper part of FIG. 7, when the same symbol appears in the frame period of the pilot symbol “0000” and a symbol “1000” in the data, as shown in the lower part of FIG. In addition to the peak {circle around (1)} due to the symbol “0000”, the peak {circle around (2)} due to the symbol “1000” appears in the data, and there is a possibility of establishing synchronization with both the symbols {circle around (1)} and {circle around (2)}. As a result, false synchronization occurs.
[0014]
In order to solve the problems in the MAM described above, it is common to use a scramble process for data. Here, the scramble means will be described. FIG. 8 is a block diagram showing an example of the configuration of the conventional scrambling means. As shown in FIG. 8, this scramble means includes adders 801 and 802 and shift registers 811, 812, 813, 814, 815 and 816.
[0015]
Here, X is a bit after scrambling, and Y is a bit before scrambling. Z ^-n X (n is an integer) is an output of the n-th shift register, and X is delayed by n bit times. For example, Z ⁻² X is the output of the second-stage shift register 815, and is a bit obtained by delaying X by 2 bit times. The scramble means for the bit Y before scramble is performed based on the following equation.
[0016]
X = Y + (Z ⁻¹ + Z ⁻⁶ ) · X (1)
[0017]
The scrambled bit Y is scrambled based on the above-described equation (1) and output as a scrambled bit X.
[0018]
Next, descrambling processing is performed on the scrambled bit X. FIG. 9 is a block diagram showing an example of the configuration of conventional descrambling means. As shown in FIG. 9, the descrambling means includes adders 901 and 902 and shift registers 911, 912, 913, 914, 915 and 916. The descrambling process of the scrambled bit X is performed based on the following equation.
[0019]
Y = (1 + Z ⁻¹ + Z ⁻⁶ ) · X (2)
[0020]
The scrambled bit X is restored as the pre-scrambled bit Y by performing a descrambling process based on the above-described equation (2).
[0021]
As described above, by performing the scramble process on the transmission data, it is possible to give randomness to the data in which a specific symbol pattern appears in the frame period. By providing randomness to the data, accurate synchronization position detection is promised.
[0022]
[Problems to be solved by the invention]
However, in the scramble process described above, depending on the relationship between the state of the shift register and the bit string input thereafter, a specific symbol pattern may be output in the frame period, so that erroneous synchronization occurs.
[0023]
The present invention has been made in view of the above-described problems, and prevents digital data from becoming continuous with a specific symbol pattern over a long period of time, enabling accurate synchronization to be established, a digital transmission device, a digital reception device, and data It is an object to provide a scrambling method and a data descrambling method.
[0024]
[Means for Solving the Problems]
In order to achieve the above-described object, the present invention provides a digital transmission device for giving non-periodicity to data in digital communication, and a range in which data is determined when the existence of the non-periodicity is not confirmed. A first data inversion means for inverting the bit string, a scramble shift register string for performing a scramble process on the output of the first data inversion means, and a state of the scramble shift register string in the immediately preceding frame, First comparison means for comparing whether or not a state of the scramble shift register sequence in the current frame is equal; a first counter for updating a value based on a result of the first comparison means; Instructs the first data inversion means to invert data based on the determination whether the value of one counter is equal to or greater than a predetermined threshold value. That a first reversing instructing means, is characterized in that a modulation processing means for transmitting the output of the scramble shift register sequence to modulate externally.
[0025]
According to such a configuration, when the presence of non-periodicity in the data is not confirmed, by performing inversion processing on a bit string in a predetermined range of data input in the next frame, Data periodicity can be prevented.
[0026]
In the digital transmission apparatus of the present invention, the modulation processing means periodically inserts a known symbol at a predetermined position with respect to the output of the scramble shift register train. . The modulation processing means can use a QAM modulation method, a QPSK modulation method, or the like as a specific modulation method.
[0027]
According to such a configuration, the synchronization position can be easily detected.
[0028]
Furthermore, in the digital transmission apparatus of the present invention, the known symbol is arranged at the maximum amplitude among possible symbols.
[0029]
According to such a configuration, the synchronization position can be detected in the demodulation process by taking the maximum amplitude among the symbols that can be taken by the known symbols.
[0030]
According to another aspect of the present invention, there is provided a digital reception device that receives a signal from the digital transmission device described above, wherein the demodulation processing means demodulates the signal from the digital transmission device, and the output of the demodulation processing means. A descrambling shift register string for performing descrambling processing corresponding to the scramble shift register string, a state of the descrambling shift register string in the immediately preceding frame, and a descrambling shift register string in the current frame Second comparison means for comparing whether or not the state of the second state is equal, a second counter for updating the value based on the result of the second comparison means, and a threshold value for which the value of the second counter is predetermined A second inversion instruction means for instructing data inversion based on the determination as to whether or not the data is in the above; A bit string of a predetermined range of the output of the static column, is characterized in that a second data inversion means for inverting accordance with the output of said second inverting instruction means.
[0031]
According to such a configuration, it is possible to restore the scrambled data by performing a process similar to the process performed on the transmitter side.
[0032]
In the digital receiver of the present invention, the demodulation processing means detects a symbol having the maximum amplitude among possible symbols and performs synchronization.
[0033]
According to such a configuration, the synchronization position can be detected by detecting the symbol with the maximum amplitude.
[0034]
The present invention is also a data scramble method for giving non-periodicity to data in digital communication, and inversion processing is performed on a bit string in a predetermined range when the existence of the non-periodicity is not confirmed. The scramble process using the scramble shift register string is performed on the result of the inversion process, the state of the scramble shift register string in the previous frame is stored, and the scramble shift register string in the current frame is stored. In order to determine whether the first counter value is equal to or greater than a predetermined threshold value, the first counter value is updated based on the comparison result. The presence of the non-periodicity is determined based on, and a reverse instruction is performed based on the determination result of the non-periodic presence. .
[0035]
According to such a configuration, when the presence of non-periodicity in the data is not confirmed, by performing inversion processing on a bit string in a predetermined range of data input in the next frame, Data periodicity can be prevented.
[0036]
Furthermore, the present invention provides a data descrambling method for descrambling data scrambled by the data scrambling method, wherein a descrambling shift register sequence corresponding to the scrambled register sequence is added to the scrambled data. The descrambling process is used to store the state of the descrambling shift register sequence in the immediately preceding frame, and the state of the descrambling shift register sequence in the current frame is compared to determine whether or not they are equal. Updating the value of the second counter based on the comparison result, determining the presence of the non-periodicity based on the determination of whether the value of the second counter is equal to or greater than a predetermined threshold value, and the non-periodicity The inversion instruction is performed based on the result of determination of the presence of.
[0037]
According to such a configuration, it is possible to restore the scrambled data by performing a process similar to the process performed on the transmitter side.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram illustrating an example of a configuration of a digital transmitter and a digital receiver in this embodiment.
[0039]
The digital transmitter 100 includes a data scrambler 110 and a modulation processing unit 120. On the other hand, the digital receiver 200 includes a data descrambling device 210 and a demodulation processing unit 220.
[0040]
The data scrambler 110 includes a data inversion unit 101, a scramble shift register array 102, a comparison unit 103, a counter 104, and an inversion instruction unit 105. On the other hand, the data descrambling apparatus 210 includes a descrambling shift register train 201, a comparison unit 202, a counter 203, an inversion instruction unit 204, and a data inversion unit 205.
[0041]
In the present embodiment, the modulation processing means is the modulation processing section 120, the first data inversion means is the data inversion section 101, and the first comparison means is the comparison section 103. The first counter means the counter 104, the first inversion instruction means means the inversion instruction section 105, the demodulation processing means means the demodulation processing section 220, and the second comparison means. The second counter is the counter 203, the second inversion instruction means is the inversion instruction section 204, and the data inversion means is the data inversion section 205.
[0042]
In the present embodiment, a case will be described in which a frame configured using the PSI system shown in FIG. 4 is modulated by the QAM modulation system. The MAM described above is used as a synchronization establishment method for detecting the symbol synchronization position of a known symbol.
[0043]
Here, for example, the conventional scrambling means described with reference to FIG. 8 is applied to the scramble shift register string 102, and the conventional descrambling means described with reference to FIG. 9 is applied to the descrambling shift register string 201. .
[0044]
Next, operations of the digital transmitter and digital receiver of FIG. 1 will be described. First, the operation of the digital transmitter 100 will be described. The transmission data is input to the data scrambler 110. Data scrambler 110 performs data scramble processing on the transmission data, and outputs the scrambled data obtained as a result to modulation processing section 120. The modulation processing unit 120 generates a frame using the PSI method from the scrambled data, further performs QAM modulation, and outputs the result to the digital receiver 200 as a modulated wave.
[0045]
Next, the operation of the data scrambler 110 will be described in detail. The transmission data is input to the data inverting unit 101. In accordance with the inversion instruction output from the inversion instruction unit 105, the data inversion unit 101 performs inversion or non-inversion of a bit string in a predetermined range of transmission data input in the next frame, and outputs the result for each frame. Are output to the scramble shift register array 102. Here, if the number of bits to be inverted is a predetermined number and position in both the digital transmitter 100 and the digital receiver 200, the same effect can be obtained with one bit or a plurality of bits.
[0046]
The scramble shift register sequence 102 performs scramble processing for one frame output from the data inverting unit 101, and outputs scrambled data obtained as a result to the modulation processing unit 120. Further, the scramble shift register sequence 102 outputs the state (SR) of the shift register sequence at the end of the current frame to the comparison unit 103.
[0047]
Here, an inversion instruction operation for transmission data by the comparison unit 103, the counter 104, and the inversion instruction unit 105 will be described using a flow. FIG. 2 is a flowchart illustrating an example of an inversion instruction operation for transmission data. First, for initialization, SR (the state of the shift register train at the end of the current frame), PSR (the state of the shift register train at the end of the previous frame), SRC (counter value), X (counter count) Threshold value) is set to an initial value (S201). Next, data is input (S202), and it is determined whether the inversion flag is on or off (S203). When the inversion flag is on, the preset data sequence is inverted (S204), and the comparison unit 103 acquires SR from the scramble shift register sequence 102 at the end of the frame (S205). If the inversion flag is OFF in step S203, the process proceeds to step S205 without inversion.
[0048]
The comparison unit 103 stores the state (PSR) of the shift register sequence at the end of the immediately preceding frame, and determines whether SR is equal to PSR (S206). The comparison unit 103 outputs a comparison result as to whether SR is equal to PSR to the counter 104.
[0049]
When SR is a comparison result different from PSR (S206, N), the counter 104 sets the counter (SRC) to 0 (S213), and proceeds to processing S214. On the other hand, if SR is a comparison result equal to PSR (S206, Y), the counter 104 updates SRC by adding 1 to SRC (S207), outputs SRC to the inversion instruction unit 105, and proceeds to processing S208. . The inversion instruction unit 105 determines whether or not the SRC from the counter 104 is equal to or greater than a predetermined threshold value x (S208).
[0050]
When the SRC is equal to or greater than the threshold value x (S208, Y), the inversion instruction unit 105 determines that the scrambled data has periodicity, sets the inversion flag to ON (S209), and transmits input in the next frame. An inversion instruction for inverting a bit string in a predetermined range of the data is output to the data inversion unit 101. Further, the inversion instruction unit 105 outputs an instruction to set SRC to 0 to the counter 104. In response to this instruction, the counter 104 sets SRC to 0 (S210), and the process proceeds to step S211.
[0051]
On the other hand, if the SRC is not equal to or greater than the threshold value x (S208, N), the inversion instruction unit 105 sets the inversion flag to OFF (S214), and proceeds to the processing S207 without giving instructions to the data inversion unit 101 and the counter 104.
[0052]
The counter 104 substitutes SR for PSR (S211), determines whether there is data (S212), and if there is data (S212, Y), proceeds to step S203, and if there is no data (S212, N). Ends the flow.
[0053]
Next, the operation of the digital receiver 200 will be described. The modulated wave transmitted from the digital transmitter 100 is input to the demodulation processing unit 220. The demodulation processing unit 220 performs demodulation processing of the modulated wave, and outputs the demodulated data obtained as a result to the data descrambling device 210. The data descrambling device 210 performs a data descrambling process on the demodulated data, and outputs the result as reception data to the outside.
[0054]
Next, the operation of the data descrambling device 210 will be described in detail. The descrambling shift register train 201 performs descrambling processing on one frame output from the demodulation processing unit 220, and outputs the descrambling data obtained as a result to the data inversion unit 205. Further, the descrambling shift register array 201 outputs the SR to the comparison unit 202.
[0055]
In accordance with the inversion instruction output from the inversion instruction unit 204, the data inversion unit 205 inverts or non-inverts a bit string in a predetermined range of descrambling data input in the next frame, and the result is received data. Is output to the outside every frame.
[0056]
Here, an inversion instruction operation for descrambling data by the comparison unit 202, the counter 203, and the inversion instruction unit 204 will be described using a flow. FIG. 3 is a flowchart showing an example of an inversion instruction operation for descrambling data. First, for initialization, SR (the state of the shift register train at the end of the current frame), PSR (the state of the shift register train at the end of the previous frame), SRC (counter value), X (counter count) Threshold value) is set to an initial value (S301). Next, data is input (S302), and the comparison unit 202 acquires SR from the descrambling shift register train 201 at the end of the frame (S303).
[0057]
Here, the comparison unit 202 stores PSR, and determines whether SR is equal to PSR (S304). The comparison unit 202 outputs a comparison result indicating whether SR is equal to PSR to the counter 203.
[0058]
When SR is a comparison result different from PSR (S304, N), the counter 203 sets SRC to 0 (S313), and proceeds to processing S314. On the other hand, if SR is a comparison result equal to PSR (S304, Y), the counter 203 adds 1 to SRC to update SRC (S305), outputs SRC to the inversion instruction unit 204, and proceeds to processing S304. . The inversion instruction unit 204 determines whether or not the SRC from the counter 203 is equal to or greater than a predetermined threshold value x (S306).
[0059]
When the SRC is equal to or greater than the threshold value x (S306, Y), the inversion instruction unit 204 determines that the demodulated data has periodicity, sets the inversion flag to ON (S307), and receives the data input in the next frame. An inversion instruction for inverting a bit string in a predetermined range in the scrambled data is output to the data inverting unit 205. Further, the inversion instruction unit 204 outputs an instruction to set SRC to 0 to the counter 203. In response to this instruction, the counter 203 sets SRC to 0 (S308), and the process proceeds to S309.
[0060]
On the other hand, if the SRC is not equal to or greater than the threshold value x (S306, N), the inversion instruction unit 204 sets the inversion flag to OFF (S314), and the process proceeds to step S309 without giving instructions to the data inversion unit 205 and the counter 203.
[0061]
The counter 203 substitutes SR for PSR (S309), determines whether the inversion flag is on or off (S310), and if it is on, inverts a preset data string (S311) to determine whether there is data. Is determined (S312). If the reverse flag is off, step S311 is omitted and the process proceeds to step S312. If there is data (S312, Y), the process proceeds to step S303, and if there is no data (S312, N), the flow ends.
[0062]
A part or all of the data scrambler 110 and the data descrambler 210 described above can be realized by software using a DSP or the like. The calculation amount of the data scrambler and the data descrambler in this embodiment is about 100 steps each, and there is little addition of processing when realized by a DSP. In this embodiment, the QAM modulation method is used as the modulation method. However, the present invention can be applied even when another modulation method, for example, a QPSK modulation method is used.
[0063]
【The invention's effect】
As described in detail above, according to the present invention, the state of the shift register string is confirmed at the end of the frame, and when the existence of periodicity in the data is confirmed, it is determined in advance among the data input in the next frame. By performing inversion processing on the bit string in the specified range, it is possible to prevent data from continuing a specific symbol pattern over a long period of time, and to prevent erroneous detection of the synchronization position.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an example of a configuration of a digital transmission device and a digital reception device in the present embodiment.
FIG. 2 is a flowchart illustrating an example of an inversion instruction operation for transmission data.
FIG. 3 is a flowchart illustrating an example of an inversion instruction operation for descrambling data.
FIG. 4 is a diagram illustrating an example of a frame configuration using a PSI method.
FIG. 5 is a diagram illustrating an example of mapping positions corresponding to known pilot symbols.
FIG. 6 is a diagram illustrating mapping of symbols in 16QAM.
FIG. 7 is a diagram illustrating an example of a result of long-term averaging of symbol power in a frame period.
FIG. 8 is a block diagram showing an example of a configuration of conventional scramble means.
FIG. 9 is a block diagram showing an example of a configuration of conventional descrambling means.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 Digital transmitter, 110 Data scrambler, 101 Data inversion part, 102 Shift register sequence for scramble, 103 Comparator, 104 counter, 105 Inversion instruction part, 120 Modulation processing part, 200 Digital receiver, 210 Data descrambler, 201 Descramble shift register string, 202 comparison unit, 203 counter, 204 inversion instruction unit, 205 data inversion unit, 220 demodulation processing unit

Claims (7)

A digital transmission device for making data non-periodic in digital communication,
First data inversion means for inverting a bit string in a predetermined range of data when the presence of the aperiodicity is not confirmed;
A scramble shift register string for performing scramble processing on the output of the first data inversion means;
First comparison means for storing the state of the scramble shift register sequence in the immediately preceding frame and comparing whether or not the state of the scramble shift register sequence in the current frame is equal;
A first counter that updates a value based on a result of the first comparing means;
First inversion instruction means for instructing the first data inversion means to invert data based on determination of whether the value of the first counter is equal to or greater than a predetermined threshold;
A digital transmission apparatus comprising modulation processing means for modulating the output of the scramble shift register train and transmitting the modulated output to the outside. The digital transmitter according to claim 1, wherein
The digital transmission apparatus characterized in that the modulation processing means periodically inserts known symbols at predetermined positions with respect to the output of the scramble shift register train. The digital transmission device according to claim 2,
The digital transmission apparatus according to claim 1, wherein the known symbol is arranged at a maximum amplitude among possible symbols. A digital receiver for receiving a signal from the digital transmitter according to any one of claims 1 to 3,
Demodulation processing means for demodulating a signal from the digital transmission device;
A descrambling shift register sequence for performing descrambling processing corresponding to the scramble shift register sequence for the output of the demodulation processing means;
Second comparison means for storing the state of the descrambling shift register sequence in the immediately preceding frame and comparing whether or not the state of the descrambling shift register sequence in the current frame is equal;
A second counter that updates a value based on a result of the second comparing means;
Second inversion instruction means for instructing data inversion based on determination of whether the value of the second counter is greater than or equal to a predetermined threshold;
2. A digital receiving apparatus comprising: a second data inversion means for inverting a bit string in a predetermined range in the output of the descrambling shift register string in accordance with an output of the second inversion instruction means. The digital receiver according to claim 4, wherein
The digital receiving apparatus characterized in that the demodulation processing means detects a symbol having the maximum amplitude among possible symbols and performs synchronization. A data scramble method for giving non-periodicity to data in digital communication,
When the presence of the non-periodicity is not confirmed, inversion processing is performed on a bit string in a predetermined range of data,
A scramble process using a scramble shift register sequence is performed on the result of the inversion process,
Stores the state of the scramble shift register sequence in the previous frame, and compares whether the state of the scramble shift register sequence in the current frame is equal,
Updating the value of the first counter based on the result of the comparison;
Determining the presence of the aperiodicity based on a determination as to whether the value of the first counter is greater than or equal to a predetermined threshold;
A data scramble method characterized by performing an inversion instruction based on the determination result of the existence of non-periodicity. A data descrambling method for descrambling data scrambled by the data scrambling method according to claim 6,
A descrambling process is performed on the scrambled data using a descrambling shift register sequence corresponding to the scrambled register sequence,
Storing the state of the descrambling shift register sequence in the immediately preceding frame, and comparing whether the state of the descrambling shift register sequence in the current frame is equal;
Updating the value of the second counter based on the comparison result;
Determining the presence of the aperiodicity based on a determination as to whether the value of the second counter is equal to or greater than a predetermined threshold;
A data descrambling method, wherein an inversion instruction is performed based on a determination result of the presence of the non-periodicity.

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