JP4603111B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention uses a redundant selection line when a defect occurs in a part of a plurality of selection lines for selecting a specific memory cell from a plurality of memory cells and writing or reading data. The present invention relates to a semiconductor memory device having a shift redundancy function for relief.
[0002]
Recent dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, ferroelectric random access memory (FRAM, ie, Ferromagnetic RAM), etc. When mass-producing a large-capacity semiconductor memory device, it is practically difficult to manufacture a semiconductor chip (semiconductor integrated circuit) having no defects in selection lines and the like. In particular, since there is a high probability that a defect will occur at the initial stage of mass production, this semiconductor chip must be disposed of in the worst case, which may reduce the yield in chip manufacture. In order to suppress the decrease in the yield in manufacturing the chip as much as possible, it is indispensable to take measures for relieving defects by using redundant circuit elements such as redundant selection lines provided in advance in the semiconductor chip.
[0003]
[Prior art]
Various methods are currently used as redundancy methods using redundant circuit elements in the semiconductor chip. Among these, the shift redundancy method has features such as high access speed and low current consumption (power consumption). Therefore, it is considered to be an effective means for recent large-capacity semiconductor memory devices. Until now, when one or two defect selection lines occur due to a short-circuit between selection lines, etc., shift redundancy that repairs the defect selection line by performing 1-bit or 2-bit shift redundancy A semiconductor memory device of the type is known.
[0004]
FIG. 21 is a block diagram showing a configuration example of a semiconductor memory device having the conventional 2-bit (or 1-bit) shift redundancy function as described above, and FIG. 22 is a 2-bit shift redundancy operation according to FIG. It is a schematic diagram for demonstrating. However, here, the configuration of a semiconductor memory device having a shift redundancy function of 2 bits (or 1 bit) with respect to a plurality of selection lines (for example, n (n is an arbitrary positive integer of 2 or more)) is schematically illustrated. Will be shown. Furthermore, here, a case where a defect occurs in the two selection lines sl2 and sl (n-3) will be exemplified.
[0005]
An example of the configuration of a conventional semiconductor memory device having a 2-bit shift redundancy function as shown in FIGS. 21 and 22 is, for example, a prior patent application filed on Nov. 9, 1998. It is disclosed in the specification of 318164.
The semiconductor memory device shown in FIG. 21 is provided with a decoder circuit 500 that decodes an address signal Add supplied from the outside. Further, in this semiconductor memory device, a plurality of selection lines for selecting a specific memory cell from a plurality of memory cells and writing or reading data based on the address of the decode signal Sdec output from the decoder circuit 500. sl0 to sl (n− 1 ) (N is an arbitrary positive integer greater than or equal to 2), and when there is no defect in the plurality of selection lines, it is not connected to any of the plurality of decode signal lines to which the decode signal Sdec is transferred 2 The redundant selection lines slj0 and slj1 are respectively arranged at one end position and the other end position among the plurality of selection lines.
[0006]
Further, in FIG. 21, there is provided a shift redundancy circuit 100 for controlling the connection relationship between the plurality of decode signal lines and the plurality of selection lines and redundancy selection lines. The shift redundant circuit 100 includes a switch unit 200 including a plurality of switch elements, and a shift redundant fuse circuit unit 400 having a plurality of fuses provided corresponding to the plurality of selection lines and the redundant selection lines. The switch unit 200 is configured to connect a plurality of decode signal lines to a plurality of selection lines and redundant selection lines in a switchable manner by an on / off operation of the plurality of switch elements. When one or two defects occur in the plurality of selection lines, the shift redundant fuse circuit unit 400 corresponds to the fuse corresponding to the defect selection line in which these defects have occurred and the redundancy selection line. The redundant selection fuse is cut. Here, the signal output from the shift redundancy fuse circuit unit 400 is input to the shift redundancy control circuit unit 300. Further, the signal output from the shift redundancy control circuit unit 300 is used as a shift control signal for controlling the switch unit 200.
[0007]
Furthermore, the shift redundancy circuit 100 in FIG. 21 makes the non-selection state in which the defect selection line is not connected to any of the decode signal lines according to the output result from the shift redundancy fuse circuit section 400, and the plurality of selections are made. The plurality of decode signal lines are shifted by one selection line (ie, one bit) in the direction of the first redundant selection line slj0 located at one end (for example, the left end) of the lines. Or the plurality of decode signal lines are shifted by one selection line in the direction of the second redundant selection line slj1 located at the other end (for example, the right end) of the plurality of selection lines. As described above, the shift redundancy control circuit unit 300 that controls the switching operation of the plurality of switch elements is provided. In other words, the semiconductor memory device of FIG. 21 shifts by 1 bit or 2 bits by shifting in the direction of the first redundancy selection line, the direction of the second redundancy selection line, or both. Configured to provide redundancy. Here, “shifting the decoding signal line” means shifting the connection state between the selection line and the decoding signal line.
[0008]
Further, in the semiconductor memory device shown in FIG. 21, a mode in which each of the plurality of switch elements in the switch unit 200 performs a shift operation in the direction of the first redundant selection line slj0 (that is, a leftward shift described later). It is possible to select a mode in which a shift operation in the direction of the second redundancy selection line (that is, a rightward shift described later) or a mode in which no shift operation is performed (that is, no shift described later) 3 It is composed of directional switch elements.
[0009]
Next, an outline of the 2-bit shift redundancy operation will be described with reference to the schematic diagram of FIG. In FIG. 22, clj0 and clj1 indicate redundancy selection lines (for example, redundancy selection column selection lines) used in the shift redundancy operation, and cl0 to cl63 indicate selection lines for normal selection used in the normal operation ( For example, a column selection line) is shown. These selection lines are connected to decode signal lines d0 to d63 obtained by decoding an address signal supplied from the outside of the semiconductor chip via a plurality of switch elements in the switch unit 200. Before the shift redundancy process or when there is no defect in the selection line or the like, the switching elements control so that cl0 and d0, cl1 and d1,... Cl62 and d62, and cl63 and d63 are connected. A case where the selection line cl # and the decode signal line d # (#: 0 to 63) are connected is referred to as NS (Non-Shift: no shift).
[0010]
The schematic diagram of FIG. 22 is for explaining a case where defects exist in the two selection lines cl2 and cl57 and shift redundancy is performed on these defects. Decode signal lines d0, d1, and d2 are connected to redundant selection line clj0, selection line cl0, and selection line cl1, respectively (SL (Shift Left): leftward shift). The selection lines cl2 and cl57 are not connected to any decode signal line and are always in a non-selected state. The selection lines cl3 to cl56 are in the NS state, and the selection line, cl58 to cl63, and the redundant selection line clj1 are connected to the decode signal lines d57 to d63, respectively (SR (Shift Right): rightward shift) ).
[0011]
[Problems to be solved by the invention]
As described above, in the semiconductor memory device having the conventional 2-bit shift redundancy function as shown in FIG. 21, when a defect occurs in two of the plurality of selection lines, one redundancy selection line By shifting the decode signal line in the direction and in the direction of the other redundant selection line, it is possible to perform two-bit shift redundancy and relieve two defect selection lines (two defects). On the other hand, if a defect occurs in one of the plurality of selection lines, 1-bit shift redundancy can be achieved by shifting the decode signal line in either direction of the two redundant selection lines. It is also possible to repair one defect selection line (one defect).
[0012]
However, when a semiconductor chip is manufactured for the purpose of mass production of DRAM, SRAM, flash memory, etc., in reality, dust larger than the pitch of the selected line is generated and adhered to the semiconductor chip due to an abnormality in the manufacturing process. There is. In such a case, there are not a few group defects in which three or more defect selection lines (three or more defects) are concentrated on a certain part on the semiconductor chip. In particular, at the initial stage of mass production, there is a tendency that this group defect is relatively likely to occur.
[0013]
Therefore, when three or more defects are generated on the semiconductor chip due to the above-described group failure or the like, it is impossible to relieve the defects even if the conventional 2-bit shift redundancy method is used. It was. As a result, there has arisen a problem that an improvement in yield in chip manufacturing can be suppressed, particularly at the initial stage of mass production.
The present invention has been made in view of the above problems, and when three or more defect selection lines are generated on a semiconductor chip, such defect selection lines are relieved and the yield in chip manufacturing is dramatically improved. It is an object of the present invention to provide a shift redundancy type semiconductor memory device that can be improved greatly.
[0014]
[Means for Solving the Problems]
FIG. 1 is a block diagram showing the principle configuration of the present invention. Here, the configuration of the semiconductor memory device of the present invention having a plurality of selection lines R0 to R (n-1) (in this case, n is an arbitrary positive integer of 2 or more) is schematically shown. To do. Furthermore, here, the state of the switching operation of the switch unit when a defect occurs in the four selection lines Rl, R3, R (n-4), and R (n-2) is illustrated.
[0015]
In order to solve the above problem, the semiconductor memory device of the present invention selects a specific memory cell from a plurality of memory cells based on an address signal Add supplied from the outside, as shown in FIG. A plurality of selection lines R0 to R (n-1) (that is, real selection lines) for performing writing or reading are arranged, and at least two of the plurality of selection lines located at one end are arranged. First redundant selection lines (for example, two leftmost redundant selection lines JL0 and JL1) and at least two second redundant selection lines (for example, two leftmost redundant selection lines) located at the other end Lines JR0, JR1) and a plurality of decode signal lines obtained by decoding the address signal are connected to the plurality of selection lines and the redundancy selection line in a switchable manner at least in a first switch arranged in two stages. And a section 2-1 and a second switch section 2-2. These first and second switch units 2-1 and 2-2 constitute a main part of a shift redundancy circuit 1 having a 4-bit shift redundancy function described later.
[0016]
In the configuration including the first and second switch units 2-1 and 2-2 as described above, when defects occur in the plurality of selection lines (in FIG. 1, four selection lines are defective). Or a first switching operation for shifting at least one of the decode signal lines in the direction of the first redundant selection line by the first switch unit 2-1, or A second switching operation for shifting at least one of the decode signal lines in the direction of the second redundant selection line is performed, or a switching operation between both the first switching operation and the second switching operation. And the second switch section 2-2 further shifts at least one of the decoded signal lines on which the first switching operation has been performed in the direction of the first redundant selection line. Switching operation or the second A fourth switching operation is performed in which at least one of the decoded signal lines that have undergone the switching operation is further shifted in the direction of the second redundancy selection line, or the third switching operation and the fourth switching operation are performed. Both switching operations of the switching operation are performed, or none of the third switching operation and the fourth switching operation is performed. Here, “shifting the decode signal line” means shifting the state of connection between the selection line and the decode signal line as described in the section “Prior Art”.
[0017]
Preferably, when a defect occurs in four selection lines in the plurality of selection lines, both the first switching operation and the second switching operation by the first switch unit are performed. At the same time, the second switch unit is configured to perform both the third switching operation and the fourth switching operation.
Further preferably, when a defect occurs in three selection lines in the plurality of selection lines, the switching operation of both the first switching operation and the second switching operation by the first switch unit. And the switching operation of either the third switching operation or the fourth switching operation by the second switch unit is performed.
[0018]
Further preferably, when a defect occurs in two selection lines in the plurality of selection lines, one of the first switching operation and the second switching operation by the first switch unit is performed. In addition to performing the switching operation, it is configured to perform any one of the third switching operation and the fourth switching operation by the second switch unit.
[0019]
Further preferably, when a defect occurs in two selection lines in the plurality of selection lines, the switching operation of both the first switching operation and the second switching operation by the first switch unit. And the switching operation of the third switching operation and the fourth switching operation by the second switch unit is not performed.
Furthermore, preferably, when a defect occurs in one selection line in the plurality of selection lines, one of the first switching operation and the second switching operation by the first switch unit is performed. A switching operation is performed, and the switching operation of the third switching operation and the fourth switching operation by the second switch unit is not performed.
[0020]
Further, preferably, when at least one of the first redundancy selection line and the second redundancy selection line is connected to the decode signal line by the switching operation, the position is closer to the plurality of selection lines. The redundant selection lines (for example, the inner redundant selection lines JL0 and JR0) are preferentially used.
More specifically, the semiconductor memory device shown in FIG. 1 includes a decoder circuit 5 that decodes an address signal Add supplied from the outside. The decoder circuit 5 has substantially the same function as the decoder circuit 500 of FIG. Further, in the semiconductor memory device shown in FIG. 1, a plurality of memory cells for selecting or writing a specific memory cell from a plurality of memory cells based on the address of the decode signal Sdec output from the decoder circuit 5 are provided. Selected lines R0 to R (n-1) (n is an arbitrary positive integer of 2 or more). Further, in the semiconductor memory device shown in FIG. 1, two first redundant selection lines JL0 and JL1 that are not connected to any of the plurality of decode signal lines to which the decode signal Sdec is transferred are connected to the plurality of selection lines. Are arranged at one end position (for example, the left end position), and two second redundant selection lines JR0 and JR1 that are not connected to any of the plurality of decode signal lines are connected to the plurality of the plurality of decode signal lines. It arrange | positions in the position (for example, position of a right end) of the other end in a selection line.
[0021]
Further, in FIG. 1, the connection relationship between the plurality of decode signal lines and the plurality of selection lines R0 to R (n-1), the plurality of decode signal lines and the first and second redundant selection lines JL0. , JL1, JR0 and JR1 are provided with a shift redundancy circuit 1 for controlling the connection relationship. The shift redundant circuit 1 includes a first switch section 2- that includes a plurality of switch elements for connecting a plurality of decode signal lines to the plurality of select lines and the first and second redundant select lines in a switchable manner. 1 and a second switch section 2-2. Each of the first switch unit 2-1 and the second switch unit 2-2 preferably has a 2-bit shift redundancy function, and the first switch unit 2-1 and the second switch unit 2-2 By connecting a plurality of switch elements of the switch section 2-2 in two stages and in series, a shift redundancy of up to 4 bits is possible.
[0022]
More specifically, a switch unit having one end directly connected to a plurality of decode signal lines is referred to as a first switch unit 2-1, and the other end of the first switch unit and a plurality of selection lines (defects). When a selection line is generated, a switch unit connected between a plurality of selection lines and the first and second redundant selection lines) is a second switch unit 2-2, and a two-stage switch circuit is formed. It is formed. Here, when all or part of the first and second redundancy selection lines are connected to the corresponding decode signal lines, the redundancy selection lines (inner redundancy selection lines located on the side closer to the plurality of selection lines). JL0, JR0) is used first, and redundant selection lines (outer redundant selection lines JL1, JR1) located on the side away from the plurality of selection lines are used next.
[0023]
Further, the shift redundancy circuit 1 has a shift redundancy fuse circuit section 4 having a plurality of fuses provided corresponding to the plurality of selection lines and the first and second redundancy selection lines. The shift redundant fuse circuit unit 4 includes a fuse corresponding to the defect selection line in which these defects have occurred and all of the first and second redundant selection lines when a defect occurs in the plurality of selection lines. Alternatively, the redundant selection fuse corresponding to a part thereof is cut. The shift redundant fuse circuit unit 4 has substantially the same function as the shift redundant fuse circuit unit 400 of FIG.
[0024]
Here, the signal output from the shift redundancy fuse circuit unit 4 is input to a first shift redundancy control circuit unit 3-1 and a second shift redundancy control circuit unit 3-2 described later. Further, the signal output from the first shift redundancy control circuit unit 3-1 is used as a first shift control signal for controlling the first switch unit 2-1. On the other hand, the signal output from the second shift redundancy control circuit unit 3-2 is used as a second shift control signal for controlling the second switch unit 2-2.
[0025]
In the semiconductor device shown in FIG. 1, in order to simplify the description, a configuration in which switch circuits having a 2-bit shift redundancy function are arranged in two stages to execute a maximum 4-bit shift redundancy (that is, the first and the second). 2, a configuration in which a plurality of switch elements in each of the switch units 2-1 and 2-2 are connected in series with each other is disclosed. Note that up to 2N bits of shift redundancy (0, 1 bit, 2 bits,..., 2 (N−1) bits, or 2N bits of shift redundancy) are possible. Should.
[0026]
Further, the shift redundant circuit 1 in FIG. 1 switches the plurality of switch elements in the first switch unit 2-1 and the second switch unit 2-2 in accordance with the output result from the shift redundant fuse circuit unit 4. A first shift redundancy control circuit unit 3-1 and a second shift redundancy control circuit unit 3-2 are provided for controlling the operations.
More specifically, the first shift redundancy control circuit unit 3-1 connects the defect selection line corresponding to this defect to any of the plurality of decode signal lines when at least one defect occurs. In order not to be selected, only one selection line (that is, one bit) is provided in the direction of the first redundant selection line JL0 located inside the first redundant selection line at the left end. The plurality of decode signal lines are shifted by one selection line in the direction of the second redundancy selection line JR0 located inside the second redundancy selection line at the right end. The switching operation of the plurality of switch elements in the first switch unit 2-1 having a 2-bit shift redundancy function is controlled so as to shift the line. Preferably, the first shift redundancy control circuit unit 3-1 includes a plurality of first shift control circuits provided corresponding to the plurality of switch elements in the first switch unit 2-1.
[0027]
On the other hand, when two to four defects occur, the second shift redundancy control circuit unit 3-2 does not connect a defect selection line corresponding to this defect to any of the plurality of decode signal lines. In order to make a non-selected state, the amount of one selection line (that is, one bit) is increased in the direction of the first redundant selection line JL1 located outside the first redundant selection line at the left end. The plurality of decode signal lines are further shifted by the amount of one selection line in the direction of the second redundancy selection line JR1 located outside the second redundancy selection line at the right end. The switching operation of the plurality of switch elements in the second switch section 2-2 having a 2-bit shift redundancy function is controlled so as to further shift the line. Preferably, the second shift redundancy control circuit unit 3-2 includes a plurality of second shift control circuits provided corresponding to the plurality of switch elements in the second switch unit 2-2.
[0028]
In other words, the first shift redundancy control circuit unit 3-1 selects the two redundancy selection lines JL0 and JR0 located closer to the plurality of selection lines by the plurality of first shift control circuits. The first switching operation and the second switching operation of the first switch unit 2-1 used for the control are controlled. On the other hand, the second shift redundancy control circuit unit 3-2 selects two redundancy selection lines JL1 and JR1 located on the side away from the plurality of selection lines by the plurality of second shift control circuits. The third switching operation and the fourth switching operation of the second switch unit 2-2 used for the purpose are controlled. By appropriately controlling the first to fourth switching operations of the first and second switch units 2-1 and 2-2, a 1-bit to 4-bit shift redundancy function is realized.
[0029]
In addition, as a plurality of selection lines to be subjected to such 1-bit to 4-bit shift redundancy, a word selection line, a column selection line, a data bus selection line, or the like in the semiconductor memory device can be considered.
In summary, according to the present invention, two stages of switch units having a shift redundancy function of at least 2 bits are arranged in series, and the direction of one redundant selection line or the other redundant selection line is arranged for each switch unit. By performing a switching operation that shifts the decode signal line in the direction of the redundant selection lines or in the direction of both redundant selection lines, a shift redundant operation of 3 bits or more is performed when three or more defect selection lines are generated on the semiconductor chip. Thus, the defect selection line can be relieved. On the other hand, the switching operation is performed in the direction of one redundant selection line, the direction of the other redundant selection line, or the direction of both redundant selection lines for at least one of the switch sections arranged in two stages. As a result, even if one or two defect selection lines are generated on the semiconductor chip, these defect selection lines can be relieved.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings (FIGS. 2 to 20). Here, first, a specific switching operation of the first and second switch units 2-1 and 2-2 of the present invention when one to four defects occur in a plurality of selection lines will be described. And
[0031]
FIG. 2 is a schematic diagram illustrating the operation of the switch unit when defects occur in the four selection lines. FIG. 3 illustrates the first operation of the switch unit when defects occur in the three selection lines. FIG. 4 is a schematic diagram showing an example, and FIG. 4 is a schematic diagram showing a second example of the operation of the switch unit when a defect occurs in three selection lines.
Further, FIG. 5 is a schematic diagram showing a first example of the operation of the switch unit when a defect occurs in two selection lines, and FIG. 6 shows a switch when a defect occurs in two selection lines. FIG. 7 is a schematic diagram illustrating a third example of the operation of the switch unit when a defect occurs in two selection lines.
[0032]
Further, FIG. 8 is a schematic diagram showing a first example of the operation of the switch unit when a defect occurs in one selection line, and FIG. 9 shows a switch when a defect occurs in one selection line. FIG. 10 is a schematic diagram illustrating the operation of the switch unit when there is no defect in the selection line. However, in FIGS. 2 to 10, in order to simplify the description of the switching operation of the switch unit, the configuration of the switch unit and the plurality of selection lines is shown in a simplified manner. Hereinafter, the same components as those described above are denoted by the same reference numerals.
[0033]
2 to 10, eight selection lines R0 to R7 for normal selection used in normal operation, two first redundancy selection lines JL0 and JL1, and two second redundancy selections are used. Lines JR0 and JR1 are provided. The selection lines R0 to R7 for normal selection are connected to a plurality of switch elements of the second switch section 2-2 as shown in FIG. Further, the plurality of switch elements of the second switch unit 2-2 are connected to the plurality of switch elements of the first switch unit 2-1. Further, the plurality of switch elements of the first switch section 2-1 are connected to eight decode signal lines (not shown) obtained by decoding an address signal given from the outside of the semiconductor chip. Before the shift redundancy process or when there is no defect in the selection line or the like, the plurality of switch elements of the first and second switch units operate so that the selection lines R0 to R7 and the corresponding decode signal line are connected. (No shift). That is, in the case of FIG. 10, the first and second switch units 2-1 and 2-2 do not perform the switching operation for shifting the decode signal line in the direction of the redundant selection line, so that four redundant selection lines are It is not connected to the decode signal line.
[0034]
FIG. 2 is for explaining a case where defects are present in the four selection lines R1, R3, R5, and R7, and 4-bit shift redundancy is performed for these defects. In FIG. 2, the first switch unit 2-1 shifts the left four decode signal lines in the direction of the first redundant selection line JL0 located on the side close to the normal selection line R0 (1 The corresponding four switching elements are switched (left shift) so as to perform bit shift). Further, the first switch section 2-1 shifts the right three decode signal lines in the direction of the second redundant selection line JR0 located on the side closer to the normal selection line R7 (1-bit shift). ), The switching operation of the corresponding three switch elements is performed (rightward shift). Further, the first switch unit 2-1 and the second switch unit 2-2 do not perform either the leftward shift or the rightward shift so that the decode signal line and the selection line R4 are connected. The switch element is operated (no shift).
[0035]
Further, in FIG. 2, the second switch unit 2-2 is configured such that the left three decode signal lines are in the direction of the first redundant selection line JL1 located on the side away from the selection line R0 for normal selection. In order to further shift (1 bit shift), switching operation of the corresponding three switch elements is performed (left shift). Further, the second switch section 2-2 further shifts the right two decode signal lines in the direction of the second redundant selection line JR1 located on the side away from the selection line R7 for normal selection (1 The switching operation of the corresponding two switch elements is performed (right shift). Further, the second switch unit 2-2 is configured so that the switch element of the first switch unit 2-1 and the selection line R2 are connected without performing either the leftward shift or the rightward shift. Operate the element (no shift). Further, the second switch unit 2-2 operates the switch element so that the switch element of the first switch unit and the selection line R6 are connected without performing either the left shift or the right shift. (No shift) In this case, the defect selection lines R1, R3, R5, and R7 corresponding to the four defects are not connected to any decode signal line and are always in a non-selected state.
[0036]
In other words, in FIG. 2, 2-bit shift redundancy is performed using the redundant selection lines JL0 and JR0 located on the side closer to the selection line for normal selection, and the side away from the selection line for normal selection. By using the redundancy selection lines JL1 and JR1 positioned at the position 2 to perform 2-bit shift redundancy, it is finally possible to perform 4-bit shift redundancy.
[0037]
FIG. 3 is a diagram for explaining a first example in which defects are present in three selection lines R1, R3, and R6 and 3-bit shift redundancy is performed for these defects. In FIG. 3, the first switch section 2-1 shifts the left four decode signal lines in the direction of the first redundant selection line JL0 located on the side close to the normal selection line R0. Then, the switching operation of the corresponding four switch elements is performed (shift in the left direction). Further, the first switch unit 2-1 shifts the right two decode signal lines in the direction of the second redundant selection line JR0 located on the side closer to the normal selection line R7. The corresponding two switch elements are switched (rightward shift). Further, the first switch unit 2-1 and the second switch unit 2-2 are connected to the decode signal line and the selection lines R4 and R5 without performing either the left shift or the right shift. Then, the switch element is operated (no shift).
[0038]
Further, in FIG. 3, the second switch unit 2-2 is configured such that the left three decode signal lines are in the direction of the first redundant selection line JL1 located on the side away from the normal selection line R0. In order to further shift, the switching operation of the corresponding three switch elements is performed (leftward shift). Further, the second switch unit 2-2 does not perform either the left shift or the right shift, and the switch elements of the first switch unit, the selection lines R2, R7, and the second redundant selection line JR0. The switch element is operated so as to be connected (no shift). In this case, the defect selection lines R1, R3, and R6 corresponding to the three defects are not connected to any decode signal line and are always in a non-selected state. Further, the second redundant selection line JR1 located on the side away from the selection line R7 for normal selection is also not connected to the decode signal line.
[0039]
FIG. 4 is a diagram for explaining a second example in which defects are present in the three selection lines R1, R3, and R6 and 3-bit shift redundancy is performed for these defects. In FIG. 4, the first switch section 4-1 shifts the left two decode signal lines in the direction of the first redundant selection line JL0 located on the side close to the normal selection line R0. In addition, the switching operation of the corresponding two switch elements is performed (leftward shift). Further, the first switch unit 2-1 shifts the right five decode signal lines in the direction of the second redundant selection line JR0 located on the side closer to the normal selection line R7. The corresponding five switch elements are switched (rightward shift). Further, the first switch unit 2-1 and the second switch unit 2-2 do not perform either the leftward shift or the rightward shift so that the decode signal line and the selection line R2 are connected. The switch element is operated (no shift).
[0040]
Further, in FIG. 4, the second switch unit 2-2 is configured such that the right three decode signal lines are in the direction of the second redundant selection line JR1 located on the side away from the normal selection line R7. In order to further shift, the corresponding three switching elements are switched (rightward shift). Furthermore, the second switch unit 2-2 does not perform either the left shift or the right shift, and the switch elements of the first switch unit 2-1, the selection lines R0, R4, R5, and the first switch The switch element is operated so that the redundant selection line JL0 is connected (no shift). In this case, the defect selection lines R1, R3, and R6 corresponding to the three defects are not connected to any decode signal line and are always in a non-selected state. Further, the second redundant selection line JL1 located on the side away from the selection line R0 for normal selection is also not connected to the decode signal line.
[0041]
In other words, in FIGS. 3 and 4, 2-bit shift redundancy is performed using the redundancy selection lines JL0 and JR0 located on the side closer to the selection line for normal selection, and from the selection line for normal selection. By performing 1-bit shift redundancy using one of the redundancy selection lines JL1 and JR1 located on the far side, it becomes possible to finally perform 3-bit shift redundancy.
[0042]
FIG. 5 is a diagram for explaining a first example in which defects are present in the two selection lines R2 and R5 and shift redundancy of 2 bits is performed for these defects. In FIG. 5, the first switch unit 2-1 shifts the left six decode signal lines in the direction of the first redundant selection line JL0 located on the side closer to the normal selection line R0. Then, the switching operation of the corresponding six switch elements is performed (shift in the left direction). Furthermore, the first switch unit 2-1 and the second switch unit 2-2 are connected to the decode signal line and the selection lines R6 and R7 without performing either the left shift or the right shift. Then, the switch element is operated (no shift).
[0043]
Further, in FIG. 5, the second switch section 2-2 is configured such that the left four decode signal lines are in the direction of the first redundant selection line JL1 located on the side away from the selection line R0 for normal selection. The corresponding four switch elements are switched so as to shift further (leftward shift). Further, the second switch unit 2-2 is connected to the switch elements of the first switch unit 2-1 and the selection lines R3 and R4 without performing any leftward shift or rightward shift. The switch element is operated (no shift). In this case, the defect selection lines R2 and R5 corresponding to the two defects are not connected to any decode signal line and are always in a non-selected state. Further, none of the redundant selection lines JR0 and JR1 located on the normal selection line R7 is connected to the decode signal line.
[0044]
FIG. 6 is a diagram for explaining a second example in which defects are present in the two selection lines R2 and R5 and shift redundancy of 2 bits is performed for these defects. In FIG. 5, the first switch unit 2-1 shifts the left three decode signal lines in the direction of the first redundant selection line JL0 located on the side closer to the normal selection line R0. Then, the switching operation of the corresponding three switch elements is performed (leftward shift). Further, the first switch unit 2-1 shifts the right three decode signal lines in the direction of the second redundant selection line JR0 located on the side closer to the normal selection line R7. The corresponding three switch elements are switched (rightward shift). Further, the first switch unit 2-1 and the second switch unit 2-2 are connected to the decode signal line and the selection lines R3 and R4 without performing either the left shift or the right shift. Then, the switch element is operated (no shift).
[0045]
Further, in FIG. 6, the second switch unit 2-2 does not perform either the leftward shift or the rightward shift, and the switch element of the first switch unit 2-1, and the selection lines R0, R1, and R6. , R7, the first redundant selection line JL0 on the inner side, and the second redundant selection line JR0 on the inner side are operated (no shift). In this case, the defect selection lines R2 and R5 corresponding to the two defects are not connected to any decode signal line and are always in a non-selected state. Further, the outer first redundant selection line JL1 and the outer second redundant selection line JR1 are not connected to the decode signal line.
[0046]
FIG. 7 is a diagram for explaining a third example in which defects are present in two selection lines R2 and R5 and shift redundancy of 2 bits is performed for these defects. In FIG. 7, the first switch section 2-1 shifts the right six decode signal lines in the direction of the second redundant selection line JR0 located on the side closer to the normal selection line R7. In addition, the switching operation of the corresponding six switch elements is performed (rightward shift). Further, the first switch unit 2-1 and the second switch unit 2-2 are connected to the decode signal line and the selection lines R0 and R1 without performing either the left shift or the right shift. Then, the switch element is operated (no shift).
[0047]
Further, in FIG. 7, the second switch section 2-2 is configured so that the four right decode signal lines are in the direction of the second redundant selection line JR1 located on the side away from the selection line R7 for normal selection. The corresponding four switch elements are switched so as to shift further (rightward shift). Further, the second switch unit 2-2 is connected to the switch elements of the first switch unit 2-1 and the selection lines R3 and R4 without performing any leftward shift or rightward shift. The switch element is operated (no shift). In this case, a defect selection line corresponding to two defects R2, R5 Are not connected to any decode signal line and are always in a non-selected state. Furthermore, none of the redundant selection lines JL0 and JL1 located on the normal selection line R0 is connected to the decode signal line.
[0048]
In other words, in FIG. 6, 2-bit shift redundancy can be performed using the inner first redundancy selection line JL0 and the second redundancy selection line JR0. In this case, only the switch element of the first switch unit performs a switching operation for shifting the decode signal line in the direction of the redundant selection line. On the other hand, in FIGS. 5 and 7, 2-bit shift redundancy can be performed using the two leftmost redundant selection lines or the two rightmost redundant selection lines. In this case, the switch element of the first switch unit performs a switching operation for shifting the decode signal line in the direction of the redundant selection line located inside the left end or the right end, and the switch element of the second switch unit The switching operation for shifting the decode signal line in the direction of the redundant selection line located outside the same end is performed.
[0049]
FIG. 8 is a diagram for explaining a first example in which defects exist in one selection line R2 and 1-bit shift redundancy is performed for these defects. Figure 8 In the first switch section 2-1, the left three decode signal lines are shifted in the direction of the first redundant selection line JL0 located on the side close to the normal selection line R0. The corresponding three switch elements are switched (leftward shift). Further, the first switch unit 2-1 and the second switch unit 2-2 are connected to the decode signal line and the selection lines R3 to R7 without performing either the left shift or the right shift. Then, the switch element is operated (no shift).
[0050]
Further, in FIG. 8, the second switch unit 2-2 does not perform either the left shift or the right shift, and the switch elements of the first switch unit 2-1, the selection lines R0, R1, and the first switch. The switch element is operated so as to be connected to one redundant selection line JL0 (no shift). In this case, the defect selection line R2 corresponding to one defect is not connected to any decode signal line and is always in a non-selected state. Furthermore, both the first redundant selection line JL1 located on the normal selection line R0 and the second redundant selection lines JR0 and JR1 located on the normal selection line R7 are both decoded signals. It is not connected to the line.
[0051]
FIG. 9 is a diagram for explaining a second example in the case where defects exist in one selection line R2 and 1-bit shift redundancy is performed for these defects. In FIG. 9, the first switch section 2-1 shifts the right six decode signal lines in the direction of the second redundant selection line JR0 located on the side closer to the normal selection line R7. Then, the switching operation of the corresponding six switch elements is performed (rightward shift). Further, the first switch unit 2-1 and the second switch unit 2-2 are connected to the decode signal line and the selection lines R0 and R1 without performing either the left shift or the right shift. Then, the switch element is operated (no shift).
[0052]
Further, in FIG. 9, the second switch unit 2-2 does not perform either the left shift or the right shift, and the switch elements of the first switch unit 2-1, the selection lines R3 to R7, and the first switch. The switch element is operated (no shift) so that the two redundant selection lines JR0 are connected. In this case, the defect selection line R2 corresponding to one defect is not connected to any decode signal line and is always in a non-selected state. Further, the first redundant selection lines JL0 and JL1 positioned on the normal selection line R0 side and the second redundant selection line JR1 positioned on the normal selection line R7 are both decoded signals. It is not connected to the line.
[0053]
In other words, in FIGS. 8 and 9, 1-bit shift redundancy can be performed using one of the redundancy selection lines JL0 and JR0 located on the side closer to the selection line for normal selection. . In this case, only the switch element of the first switch unit performs a switching operation for shifting the decode signal line in the direction of any one redundant selection line.
[0054]
FIG. 11 is a diagram showing the signal level of each part due to the operation of the switch unit when a defect occurs in the four selection lines, and FIG. 12 shows the state of the switch part when a defect occurs in the three selection lines. It is a figure which shows the signal level of each part by operation | movement. Here, the two first redundant selection lines JL0, JL1, and the second 2 In the semiconductor memory device provided with the redundant selection lines JR0, JR1 and the eight normal selection lines R0 to R7, the first and the second selection lines are defective when four or three selection lines are defective. The signal level of each part when the second switch part performs the switching operation is shown. FIG. 11 shows the signal level of each part when the switching operation of the switch part as shown in FIG. 2 is performed, and FIG. 12 shows each part when the switching operation of the switch part as shown in FIG. 3 is performed. The signal level is shown.
[0055]
The shift redundant fuse circuit unit 4 shown in FIG. 1 has a normal selection fuse circuit used during normal operation, a redundancy selection fuse circuit used during redundancy selection, and whether or not the redundancy selection line is defective. Forcibly redundant fuse circuit used at the time of forced redundancy. These normal selection fuse circuits output a low voltage level (“L” level) when the corresponding fuse is cut, and output a high voltage level (“H” level) when the fuse is not cut. On the other hand, the redundancy selection fuse circuit (and the forced redundancy fuse circuit), on the other hand, outputs “H” level when the fuse (redundancy selection fuse) is cut, and “ L ”level is output. In this case, for 1-bit shift redundancy, the fuse of the fuse circuit corresponding to the defect selection line and the redundancy selection fuse circuit corresponding to any one of the first and second redundancy selection lines Two of the fuses are cut. Therefore, when 4-bit shift redundancy is performed as shown in FIG. 11, four fuses corresponding to four defect selection lines and redundancy corresponding to all four first and second redundancy selection lines. A total of eight fuses (redundancy selection fuses) in the selection fuse circuit are cut. On the other hand, when 3-bit shift redundancy is performed as shown in FIG. 12, it is located inside the three fuses corresponding to the three defect selection lines and the first and second redundancy selection lines. A total of six fuses including two fuses and one fuse located outside are cut.
[0056]
Further, the plurality of shift control circuits in the first shift redundancy control circuit unit 3-1 connect one first input signal uin0 and one first output signal uout0, as will be described later with reference to FIG. At the same time, by connecting the other first input signal lin0 and the other first output signal lout0, as shown in FIG. 19 to be described later, a series-connected circuit has two stages. Yes. On the other hand, the plurality of shift control circuits in the second shift redundancy control circuit unit 3-2 also includes one second input signal uin1 and one second output signal, as will be described later with reference to FIG. By connecting uout1 and the other second input signal lin1 and the other second output signal lout1, a configuration in which the series-connected circuits are arranged in two stages as shown in FIG. 19 described later. ing.
[0057]
The switching operation of each switch element in the first switch unit 2-1 is performed by “H” of the first output signal uout 0 and the first output signal lout 0 output from the first shift redundancy control circuit unit 3-1. It is controlled by a combination of “level” and “L” level. When the fuse is not cut, the output levels of the first output signal uout0 and the first output signal lout0 are all “L” level. Further, at this time, in the shift redundant fuse circuit unit 4, the output of the fuse circuit corresponding to the selection line other than the redundant selection line becomes “H” level, and the output of the redundant selection fuse circuit corresponding to the redundant selection line is “ L ”level. In this case, it is determined that there is no shift redundancy operation.
[0058]
On the other hand, the switching operation of each switch element in the second switch unit 2-2 is performed by the second output signal uout1 and the second output signal output from the second shift redundancy control circuit unit 3-2. It is controlled by a combination of the “H” level and “L” level of lout1. When the fuse is not cut, the output levels of the second output signal uout1 and the second output signal lout1 are all “L” level.
[0059]
Here, as shown in FIG. 11, the fuses corresponding to the four defect selection lines R1, R3, R5, and R7 are cut, and the four first and second redundancy selection lines JL0, JL1, JR0. Consider a case where four fuses (redundancy selection fuses) of the redundancy selection fuse circuit corresponding to JR1 and JR1 are cut. At this time, the output of the fuse circuit corresponding to each of the four defect selection lines R1, R3, R5, and R7 cut to "L" level, and the four redundant selection lines JL0, JL1, JR0, and JR1 cut The output of the redundancy selection fuse circuit corresponding to each becomes "H" level.
[0060]
In this case, the first shift redundancy control circuit unit 3-1 shifts the left four decode signal lines in the direction of the first redundancy selection line JL0 located on the side closer to the selection line R0 for normal selection. Thus, the switching operation of the first switch unit 2-1 is controlled (left shift ←). Further, the first shift redundancy control circuit unit 3-1 shifts the right three decode signal lines in the direction of the second redundancy selection line JR0 located on the side closer to the selection line R7 for normal selection. In this manner, the switching operation of the first switch unit 2-1 is controlled (rightward shift →). Further, the first shift redundancy control circuit unit 3-1 and the second shift redundancy control circuit unit 3-2 perform the decoding signal line and the selection line R4 without performing either the left shift or the right shift. The operation of the first switch unit 2-1 and the second switch unit 2-2 is controlled so as to be connected (no shift ↑). Further, the first shift redundancy control circuit unit 3-1 and the second shift redundancy control circuit unit 3-2 are in a non-selected state in which the defect selection lines R3 and R5 are not connected to the decode signal line (FIG. 11). Of the first and second shift redundancy control circuit sections 3-1 and 3-2 (corresponding to the portion related to the defect selection lines R 3 and R 5), the first switch section 2 -1 and the operation of the second switch section 2-2.
[0061]
Further, as shown in FIG. 11, the second shift redundancy control circuit unit 3-2 includes the first redundancy signal line in which the left three decode signal lines are located on the side away from the normal selection line R0. The switching operation of the second switch section 2-2 is controlled so as to further shift in the direction of the selection line JL1 (left shift ←). Further, the second shift redundancy control circuit unit 3-2 further includes two right decode signal lines in the direction of the second redundancy selection line JR1 located on the side away from the selection line R7 for normal selection. The switching operation of the second switch unit 2-2 is controlled so as to shift (rightward shift →). Further, the second shift redundancy control circuit unit 3-2 performs the second switch so that the decode signal line and the selection lines R2 and R6 are connected without performing either the left shift or the right shift. The switching operation of the unit 2-2 is controlled (no shift ↑). Further, the second shift redundancy control circuit unit 3-2 is in a non-selected state in which the two defect selection lines R1 and R7 are not connected to the decode signal line (second shift redundancy control circuit unit in FIG. 11). The operation of the second switch section 2-2 is controlled by “X” in the column 3-2 (corresponding to the portion related to the defect selection lines R1 and R7). In this way, by setting the four defect selection lines R1, R3, R5, and R7 to a non-selected state that is not connected to any decode signal line, these defect selection lines can be relieved.
[0062]
At this time, in the first shift redundancy control circuit unit 3-1, only the first output signal uout0 at the position where the signal from the normal selection fuse and the redundancy selection fuse to which the leftward shift is performed is “H”. Since the first output signals uout0 at the other positions are all at the “L” level, one first output signal uout0 = “H” and the other first output signal lout0 = The “L” state may be determined as a leftward shift. On the other hand, in the second shift redundancy control circuit section 3-2, only the second output signal uout1 at the position where the signal from the normal selection fuse and the redundancy selection fuse to which the leftward shift is performed is “ Since the second output signals at the other positions are all at the “L” level, one of the second output signals uout1 = “H” and the other second output signal lout1 = The “L” state may be determined as a leftward shift.
[0063]
Further, in the first shift redundancy control circuit section 3-1, only the first output signal lout0 at the position where the signal from the normal selection fuse and the redundancy selection fuse subjected to the rightward shift is input is “H”. Since the first output signals lout0 at other positions are all at the “L” level, one of the first output signals uout0 = “L” and the other first output signal lout0 = “ What is necessary is just to determine the state of H "as a rightward shift. On the other hand, in the second shift redundancy control circuit section 3-2, only the second output signal lout1 at the position where the signal from the normal selection fuse and the redundancy selection fuse to which the right shift is performed is input. Since the second output signal lout1 at other positions is at the “L” level, the other second output signal lout1 is at the second output signal uout1 = “L”. = ”H” may be determined as a right shift.
[0064]
On the other hand, as shown in FIG. 12, the fuses corresponding to the three defect selection lines R1, R3, and R6 are cut, and the two first redundancy selection lines JL0, JL1, and one first selection line are disconnected. Consider a case where the three fuses (redundancy selection fuses) of the redundancy selection fuse circuit respectively corresponding to the two redundancy selection lines JR0 (that is, three redundancy selection lines) are cut. At this time, the outputs of the fuse circuits corresponding to the three cut defect selection lines R1, R3, and R6 are at the “L” level, and correspond to the three cut redundancy selection lines JL0, JL1, and JR0, respectively. The output of the redundancy selection fuse circuit is at "H" level.
[0065]
In this case, the first shift redundancy control circuit unit 3-1 shifts the left four decode signal lines in the direction of the first redundancy selection line JL0 located on the side closer to the selection line R0 for normal selection. Thus, the switching operation of the first switch unit 2-1 is controlled (left shift ←). Further, in the first shift redundancy control circuit unit 3-1, the two right decode signal lines shift in the direction of the second redundancy selection line JR0 located on the side closer to the selection line R7 for normal selection. In this manner, the switching operation of the first switch unit 2-1 is controlled (rightward shift →). Further, the first shift redundancy control circuit unit 3-1 and the second shift redundancy control circuit unit 3-2 perform neither the left shift nor the right shift, and the decode signal line and the selection lines R4 and R5. Are controlled so that they are connected to each other (no shift ↑). Further, the first shift redundancy control circuit unit 3-1 and the second shift redundancy control circuit unit 3-2 are in a non-selected state in which the defect selection lines R3 and R6 are not connected to the decode signal line (FIG. 12). Of the first and second shift redundancy control circuit sections 3-1 and 3-2 (corresponding to a portion related to the defect selection lines R 3 and R 6), the first switch section 2 -1 and the operation of the second switch section 2-2.
[0066]
Further, as shown in FIG. 12, the second shift redundancy control circuit unit 3-2 includes the first redundancy in which the left three decode signal lines are located on the side away from the selection line R0 for normal selection. The switching operation of the second switch section 2-2 is controlled so as to further shift in the direction of the selection line JL1 (left shift ←). Further, the second shift redundancy control circuit unit 3-2 connects the decode signal line, the selection lines R2, R7, and the second redundancy selection line JR0 without performing either the left shift or the right shift. Switch element is operated (no shift). Further, the second shift redundancy control circuit unit 3-2 is in a non-selected state in which one defect selection line R1 is not connected to the decode signal line (second shift redundancy control circuit unit 3- The operation of the second switch section 2-2 is controlled by “X” in the column 2 (corresponding to a portion related to the defect selection line R1). In this way, by setting the three defect selection lines R1, R3, and R6 to a non-selected state that is not connected to any decode signal line, these defect selection lines can be relieved.
[0067]
At this time, in the first shift redundancy control circuit section 3-1, as in the case of FIG. 11, the positions from which signals from the normal selection fuse and the redundancy selection fuse to which the leftward shift is performed are input. Only the first output signal uout0 is at “H” level, and all the first output signals uout0 at other positions are at “L” level, so that one of the first output signals uout0 = “H”. Thus, the state of the other first output signal lout0 = "L" may be determined as a leftward shift. On the other hand, in the second shift redundancy control circuit unit 3-2, as in the case of FIG. 11, signals from the normal selection fuse and the redundancy selection fuse that are shifted leftward are input. Only the second output signal uout1 at the position is at the “H” level, and all the second output signals at other positions are at the “L” level. Therefore, one of the second output signals uout1 = “H”. Thus, the state of the other second output signal lout1 = “L” may be determined as a leftward shift.
[0068]
Next, the structure of the main part of one embodiment of the semiconductor memory device having the 1-bit to 4-bit shift redundancy function of the present invention will be sequentially described.
FIG. 13 is a circuit diagram showing a configuration of a normal selection fuse circuit in one embodiment of the present invention. The normal selection fuse circuit 60 in FIG. 13 (except for the selection line fuse circuit redundant in forced redundancy) 60 has selection lines R0 to R3 and R6 to R (n-7) as shown in FIG. ), And R (n-4) to R (n-1), one of a plurality of fuse circuits in the shift redundant fuse circuit unit 4 provided in one-to-one correspondence.
[0069]
In FIG. 13, for example, stttx is a control signal that is at “H” level until the power supply is turned on when the power is turned on, and is “L” level after the power supply is turned on, and cfs is an output signal of the fuse circuit 60. is there. The fuse circuit 60 shown in FIG. 13 includes a P-channel transistor 41 and an N-channel transistor 42 to which a control signal stttx is input, an N-channel transistor 44, and two inverters 43 and 45. When the fuse 40 is not cut, the output signal cfs of the fuse circuit becomes “H” level after the power is turned on. When the fuse 40 is cut, the output signal cfs of the fuse circuit becomes “L” level.
[0070]
FIG. 14 is a circuit diagram showing a configuration of a redundancy selection fuse circuit in one embodiment of the present invention. The redundancy selection fuse circuit 60j of FIG. 14 is provided for each of the redundancy selection fuse circuits used for the first and second redundancy selection lines JL0, JL1, JR0 and JR1 in the shift redundancy fuse circuit section 4 of FIG. Corresponding.
In FIG. 14, ftpz is a control signal that becomes “H” level when forced redundancy is performed to check whether or not the redundancy selection line is defective. The redundant selection fuse circuit 60j shown in FIG. 14 includes a P-channel transistor 41r and an N-channel transistor 43r to which a control signal stttx is input, and a P-channel transistor 42r and an N-channel transistor 44r to which a control signal ftpz is input. An N-channel transistor 45r and an inverter 46r. When the fuse (redundancy selection fuse) 40r is not cut and forced redundancy is not performed (control signal ftpz = “L”), the output signal cfsj of the redundancy selection fuse circuit is set to the “L” level. . On the other hand, when the fuse 40r is actually cut, the output signal cfsj of the redundancy selecting fuse circuit becomes the “H” level.
[0071]
Further, in FIG. 14, when the fuse 40r is not cut and forced redundancy is performed (control signal ftpz = “H”), the P-channel transistor 42r is turned off, and the N-channel transistor 44r is turned on. The node n03 becomes “L” level in the ON state. As a result, the output signal cfsj of the redundancy selection fuse circuit becomes “H” level. In this case, the fuse 40r is apparently cut, and forced redundancy is performed together with a forced redundancy selection fuse circuit shown in FIG. it can.
[0072]
In both the normal selection fuse circuit of FIG. 13 and the redundancy selection fuse circuit of FIG. 14, the fuse of the fuse circuit corresponding to the selection line to be redundant and the redundancy selection fuse corresponding to the redundancy selection line The circuit fuse is disconnected.
FIG. 15 is a circuit diagram showing a configuration of a forced redundancy selection fuse circuit in one embodiment of the present invention. FIG. 5 The forced redundancy selection fuse circuit 60pj shown in FIG. 1 includes four forced redundancy selection lines (for example, selection lines R4, R5, R (n-6) and R (n-5) in the shift redundancy fuse circuit section 4 of FIG. ) Corresponding to each of the forced redundancy fuse circuits used for the selection line that is not adjacent to the redundancy selection line and is close to the redundancy selection line.
[0073]
In FIG. 15, ftpz is a control signal that becomes “H” level when forced redundancy is performed as described above. The forced redundancy fuse circuit 60pj shown in FIG. 15 includes a P-channel transistor 41f and an N-channel transistor 43f that receive a control signal stttx, and a P-channel transistor 42f and an N-channel transistor 44f that receive a control signal ftpz. An N-channel transistor 45f and two inverters 46f and 47f. When it appears that the fuse 40f at the time of forced redundancy is blown, the output signal cfs of the forced redundant fuse circuit becomes “L” level. In this state, it is possible to confirm whether or not there is a defect in the redundancy selection line before cutting the fuse corresponding to the selection line that is subject to shift redundancy.
[0074]
More specifically, in the case of performing forced redundancy, the control signal ftpz at “H” level is input to the gates of the P-channel transistor 42f and the N-channel transistor 44f. In this way, the P-channel transistor 42f is turned off, the N-channel transistor 44f is turned on, and the input level of the inverter 46f becomes "L" level. As a result, the output level of the inverter 47 f becomes “L” level, and the “L” level output signal cfs is generated.
[0075]
On the other hand, when forced redundancy is not performed (control signal ftpz = “L”), the P-channel transistor 42f is turned on, the N-channel transistor 44f is turned off, and the input level of the inverter 46f is Becomes “H” level. As a result, the output level of the inverter 47f becomes “H” level, and the “H” level output signal cfs is generated. Further, when the fuse 40f is actually cut, the N-channel transistor 45f is turned off. N In this state, the input level of the inverter 46f becomes “L” level. As a result, the output level of the inverter 47 f becomes “L” level, and the “L” level output signal cfs is generated.
[0076]
FIG. 16 is a circuit diagram showing a configuration of first and second shift control circuits in one embodiment of the present invention. Here, the plurality of first shift control circuits constituting the first shift redundancy control circuit unit 3-1 (see FIG. 1) that controls the switching operation of the first switch unit 2-1 (see FIG. 1). Each of the plurality of second shift controls constituting the second shift redundancy control circuit unit 3-2 (see FIG. 1), which shows each of them and controls the switching operation of the second switch unit 2-2 (see FIG. 1). Each of the circuits is shown.
[0077]
In FIG. 16, uout0 indicates one output signal in the first shift control circuit of each of the first shift redundancy control circuit sections 3-1, and lout0 indicates the other output signal in the first shift control circuit. . Further, uout1 indicates one output signal in each second shift control circuit of the second shift redundancy control circuit unit 3-2, and lout1 indicates the other output signal in the second shift control circuit. cfs indicates an output signal of the fuse circuit 60 (and the redundancy selection fuse circuit 60j) of FIGS. 13 and 14 described above.
[0078]
Further, in FIG. 16, each first shift control circuit 30-1 is a circuit that receives the output signal cfs of the fuse circuit and controls each switch element of the first switch unit 2-1. A first shift control circuit 30-1-l for left shift and a first shift control circuit 30-1-r for right shift are included. The first shift control circuit 30-1-l for left shift is composed of a circuit in which two NAND gates 31-1, 32-1 are connected as shown in FIG. Further, the first shift control circuit 30-1-r for right shifting is also configured by a circuit in which two NAND gates 33-1 and 34-1 are connected as shown in FIG.
[0079]
Here, the plurality of shift control circuits in the first shift redundancy control circuit unit 3-1 include one first input signal uin0 and one of the first input signals uin0 in the first shift control circuit 30-1-l for left shift. By connecting the first output signal uout0 and connecting the other first input signal lin0 and the other first output signal lout0 in the first shift control circuit 30-1-r for right shift, It has a configuration in which two series-connected circuits are provided. In the first shift redundancy control circuit section 3-1, the input signal uin0 of the first shift control circuit for the left shift located at one end and the right shift for the right shift located at the other end. The input signal lin0 of the first shift control circuit is connected to the power supply (power supply voltage Vii) on the high voltage side, and the “H” level voltage is input.
[0080]
Further, in FIG. 16, each second shift control circuit 30-2 receives the output signal cfs of the above-described normal selection fuse circuit 60 (and redundant selection fuse circuit 60j) and receives the second switch section 2. -2 is a circuit for controlling each switch element, and includes a second shift control circuit 30-2-l for left shift and a second shift control circuit 30-2-r for right shift. The second shift control circuit 30-2-l for left shift is composed of a circuit in which a NAND gate 31-2 and an inverter 32-2 are connected as shown in FIG. Further, the second shift control circuit 30-2-r for right shift is also configured by a circuit in which a NAND gate 33-2 and an inverter 34-2 are connected as shown in FIG.
[0081]
Here, the plurality of shift control circuits in the second shift redundancy control circuit unit 3-2 include one second input signal uin1 and one of the second input signals uin1 in the second shift control circuit 30-2-l for left shift. By connecting the second output signal uout1 and connecting the other second input signal lin1 and the other second output signal lout1 in the second shift control circuit 30-2-r for right shift, It has a configuration in which two series-connected circuits are provided. In the second shift redundancy control circuit unit 3-2, the input signal uin1 of the second shift control circuit for left shift located at one end and the right shift signal located at the other end The input signal lin1 of the second shift control circuit is connected to the power supply (power supply voltage Vii) on the high voltage side, and the “H” level voltage is input.
[0082]
The switching operation of each switch element in the first switch unit 2-1 is performed by “H” of the first output signal uout 0 and the first output signal lout 0 output from the first shift redundancy control circuit unit 3-1. It is controlled by a combination of “level” and “L” level. Further, the switching operation of each switch element in the second switch unit 2-2 is performed by the second output signal uout1 and the second output signal lout1 output from the second shift redundancy control circuit unit 3-2. It is controlled by a combination of “H” level and “L” level.
[0083]
Further, in FIG. 16, the output terminal of the NAND gate 31-2 of the second shift control circuit 30-2-l for left shift is the NAND gate of the first shift control circuit 30-1-l for left shift. It is connected to one input terminal of 32-1. Similarly, the output terminal of the NAND gate 33-2 of the second shift control circuit 30-2-r for right shift is connected to the NAND gate 34- of the first shift control circuit 30-1-r for right shift. 1 is connected to one input terminal. In such a circuit configuration, the switch element of the second switch section 2-2 by the second shift control circuit left When the direction shift operation or the right direction shift operation is performed, the first shift control circuit always performs the shift operation in the same direction of the switch element of the first switch unit 2-1. The switching operation for shift redundancy by the second switch units 2-1 and 2-2 can be executed without error.
[0084]
FIG. 17 is a circuit diagram showing the configuration of the first switch section in one embodiment of the present invention, and FIG. 18 is a circuit diagram showing the configuration of the second switch section in one embodiment of the present invention. Here, the circuit configuration of each of a plurality of switch elements in the first switch unit 2-1 and the second switch unit 2-2 is shown. In this case, the plurality of switch elements of the first and second switch units 2-1 and 2-2 are connected in two stages and in series as described above. The first and second switch units 2-1 and 2-2 include circuit elements corresponding to the respective switch elements, and drive the selection line when the load on the selection line increases. And a function of supplying a predetermined output voltage.
[0085]
As shown in FIG. 17, each switch element in the first switch unit 2-1 in the first stage includes the first shift control circuit in the first shift redundancy control circuit unit 3-1. Output signal uout0 is input, and the first output signal lout0 in the first shift control circuit is input. cfs represents an output signal of the above-described fuse circuit 60 (see FIG. 13), and pcll0, pclm0, and pclr0 are three decode signal lines d (#-1) adjacent to each other among the plurality of decode signal lines, respectively. This corresponds to a decode signal from d # and d (# + 1). Here, # represents the number of a predetermined decode signal line. pcl1 is an output signal of an arbitrary switch element of the first switch unit 2-1, and is supplied to any one switch element of the second switch unit 2-2 in the second stage.
[0086]
Preferably, each switch element of the first switch unit 2-1 shown in FIG. 17 includes the first output signal uout0 in each first shift control circuit of the first shift redundancy control circuit unit 3-1. A mode for performing a shift operation in the direction of the first redundant selection line JL0 (that is, a shift in the left direction) according to the combination of lout0, and a shift operation in the direction of the second redundant selection line JR0 (that is, in the right direction) It is possible to select a mode in which (shift) is performed or a mode in which no shift operation is performed (that is, no shift).
[0087]
Further, each switch element of the first switch unit 2-1 shown in FIG. 17 includes a signal obtained by inverting the output signal cfs of the fuse circuit by the inverter 20-1, and one output signal uout1 of the first shift control circuit. And NOR gate 21-1 having the other output signal lout1 of the first shift control circuit as three input signals, three inverters 22-1, 24-1 and 26-1, and 3 And three-way switch elements including transfer gates 23-1, 25-1, and 27-1.
[0088]
More specifically, when both the output signals uout0 and lout0 of the first shift control circuit are at the “L” level and the output signal cfs of the fuse circuit is at the “H” level, the mode in which the shift redundant operation is not performed is selected. Thus, the second transfer gate 25-1 is turned on. When the output signals uout0 and lout0 of the first shift control circuit are at the “H” level and “L” level, respectively, and the output signal cfs of the fuse circuit is at the “H” level, a shift redundant operation in one direction is performed. The mode is selected and the first transfer gate 23-1 is turned on. When the output signals uout0 and lout0 of the first shift control circuit are “L” level and “H” level, respectively, and the output signal cfs of the fuse circuit is “H” level, the shift redundant operation in the other direction is performed. The mode is selected and the third transfer gate 27-1 is turned on.
[0089]
On the other hand, as shown in FIG. 18, the second shift control of the second shift redundancy control circuit unit 3-2 is included in each switch element in the second switch unit 2-2 in the second stage. The second output signal uout1 in the circuit is input, and the second output signal lout1 in the second shift control circuit is input. cfs represents an output signal of the above-described fuse circuit 60 (see FIG. 13), and pcll1, pclm1, and pclr1 are three adjacent switch elements among the plurality of switch elements of the first switch section 2-1, respectively. Corresponds to the output signal (pc1 in FIG. 17). csl is an output signal of any switch element of the second switch section 2-2, and is supplied to any one selection line.
[0090]
Preferably, each switch element of the second switch unit 2-2 illustrated in FIG. 18 includes the second output signal uout1 in each second shift control circuit of the second shift redundancy control circuit unit 3-2. a mode in which a shift operation in the direction of the second redundancy selection line JL1 (that is, leftward shift) is performed according to the combination of lout1, the second redundancy selection line J R It is possible to select a mode that performs a shift operation in the direction of 0 (that is, a right shift) or a mode that does not perform a shift operation (that is, no shift).
[0091]
Further, each switch element of the second switch section 2-2 shown in FIG. 18 includes a signal obtained by inverting the output signal cfs of the fuse circuit by the inverter 20-2, one output signal uout1 of the second shift control circuit, And a NOR gate (negative OR gate) 21-2 having the other output signal lout1 of the second shift control circuit as three input signals, three inverters 22-2, 24-2 and 26-2, 3 And a three-way switch element composed of two transfer gates 23-2, 25-2, and 27-2.
[0092]
More specifically, when both the output signals uout1 and lout1 of the second shift control circuit are at the “L” level and the output signal cfs of the fuse circuit is at the “H” level, the mode in which the shift redundant operation is not performed is selected. Thus, the second transfer gate 25-2 is turned on. When the output signals uout1 and lout1 of the second shift control circuit are at the “H” level and “L” level, respectively, and the output signal cfs of the fuse circuit is at the “H” level, a shift redundant operation in one direction is performed. The mode is selected and the first transfer gate 23-2 is turned on. When the output signals uout1 and lout1 of the second shift control circuit are “L” level and “H” level, respectively, and the output signal cfs of the fuse circuit is “H” level, the shift redundancy operation in the other direction is performed. The mode is selected and the third transfer gate 27-2 is turned on.
[0093]
Further, when the output signals uout1 and lout1 of the second shift control circuit are both at the “L” level and the output signal cfs of the fuse circuit is at the “L” level, the three transfer gates 23-1, 25-1 and 27-1 is turned off. At this time, the P-channel transistor 28-2 is turned on, and an “H” level voltage is input to the inverter 29-2. The inverter 29-2 functions as an output driver, and the output voltage of the output driver becomes “L” level. That is, when the selection line connected to the output driver 29-2 is a defect selection line, the defect selection line can always be in a non-selected state.
[0094]
FIG. 19 and FIG. 20 show the first and second block diagrams showing the overall circuit configuration according to one embodiment of the present invention, respectively. Here, the normal selection fuse circuit of FIG. 13, the redundancy selection fuse circuit of FIG. 14, the first and second shift control circuits of FIG. 16, the first and second shift circuits of FIG. 17 and FIG. 64 selection lines R0 to R63 and four first and second redundant selection lines JL0, JL0, JR0 and JR1 are arranged by connecting a plurality of sub-circuits composed of two switch sections and the like. A case where a semiconductor memory device (parent circuit) is formed is illustrated.
[0095]
FIG. 19 shows the left end of such a parent circuit, and FIG. 20 shows the right end of the parent circuit. 19 and 20, a plurality of normal selection fuse circuits (for example, the first fuse circuit 60-0 to the 64th fuse circuit 60-63) are connected to the plurality of first shift control circuits, respectively. Has been. The first shift control circuit includes a first left shift first shift control circuit 30-1-l0 to a 64th left shift first shift control circuit 30-1-l63, Second shift control circuit 30-1-r0 for the right shift and first shift control circuit 30-1-r63 for the right shift.
[0096]
Furthermore, the output signals (uout0 and lout0) from these first shift control circuits are used for controlling the switching operation of the plurality of switch elements of the first switch section 2-1. Further, the decode signal line of the decoder circuit shown in FIG. 1 is connected to a plurality of switch elements of the first switch section 2-1, and the decode signal Sdec output from the decoder circuit is a first switch. Supplied to the plurality of switch elements of the section 2-1. As described above, each of the plurality of switch elements of the first switch unit 2-1 includes circuit elements corresponding to these switch elements.
[0097]
Further, in FIG. 19 and FIG. 20, a plurality of normal selection fuse circuits are connected to a plurality of second shift control circuits, respectively. These second shift control circuits include a first left shift second shift control circuit 30-2-10 to a 64th left shift second shift control circuit 30-2-166, Second shift control circuit 30-2-r0 for the right shift and first shift control circuit 30-2-r63 for the 64th right shift.
[0098]
Further, the output signals (uout1 and lout1) from these second shift control circuits are used for controlling the switching operation of the plurality of switch elements of the second switch section 2-2. Further, the plurality of switch elements of the first switch unit 2-1 shown in FIG. 1 are connected to the plurality of switch elements of the second switch unit 2-2, and the decode signal output from the decoder circuit Sdec is supplied to the plurality of switch elements of the second switch section 2-2 via the plurality of switch elements of the first switch section 2-1. In this case as well, each of the plurality of switch elements of the second switch section 2-2 includes circuit elements corresponding to these switch elements.
[0099]
Further, in FIGS. 19 and 20, the redundancy selection fuse circuit 60j-l0 located on the side closer to the leftmost selection line R0 is replaced with the first redundancy selection shift control circuit 30-1-jll0 for left shift. It is connected to the. On the other hand, the redundancy selection fuse circuit 60j-r0 located on the side close to the rightmost selection line R63 is connected to the first redundancy selection shift control circuit 30-1-jrr0 for right shift.
[0100]
Further, in FIGS. 19 and 20, the redundancy selection fuse circuit 60j-l0 located on the side closer to the leftmost selection line R0 is replaced with a second redundancy selection shift control circuit 30-2-jll0 for left shift. And a second redundancy selection shift control circuit 30-2-jlr0 for right shift. Further, the redundancy selection fuse circuit 60j-l1 located on the side away from the leftmost selection line R0 is connected to the second redundancy selection shift control circuit 30-2-jll1 for left shift. On the other hand, the redundancy selection fuse circuit 60j-r0 located on the side closer to the rightmost selection line R63 includes the second redundancy selection shift control circuit 30-2-jrl0 for left shift and the right shift. The second redundancy selection shift control circuit 30-2-jrr0 is connected. Further, the redundancy selection fuse circuit 60j-r1 located on the side away from the rightmost selection line R63 is connected to the second redundancy selection shift control circuit 30-2-jrr1 for right shift.
[0101]
Further, the shift control circuits of FIG. 19 and FIG. 20 connect one first input signal uin0 and one first output signal uout0 in the first shift control circuits for left shift adjacent to each other, and By connecting the other first input signal lin0 and the other first output signal lout0 in the adjacent first shift control circuit for the right shift, the circuit connected in series has two stages. ing. Input signal uin0 of the first redundancy selection shift control circuit 30-1-jll0 for left shift located at the left end, and the second redundancy selection shift control circuit 30- for right shift located at the right end The input signal lin0 of 1-jrr0 is input with a voltage of “H” level from the power supply (power supply voltage Vii) on the high voltage side.
[0102]
Further, the shift control circuits of FIGS. 19 and 20 connect one second input signal uin1 and one second output signal uout1 in the second shift control circuit for left shift adjacent to each other, and to the right By connecting the other second input signal lin1 and the other second output signal lout1 in the second shift control circuit for shifting, the circuit connected in series has two stages. An input signal uin1 of the second redundancy selection shift control circuit 30-2-jll1 located at the left end and a second redundancy selection shift control circuit 30- located at the right end of the right shift. The input signal lin1 of 2-jrr1 is input with a voltage of “H” level from the power supply (power supply voltage Vii) on the high voltage side.
[0103]
In the above embodiment, in order to perform 1-bit to 4-bit shift redundancy processing, it is necessary to provide fuses in a one-to-one correspondence with a plurality of selection lines. Therefore, the number of fuses increases as the number of select lines increases. For example, in a semiconductor memory device in which 64 selection lines are arranged, a total of 68 fuses corresponding to 64 selection lines and 4 redundant selection lines must be laid out on the semiconductor chip.
[0104]
In consideration of this point, in order to reduce the number of necessary fuses as much as possible, it is possible to generate a fuse decode signal by decoding a signal generated by a combination of a plurality of fuses. For example, when generating fuse decode signals respectively corresponding to 64 select lines, 6 (2 ⁶ = 64), 64 fuse decode signals are generated. Therefore, it is sufficient to prepare 16 fuses including 4 redundant selection fuses.
[0105]
【The invention's effect】
As described above, according to the semiconductor memory device of the present invention, the switch units having at least 2-bit shift redundancy function are arranged in two stages in series, and one end of each switch unit is redundantly selected. Three or more lines are formed on the semiconductor chip due to a group defect or the like by performing a switching operation for shifting the decode signal line in the direction of the line, the redundant selection line at the other end, or both redundant selection lines. When the defect selection line is generated, the above-described defect selection line can be relieved by performing a shift redundancy operation of 3 bits or more, so that the yield in chip manufacturing is improved.
[0106]
Furthermore, according to the semiconductor memory device of the present invention, the direction of one redundant selection line or the direction of the other redundant selection line or the redundant selection of both is selected for at least one of the switch sections arranged in two stages. By performing the switching operation in the line direction, even when one or two defect selection lines are generated on the semiconductor chip, these defect selection lines can be relieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a principle configuration of the present invention.
FIG. 2 is a schematic diagram illustrating an operation of a switch unit when a defect occurs in four selection lines.
FIG. 3 is a schematic diagram illustrating a first example of an operation of a switch unit when a defect occurs in three selection lines.
FIG. 4 is a schematic diagram illustrating a second example of the operation of the switch unit when a defect occurs in three selection lines.
FIG. 5 is a schematic diagram showing a first example of the operation of the switch section when a defect occurs in two selection lines.
FIG. 6 is a schematic diagram illustrating a second example of the operation of the switch unit when a defect occurs in two selection lines.
FIG. 7 is a schematic diagram illustrating a third example of the operation of the switch unit when a defect occurs in two selection lines.
FIG. 8 is a schematic diagram illustrating a first example of the operation of the switch unit when a defect occurs in one selection line.
FIG. 9 is a schematic diagram illustrating a second example of the operation of the switch unit when a defect occurs in one selection line.
FIG. 10 is a schematic diagram showing the operation of the switch unit when there is no defect in the selection line.
FIG. 11 is a diagram illustrating signal levels of respective units according to the operation of the switch unit when defects occur in four selection lines.
FIG. 12 is a diagram illustrating signal levels of the respective units according to the operation of the switch unit when defects occur in three selection lines.
FIG. 13 is a circuit diagram showing a configuration of a normal selection fuse circuit in an embodiment of the present invention.
FIG. 14 is a circuit diagram showing a configuration of a redundancy selection fuse circuit in an embodiment of the present invention.
FIG. 15 is a circuit diagram showing a configuration of a forced redundancy fuse circuit in an embodiment of the present invention.
FIG. 16 is a circuit diagram showing a configuration of first and second shift control circuits in an embodiment of the present invention.
FIG. 17 is a circuit diagram showing a configuration of a first switch section in an embodiment of the present invention.
FIG. 18 is a circuit diagram showing a configuration of a second switch section in an embodiment of the present invention.
FIG. 19 is a block diagram (No. 1) showing an overall circuit configuration according to an embodiment of the present invention;
FIG. 20 is a block diagram (part 2) illustrating an overall circuit configuration according to an embodiment of the present invention.
FIG. 21 is a block diagram showing a configuration example of a conventional semiconductor memory device having a 2-bit shift redundancy function.
22 is a schematic diagram for explaining a 2-bit shift redundancy operation according to FIG. 21;
[Explanation of symbols]
1 ... Shift redundancy circuit
2-1. First switch section
2-2. Second switch part
3-1. First shift redundancy control circuit section
3-2. Second shift redundancy control circuit section
4 ... Shift redundant fuse circuit
5 ... Decoder circuit
20-1, 20-2 ... Inverter
21-1, 21-2 ... NOR gate
22-1, 24-1 and 26-1 ... Inverter
22-2, 24-2 and 26-2 ... Inverter
23-1, 25-1 and 27-1 ... Transfer gate
23-2, 25-2 and 27-2 ... Transfer gate
28-2 ... P-channel transistor
30-1... First shift control circuit
30-1-l: first shift control circuit for left shift
30-1-r: first shift control circuit for right shift
30-2 ... Second shift control circuit
30-2-l Second shift control circuit for left shift
30-2-r ... Second shift control circuit for right shift
31-1, 31-2 ... NAND gate
32-1 ... NAND gate
32-2 ... Inverter
33-1, 33-2 ... NAND gate
34-1 ... NAND gate
34-2 ... Inverter
40 ... Fuse
41 ... P-channel transistor
42, 44 ... N-channel type transistors
43, 45 ... Inverter
60. Fuse circuit
60j ... Redundant selection fuse circuit
60pj ... Forced redundancy fuse circuit
100: Shift redundancy circuit
200 ... switch part
300: Shift redundancy control circuit section
400: Shift redundant fuse circuit section
500 ... Decoder circuit
R0 to R (n-1) ... selection line
JL0, JL0, JR0 and JR1 ... Redundant selection line
sl0 to sl (n-1) ... selection line
slj0, slj1... redundant selection line
cl0-sl63 ... selection line
clj0, clj1... redundant selection line

Claims (6)

In a semiconductor memory device in which a plurality of selection lines for selecting a specific memory cell from a plurality of memory cells and writing or reading data based on an address signal supplied from the outside are arranged.
Among the plurality of selection lines, at least two first redundant selection lines located at one end and at least two second redundant selection lines located at the other end;
A first switch unit and a second switch unit arranged in at least two stages to connect a plurality of decode signal lines obtained by decoding the address signal to the plurality of selection lines and the redundant selection line in a switchable manner. And
When a defect occurs in the plurality of selection lines, the first switch operation is performed by the first switch unit to shift at least one of the decoded signal lines in the direction of the first redundant selection line. Or a second switching operation for shifting at least one of the decode signal lines in the direction of the second redundant selection line is performed, or the first switching operation and the second switching operation are performed. To perform both switching operations,
Performing a third switching operation of shifting at least one of the decoded signal lines that has performed the first switching operation further in the direction of the first redundant selection line by the second switch unit; or A fourth switching operation for shifting at least one of the decode signal lines that have performed the second switching operation in the direction of the second redundant selection line is performed, or the third switching operation is performed. And the fourth switching operation, or the switching operation of either the third switching operation or the fourth switching operation is not performed. . When a defect occurs in four selection lines in the plurality of selection lines, the first switching unit performs both the first switching operation and the second switching operation by the first switch unit, and The semiconductor memory device according to claim 1, wherein the second switching unit is configured to perform both the third switching operation and the fourth switching operation. When a defect occurs in three selection lines in the plurality of selection lines, the first switch unit performs both of the first switching operation and the second switching operation, and 2. The semiconductor memory device according to claim 1, configured to perform either one of the third switching operation and the fourth switching operation by a second switch unit. When a defect occurs in two selection lines in the plurality of selection lines, one of the first switching operation and the second switching operation by the first switch unit is performed. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to perform any one of the third switching operation and the fourth switching operation by the second switch unit. When a defect occurs in two selection lines in the plurality of selection lines, both the first switching operation and the second switching operation by the first switch unit are performed, and the first switching operation is performed. 2. The semiconductor memory device according to claim 1, configured so as not to perform any of the third switching operation and the fourth switching operation by the second switch unit. When a defect occurs in one selection line of the plurality of selection lines, the switching operation of either the first switching operation or the second switching operation by the first switch unit is performed, 2. The semiconductor memory device according to claim 1, wherein the second switching unit is configured not to perform any switching operation of the third switching operation and the fourth switching operation.

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