JP4601344B2 - Nonvolatile semiconductor memory device and data read / write method - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a multi-value nonvolatile semiconductor device and a data read / write method.

  A nonvolatile semiconductor memory device such as a flash memory stores data by injecting electrons (for example, hot electrons) into a floating gate of a memory cell and changing a threshold voltage Vth of the memory cell. The threshold voltage Vth of the memory cell increases when electrons are injected into the floating gate, and decreases when electrons are extracted from the floating gate. In recent years, in order to increase the storage capacity, a multi-value type nonvolatile semiconductor memory device in which a plurality of bits of data is stored in one memory cell has been proposed. In this case, the amount of charge injected into the floating gate is controlled with high accuracy.

FIG. 1 shows a distribution of threshold voltages Vth of memory cells in a quaternary flash memory. In FIG. 1, the vertical axis represents the threshold voltage Vth of the memory cell (memory transistor), and the horizontal axis represents the number of memory cells (distribution frequency). The threshold voltage Vth of the memory cell differs depending on the programmed data (“00”, “01”, “10”, “11”). Further, the threshold voltage Vth may differ between memory cells programmed with the same data due to variations in the structure of each memory cell. That is, the threshold voltage Vth of the entire memory cell has a plurality of distributions D _{0 to} D ₃ as shown in FIG. Distributions D _{0 to} D ₃ correspond to 2-bit data “00”, “01”, “10”, and “11”, respectively. The threshold voltage Vth of each memory cell belongs to one of distributions D _{0 to} D ₃ according to programmed (written) data. Data reading is performed by comparing the threshold voltage Vth of the memory cell with the read reference voltages VR _{0 to} VR ₂ . These read reference voltages VR _{0 to} VR ₂ are set so as to be positioned at a margin between distributions.

  The followings are known as techniques relating to such a nonvolatile semiconductor memory device.

  The technique disclosed in Patent Document 1 relates to a nonvolatile semiconductor memory device that stores binary data (“0”, “1”), and aims to reduce time for writing data. The nonvolatile semiconductor memory device includes a counting circuit, a writing circuit, and a recording unit. At the time of data writing, the counting circuit counts the total number of data “0” or data “1” written to the entire memory cell array. The writing circuit writes data after “normally rotating” or “inverting” the phase of data at the time of data writing based on the count result. The recording unit records phase information indicating “forward” or “inverted” by the writing circuit.

  A technique for “normally rotating” or “inverting” write data as in the technique according to Patent Document 1 is disclosed in Patent Document 2. The technique disclosed in Patent Document 2 relates to a nonvolatile semiconductor memory device that writes multi-value data into memory cells in units of pages, and aims to improve disturb / retention characteristics. The nonvolatile semiconductor memory device includes a determination circuit, a flag memory cell, and a write circuit. At the time of data writing, the determination circuit counts the number of bit data indicating the distribution with the higher threshold voltage, and determines whether the number is more than or less than ½ page. Then, the determination circuit generates flag data indicating the determination result. When the distribution with the higher threshold voltage is more frequent, the writing circuit “inverts” the logic level of the write data and writes to the memory cell. On the other hand, when the distribution with the higher threshold voltage is less, the writing circuit performs “normal rotation” of the logic level of the write data and writes into the memory cell. Further, the write circuit stores the flag data in the flag memory cell.

  In recent years, the amount of data processed in a nonvolatile semiconductor memory device continues to increase, and an improvement in operation speed is increasingly required. Therefore, a nonvolatile semiconductor memory device that can further reduce the time for writing data to the memory cell (hereinafter referred to as “write time”) is desired.

JP-A-8-335396 JP-A-10-55687

  An object of the present invention is to provide a nonvolatile semiconductor memory device and a data read / write method capable of reducing the data write time.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  The nonvolatile semiconductor memory device (10) according to the present invention includes a memory cell (21, 26) in which a predetermined threshold voltage (Vtm) is set among a plurality of threshold voltages (Vtm), and the predetermined threshold voltage ( And a data processing circuit (100) for setting a data value corresponding to Vtm). Here, the setting of the data value is variable. The data processing circuit (100) selects and sets a data value corresponding to the predetermined threshold voltage (Vtm) from a plurality of data values. In addition, when the data processing circuit (100) performs a batch write on the plurality of memory cells (21, 26), the sum of a predetermined threshold voltage (Vtm) in each of the plurality of memory cells (21, 26). Is set such that the correspondence between the threshold voltage and the data value is minimized. The nonvolatile semiconductor memory device (10) further includes a shift value storage area (25) for storing a shift value (SFT) indicating the corresponding relationship, and a control circuit (50). The control circuit (50) is connected to the plurality of memory cells (21, 26), the shift value storage area (25), and the data processing circuit (100), and includes the plurality of memory cells (21, 26) and the shift value. Controls reading and writing of data to the storage area (25).

  A nonvolatile semiconductor memory device (10) according to the present invention includes a memory cell array (20) in which a plurality of memory cells (21, 26) are arranged in an array, and a shift value storage area (SFT) for storing a shift value (SFT). 25), a control circuit (50) for controlling reading and writing of data with respect to the memory cell array (20) and the shift value storage area (25), and a data processing circuit (100) connected to the control circuit (50). Here, “shift value (SFT)” indicates a correspondence relationship between a plurality of data values indicated by the multi-value data and a plurality of threshold voltages (Vtm) included in the memory cells (21, 26). The data processing circuit (100) sets the shift value (SFT) to be variable.

Specifically, at the time of data writing, the data processing circuit (100) refers to the contents of input data (Din, DW _M ) input from the outside, and the threshold voltage of the memory cell group (21) to which writing is performed. The input data (Din, DW _M ) is converted into write data (DW) using one shift value (SFT) of the plurality of shift values (SFT ′) so that the sum of (Vtm) is minimized. To do. Alternatively, the data processing circuit (100) refers to the content of input data (Din, DW _M ) input from the outside, and sets a constant corresponding to the threshold voltage (Vtm) of the memory cell group (21) to which writing is performed. The input data (Din, DW _M ) is converted into write data (DW) using one shift value (SFT) of the plurality of shift values (SFT ′) so that the sum is minimized. Here, the constant indicates a writing time associated with the threshold voltage (Vtm). Then, the data processing circuit (100) outputs the write data (DW) and one shift value (SFT) to the control circuit (50). The control circuit (50) writes the write data (DW) to the memory cell group (21) in the memory cell array (20), and writes one shift value (SFT) to the shift value storage area (25, 26). When data is read, the control circuit (50) reads the read data (DR) from the memory cell group (21), reads one shift value (SFT) from the shift value storage area (25, 26), and reads the read data. (DR) and one shift value (SFT) are output to the data processing circuit (100). The data processing circuit (100) converts the read data (DR) into output data (DR _M , Dout) using one shift value (SFT), and outputs the output data (DR _M , Dout) to the outside. .

According to the nonvolatile semiconductor memory device (10) of the present invention, the sum of the threshold voltages (Vtm) of the memory cell group (21) to which data is written or the sum of constants corresponding to the threshold voltage (Vtm) is minimized. As described above, the input data (Din, DW _M ) is converted into write data (DW). Then, instead of the input data (Din, DW _M ), the write data (DW) is actually written into the memory cell group (21). The data writing time for a certain memory cell (21) depends on the threshold voltage (Vtm) after writing. Therefore, according to the present invention, the total data writing time (Tall) is reduced.

  The plurality of data values indicated by the multi-value data include first to Nth data values (N is a natural number of 3 or more). The plurality of threshold voltages (Vtm) included in the memory cell (21) include first to Nth threshold voltages. At this time, the plurality of shift values (SFT ′) include first to Nth shift values (SFT ′), and each of the first to Nth shift values (SFT ′) includes first to Nth data values. It is preferable to show N types of correspondence relationships between the first to Nth threshold voltages (Vtm). In this case, there is an effect that one shift value (SFT) selected from the first to Nth shift values (SFT ′) is also stored in the shift value storing memory cell (26) in the memory cell array (20). It is done.

  The first shift value (SFT ′) associates each of the first to Nth data values with each of the first to Nth threshold voltages (Vtm), and the i-th shift value (i is 2 to N). Of the first to (i−1) th data values correspond to the (N−i + 2) th to Nth threshold voltage (Vtm) respectively, and the i th to Nth data values Each may be associated with each of the first to (N−i + 1) th threshold voltages (Vtm). For example, when N is 4, the first shift value (SFT ′) is the first, second, third, and fourth data values, and the first, second, third, and fourth threshold voltages (Vtm). ). The second shift value (SFT ′) associates each of the first, second, third, and fourth data values with each of the fourth, first, second, and third threshold voltages (Vtm). The third shift value (SFT ′) associates each of the first, second, third, and fourth data values with each of the third, fourth, first, and second threshold voltages (Vtm). The fourth shift value (SFT ') associates each of the first, second, third, and fourth data values with each of the second, third, fourth, and first threshold voltages (Vtm).

In the nonvolatile semiconductor memory device (10) according to the present invention, the data processing circuit (100) is connected to the write data conversion circuit (110) connected to the control circuit (50) and the write data conversion circuit (110). A shift value determining circuit (130) and a read data conversion circuit (120) connected to the control circuit (50). When writing data, the shift value determining circuit (130) receives input data (DW _M), by referring to the contents of the input data (DW _M), one shift from a plurality of shift values (SFT ') Select a value (SFT). Then, the shift value determination circuit (130) outputs the one shift value (SFT) to the write data conversion circuit (110). The write data conversion circuit (110) receives the input data (DW _M ) and one shift value (SFT), and converts the input data (DW _M ) into the write data (DW _M ) according to the correspondence relationship indicated by the one shift value (SFT). DW). Then, the write data conversion circuit (110) outputs the write data (DW) and one shift value (SFT) to the control circuit (50). When reading data, the read data conversion circuit (120) receives the read data (DR) and one shift value (SFT) from the control circuit (50). Then, the read data conversion circuit (120) converts the read data (DR) into output data (DR _M ) in accordance with the correspondence relationship indicated by the one shift value (SFT).

  In the nonvolatile semiconductor memory device (10) according to the present invention, the plurality of memory cells (21, 26) include a shift value storage memory cell (26) as a shift value storage region (25). At this time, the memory cell group (21) and the shift value storage memory cell (26) are connected to the same word line (WL).

In the nonvolatile semiconductor memory device (10) according to the present invention, the shift value determination circuit (130) includes a verification data generation circuit (132) and a write time calculation circuit (201) connected to the verification data generation circuit (132). And a determination circuit (202) connected to the write time calculation circuit (201). The verification data generation circuit (132) receives the input data (DW _M ), and based on a plurality of correspondence relationships indicated by each of the plurality of shift values (SFT ′), a plurality of verification data from the input data (DW _M ). (DT) is generated. The write time calculation circuit (201) receives the plurality of verification data (DT) and calculates a write time (Tall) required for writing the plurality of verification data (DT) to each memory cell group (21). The determination circuit (202) detects the shortest one writing time (Tall) among the plurality of writing times (Tall), and determines the shift value (SFT ′) associated with the one writing time (Tall) as one Select as shift value (SFT).

  The write time calculation circuit (201) includes a counter (133), a multiplier (134) connected to the counter (133), and an adder (135) connected to the multiplier (134). The counter (133) receives each verification data (DT) and counts the number of each of a plurality of data values included in each verification data (DT). The multiplier (134) calculates a plurality of multiplication values by multiplying the number of each of the plurality of data values by a plurality of constants corresponding to the plurality of threshold voltages (Vtm). The adder (135) calculates the total write time (Tall) by adding a plurality of multiplication values.

In the nonvolatile semiconductor memory device (10) according to the present invention, the shift value determination circuit (130) includes a verification data generation circuit (132) and a write time calculation circuit (201) connected to the verification data generation circuit (132). And a determination circuit (202) connected to the write time calculation circuit (201). The verification data generation circuit (132) receives the input data (DW _M ), and based on the correspondence relationship indicated by each of the plurality of shift values (SFT ′), a plurality of verification data (DT) from the input data (DW _M ). ) Is generated. The write time calculation circuit (201) receives a plurality of verification data (DT) and a plurality of shift values (SFT ′). Then, the write time calculation circuit (201) writes data required to write each verification data (DT) and the corresponding shift value (SFT ′) to the memory cell group (21) and the shift value storage memory cell (26). Time (Tall) is calculated. The determination circuit (202) detects the shortest one writing time (Tall) among the plurality of writing times (Tall), and determines the shift value (SFT ′) associated with the one writing time (Tall) as one Select as shift value (SFT).

  The write time calculation circuit (201) includes a counter (143), a multiplier (144) connected to the counter (143), and an adder (145) connected to the multiplier (144). The counter (143) receives each verification data (DT) and the corresponding shift value (SFT '), and receives a plurality of data values included in each of the verification data (DT) and the corresponding shift value (SFT'). Count the number of each. The multiplier (144) calculates a plurality of multiplied values by multiplying the number of each of the plurality of data values by a plurality of constants corresponding to each of the plurality of threshold voltages (Vtm). The adder (145) calculates the total write time (Tall) by adding a plurality of multiplication values.

  The determination circuit (202) is connected to the comparators (137, 147) connected to the write time calculation circuit (201) and a reference value register (Tref) connected to the comparators (137, 147). 138, 148). The comparators (137, 147) sequentially compare a plurality of write times (Tcalc) calculated by the write time calculation circuit (201) with a reference value (Tref). When the write time (Tcalc) is smaller than the reference value (Tref), the comparators (137, 147) update the reference value (Tref) with the write time (Tcalc) to thereby obtain a plurality of write times (Tcalc). The one write time (Tall) is detected.

  According to the nonvolatile semiconductor memory device and the data read / write method according to the present invention, the data write time is reduced.

  According to the nonvolatile semiconductor memory device and the data read / write method according to the present invention, the operation speed is improved.

  A nonvolatile semiconductor memory device according to the present invention and a data read / write method for the nonvolatile semiconductor memory device will be described with reference to the accompanying drawings.

  First, the “shift value” used in this specification will be described.

  The memory cell of the nonvolatile semiconductor memory device according to the present invention is a nonvolatile memory cell having a control gate and a floating gate. Multi-value data is stored in one memory cell. The multi-value data indicates a plurality of data values, for example, four data values such as “00”, “01”, “10”, and “11”. The plurality of data values respectively correspond to a plurality of threshold voltages included in the memory cell (memory cell transistor). That is, the threshold voltage is controlled by adjusting the amount of electrons injected into the floating gate, thereby realizing storage of multi-value data.

  FIG. 2 shows an example of the distribution of the threshold voltage Vth in the nonvolatile semiconductor memory device according to the present invention. In FIG. 2, the vertical axis represents the threshold voltage Vth of the memory cell, and the horizontal axis represents the number of memory cells (distribution frequency). According to this nonvolatile semiconductor memory device, for example, quaternary (2-bit) data can be stored in one memory cell, and as shown in FIG. 2, the distribution of threshold voltage Vth of the entire memory cell Has four distributions A0 to A3. Here, the threshold voltage Vth representing each of the distributions A0 to A3 is defined as threshold voltages Vtm0 to Vtm3.

  In the present invention, the correspondence relationship between the plurality of threshold voltages Vtm0 to Vtm3 and the plurality of data values (“00”, “01”, “10”, “11”) is not fixed and is variable. For example, the threshold voltage Vtm0 (distribution A0), threshold voltage Vtm1 (distribution A1), threshold voltage Vtm2 (distribution A2), and threshold voltage Vtm3 (distribution A3) are data values “01”, “11”, “00”, respectively. , “10” may be supported. In this specification, such a correspondence relationship between a plurality of threshold voltages and a plurality of data values is referred to as a “shift value SFT”. In the case of quaternary data as shown in FIG. 2, up to 24 (= 4!) Types of patterns can be considered as this correspondence. That is, 24 types of “shift value SFT” may exist.

  As will be described in detail later, according to the present invention, one shift value SFT is selected from such a plurality of shift values SFT, and data is read and written by using the one shift value SFT. As such a plurality of shift values SFT, all types of shift values SFT that may exist may be prepared, or several types of shift values SFT extracted as appropriate may be prepared.

  FIG. 3 shows an example of the correspondence relationship indicated by the shift value SFT and the shift value. Here, as an example, four types of shift values (SFT = 0 to 3) are prepared. When the shift value SFT is 0 (SFT = 0), the input / output data values “00”, “01”, “10”, and “11” are the threshold voltages Vtm3, Vtm2, It corresponds to each of Vtm1 and Vtm0 (see FIGS. 1 and 2).

  When the shift value SFT is 1 (SFT = 1), the input / output data values “00”, “01”, “10”, and “11” are the threshold voltages Vtm0, Vtm3, Vtm2, and Vtm1, respectively. It corresponds to. In order to realize such a correspondence and to make use of the configuration of a conventional write / read circuit, the value of input / output data may be converted intentionally and regularly. That is, the data “00”, “01”, “10”, “11” input at the time of writing is converted into data “11”, “00”, “01”, “10” as shown in FIG. The converted data (write data) may be actually written into the memory cell. On the other hand, at the time of reading, data (read data) “11”, “00”, “01”, “10” read directly from the memory cells are data “00”, “01”, “10”, “ 11 ″, and the converted data may be output as output data. Thereby, the above-mentioned correspondence is realized.

  Similarly, when the shift value SFT is 2 (SFT = 2), the input / output data values “00”, “01”, “10”, and “11” are the threshold voltages Vtm1, Vtm0, Vtm3, This corresponds to each of Vtm2. When the shift value SFT is 3 (SFT = 3), the input / output data values “00”, “01”, “10”, “11” are the threshold voltages Vtm2, Vtm1, Vtm0, Vtm3, respectively. It corresponds to. Thus, the threshold voltage (write data) “shifts” each time the shift value SFT increases.

  In this case, since four types of shift values SFT (0 to 3) are used, the shift value SFT itself can be expressed by 2 bits. Therefore, it is possible to store the shift value SFT in a memory cell similar to the memory cell storing quaternary data, which is preferable.

  In the present invention, data stored in the memory cell is not limited to quaternary data. More generally, in the case of N-value data (N is a natural number of 3 or more), the N-value data includes first to Nth data values. At this time, the memory cell has N-level threshold voltages (first to Nth threshold voltages). In this case, as a correspondence relationship between the first to Nth data values and the first to Nth threshold voltages, the maximum N! There are different types of patterns. In other words, N! There may be different types of shift values SFT.

  N types of shift values SFT (first to Nth shift values) are preferably used to store the shift value SFT itself in a memory cell similar to a memory cell in which N-value data is stored. The N types of shift values SFT indicate N types of corresponding relationships. For example, the first shift value associates each of the first to Nth data values with each of the first to Nth threshold voltages. The i-th shift value (i is a natural number greater than or equal to 2 and less than or equal to N) associates each of the first to (i−1) data values with each of the (N−i + 2) to Nth threshold voltages, and Each of the i-th to N-th data values is associated with each of the first to (N−i + 1) th threshold voltages (see FIG. 3). In this case, every time the shift value SFT changes, the threshold voltage (write data) shifts.

  The configuration and operation of the nonvolatile semiconductor memory device according to the present invention will be described below.

  FIG. 4 is a block diagram showing a configuration of the nonvolatile semiconductor memory device according to the present invention. The nonvolatile semiconductor memory device 10 includes a memory cell array 20, an I / O buffer 30, an R / W control circuit 50, and a data processing circuit 100.

  The memory cell array 20 includes a plurality of memory cells arranged in an array. FIG. 5 is a circuit diagram showing a part of the memory cell array 20 in detail. As shown in FIG. 5, in the memory cell array 20, a plurality of word lines (WL1 to WL3) are formed to be orthogonal to a plurality of bit lines (DL1 to DL9). Each memory cell is a nonvolatile memory cell having a control gate and a floating gate, and multi-value data is stored in one memory cell. The control gate of the memory cell is connected to one of the word lines (WL), its drain is connected to one of the bit lines (DL), and its source is connected to a common source line SL.

  The plurality of memory cells include a memory cell 21 for storing data and a shift value storage memory cell 26 for storing the above-described shift value SFT. For example, a memory cell group 21-11 to 21-18 connected to the bit lines DL1 to DL8 and a shift value storage memory cell 26-1 connected to the bit line DL9 are connected to the word line WL1. The word line WL2 is connected to memory cell groups 21-21 to 21-28 connected to the bit lines DL1 to DL8 and a shift value storage memory cell 26-2 connected to the bit line DL9. The word line WL3 is connected to memory cell groups 21-31 to 21-38 connected to the bit lines DL1 to DL8 and a shift value storage memory cell 26-3 connected to the bit line DL9. These shift value storage memory cells 26-1 to 26-3 constitute a shift value storage memory cell group 25. This shift value storage memory cell group 25 is used as a “shift value storage area” for storing the shift value SFT.

  Thus, the memory cell group and the shift value storage memory cell 26 are connected to the same word line. Therefore, by selecting one word line WL, it is possible to write the write data and the shift value SFT to the memory cell group and the shift value storage memory cell 26, respectively. Similarly, by selecting one word line WL, it is possible to read the read data and the shift value SFT from the memory cell group and the shift value storage memory cell 26, respectively. That is, it is possible to store certain data and a certain shift value SFT in the memory cell array 20 in association with each other.

  As shown in FIG. 4, the plurality of word lines (WL) are connected to the X decoder 61. The plurality of bit lines (DL) are connected to the Y decoder 62 via the Y selector 63. The R / W control circuit 50 is connected to the memory cell array 20 via an X decoder 61, a Y decoder 62, and a Y selector 63. The R / W control circuit 50 controls reading / writing of data from / to the memory cell array 20 including the shift value storing memory cell group 25.

  The I / O buffer 30 is connected to the data processing circuit 100 via a multi-value conversion unit 41 and a binary conversion unit 42. The nonvolatile semiconductor memory device 10 exchanges data with the outside via the I / O buffer 30. The multi-value conversion unit 41 has a function of converting binary data into multi-value data. In addition, the binary conversion unit 42 has a function of converting multi-value data into binary data.

  The data processing circuit 100 is connected to the I / O buffer 30 via the multi-value conversion unit 41 and the binary conversion unit 42. The data processing circuit 100 is connected to the R / W control circuit 50. The data processing circuit 100 uses one shift value SFT among the plurality of shift values SFT described above, and converts externally input data into write data DW according to the conversion pattern shown in FIG. Then, the data processing circuit 100 outputs the write data DW and one shift value SFT to the R / W control circuit 50. Further, the data processing circuit 100 receives the read data DR read from the memory cell group by the R / W control circuit 50 and one shift value SFT read from the shift value storage area (shift value storage memory cell 26). Then, the data processing circuit 100 converts (restores) the read data DR into data corresponding to data input from the outside according to the conversion pattern shown in FIG. 3 using the one shift value SFT.

  As shown in FIG. 4, the data processing circuit 100 includes a write data conversion circuit 110, a read data conversion circuit 120, and a shift value determination circuit 130. The write data conversion circuit 110 is connected to the multi-value conversion unit 41 and the R / W control circuit 50, and performs data conversion during a write operation. The read data conversion circuit 120 is connected to the binary conversion unit 42 and the R / W control circuit 50, and performs data conversion during a read operation. The shift value determination circuit 130 is connected to the multi-value conversion unit 41 and the write data conversion circuit 110, and selects one shift value from a plurality of shift values SFT. The read data conversion circuit 120 may be further connected to the shift value determination circuit 130.

  FIG. 6 is a block diagram showing the configuration of the shift value determination circuit 130 in more detail. The shift value determination circuit 130 includes a verification data generation circuit 132, a write time calculation circuit 201 connected to the verification data generation circuit 132, and a determination circuit 202 connected to the write time calculation circuit 201.

  Next, the operation of the nonvolatile semiconductor memory device 10 according to the present invention will be described in detail with reference to the configuration shown in FIGS. 4 to 6 and the flowcharts shown in FIGS.

(Write operation)
FIG. 7 is a flowchart for explaining the “write operation” in the nonvolatile semiconductor memory device 10 according to the present invention.

Step S10:
First, data stored in the nonvolatile semiconductor memory device 10 (hereinafter referred to as “input data Din”) is input to the I / O buffer 30. This input data Din is composed of binary data (“0”, “1”). For example, the input data Din indicates “1, 0, 1, 0, 1, 0, 0, 0”.

Step S20:
Next, the input data Din is output from the I / O buffer 30 to the multi-value conversion unit 41 as “binary write data DW _B ”. Multi-level conversion unit 41, the binary write data DW _B, converted into multi-valued data "multilevel write data DW _M". For example, binary data “1, 0, 1, 0, 1, 0, 0, 0” is converted into multi-value data “10, 10, 10, 00”. The multi-value write data DW _M that generated as is output to the data processing circuit 100.

Step S30:
Shift value determining circuit 130 of the data processing circuit 100 receives the multi-value write data DW _M. Then, the shift value determining circuit 130 refers to the contents of the multi-value write data DW _M, selects one shift value SFT from a plurality of shift values SFT.

Specifically, (see FIG. 6) the verification data generation circuit 132 of the shift value determining circuit 130, a plurality with each of the plurality of shift values SFT, in accordance with the conversion pattern shown in FIG. 3, the multi-value write data DW _M To the verification data DT. The plurality of shift values SFT (0 to 3) are sequentially input to the verification data generation circuit 132 as “provisional shift value SFT ′”, for example. For example, when “2” is input as the temporary shift value SFT ′, the verification data generation circuit 132 converts the multi-value write data “10, 10, 10, 00” into the verification data according to the conversion pattern shown in FIG. Convert to “00, 00, 00, 10”. Thus, based on a plurality of correspondence relationships shown each of the temporary shift values SFT ', a plurality of verification data DT from the multi-value write data DW _M is generated. The plurality of generated verification data DT is output to the write time calculation circuit 201.

  The write time calculation circuit 201 estimates and calculates the time (write time) required to write each verification data DT to the memory cell group. In general, the data writing time for a certain memory cell depends on the threshold voltage Vth after writing. For example, when the potential applied to the memory cell transistor and the time during which the potential is applied are constant, the higher the threshold voltage Vth after writing, the longer the writing time, and the lower the writing voltage, the shorter the writing time. More generally, each of the plurality of threshold voltages can be associated with a “predetermined constant” indicating the writing time. For example, when the verification data “00, 00, 00, 10” is received, the write time calculation circuit 201 is based on the threshold voltages “Vtm3, Vtm3, Vtm3, Vtm1 (see FIG. 3)” corresponding to the respective data values. It is possible to estimate and calculate the writing time. In this way, a plurality of write times are calculated corresponding to each of the plurality of verification data DT. The write time calculation circuit 201 outputs a write time signal ST indicating the calculated write time to the determination circuit 202.

  The determination circuit 202 receives a plurality of write time signals ST corresponding to each of the plurality of temporary shift values SFT ′. Then, the determination circuit 202 detects the shortest writing time from the plurality of writing times indicated by the plurality of writing time signals. Then, the determination circuit 202 determines the temporary shift value SFT ′ related to the shortest writing time as the above “one shift value”.

  As described above, according to the present invention, the shift value determining circuit 130 of the data processing circuit 100 can generate one shift value SFT from a plurality of shift values SFT so that the sum of the threshold voltages Vth of the memory cell group to be written is minimized. A shift value SFT is selected. Alternatively, the shift value determination circuit 130 selects one shift value SFT from the plurality of shift values SFT so that the sum of predetermined constants corresponding to the threshold voltage Vth of the memory cell group to which writing is performed is minimized. Then, the shift value determination circuit 130 outputs the shift value SFT to the write data conversion circuit 110.

Step S40:
The write data conversion circuit 110 receives the multi-value write data DW _M generated by the multi-value conversion unit 41, a shift value SFT determined by the shift value determining circuit 130. The write data conversion circuit 110, according to the corresponding relationship (see FIG. 3) indicated by the shift value SFT, into data DW writing multilevel write data DW _M. For example, when the shift value SFT is “3”, the write data conversion circuit 110 converts the multi-value write data “10, 10, 10, 00” into the write data “11, 11, 11, 01 ". Then, the write data conversion circuit 110 outputs the write data DW and the shift value SFT to the R / W control circuit 50.

Step S50:
The R / W control circuit 50 receives “address data DA” indicating the address of the memory cell to be accessed from the I / O buffer 30 and outputs the address data DA to the X decoder 61 and the Y decoder 62. As a result, a predetermined word line WL and bit line DL are selected, and the “memory cell group” and “shift value storage memory cell 26” to be accessed are selected. The R / W control circuit 50 sets a write voltage and the like according to the write data DW.

Step S60:
The R / W control circuit 50 writes the write data DW to the selected memory cell group via the Y selector 63 and writes the shift value SFT to the shift value storage memory cell 26 (shift value storage area). Thus, when the shift value SFT is also expressed by 2 bits, the shift value SFT can be stored in the memory cell array 20, which is preferable. However, the region in which the shift value SFT is stored is not limited to the shift value storage memory cell group 25 in the memory cell array 20. A shift value storage area for storing the shift value SFT may be provided independently of the memory cell array 20. In this case, the R / W control circuit 50 stores the shift value SFT in the shift value storage area.

  As described above, according to the nonvolatile semiconductor memory device 10 of the present invention, the input is performed so that the sum of the threshold voltages Vth of the memory cells to be written or the sum of constants corresponding to the threshold voltage Vth is minimized. Data Din is converted into write data DW. Then, instead of the input data Din, the write data DW is actually written into the memory cell group. Therefore, the data writing time is reduced.

(Read operation)
FIG. 8 is a flowchart for explaining the “read operation” in the nonvolatile semiconductor memory device 10 according to the present invention.

Step S70:
The R / W control circuit 50 receives “address data DA” indicating the address of the memory cell to be accessed from the I / O buffer 30 and outputs the address data DA to the X decoder 61 and the Y decoder 62. As a result, a predetermined word line WL and bit line DL are selected, and the “memory cell group” and “shift value storage memory cell 26” to be accessed are selected.

  Thereafter, the R / W control circuit 50 reads “read data DR” from the selected memory cell group via the Y selector 63, and “shift value SFT” from the shift value storage memory cell 26 (shift value storage area). Is read. Here, data is read by comparing the threshold voltage Vth of the memory cell with the read reference voltages Vref1 to Vref3 shown in FIG. As shown in FIG. 2, these read reference voltages Vref1 to Vref3 are set so as to be located in the margin between distributions. The read data DR and the shift value SFT that have been read are output from the R / W control circuit 50 to the read data conversion circuit 120 of the data processing circuit 100.

Step S80:
The read data conversion circuit 120 of the data processing circuit 100 receives the read data DR and the shift value SFT. The read data conversion circuit 120 may receive the shift value SFT from the shift value determination circuit 130. Then, the read data conversion circuit 120 converts the read data DR into “multi-value read data DR _M ” in accordance with the correspondence relationship indicated by the shift value SFT (see FIG. 3). For example, when the read data DR is “11, 11, 11, 01” and the shift value SFT is “3”, the read data conversion circuit 120 reads the read data “11, 11” according to the conversion pattern shown in FIG. , 11, 01 ”are converted into multi-value read data“ 10, 10, 10, 00 ”. That is, the read data conversion circuit 120, the read data DR is restored to the multi-level read data DR _M corresponding to multi-value write data DW _M. The multi-level read data DR _M is output to the binary conversion unit 42.

Step S90:
Binary converter 42 converts the multi-level read data DR _M, which is the binary data "binary read data DR _B". For example, the multi-value data “10, 10, 10, 00” is converted into binary data “1, 0, 1, 0, 1, 0, 0, 0”. The binary read data DR _B generated in this way is output to the I / O buffer 30.

Step S100:
The binary read data DR _B is output from the I / O buffer 30 to the outside as “output data Dout”. This output data Dout corresponds to the input data Din.

  Next, effects of the nonvolatile semiconductor memory device 10 according to the present invention described above will be described with reference to FIGS. 9A to 9D.

  Assume that “1, 0, 1, 0, 1, 0, 0, 0” is input to the I / O buffer 30 as the input data Din. When the shift value SFT is “0”, “10, 10, 10, 00” is generated as the write data DW as shown in FIG. 9A (see FIG. 3). At this time, electrons are injected into each of the four designated memory cells 21 such that the threshold voltages are Vtm1, Vtm1, Vtm1, and Vtm3, respectively.

  FIG. 10 shows an example of the “predetermined constant” associated with each of the threshold voltages Vtm3, Vtm2, Vtm1, and Vtm0. These “predetermined constants” indicate values corresponding to the writing time. In FIG. 10, the constants corresponding to the threshold voltages Vtm3, Vtm2, Vtm1, and Vtm0 are represented by “3”, “2”, “1”, and “0”, respectively. At this time, in the above example, the write time for each of the four memory cells 21 is “1”, “1”, “1”, “3”, and the total write time Tall is given by “6”.

  When the shift value SFT is “1”, “01, 01, 01, 11” is generated as the write data DW as shown in FIG. 9B (see FIG. 3). At this time, electrons are injected into each of the four designated memory cells 21 such that the threshold voltages are Vtm2, Vtm2, Vtm2, and Vtm0, respectively. At this time, the write time for each of the four memory cells 21 is “2”, “2”, “2”, “0”, and the total write time Tall is given by “6”.

  When the shift value SFT is “2”, “00, 00, 00, 10” is generated as the write data DW as shown in FIG. 9C (see FIG. 3). At this time, electrons are injected into each of the four designated memory cells 21 such that the threshold voltages are Vtm3, Vtm3, Vtm3, and Vtm1, respectively. At this time, the write time for each of the four memory cells 21 is “3”, “3”, “3”, “1”, and the total write time Tall is given by “10”.

  When the shift value SFT is “3”, “11, 11, 11, 01” is generated as the write data DW as shown in FIG. 9D (see FIG. 3). At this time, electrons are injected into each of the four designated memory cells 21 such that the threshold voltages are Vtm0, Vtm0, Vtm0, and Vtm2, respectively. At this time, the write time for each of the four memory cells 21 is “0”, “0”, “0”, “2”, and the total write time Tall is given by “2”.

  As described above, the shift value determination circuit 130 (determination circuit 202) is configured so that the sum of constants corresponding to the threshold voltage Vth of the memory cell group to be written is minimized, that is, the total write time Tall is minimized. The shift value SFT is selected so that That is, according to the nonvolatile semiconductor memory device 10 of the present invention, “3” is selected as the shift value SFT. At this time, the total write time Tall is given by “2”.

  For comparison, consider the operation of the prior art. According to the techniques disclosed in Patent Document 1 and Patent Document 2, input data is “normally rotated” or “inverted” and then written into a memory cell group. “Forward” corresponds to the case where the shift value SFT shown in FIG. 9A is “0”. At this time, the total write time Tall is given by “6”. On the other hand, the case of “inversion” corresponds to the case where the shift value SFT shown in FIG. 9B is “1”. At this time, the total write time Tall is given by “6”.

  As described above, according to the nonvolatile semiconductor memory device 10 and the data read / write method according to the present invention, the data write time is reduced. Therefore, the operation speed of the nonvolatile semiconductor memory device 10 is improved.

  Next, the configuration and operation of the shift value determination circuit 130 according to the present invention and the method for determining the shift value SFT will be described in more detail.

(First embodiment)
FIG. 11 is a block diagram showing in detail the configuration of the shift value determination circuit 130 according to the first embodiment of the present invention. The shift value determination circuit 130 includes a shift value generation circuit 131, a verification data generation circuit 132, a counter 133, a multiplier 134, an adder 135, a calculation value register 136, a comparator 137, a reference value register 138, and a result storage circuit 139. It has. The shift value generation circuit 131 is a circuit that sequentially generates and outputs a plurality of temporary shift values SFT ′ (0 to 3). The reference value register 138 stores “reference value Tref”. Here, the reference value Tref indicates a writing time and is a rewritable amount.

  The shift value generation circuit 131 is connected to the verification data generation circuit 132 and the result storage circuit 139. The counter 133 is connected to the verification data generation circuit 132. The multiplier 134 is connected to the counter 133. The adder 135 is connected to the multiplier 134. The calculated value register 136 is connected to the adder 135. The comparator 137 is connected to the calculated value register 136, the reference value register 138, and the result storage circuit 139.

  FIG. 12 is a flowchart showing the operation of the shift value determining circuit 130.

Step S31:
After step S20 shown in FIG. 7, the shift value determining circuit 130 is initialized. Specifically, the temporary shift value SFT ′ output from the shift value generation circuit 131 is set to “0”. Further, the reference value Tref stored in the reference value register 138 is set to the maximum value by the reset signal RES. Here, the maximum value indicates the maximum time among the writing times.

Step S32:
First, the shift value generation circuit 131 outputs “0” as the temporary shift value SFT ′ to the verification data generation circuit 132 and the result storage circuit 139. Verification data generation circuit 132, as described above, by using the temporary shift value SFT ', generates verification data DT from the multi-value write data DW _M. The verification data DT is output from the verification data generation circuit 132 to the counter 133.

  The counter 133 counts the number of each of the plurality of write data values (00, 01, 10, 11) included in the verification data DT. For example, when the verification data DT is “10, 10, 10, 00”, the numbers j, k, l, and m (see FIG. 2) of the write data values 00, 01, 10, 11 are 1 and 0, respectively. Pieces, three pieces, and zero pieces are obtained. The counter 133 outputs a count signal SC indicating the obtained number to the multiplier 134.

  Multiplier 134 multiplies each of the number of data values indicated by count signal SC by a predetermined constant. This predetermined constant is, for example, the writing time associated with each of the plurality of threshold voltages shown in FIG. That is, the number “j” of the write data values 00 corresponding to the threshold voltage Vtm3 is multiplied by a constant “3”. The number k of write data values 01 corresponding to the threshold voltage Vtm2 is multiplied by a constant “2”. The number l of the write data values 10 corresponding to the threshold voltage Vtm1 is multiplied by a constant “1”. The number m of write data values 11 corresponding to the threshold voltage Vtm0 is multiplied by a constant “0”. Thereby, a plurality of multiplication values (3 × j), (2 × k), (1 × l), and (0 × m) are calculated.

  The adder 135 adds a plurality of multiplication values calculated by the multiplier 134. Thereby, the total writing time Tall is calculated. This total writing time Tall is given by Tall = (3 × j) + (2 × k) + (1 × l) + (0 × m). The adder 135 outputs a write time signal ST indicating the calculated total write time Tall to the calculated value register 136. As described above, the combination of the counter 133, the multiplier 134, and the adder 135 corresponds to the write time calculation circuit 201 shown in FIG.

Step S33:
The calculated value register 136 stores the time indicated by the write time signal ST as a calculated value Tcalc. The reference value register 138 stores a reference value Tref. As described above, the initial value of the reference value Tref is the maximum value. When activated by the control signal CNT, the comparator 137 performs a comparison between the calculated value Tcalc and the reference value Tref.

  When the calculated value Tcalc is smaller than the reference value Tref (step S34; Yes), the comparator 137 outputs the shift value setting signal SS to the result storage circuit 139. The result storage circuit 139 is a circuit for storing the shift value SFT determined by the shift value determination circuit 130. When receiving the shift value setting signal SS, the result storage circuit 139 reads the temporary shift value SFT 'at that time, and updates the shift value SFT with the temporary shift value SFT' (step S35). The comparator 137 outputs the calculated value Tcalc at that time to the reference value register 138 as a new reference value Tref. Thereby, the reference value stored in the reference value register 138 is updated (step S36). The calculated value register 146, the comparator 147, the reference value register 148, and the result storage circuit 149 function as the determination circuit 202 shown in FIG.

  When the calculated value Tcalc is larger than the reference value Tref (step S34; No), step S35 and step S36 are not executed. Next, the shift value generation circuit 131 outputs the next temporary shift value SFT '(step S37). Specifically, the shift value generation circuit 131 adds 1 to the temporary shift value SFT ′ and outputs the result. In this way, the shift value generation circuit 131 sequentially outputs “0”, “1”, “2”, “3” as the temporary shift value SFT ′. Then, the same processing as described above is executed for each temporary shift value SFT '.

Step S38:
When the verification of the total write time Tall for all the temporary shift values SFT ′ is completed, the result storage circuit 139 stores the shift value SFT related to the shortest total write time Tall. In this way, one shift value SFT is determined. Thereafter, the shift value SFT stored in the result storage circuit 139 is taken in by the write data conversion circuit 110, and step S40 shown in FIG. 7 is executed.

  Thus, according to the shift value determining circuit 130 according to the present embodiment, the shift value SFT is selected so that the sum of constants corresponding to the threshold voltage Vth of the memory cell group to which writing is performed is minimized. The Therefore, according to the nonvolatile semiconductor memory device 10 and the data read / write method according to the present invention, the data write time is reduced.

(Second embodiment)
FIG. 13 is a block diagram showing in detail the configuration of the shift value determination circuit 130 according to the second embodiment of the present invention. The shift value determination circuit 130 includes a shift value generation circuit 141, a verification data generation circuit 142, a counter 143, a multiplier 144, an adder 145, a calculation value register 146, a comparator 147, a reference value register 148, and a result storage circuit 149. It has.

  The shift value generation circuit 141 is connected to the verification data generation circuit 142, the counter 143, and the result storage circuit 149. The counter 143 is connected to the verification data generation circuit 142. The multiplier 144 is connected to the counter 143. The adder 145 is connected to the multiplier 144. The calculated value register 146 is connected to the adder 145. The comparator 147 is connected to the calculated value register 146, the reference value register 148, and the result storage circuit 149.

  As in the first embodiment, first, the shift value determining circuit 130 is initialized (step S31). Specifically, the temporary shift value SFT ′ output from the shift value generation circuit 141 is set to “0”. Further, the reference value Tref stored in the reference value register 148 is set to the maximum value by the reset signal RES. Here, the maximum value indicates the maximum time among the writing times.

First, the shift value generation circuit 141 outputs “0” as the temporary shift value SFT ′ to the counter 143 together with the verification data generation circuit 142 and the result storage circuit 149. Verification data generation circuit 142, as described above, by using the temporary shift value SFT ', generates verification data DT from the multi-value write data DW _M. The counter 143 counts the number of data values indicated by the temporary shift value SFT ′ in addition to the number of data values (00, 01, 10, 11) included in the verification data DT. For example, when the temporary shift value SFT ′ is “0”, 1 is further added to the number m of data values 11, and when the temporary shift value SFT ′ is “3”, 1 is further added to the number j of data values 00. Is done. The counter 143 outputs a count signal SC indicating the obtained number to the multiplier 144.

  The multiplier 144 multiplies each of the number of data values indicated by the count signal SC by a predetermined constant shown in FIG. Thereby, a plurality of multiplication values (3 × j), (2 × k), (1 × l), and (0 × m) are calculated. The adder 145 adds the plurality of multiplication values calculated by the multiplier 144. Thereby, the total writing time Tall is calculated (step S32). This total writing time Tall is given by Tall = (3 × j) + (2 × k) + (1 × l) + (0 × m). The adder 145 outputs a write time signal ST indicating the calculated total write time Tall to the calculated value register 146. As described above, the combination of the counter 143, the multiplier 144, and the adder 145 corresponds to the write time calculation circuit 201 shown in FIG.

  The calculated value register 146 stores the time indicated by the write time signal ST as a calculated value Tcalc. The reference value register 148 stores a reference value Tref. When activated by the control signal CNT, the comparator 147 performs a comparison between the calculated value Tcalc and the reference value Tref (step S33). When the calculated value Tcalc is smaller than the reference value Tref (step S34; Yes), the shift value SFT stored in the result storage circuit 149 is updated with the temporary shift value SFT 'at that time (step S35). Further, the reference value stored in the reference value register 148 is updated with the calculated value Tcalc at that time (step S36).

  When the calculated value Tcalc is larger than the reference value Tref (step S34; No), step S35 and step S36 are not executed. Next, the shift value generation circuit 141 outputs the next temporary shift value SFT '(step S37). Specifically, the shift value generation circuit 141 adds 1 to the temporary shift value SFT ′ and outputs the result. In this way, the shift value generation circuit 141 sequentially outputs “0”, “1”, “2”, and “3” as the temporary shift value SFT ′. Then, the same processing as described above is executed for each temporary shift value SFT '.

  When the verification of the total write time Tall for all the temporary shift values SFT 'is completed (step S38; Yes), the result storage circuit 149 stores the shift value SFT related to the shortest total write time Tall. In this way, one shift value SFT is determined. Thereafter, the shift value SFT stored in the result storage circuit 149 is taken in by the write data conversion circuit 110, and step S40 shown in FIG. 7 is executed.

  According to the present embodiment, the shift value SFT written in the shift value storage memory cell 26 as well as the write data DW written in the memory cell group is taken into consideration in the calculation of the total write time Tall. Therefore, the effect that the total writing time Tall is calculated more accurately can be obtained.

(Third embodiment)
FIG. 14 is a block diagram showing in detail the configuration of the shift value determination circuit 130 according to the third embodiment of the present invention. The shift value determination circuit 130 includes a shift value generation circuit 151, a plurality of verification data generation circuits 152, a multiplier 154, an adder 155, a calculation value register 156, a comparator 157, a reference value register 158, and a result storage circuit 159. I have.

  The shift value generation circuit 151 is connected to a plurality of verification data generation circuits 152, a multiplier 154, and a result storage circuit 159. The multiplier 154 is connected to a plurality of verification data generation circuits 152. The adder 155 is connected to the multiplier 154. The calculated value register 156 is connected to the adder 155. The comparator 157 is connected to the calculated value register 156, the reference value register 158, and the result storage circuit 159.

  As in the first embodiment, first, the shift value determining circuit 130 is initialized (step S31). Specifically, the temporary shift value SFT ′ output from the shift value generation circuit 151 is set to “0”. Also, the reference value Tref stored in the reference value register 158 is set to the maximum value by the reset signal RES. Here, the maximum value indicates the maximum time among the writing times.

The shift value generation circuit 151 first outputs “0” as the temporary shift value SFT ′ to the plurality of verification data generation circuits 152, the multiplier 154, and the result storage circuit 159. A plurality of verification data generation circuit 152, 1 data stored multi-level write data DW _M in one memory cell ( "00", "01", "10", "11") receives in parallel for each. Each verification data generation circuit 152 generates verification data DT from the received data by using the temporary shift value SFT ′. Each of the plurality of verification data generation circuits 152 outputs each of the plurality of verification data DT to the multiplier 154.

  The multiplier 154 receives the plurality of verification data DT and the temporary shift value SFT ′ in parallel. Then, the multiplier 154 multiplies the number (one) by the predetermined constant shown in FIG. 10 according to the data values indicated by the plurality of verification data DT and the temporary shift value SFT ′. Thereby, a plurality of multiplication values are calculated. The adder 155 adds a plurality of multiplication values calculated by the multiplier 154. Thereby, the total writing time Tall is calculated (step S32). The adder 155 outputs a write time signal ST indicating the calculated total write time Tall to the calculated value register 156.

  The calculated value register 156 stores the time indicated by the write time signal ST as a calculated value Tcalc. The reference value register 158 stores a reference value Tref. When activated by the control signal CNT, the comparator 157 performs a comparison between the calculated value Tcalc and the reference value Tref (step S33). When the calculated value Tcalc is smaller than the reference value Tref (step S34; Yes), the shift value SFT stored in the result storage circuit 159 is updated with the temporary shift value SFT 'at that time (step S35). Further, the reference value stored in the reference value register 158 is updated with the calculated value Tcalc at that time (step S36).

  When the calculated value Tcalc is larger than the reference value Tref (step S34; No), step S35 and step S36 are not executed. Next, the shift value generation circuit 151 outputs the next temporary shift value SFT '(step S37). Specifically, the shift value generation circuit 151 adds 1 to the temporary shift value SFT ′ and outputs the result. In this way, the shift value generation circuit 151 sequentially outputs “0”, “1”, “2”, and “3” as the temporary shift value SFT ′. Then, the same processing as described above is executed for each temporary shift value SFT '.

  When the verification of the total write time Tall for all the temporary shift values SFT 'is completed (step S38; Yes), the result storage circuit 159 stores the shift value SFT related to the shortest total write time Tall. In this way, one shift value SFT is determined. Thereafter, the shift value SFT stored in the result storage circuit 159 is taken in by the write data conversion circuit 110, and step S40 shown in FIG. 7 is executed.

According to the present embodiment, multi-value write data DW _M , a plurality of verification data DT, and a plurality of multiplication values are input / output in parallel. Therefore, the calculation time of the total writing time Tall is reduced. Therefore, the effect that the data writing time is further reduced can be obtained.

(Fourth embodiment)
Data stored in the memory cell is not limited to quaternary data (2-bit data). FIG. 15 shows another example of the distribution of the threshold voltage Vth in the nonvolatile semiconductor memory device according to the present invention. In FIG. 15, the vertical axis represents the threshold voltage Vth of the memory cell, and the horizontal axis represents the number of memory cells (distribution frequency). According to this nonvolatile semiconductor memory device, for example, 8-level (3-bit) data can be stored in one memory cell, and as shown in FIG. 15, the distribution of threshold voltage Vth of the entire memory cell Has eight distributions B0 to B7. Here, the threshold voltage Vth representing each of the distributions B0 to B7 is defined as threshold voltages Vtm0 to Vtm7. The number of memory cells 21 included in each of the distributions B0 to B7 is assumed to be q to j.

  The data writing time for the memory cell depends on the threshold voltage Vth after writing. When the potential applied to the memory cell transistor and the time during which the potential is applied are constant, the higher the threshold voltage Vth after writing, the longer the time required for electron injection, that is, the writing time. Conversely, the lower the threshold voltage Vth after writing, the shorter the writing time. In the example shown in FIG. 15, the threshold voltage Vtm7 is the highest and the writing time is the longest. On the other hand, the threshold voltage Vtm0 is the lowest and the writing time is the shortest. FIG. 16 shows predetermined constants corresponding to the threshold voltages Vtm7 to Vtm0. As shown in FIG. 16, it is assumed that the predetermined constants corresponding to the threshold voltages Vtm7 to Vtm0 are represented by “7” to “0”, respectively, using predetermined units.

  At this time, the total write time Tall for the selected memory cell group is Tall = (7 × j) + (6 × k) + (5 × l) + (4 × m) + (3 × n) + (2 Xo) + (1 * p) + (0 * q). Similar to the above-described embodiment, the shift value determination circuit 130 of the data processing circuit 100 is configured so that the total write time Tall is minimized, that is, the sum of the threshold voltages Vth of the memory cell group is minimized. Then, one shift value SFT is selected from the plurality of shift values SFT.

  More generally, in the case of N-value data (N is a natural number of 3 or more), the N-value data includes first to Nth data values. The memory cell has N-stage threshold voltages (first to Nth threshold voltages). In this case, a maximum of N! There may be different types of shift values SFT. N types of shift values SFT (first to Nth shift values) are preferably used to store the shift value SFT itself in a memory cell similar to a memory cell in which N-value data is stored. The N types of shift values SFT indicate N types of corresponding relationships. For example, the first shift value associates each of the first to Nth data values with each of the first to Nth threshold voltages. The i-th shift value (i is a natural number greater than or equal to 2 and less than or equal to N) associates each of the first to (i−1) data values with each of the (N−i + 2) to Nth threshold voltages, and Each of the i-th to N-th data values is associated with each of the first to (N−i + 1) th threshold voltages (see FIG. 3). In this case, every time the shift value SFT changes, the threshold voltage (write data) shifts.

  As described above, according to the nonvolatile semiconductor memory device 10 and the data read / write method according to the present invention, the data write time is reduced. Therefore, the operation speed of the nonvolatile semiconductor memory device 10 is improved.

FIG. 1 is a diagram showing a threshold voltage distribution of memory cells in a multi-value type nonvolatile semiconductor memory device. FIG. 2 is a diagram showing an example of threshold voltage distribution in the nonvolatile semiconductor memory device according to the present invention. FIG. 3 is a diagram for explaining the shift value in the present invention. FIG. 4 is a block diagram showing a configuration of the nonvolatile semiconductor memory device according to the present invention. FIG. 5 is a circuit diagram showing the configuration of the memory cell array of the nonvolatile semiconductor memory device according to the present invention. FIG. 6 is a block diagram showing the configuration of the shift value determination circuit of the nonvolatile semiconductor memory device according to the present invention. FIG. 7 is a flowchart showing a write operation in the nonvolatile semiconductor memory device according to the present invention. FIG. 8 is a flowchart showing a read operation in the nonvolatile semiconductor memory device according to the present invention. FIG. 9A is a diagram for explaining the effect of the nonvolatile semiconductor memory device according to the present invention. FIG. 9B is a diagram for explaining the effect of the nonvolatile semiconductor memory device according to the present invention. FIG. 9C is a diagram for explaining the effect of the nonvolatile semiconductor memory device according to the present invention. FIG. 9D is a diagram for explaining the effect of the nonvolatile semiconductor memory device according to the present invention. FIG. 10 is a diagram for explaining the effect of the nonvolatile semiconductor memory device according to the present invention. FIG. 11 is a block diagram showing the configuration of the shift value determining circuit according to the first embodiment of the present invention. FIG. 12 is a flowchart showing a write operation in the nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 13 is a block diagram showing a configuration of a shift value determining circuit according to the second embodiment of the present invention. FIG. 14 is a block diagram showing a configuration of a shift value determining circuit according to the third embodiment of the present invention. FIG. 15 is a diagram for explaining a write operation in the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention. FIG. 16 is a diagram for explaining a write operation in the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Nonvolatile semiconductor memory device 20 Memory cell array 21 Memory cell 25 Shift value storage memory cell group 26 Shift value storage memory cell 30 I / O buffer 41 Multi-value conversion part 42 Binary conversion part 50 R / W control circuit 61 X decoder 62 Y decoder 63 Y selector 100 Data processing circuit 110 Write data conversion circuit 120 Read data conversion circuit 130 Shift value determination circuit 131, 141, 151 Shift value generation circuit 132, 142, 152 Verification data generation circuit 133, 143 Counter 134, 144, 154 Multiplier 135, 145, 155 Adder 136, 146, 156 Calculated value register 137, 147, 157 Comparator 138, 148, 158 Reference value register 139, 149, 159 Result storage circuit 201 Write time calculation times 202 decision circuit

Claims (5)

A memory cell to which multi-value data is written;
A data processing circuit that executes conversion processing for converting first multi-value write data received as write data to the memory cell into second multi-value write data that is actually written to the memory cell;
With
The threshold voltage of the memory cell after writing depends on the second multi-level write data,
The higher the threshold voltage after writing, the longer the write time of the second multi-value write data to the memory cell,
In the conversion process, the data processing circuit selects a conversion pattern between the first multi-value write data and the second multi-value write data from a plurality of conversion patterns,
When writing data to a plurality of memory cells, the data processing circuit selects one of the plurality of conversion patterns so that the sum of the write times to the plurality of memory cells is minimized, and the selected The conversion process is executed according to a single conversion pattern
Nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
The plurality of conversion patterns are associated with each of a plurality of shift values,
At the time of writing data to the plurality of memory cells, the data processing circuit selects one of the plurality of shift values so that the sum of the writing times to the plurality of memory cells is minimized, and the selected one is selected. The conversion process is executed using a single shift value.
Nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 2,
The plurality of shift values are represented by multi-value data having the same number of bits as the first multi-value write data and the second multi-value write data.
The plurality of memory cells to be written also include shift value storage memory cells to which the multi-value data indicating the selected one shift value is written.
Nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 2, wherein
The multi-value data includes first to Nth data values (N is a natural number of 3 or more),
The plurality of shift values include first to Nth shift values,
The conversion pattern between the first multi-value write data and the second multi-value write data has N types associated with the first to N-th shift values.
Nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
The data processing circuit includes:
A plurality of write times corresponding to each of the plurality of conversion patterns, the total of the write times for the plurality of memory cells when the conversion process is executed according to each of the plurality of conversion patterns; A write time calculation circuit for generating a write time signal of
A determination circuit that selects, based on the plurality of write time signals, the one conversion pattern that minimizes the sum of the write times from the plurality of conversion patterns;
With
Nonvolatile semiconductor memory device.

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