JP2009146555A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten automatic writing operation time as much as possible. <P>SOLUTION: The nonvolatile semiconductor storage device includes a memory cell array 4 having a plurality of nonvolatile memory cells, an address search circuit 35 which searches for write object data and outputs an address where the write object data are present, when writing data in the nonvolatile memory cells, and a control circuit 20 which exercises control to write the write object data into the nonvolatile memory cells in accordance with the address output from the address search circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  In general, in a nonvolatile semiconductor memory device represented by a flash memory, an automatic word write operation capable of writing to a memory cell in units of words and an automatic page write enabling a plurality of words to be written to shorten the write time. There is an operation (for example, see Patent Document 1).

  In recent years, with the increase in capacity of nonvolatile semiconductor memory devices, the number of words that can be written by one automatic page write operation has been changed from the conventional 8 words, 16 words, 32 words to 256 words, 512 words, The entire writing time is shortened.

In an automatic page write operation of a conventional nonvolatile semiconductor memory device, for example, an 8-word automatic page write operation, first, four pages of data decoded by a page address are output from the data buffer and written. When the write time for the first page ends, the address generation circuit increments the address by +4, moves the page address to the data area for the next four pages, reads the next write data from the data buffer, and performs the same write operation I do.
JP 2006-172681 A

  The present invention provides a nonvolatile semiconductor memory device capable of reducing the automatic write operation time as much as possible.

  According to one embodiment of the present invention, a nonvolatile semiconductor memory device includes a memory cell array having a plurality of nonvolatile memory cells, and searches for data to be written when writing data to the plurality of nonvolatile memory cells. An address search circuit that outputs an address in which the data exists, and a control circuit that controls to write the data to be written to the memory cell according to the address output from the address search circuit. To do.

  According to the present invention, the automatic write operation time can be shortened as much as possible.

  Conventionally, in the automatic page write operation, when there is no write data, that is, when there is no write data and no write is performed, the same write time as when there is write data is passed, and then the address is set to +4 Only increase. After all the pages have been written, the address is returned to the top address where the page is written, and the verify operation is started. Also in this verify operation, an address increment operation occurs every time regardless of the presence or absence of write data.

  If the number of pages is small, even if all page address increments are inserted regardless of whether there is write data, the total write operation time will not be affected so much, but if the number of pages increases, it can be ignored. There is a problem that the total write operation time becomes longer.

  Also in the conventional automatic erase operation mode, for example, in the erase verify operation, over-erase verify operation, and over-erase cell rewrite operation, the page address increase operation occurs every time regardless of the presence or absence of the target bit. . For this reason, there has been a problem that the total erase operation time becomes long.

  In response to the above-mentioned problems found by the applicant, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
A nonvolatile semiconductor memory device according to a first embodiment of the present invention is shown in FIG. The nonvolatile semiconductor memory device of this embodiment includes a plurality of memory blocks 2, a read sense amplifier circuit 12, an automatic operation sense amplifier circuit 14, an automatic operation control system 20, a data control system 30, and a CE terminal. 101, a WE terminal 102, an address input terminal 103, and a data input / output terminal 104 capable of inputting / outputting 16-bit data at the same time.

  Each of the memory blocks 2 is provided with a memory cell array 4 and a memory decoder 6 provided around the memory cell array 4. The memory decoder 6 is, for example, a row decoder or a column decoder. The memory cell array 4 has a plurality of memory cells arranged in a matrix, for example, capable of storing quaternary data.

  In the present embodiment, the nonvolatile semiconductor memory device is a NOR flash memory, and each memory cell includes a source region and a drain region formed on a semiconductor substrate so as to be separated from each other, and the source region and the drain region. A tunnel insulating film formed on the region of the semiconductor substrate serving as a channel between the floating insulating film, a floating gate formed on the tunnel insulating film, an interelectrode insulating film formed on the floating gate, and the electrode And a control gate formed on the intermediate insulating film.

  By applying a high positive voltage to the control gate and the drain region and setting the source region and the semiconductor substrate to the ground potential, electrons are injected from the semiconductor substrate through the tunnel insulating film into the floating gate and accumulated. The threshold value of the memory cell changes. In the present embodiment, quaternary data is represented as data (11), (10), (00), and (01) in order from the lowest threshold value. That is, the data (11) represents a state where electrons are not accumulated in the floating gate (erased state).

  The automatic operation control system 20 includes a command determination circuit 22, an address generation circuit 24, and an automatic operation control circuit 26.

  The data control system 30 includes a first data buffer 31 that can hold 256 pages of data, a data conversion circuit 32, a data input selection circuit 33, a data holding circuit and data that can hold 256 pages of data. A second data buffer 34 including a determination circuit, an automatic address search circuit 35 (hereinafter also referred to as AAS circuit 35) for automatically searching for and outputting an address where write data exists, an address selection circuit 36, and write data multi-value compression A circuit 37, a verify data control circuit 38, and a verify data output decoding circuit 39 are provided.

Automatic Write Operation Next, the configuration and operation of the nonvolatile semiconductor memory device of this embodiment will be described by taking an automatic page write operation as an example. As an example of this automatic page write operation, a control sequence for writing data (10) and its verification, subsequently writing data (00) and its verification, and finally writing and verifying data (01) will be described.

  First, a chip enable signal is input from the CE terminal 101 to start the nonvolatile semiconductor memory device. It is assumed that each memory cell in the region of the memory cell array 4 where the automatic page write operation is performed is in an erased state (data (11)) before the automatic page write operation is performed.

  Next, an automatic page write command is input from the address terminal 103 and the data input / output terminal 104. Then, the command determination circuit 22 recognizes the automatic page write operation and outputs a command interrupt signal for notifying the automatic operation control circuit 26 of the start of control of the automatic page write operation.

  Subsequently, a write address and write data are input from the address terminal 103 and the data input / output terminal 104. Then, the address generation circuit 24 latches the head address of the write address according to the address control signal input from the automatic operation control circuit 26, and sets the column address A for storing the write data to the first address of the data control system 30. 1 output to the data buffer 31.

  The write data is sent and latched to the area of the first data buffer 31 indicated by the column address A via the input data bus by the pulse of the latch clock CLKA generated by the command determination circuit 22 for every command input. The column address A is automatically incremented every data latch.

  When the write data for all pages is stored in the first data buffer 31, the address generation circuit 24 indicates the block address, row address, and head page address to be page-written as column address A. The first data buffer 31 stores 256 pages of data Page0 to Page255, each page having 16 bits.

  In order to retrieve the data (10) to be written from the write data stored in the first data buffer 31, the stored write data is converted by the data conversion circuit 32. The data converted by the data conversion circuit 32 is stored in the holding circuit of the second data buffer 34 via the data input selection circuit 33. This data conversion is performed as follows.

  First, since the data to be written (data to be written) is data (10), the data pattern selection signal [1: 0] sent from the automatic operation control circuit 26 to the data conversion circuit 32 is “10”. . When the data to be written is data (00) and data (01), as shown in FIG. 2, the data pattern selection signals [1: 0] are “00” and “01”, respectively. When the data pattern selection signal [1: 0] is “11”, this is a case of state multi-write described later.

  On the other hand, a data group of 16 pages (256 bits) is sent from the first data buffer 31 through the data bus in one transfer, and this transfer is performed 16 times. That is, after the data groups Page0 to Page15 are sent, the data groups Page16 to Page31 are sent. After the data transfer is performed 15 times, the data groups Page 240 to Page 255 are finally sent to the data conversion circuit 32.

  Of the data group sent from the first buffer circuit 31 by one transfer, the data group for the first eight pages is the upper bit data group, and the data group for the second eight pages is the lower bit data group. For example, if the data group sent in one transfer is Page0 to Page15, the upper bit data group is the data group Page0 to Page7, and the lower bit data group is the data group Page8 to Page15.

  For example, a set of data having the same order in the upper bit data group Page0 to Page7 and the lower bit data group Page8 to Page15, for example, a set of data Page0 and DataPage8, sent in one transfer is expressed as “multi-value compression”. Called “Pair”. Therefore, the set of data Page 1 and data Page 9 is also a multi-value compression pair, and the set of data Page 2 and data Page 10 is also a multi-value compression pair.

  A set of the data Page 241 and the data Page 249 is also a multi-value compression pair, and a set of the data Page 248 and the data Page 255 is also a multi-value compression pair. Data included in the upper bit data group in the multi-value compression pair is referred to as upper bit data, and data included in the lower bit data group is referred to as lower bit data.

  Since this multi-value compression pair, for example, data Page 0 and Page 8 is 16-bit data, respectively, as shown in FIG. 3, 16 binary bits IO <0>, IO <1>,. It is assumed that it is composed of IO <15>. Here, each IO <i> (i = 0,..., 15) represents a binary bit input from the i-th input / output terminal 104.

  In the multi-value compression pair, binary bits input from the same input / output terminal of the upper bit data and the lower bit data are respectively converted into upper bits (hereinafter also referred to as UB) and lower bits (hereinafter also referred to as LB). These bits are called “multi-value compression bit pairs”.

  In the data conversion circuit 32, when the data pattern selection signal is “00” or “10”, as shown in FIG. 4A, the multi-value of the multi-value compression pair in the data group input to the data conversion circuit 32 The upper bits and lower bits constituting the compressed bit pair are output by changing the bit values of the upper bit data and lower bit data of the multi-value compression bit pair output by the combination.

  For example, when the upper bit UB of the input multi-value compression bit pair is “0” and the lower bit LB is “0”, the upper bit UB of the output multi-value compression bit pair is not changed, but “0”, the lower bit LB Is replaced with “1”. When the upper bit UB of the input multi-value compression bit pair is “0” and the lower bit LB is “1”, the upper bit UB of the output multi-value compression bit pair is changed to “1”, and the lower bit LB is not changed. “1”.

  When the upper bit UB of the input multi-value compression bit pair is “1” and the lower bit LB is “0”, the upper bit UB and the lower bit LB of the output multi-value compression bit pair are not changed. Even when the upper bit UB of the input multi-value compression bit pair is “1” and the lower bit LB is “1”, the upper bit UB and the lower bit LB of the output multi-value compression bit pair are not changed.

  That is, when the data pattern selection signal is “00” or “10” (when the data to be written is (00) or (10)), the upper bit UB and the lower bit LB of the input multi-value compression bit pair are respectively When “0” and “0”, only the lower bit LB of the output multi-value compression bit pair is changed to “1” and output. When the upper bit UB and lower bit LB of the input multi-value compression bit pair are “0” and “1”, respectively, only the upper bit UB of the output multi-value compression bit pair is changed to “1” and output. When the input multi-value compression bit pair is other than that, the upper bit UB and the lower bit LB of the output multi-value compression bit are output without being changed.

  When the data pattern selection signal is “01”, as shown in FIG. 4B, the upper bits UB constituting the multi-value compression bit pair of the multi-value compression pair of the data group input to the data conversion circuit 32 are displayed. And the lower bit LB change the bit value of the upper bit data and the lower bit data of the multi-value compression bit pair output by the combination and output.

  That is, when the data pattern selection signal is “01” (when the data to be written is (01)), the upper bit UB and the lower bit LB of the input multi-value compression bit pair are “0” and “1”, respectively. Alternatively, when “1” and “1”, respectively, the upper bit UB and the lower bit LB of the output multi-value compression bit are output without being changed. When the upper bit UB and lower bit LB of the input multi-value compression bit pair are “0” and “0”, respectively, the upper bit UB and lower bit LB of the output multi-value compression bit pair are changed to “1”. When the upper bit UB and the lower bit LB of the multi-value compression bit pair are “1” and “0”, respectively, the upper bit UB of the output multi-value compression bit pair is not changed, and the lower bit LB is “1”. To output.

  The reason for performing such data conversion is that information on the target bits of data (00) and data (10) is necessary when a state multi-write operation to be described later is realized, and the data determination circuit of the second data buffer 34 This is to simplify the configuration. That is, when the multi-value compression bit pair “00” is output as “00” after conversion, the logic for distinguishing the data (10) and the data (00) in the data determination circuit increases.

  The data converted in this way is transferred to the second data buffer 34 via the data input selection circuit 33. The data input selection circuit 33 changes the data conversion circuit 32 from the first data buffer 31 based on the path selection signal [1: 0] or the signal APRG [1: 0] sent from the automatic operation control circuit 26. One of the data group transferred via the verification data control circuit 38 and the data group transferred from the verify data control circuit 38 is selected, and the selected data group is transferred to the second data buffer 34.

  A group of 16 pages (256 bits) is sent through the data bus in one transfer, and this transfer is performed 16 times. That is, after the data groups Page0 to Page15 converted by the data conversion circuit 32 are sent, the data groups Page16 to Page31 are sent. After this data transfer is performed 15 times, the data groups Page 240 to Page 255 are finally sent from the data conversion circuit 32.

  When the data from the data conversion circuit 32 is latched by the second data buffer 34, the latch address to the second data buffer 34 is the column address at the time of Page 0 to Page 15 via the column address A → column address B (AASEN = 0). The column address A [4: 1] = 0001 when A [4: 1] = 0000, Page 16 to Page 31, and the column address A [4: 1] = 1111 when Page 240 to Page 255 are incremented values. Note that Page 0 to Page 15 are simultaneously latched once, so A [0] is Don't Care.

The configuration of a specific example of the second data buffer 34 is shown in FIG. The second data buffer 34 includes 16 data buffer circuits 340 _{0 to} 340 ₁₅ . Each data buffer circuit 340 _i (i = 0,..., 15) includes 16 data holding circuits 341 _{0 to} 341 ₁₅ and first to fourth data determination circuits 343 ₁ , 343 ₂ , 343 ₃ , 343. ₄ and a determination result output circuit 345. Each data holding circuit 341 _i (i = 0,..., 15) can hold 16-bit data.

Data conversion circuit 32 from the first data group sent by the transfer Page0~Page15 are respectively stored in the data buffer circuit 340 ₀ of the data holding circuit ₃₄₁ 0-341 _15. Data groups Page (16 × (i−1)) to Page (16 × i−1) sent from the data conversion circuit 32 in the i-th (i = 1,..., 16) transfer are data. The data is stored in the data holding circuits 341 _{0 to} 341 ₁₅ of the buffer circuit 340 _i , respectively.

The selection of the data buffer circuit 340 _i (i = 0,..., 15) is performed based on the decode signal RowDECi obtained by decoding the column address B sent from the address selection circuit. Data is stored based on the latch pulse CLKB sent from the automatic operation control circuit 26 and the control signals UBEN1 and LBEN1. As shown in FIG. 5, for example, the column address of the data buffer circuit 340 data hold circuit ₃₄₁ 0 _{0-341 3} and the data holding circuit ₃₄₁ 8-341 data group held in the ₁₁ B is written into the memory cell array The address of the data to be processed is “00000”, and the column address B of the data group held in the data holding circuits 341 _{4 to} 341 ₇ and the data holding circuits 341 _{12 to} 341 ₁₅ is “00001”.

The first data determination circuit 343 ₁ is the data to be written based on the data group held in the data holding circuits 341 _{0 to} 341 ₃ in the data buffer circuit including the first data determination circuit 343 _1. It is determined whether or not (that is, data “0”) exists.

The second data determination circuit 343 ₂ receives data to be written based on the data group held in the data holding circuits 341 _{8 to} 341 ₁₁ in the data buffer circuit including the second data determination circuit 343 _2. Determine if it exists.

The third data determination circuit 343 ₃ receives data to be written based on the data group held in the data holding circuits 341 _{4 to} 341 ₇ in the data buffer circuit including the third data determination circuit 343 _3. Determine if it exists.

The fourth data determination circuit 343 ₄ receives data to be written based on the data group held in the data holding circuits 341 _{12 to} 341 ₁₅ in the data buffer circuit including the fourth data determination circuit 343 _4. Determine if it exists.

  Each data determination circuit determines that there is no data to be written when each bit of the data group to be determined is “1”, and determines that there is data to be written when “0” exists in the bit.

Data buffer circuit _{340 i (i = 0, ···} , 15) the decision result output circuit 345 of the first AND performing an AND operation on the first determination result and the control signal UBEN2 the first data determination circuit 343 ₁ gate and the first determination performed and a second aND gate for performing an aND operation, an oR operation of the outputs of the first and second aND gates and the second data determination circuit 343 of the _second determination result and LBEN2 a first OR gate for outputting a signal HIT (2i), a third aND gate for performing an aND operation on the third data determination circuit 343 of the _third determination result as control signal UBEN2, fourth data determination circuit 343 ₄ of a fourth aND gate for performing an aND operation between the fourth determination result and LBEN2, the third and fourth by performing an oR operation on the output of the aND gate second determination signal HIT (2i And includes a second OR gate for outputting the 1), the.

  FIG. 6 shows the relationship between the values of the control signals UBEN1, LBEN1, UBEN2, and LBEN2 and the operation. In FIG. 6, when the value of the control signal MODEVERIFY is “0”, a write operation or data is transferred from the first data buffer to the second data buffer, and when the value is “1”, a verify operation is performed.

  If the value of the first determination signal, for example, the first determination signal HIT0 is “1”, there is write data in the upper bit data group Page0 to Page3 or the lower bit data group Page8 to Page11, and the value is “0”. This indicates that there is no write data in the upper bit data groups Page0 to Page3 and the lower bit data groups Page8 to Page11. If the value of the second determination signal, for example, the second determination signal HIT1 is “1”, write data exists in the upper bit data groups Page4 to Page7 or the lower bit data groups Page12 to Page15, and the value is “0”. Then, this indicates that there is no write data in the upper bit data groups Page4 to Page7 and the lower bit data groups Page12 to Page15.

  From the second data buffer 34 configured in this manner, determination signals HIT0 to HIT31 indicating whether or not there is data to be written are output and sent to the automatic address search circuit 35 (AAS circuit 35).

  Next, the AAS circuit 35 is shown in FIG. The AAS circuit 35 includes an AAS main circuit 351 and a flip-flop 352. The AAS main circuit 351 outputs an output signal AAS_I based on the first and second determination signals HIT0 to HIT31 sent from the second data buffer 34 and the control signal ADDINCENT sent from the automatic operation control circuit 26. To do. The flip-flop 352 operates based on the control signal ADDINCEN, and outputs the output signal AAS_I of the AAS main circuit 351 to the address selection circuit 36 as an AAS address.

  Next, the operation of the AAS circuit 35 will be described. When the transfer of data from the first data buffer 31 to the second data buffer 34 is completed, the data is determined in the second data buffer, and the values of the first and second determination signals HIT0 to HIT31 are determined. The control signal AADINCEN is sent from the automatic operation control circuit 26 to the AAS circuit 35, and the value of the control signal AASEN sent to the address selection circuit 36 is set to “1”.

  Then, the AAS circuit is operated, and the address selection circuit 36 selects and outputs the AAS address output from the AAS circuit 35 by the address control, thereby writing based on the AAS address output from the AAS circuit (hereinafter referred to as the AAS address). , Also referred to as an AAS write operation).

  FIG. 8 shows a timing chart of the write operation based on the AAS address. In the timing chart shown in FIG. 8, only the determination signals HIT1, HIT3, and HIT31 indicate that there is data to be written.

  At the rising edge of the control signal ADDINCEN, an address corresponding to the determination signals HIT0 to HIT31 (the address corresponding to the determination signal HIT1 is “00001” and the address corresponding to the determination signal HIT3 is “00011”) is output to the AAS address. In this example, first, an address “00001” corresponding to the determination signal HIT1 is output.

  The AAS address is output to the second data buffer 34 and the memory block 2 as the column address B via the address selection circuit 36. For the second data buffer 34, it means an address for outputting write data, and for the memory block 2, it means an address for writing data. The second data buffer 34 outputs UB side (upper bit side) data Page 4 to Page 7 and LB side (lower bit side) data Page 12 to Page 15 corresponding to the determination signal HIT1.

  The output data from the second data buffer 34 is compressed by the write multi-value data compression circuit 37 and sent to the memory block 2 via the PRG data bus. Data (10) is written by outputting a bit whose lower bit LB of the multi-value compression bit pair is 0 as 1 (write target bit) to the PRG data bus.

  That is, the 128-bit data sent from the second data buffer 34 in one transfer is compressed by the multi-value data compression circuit 37 to a half of 64 bits. After the write time elapses, the control signal ADDINCEN is skipped to the next write address at the rising edge.

  For example, in FIG. 8, after data (10) is written in the area of the AAS address corresponding to the determination signal HIT1, the data (10) is skipped to the AAS address corresponding to the determination signal HIT3. ). Thereafter, the process skips to the AAS address corresponding to the determination signal HIT31 and writes data (10) in the area of the ASS address. When sequential writing is performed and the last AAS address in which write data exists is output, the AAS circuit outputs an END signal indicating that the last AAS address is being executed to the automatic operation control circuit 26.

  By receiving the END signal, the automatic operation control circuit 26 generates a control signal AASRST and initializes (resets) the AAS circuit 35 when the write time of the last address has elapsed. According to the control signal AASRST, the youngest address where the value of the determination signals HIT0 to 31 is “1”, that is, the first address 00001 where the write data exists is output to the signal AAS_I, and the verification of the data (10) is performed. Move to mode.

  FIG. 9 shows a waveform diagram when there is no bit (memory cell) to be written.

A specific example of the AAS main circuit 351 that performs the above-described operation is shown in FIG. The AAS main circuit 351 includes an address driver 354 _i (i = 0,..., 31) provided corresponding to 32 column addresses B, and 16 determination signal decoders 356 _i (i = 0,...). 15) and an output driver circuit 358 including 33 output drivers 358 _i (i = 0,..., 32).

The decision signal decoder 356 _i (i = 0,..., 15) sends the first decode signal to the address driver 354 _2i based on the decision signal HIT (2i), the decision signal HIT (2i + 1), and the control signal MODEVERIFY. A first decoder circuit for sending, and a second decode circuit for sending a second decode signal to the address driver 354 _{2i + 1} based on the determination signal HIT (2i + 1) and the control signal MODEVERIFY.

The first decoding circuit of the determination signal decoder 356 _i (i = 0,..., 15) receives the determination signal HIT (2i + 1) and the control signal MODEVERIFY, and performs a NAND operation on the first NAND gate. A first inverter that inverts the output of the gate, a NOR gate that performs NOR operation in response to the output of the first inverter and the determination signal HIT (2i), and a second inverter that inverts the output of the NOR gate; It has become.

The second decoding circuit of the determination signal decoder 356 _i (i = 0,..., 15) has a second NAND gate that performs a NAND operation on the determination signal HIT (2i + 1) and the inverted signal of the control signal MODEVERIFY. And a third inverter for inverting the output of the second NAND gate.

Each address driver 354 _i (i = 0,..., 31) includes one OR gate, one flip-flop, first and second NAND gates, and one NOR gate. Yes. The OR gate of the address driver 354 _i (i = 0,..., 31) performs an OR operation based on the output of the NOR gate and the output of the flip-flop, and sends the operation result to the flip-flop. The flip-flop operates based on the control signal ADDINCEN and is reset based on the reset signal AASRST.

The first NAND gate of the address driver 354 _2i (i = 0,..., 15) is based on the inverted signal of the output of the flip-flop and the output of the first determination signal decoding circuit of the determination signal decoder 356 _i . The NAND operation is performed, and the operation result is sent to one input terminal of each of the two input terminals of the second NAND gate and the NOR gate. Incidentally, "0" is input to the other input terminal of the NOR gate of the address driver 354 _0, the second NAND gate and the other input terminal "1" is input.

Further, a signal obtained by inverting the output of the second NAND gate of the address driver 354 _{2i + 1} is input to the other input terminal of the second NAND gate of the address driver 354 _2i (i = 1,..., 15). The output of the second NAND gate of the address driver 354 _{2i + 1} is input to the other input terminal of the NOR gate.

The first NAND gate of the address driver 354 _{2i + 1} (i = 0,..., 15) has an inverted signal of the output of the flip-flop and the output of the second determination signal decoding circuit of the determination signal decoder 356 _i . The NAND operation is performed based on the above, and the operation result is sent to one input terminal of each of the two input terminals of the second NAND gate and the NOR gate.

Further, a signal obtained by inverting the output of the second NAND gate of the address driver 354 _2i is input to the other input terminal of the second NAND gate of the address driver 354 _{2i + 1} (i = 0,..., 15). The output of the second NAND gate of the address driver _3542i is input to the other input terminal of the NOR gate. A signal obtained by inverting the output of the second NAND gate of the address driver 354 ₃₁ is an END signal.

The output driver 358 _i (i = 0,..., 31) of the output driver circuit 358 is driven based on the output of the NOR gate of the address driver 354 _i and outputs a signal AAS_I that becomes an AAS address corresponding to the determination signal HITi. The output driver 358 ₃₂ is driven based on the END signal and outputs an AAS_I signal whose AAS address is 00000.

  The operation of the AAS main circuit 351 configured as described above is shown in FIGS. FIG. 11 shows a state when write data is latched in the second data buffer 34 (the leftmost block D output is “1”). FIG. 12 shows the next write at the rising edge of the control signal ADDINCEN. FIG. 13 shows an example in which data is skipped to a certain address (third block from the left). FIG. 13 shows the rising edge of the control signal ADDINCEN, and thereafter, there is no address where write data exists, and the end signal END is output. Indicates the state.

  As can be seen from these figures, when one of the address drivers is operating, the other address drivers are in the Off state.

Data (10) Verify Determination Operation Next, the data (10) verify determination operation will be described.

  In the verification of the data (10), in order for the verification determination to be OK, there is no write data, that is, all values of the determination signals HIT0 to HIT31 are “0”, and the value of the END signal is “1”. It is to become. In order for all the values of the determination signals HIT0 to HIT31 to be “0”, all the retained data on the lower bit side (LB side) should be 1 in the second data buffer 34 shown in FIG.

  In the verify determination operation for data (10), first, the AAS circuit 35 is used to read data from the memory cell array 4 using the automatic operation sense amplifier circuit 14 only in an area where write data exists on the LB side. The read data is sent to the verify data control circuit 38. As shown in FIGS. 1 and 14, the verify data control circuit 38 operates in response to the control signal MODEEV and the control signal AASEN, and outputs the output of the sense amplifier circuit 14 and the output data corresponding to the AAS address of the second data buffer. Based on the verification, the determination result is sent to the second data buffer 34 via the input selection circuit 33. In the output data of the second data buffer, the write target bit is 0 and the non-target bit is 1.

  A circuit diagram of a specific example of the verify data control circuit 38 is shown in FIG. The verify data control circuit 38 of this specific example operates in the case of write verify (MODEEV = “0”), a clocked inverter 381 that inverts the output of the sense amplifier 14, an inverter 382 that inverts the output of the sense amplifier 14, A clocked inverter 383 that operates when erase verify (MODEEV = "1") and inverts the output of the inverter 382, a NAND gate 384 that receives the control signal AASEN and the output of the second data buffer 34, and clocked inverters 381 and 383 A NOR gate 385 for receiving one of the outputs and the output of the NAND gate 384.

  While one write operation in the memory block 2 is performed with 64 bits, the verify data control circuit 38 performs one verify operation with 128 bits. That is, when the verify determination of the second determination signal HIT1 (AAS address [4: 0] = “00001”) is performed, the first determination signal HIT0 and the second determination signal HIT1 (AAS address [4: 0] = “00000”). The verify determination is performed once for the memory cell region of “)”.

  The second data buffer 34 that latches data to be verified is also controlled by the AAS address [4: 1]. That is, the skip of the AAS address at the time of verify determination is skipped in units of AAS address [4: 1]. For example, the next address search of the first determination signal HIT0 or the second determination signal HIT1 becomes an AAS address corresponding to the first determination signal HIT2 or the second determination signal HIT3. This is realized by the control signal MODEVERIFY signal = “1” of the AAS main circuit 351 shown in FIG. The state of the AAS main circuit 351 at this time is shown in FIG.

  As described above, the present embodiment is characterized in that the address generation by the AAS circuit 35 is variable for each write mode or verify mode.

  As shown in FIG. 15, the verify data control circuit 38 inverts the verify data A (only at the time of write verify) and passes only the bits to be verified (= write target bits). Forced to 1. The reason is that the automatic operation sense amplifier circuit 14 outputs 0 in the write verify pass (verify verification is successful) of the write target bit, and 1 in the verify fail (verify verification is failed). Since 1 is output, measures are taken so that bits that are not to be written do not become bits to be written. In addition, a measure is taken so that a bit once verified passes does not become a write target bit.

  During the verify operation, the value of the END signal becomes “1” when the last AAS address is executed, as in the write mode.

  After verifying the bit of the last AAS address, the automatic operation control circuit 26 generates a control signal AASRST. At this time, if the value of the END signal is “1”, it means that the writing of the data (10) has all passed (there is no determination signal HIT, so the value of the END signal remains “1”). . If there is a fail bit, the value of the END signal becomes “0”, the value of the control signal MODEVERIFY is set to “0”, and data (10) is written again.

  FIG. 17 shows a timing chart when the write operation and the verify operation are repeated. FIG. 17 shows a verification operation (only AAS addresses corresponding to the determination signals HIT1, HIT3, and HIT31) after execution of a write operation (only AAS addresses corresponding to the determination signals HIT1, HIT3, and HIT31) and corresponds to the determination signal HIT31. A case where only the AAS address fails is shown. When the control signal AASRST is generated, only the determination signal HIT31 is 1, so END = “0” and AAS_I indicates “11111”. Therefore, when writing is executed again, it is executed from the AAS address “11111” (see FIG. 17). In this manner, the data (10) write operation and the verify operation are performed.

Data (00) Write Operation and Verify Determination Next, the data (00) write operation and verify determination will be described.

  After the write operation and verification of the data (10) are completed, the operation shifts to the write operation of the data (00). In the second data buffer 34, the write target bit of the data (00) is on the upper bit side (UB side). Since it is stored, the data pattern selection signal [1: 0] is set to “00”, and the write operation and the verify operation are performed using the AAS circuit 35 in the same manner as described in the data (10).

Data (01) Write Operation and Verify Next, the data (01) write operation and verify determination will be described.

  Since the write data of data (01) does not exist in the second data buffer 34, the data pattern selection signal [1: 0] is set to “01”, and the data is transferred from the first data buffer 31 to the second data buffer 34. Then, as described in the data (10), the write operation and the verify operation are performed using the AAS circuit 35.

  In the present embodiment, the second data buffer 34 includes an analog switch (transfer gate) 401 composed of a P-channel transistor and an N-channel transistor at the output stage of the data holding circuit 341, as shown in FIG. Yes.

  However, in order to output different data to the same output bus in different operation modes such as a write operation and a verify operation as in a modification of the present embodiment, the second data buffer 34 has a configuration as shown in FIG. The output stage of the data holding circuit 341 may include two analog switches (transfer gates) 412 and 414 each composed of a P-channel transistor and an N-channel transistor. That is, it may be configured such that 2-port output control is performed.

  In this case, the switch 412 outputs data for eight pages indicated by the column address B [4: 0] when the control signal MODEVERIFY = “0” (in the write mode). When the control signal MODEVERIFY = “1” (in the verify mode), the switch 414 has 8 pages on the column address B [4: 1] and the upper bit side (UB side) indicated by the control signal UBEN1 = “1”. Or output data for 8 pages on the lower bit side (LB side) indicated by the column address B [4: 1] and the control signal LBEN1 = "1".

  FIG. 20 shows the relationship between each page in the write operation and verify operation and the data output bus to which the output of the second data buffer is sent when this 2-port output control is performed.

For example, as shown in FIG. 20, the data of Page 4 is output to the data bus [0:15] at the time of writing, and is output to the data bus [64:79] at the time of the verify operation.

  As described above, according to the present embodiment, when the write target bit does not exist, the address is skipped to the address where the write target bit exists, so that the automatic write operation time is allowed. It can be shortened as much as possible.

(Second Embodiment)
Next, a nonvolatile semiconductor memory device according to a second embodiment of the present invention is described.

  The nonvolatile semiconductor memory device of this embodiment performs state multi-write and verify operations in the nonvolatile semiconductor memory device of the first embodiment. The state multi-write is a mode in which the (10) level and the (00) level of the multilevel storage level are simultaneously written. As described in the first embodiment, when the data pattern selection signal [1: 0] is set to “10” and data is transferred from the first data buffer 31 to the second data buffer 34, the second data buffer 34 The (00) level write target data is stored in the upper bit side (UB side) of (1), and the (10) level write target data is stored in the lower bit side (LB side).

  Before entering the write operation, the data pattern selection signal [1: 0] is set to “11” (state multi-write mode) (see FIG. 2). In FIG. 5, the values of the control signals UBEN2 and LBEN2 are both “1”, and the logic that generates the determination signal HIT searches for the write target bits at both the (10) level and the (00) level. Here, by setting the control signal AASEN = “1” and performing the same control as the writing of the data (10) by the AAS circuit 35 in the first embodiment, the address skip by the AAS circuit 35 and the (10) level (00) ) Levels can be written simultaneously.

  In the state multi-write data, the output data from the second data buffer 34 is compressed by the data multi-value compression circuit 37 and sent to the memory block 2 via the PRG data bus. In the state multi-write, the lower bit LB of the multi-value compression bit pair is 0 as the write of data (10), or the upper bit UB of the multi-value compression bit pair is 0 as the write of data (00). Is output to the PRG data bus as 1 (write target bit), and the (10) level and (00) level of the multilevel storage level can be written simultaneously.

  After the writing is completed, the verify operation is performed. However, since the (10) level and the (00) level are different threshold levels, the (10) level verification and the (00) level verification are performed separately. (10) When performing level verification, the data pattern selection signal [1: 0] is set to “10”, and verification is performed using the AAS circuit 35. Here, since the data pattern selection signal [1: 0] is set to “10”, the generation of the determination signal HIT in FIG. 5 is UBEN2 = “0”, LBEN2 = “1”, and the LB side (data ( 10) verify the address where the write target bit exists. Similarly, the data (00) is verified by setting the data pattern selection signal [1: 0] to “00” to verify only the address where the write target bit on the UB side (data (00) side) exists. be able to.

  To determine the end of the operation, after verifying the data (10) and verifying the data (00), the data pattern selection signal [1: 0] is set to “00” (status multi-write), and the value of the END signal is If “1”, the process is terminated. If the fail bit remains, data (10) and data (00) are simultaneously written by the AAS circuit 35 again from the determination signal HIT after the verify update.

  As described above, according to the present embodiment, the state multi-write operation skips the address to the address where the write target bit exists when the write target bit does not exist as in the first embodiment. Thus, the automatic write operation time can be shortened as much as possible.

(Third embodiment)
Next, a non-volatile semiconductor memory device according to a third embodiment of the present invention is described.

  The nonvolatile semiconductor memory device according to the present embodiment is the same as the nonvolatile semiconductor memory device according to the first embodiment in the erase verify of the automatic erase operation, the over-erase verify and the over-write of the over-erased cell, and the erase and write operations in the product test. The AAS circuit 35 is used.

  In a NOR flash memory, threshold control of the erased state is important. The threshold value of the memory cell after erasing needs to be controlled to 0 V or more. Hereinafter, a method for performing such threshold control with the above-described configuration will be described.

  In the nonvolatile semiconductor memory device of the first embodiment, the control signal APRG [1: 0] is input to the input side of the second data buffer 34. The control signal APRG [1] is sent to the upper bit side (UB side (128 bits)) of the input data bus of the second data buffer 34, and the data and control signal APRG [0] are sent from the input bus to the lower bit side (LB side (128 side). Bit)).

Initial setting Initial setting is performed as follows. First, the control signal AASEN = “0”, the control signal MODEVERIFY = “0”, the data pattern selection signal [1: 0] = “01”, and the control signal APRG [1: 0] = “01” is set. 2. Latching is performed by the data buffer 34. The column address A generated by the address generation circuit 24 of the automatic operation control system 20 is used as the address at this time, and all the upper bits (UB) of the second data buffer 34 are sequentially latched as “0”. At this time, the lower bit (LB) side is all “1”. Thus, after the latch is completed, the determination signals HIT0 to HIT31 are all determined to have data.

  Here, the setting of the data pattern selection signal [1: 0] = “01” does not mean that the level of the memory cell is the (01) target, but the second data buffer is used to check the presence / absence of the verification target bit. 34 is set in the sense of using the area on the UB side.

Erase Verify Erase verify is performed as follows. First, the control signal MODEEV = “1”, the control signal MODEVERIFY = “1”, and the control signal AASEN = “1” are used to perform verification using the AAS address from the AAS circuit 35. Since the determination result of the automatic operation sense amplifier circuit 14 in the erase mode outputs “1” in the erase verify pass and “0” in the erase verify fail, the verify data control circuit 38 shown in FIG. The output of the circuit 14 is latched in the second data buffer 34 without being inverted. Here, as described in the verification determination of the data (10) and the latch to the second data buffer in the first embodiment, only the verification target bit is passed, and the non-target bit outputs “1”. .

  In the first erase verify, since all the determination signals HIT0 to HIT31 have data, the AAS circuit 35 outputs the AAS address without skipping and the verification is performed. When there is an erase verify fail bit (the determination method is AASRST inserted after verify and end if the END signal is 0), the erase operation is executed → erase verify is repeated, but only the address where the target bit to be verified from the subsequent verify exists Perform verification. If there is no erase verify fail bit, a control signal AASRST is generated after verifying, and the process ends if the END signal is 0.

Overerase Verify and Overerase Cell Rewrite Next, overerase verify and overerase cell rewrite will be described. First, from the initial setting state, the control signal MODEEV = “0”, the control signal MODEVERIFY = “1”, and the control signal AASEN = “1” are used, and overerasure verification is performed using the AAS address from the AAS circuit 35. When a file bit exists in the over-erase verification, writing is performed using the AAS address from the AAS circuit 35 with the control signal MODEEV = “0”, the control signal MODEVERIFY = “0”, and the control signal AASEN = “1”. .

In the product test , the erase operation and the write operation in the product test can be skipped using the AAS circuit 35 as described above. In this case, the test time can be shortened.

  As described above, also in this embodiment, as in the first embodiment, when there is no verification target bit, the address is skipped to the address where the verification target bit exists. Therefore, it is possible to shorten the erase / write operation time in the product test as much as possible.

(Fourth embodiment)
Next, a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention is described.

  The nonvolatile semiconductor memory device of this embodiment performs a memory cell read test for confirming the cell threshold level after writing and erasing in the product test in the nonvolatile semiconductor memory device of the first embodiment.

  In the nonvolatile semiconductor memory device of the first embodiment, the verify data output decoding DEC circuit 39 shown in FIG. 1 is used.

  First, the control signal MODEVERIFY = “1”, the control signal AASEN = “0”, the data pattern selection signal [1: 0] = “01” are set, the AAS address is not used, and the automatic operation control circuit 26 generates an address. The memory cell is read (read by the automatic operation sense amplifier circuit 14) at the address generated by the circuit 24, and the read result is stored in the second data buffer 34.

  Here, since the control signal AASEN = “0”, the verify data control circuit 38 shown in FIG. 15 passes through all the bits sent from the sense amplifier 14 and stores them in the second data buffer 34. In this embodiment, since one verify read data is 128 bits, after verify read, it is possible to read pages for 8 pages using the PAGE address shown in FIG.

  The PAGE address is directly connected to the address terminal, that is, a page to be output from the external address terminal 103 can be selected. Similarly, as the address of the memory cell array at the time of verify read, the data at the address indicated by the block address, the row address, and the column address B input from the external address terminal 103 is read.

  The verify page output bus to which the output of the verify data output decoding circuit 39 is sent can be output from the data input / output terminal 104 to the outside. Further, when the output of the verify data output decoding circuit 39 is sent to the automatic operation control circuit 26, the page can be read even in the automatic operation test closed inside the chip including the BIST (Built In Self Test) test. Time can be improved. The block address, row address, column address B, and PAGE address at the time of BIST are generated from the automatic operation control circuit 26.

(Fifth embodiment)
Next, a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention is described.

In the nonvolatile semiconductor memory devices of the first to fourth embodiments, the second data buffer 34 includes 64 data determination circuits 343 _{1 to} 343 ₄ and a data holding circuit 341 that holds a total of 4096 bits of data. _{0 to} 341 ₁₅ and the occupied area in the chip is considerably large. Therefore, in the nonvolatile semiconductor memory device of this embodiment, the second data buffer has a structure in which the occupied area is made as small as possible.

  A nonvolatile semiconductor memory device of this embodiment is shown in FIG. The nonvolatile semiconductor memory device of this embodiment has substantially the same basic circuit structure as the nonvolatile semiconductor memory device of the first embodiment shown in FIG. 1, but differs in the following points.

  In the first embodiment, the first data buffer 31, the data conversion circuit 32, the data input selection circuit 33, and the second data buffer 34 are respectively referred to as a first data buffer 31A, a data conversion circuit 32A, a data input circuit 33A, and a second data buffer. In addition to the data buffer 34A, the write data multi-value compression circuit 37 is replaced with a write data mask circuit 40 and a write data switching circuit 42, and a sense amplifier data mask circuit 44 is newly provided. The write data mask circuit 40 and the write data switching circuit 42 are provided between the second data buffer 34A and the memory block 2, and the sense amplifier data mask circuit 44 is the automatic operation sense amplifier circuit 14 and the verify data control circuit 38. Between.

  The first data buffer 31A can hold 256 pages of data as in the first data buffer 31 of the first embodiment, but receives the column address signal B unlike the first data buffer 31. The data conversion circuit 32A converts 256-bit data sent from the first data buffer 31A via the first output data bus, sends the converted 128-bit data DATA to the data input selection circuit 33A, and The 128-bit UBB data is transmitted to the second data buffer 34A, the write data mask circuit 40, and the sense amplifier data mask circuit 44 via the UBB data bus.

  Next, the configuration and operation of the nonvolatile semiconductor memory device of the present embodiment will be described by taking an automatic page write operation as an example. As in the first embodiment, the number of pages for automatic page writing is 256 pages, the number of bits that can be written to the memory block 2 at one time is 64 bits, and the sense amplifier circuit 14 for automatic operation can be read at one time. A description will be given assuming that the number of bits is 128 bits.

  The process until the automatic page write command is input and the write data is stored in the first data buffer 31A is the same as described in the first embodiment. Therefore, when the transfer of the write data to the first data buffer 31A is completed, 256 pages of data Page0 to Page255 are stored in the first data buffer 31A with each page being 16 bits.

  After the transfer of the write data to the first data buffer 31A is completed, the stored write is performed in order to retrieve data to be written (for example, data (10)) from the write data stored in the first data buffer 31A. Data is converted by the data conversion circuit 32A. This data conversion is performed as follows.

  First, when the data to be written is data (01), the data pattern selection signal [1: 0] sent from the automatic operation control circuit 26 to the data conversion circuit 32A is “01”. In this case, as shown in FIG. 24B, the data conversion circuit 32A converts the value of the DATA signal of the multi-value compression bit pair (01) to “0” and transmits it to the data input selection circuit 33A. At this time, since the upper bit UB of the multi-value compression bit pair (01) is “0”, as shown in FIG. 24B, the data UBB which is the inverted data of the UB becomes “1”, and the data conversion circuit 32A 2 is transmitted to the data buffer 34A, the write data mask circuit 40, and the sense amplifier data mask circuit 44. In this case, the value of the DATA signal of other multi-value compression bit pairs (00), (10), and (11) is converted to “1” and transmitted to the data input selection circuit 33A.

  When the data to be written is data (00) or data (10), the data pattern selection signal [1: 0] sent from the automatic operation control circuit 26 to the data conversion circuit 32A is “00” or “ 10 ". In this case, as shown in FIG. 24A, the data conversion circuit 32A converts the value of the DATA signal of the multi-value compression bit pair (00) or (10) to “0” and outputs it. At this time, since the upper bits UB of the multi-value compression bit pair (00) or (10) are “0” or “1”, respectively, as shown in FIG. It becomes “1” or “0”, and is transmitted from the data conversion circuit 32 A to the second data buffer 34 A, the write data mask circuit 40, and the sense amplifier data mask circuit 44. In this case, the other multi-value compression bit pairs (01) and (11) are converted to “1” in the value of the DATA signal and transmitted to the data input selection circuit 33A.

  Thus, by performing data conversion by the data conversion circuit 32A, 2 bits of the multi-value compression bit pair are compressed to 1 bit, and the compressed bit data DATA is transmitted to the second data buffer. Accordingly, the 32-bit multi-value compression pair is compressed by the data conversion circuit 32A into 16-bit data. For example, a 32-bit multi-value compression pair composed of 16-bit data Page0 and 16-bit data Page8 is compressed by the data conversion circuit 32A into 16-bit compressed data Page0_8, and 16-bit data Page1 and 16-bit A 32-bit multi-value compression pair consisting of the data Page9 is compressed by the data conversion circuit 32A into 16-bit compressed data Page1_9. Similarly, if i is an integer from 0 to 7, a 32-bit multi-value compression pair consisting of 16-bit data Page (i) and 16-bit data Page (i + 8) is compressed by the data conversion circuit 32A. 16-bit compressed data Page (i) _ (i + 8). The data conversion circuit 32A also outputs UBB data that is an inverted signal of the upper bit UB, and transmits it to the second data buffer 34A, the write data mask circuit 40, and the sense amplifier data mask circuit 44.

  The data input selection circuit 33A is a 128-bit data group converted by the data conversion circuit 32A based on the path selection signal [1: 0] or the signal APRG [1: 0] sent from the automatic operation control circuit 26. One of the data groups transferred from the DATA and verify data control circuit 38 is selected, and the selected data group is transferred to the second data buffer 34A.

Next, the second data buffer 34A according to the present embodiment will be described. A specific example of the circuit of the second data buffer 34A is shown in FIG. In this specific example, the second data buffer 34A includes first to fourth data mask circuits 402 _{1 to} 402 ₄ , first to fourth data determination circuits 404 _{1 to} 404 ₄ , and 16 data buffer circuits 420 ₀ to 420 ₀ . 420 ₁₅ and 16 determination result output circuits 440 _{0 to} 440 ₁₅ . Each data buffer circuit 420 _i (i = 0, 1,..., 15) has eight data holding circuits 422 _{0 to} 422 ₇ . The data holding circuit 422 _i (i = 0, 1,..., 7) holds the 16-bit compressed data Page (i) _ (i + 8) compressed by the data conversion circuit 32A. Each determination result output circuit 440 _i (i = 0, 1,..., 15) includes four data holding circuits HIT10_0, HIT0X_0, HIT10_1, HIT0X_1, each holding 1-bit data, and a logic circuit 442. It has.

  Next, the configuration and operation of the second data buffer 34A will be described.

A single data transfer circuit 32A through the data input selection circuit 33A to the second data buffer 34A transfers the compressed data group consisting of 8 pieces of 16-bit compressed data to Page0_8, Page1_9, Page2_10, Page3_11, Page4_12, and Page5_13. , Page6_14 and Page7_15 are transferred and held in the data holding circuits 422 ₀ , 422 ₁ , 422 ₂ , 422 ₃ , 422 ₄ , 422 ₅ , 422 ₆ , 422 ₇ , respectively. Note that the compressed data group Page0_8, Page1_9, Page2_10, Page3_11, Page4_12, Page5_13, Page6_14, and Page7_15 by the i-th (i = 1,..., 16th) transfer are the data holding circuit 422 of the data buffer circuit 420 _{i. 0} , 422 ₁ , 422 ₂ , 422 ₃ , 422 ₄ , 422 ₅ , 422 ₆ , 422 ₇ . In this embodiment, among the 8 sets of compressed data groups Page0_8, Page1_9, Page2_10, Page3_11, Page4_12, Page5_13, Page6_14, and Page7_15, 4 sets of compressed data groups Page0_8, Page1_9, Page2_10, and Page3_11 are combined with the upper compressed data group. The remaining four sets of compressed data groups Page4_12, Page5_13, Page6_14, and Page7_15 are referred to as lower-level compressed data groups.

At each data transfer, the first to fourth data mask circuits 402 _{1 to} 402 ₄ and the first to fourth data determination circuits 404 _{1 to} 404 ₄ check whether or not there is write data.

The first data mask circuit 402 _1, and the data DATA 64-bit data of the upper compressed data group, based on the data UBB corresponding to the data DATA, there is data (10) to be written into the upper compressed data group Whether or not there is a multi-value compression bit pair of (10) in the original multi-value compression pair of the higher-order compressed data group. The first data mask circuit 402 _1, and the data DATA, the data UBB and is input paired 64-bit pairs, the input 64-bit toward China, DATA = 0 and UBB = 0 the bits pairs Only in this case, the corresponding output bit is output as “0”, and in the case of other bit pairs, the corresponding output bit is output as “1”. Thus, in the first data mask circuit 402 ₁ outputs "0" when the data to be written has (10), if data to be written other than (10), by masking outputs "1" To do.

Similarly, the second data mask circuit 402 _2, and the data DATA of 64-bit data of the lower compressed data group, based on the data UBB corresponding to the data DATA, the data to be written into the lower compressed data groups (10 ) Or not. The second data mask circuit 402 _2, as ₁ and the first data mask circuit 402, and the data DATA, the data UBB and is input 64-bit pairs forming a pair is, the input 64-bit toward China, DATA = Only when the bit pair is 0 and UBB = 0, the corresponding output bit is output as “0”, and when the bit pair is other than that, the corresponding output bit is output as “1”. Accordingly, in the second data mask circuit 402 _2, and outputs "0" when there is data (10) to be written, if the data to be written is other than (10), by masking outputs "1" .

Third data mask circuit 402 _3, and the data DATA of 64-bit data of the upper compressed data group, based on the data UBB corresponding to the data DATA, the data to be written into the upper compressed data set (00) or ( 01) is determined. This third data mask circuit 402 _3, a data DATA, data UBB and 64 bit pairs to be pairs are input, the input 64-bit toward China, DATA = 0 and UBB = 1 the bits pairs Only in this case, the corresponding output bit is output as “0”, and in the case of other bit pairs, the corresponding output bit is output as “1”. Thus, in the first data mask circuit 402 _1, if if there is data (00) or (01) to be written outputs "0", the data to be written is other than (00) or (01), the mask And “1” is output.

Fourth data mask circuit 402 _4, and the data DATA 64-bit data of the lower compressed data group, based on the data UBB corresponding to the data DATA, the data to be written into the lower compressed data set (00) or ( 01) is determined. The fourth data mask circuit 402 _4, like the third data mask circuit 402 _3, a data DATA, data UBB and is input 64-bit pairs forming a pair is, the input 64-bit toward China, DATA = Only when the bit pair is 0 and UBB = 1, the corresponding output bit is output as “0”, and when the bit pair is other than that, the corresponding output bit is output as “1”. Thus, in the first data mask circuit 402 _1, if if there is data (00) or (01) to be written outputs "0", the data to be written is other than (00) or (01), the mask And “1” is output.

The first data determination circuit 404 ₁ determines whether or not there is write data based on the 64-bit output of the first data mask circuit 402 ₁ . When there is write data, that is, when there is at least one bit that is “0” in the 64 bits that are the output of the first data mask circuit 402 ₁ , “1” is output as the first determination result, that is, When all 64 bits that are the output of the first data mask circuit 402 ₁ are “1”, “0” is output as the first determination result, and this first determination result is sent to the data holding circuit HIT10_0 to be held. .

Second data determination circuit 404 _2, based on the 64-bit output of the second data mask circuit 402 ₂ determines whether the write data is present. If the bit is "0" when that is 64 bits in a second output data mask circuit 402 ₂ write data there is even one outputs "1" as the second determination result, when there is no i.e. If 64-bit, which is the output of the second data mask circuit 402 ₂ are all "1" outputs "0" as the second determination result, it sends the second determination result to the data holding circuit HIT10_1, to hold .

Third data determination circuit 404 ₃ based on the 64-bit output of the third data mask circuit 402 ₃ determines whether the write data is present. If the bit is "0" when that is 64 bits in an output of the third data mask circuit 402 ₃ write data there is even one outputs "1" as the third determination result, if there is no i.e. If 64-bit third which is the output of the data mask circuit 402 ₃ are all "1" outputs "0" as the third determination result, sends the third determination result to the data holding circuit HIT0X_0, to hold .

Fourth data determination circuit 404 _4, based on the output of the fourth data mask circuit 402 _4, determines whether the write data is present. If the bit is "0" if that is the fourth 64-bit in an output of the data mask circuit 402 ₄ write data there is even one outputs "1" as the fourth judgment result, if no i.e. If 64-bit fourth is the output of the data mask circuit 402 ₃ are all "1" outputs "0" as the fourth determination result, it sends the fourth determination result to the data holding circuit HIT0X_1, to hold .

The timing for holding the determination result in the data holding circuits HIT10_0, HIT10_1, HIT0X_0, and HIT0X_1 is the same as the timing for holding the data in each data holding circuit 422 _i (i = 0, 1,..., 7). .

The logic circuit 442 of each determination result output circuit 440 _i (i = 0,..., 15) has first to sixth NOR gates. The first NOR gate performs a NOR operation based on the first determination result held in the data holding circuit HIT10_0 and the signal PRGPTN1XB. The second NOR gate performs a NOR operation based on the third determination result held in the data holding circuit HIT0X_0 and the signal PRGPTNN10. The third NOR gate performs a NOR operation based on the outputs of the first and second NOR gates and outputs a determination signal HIT (2i). The fourth NOR gate performs a NOR operation based on the second determination result held in the data holding circuit HIT10_1 and the signal PRGPTN1XB. The fifth NOR gate performs a NOR operation based on the fourth determination result held in the data holding circuit HIT0X_1 and the signal PRGPTNN10. The sixth NOR gate performs a NOR operation based on the outputs of the fourth and fifth NOR gates and outputs a determination signal HIT (2i + 1). In addition,
When all the data is transferred from the first data buffer 31A to the second data buffer 34A, when the data pattern selection signal [1: 0] is “10”, the signal PRGPTN10 is “1” and the signal PRGPTN1XB is “0”. Thus, the output of the data holding circuits HIT10_0 and HIT10_1, that is, the determination result of the location where the data is “10” appears in the determination signals HIT0 to HIT31. When the data pattern selection signal [1: 0] is “00” or “01”, the signal PRGPTN10 is “0” and the signal PRGPTN1XB is “1”, and the outputs of the data holding circuits HIT0X_0 and HIT0X_1, that is, data The determination result of the place where “00” or data “01” is present appears in the determination signals HIT0 to HIT31. The determination signals HIT0 to HIT31 are “1” when there is write data.

  In the state multi-write operation, the data pattern selection signal [1: 0] is set to “11” (state multi-write mode) before entering the write operation. In this case, the signal PRGPTN10 shown in FIG. 25 is “0” and the signal PRGPTN1XB is “0”, and the logic that generates the determination signals HIT0 to HIT31 searches the write target bits of the data holding circuits HIT10_0, HIT10_1, HIT0X_0, and HIT0X_1. By doing.

The output data of the second data buffer is input to the write data mask circuit 40. A specific example of the write data mask circuit 40 is shown in FIG. The write data mask circuit 40 includes _first to _fourth NAND gates 40 ₁ to 40 ₄ . The first NAND gate 40 ₁ includes a signal PRGPTN10, performs a NAND operation on the basis of an inverted signal UBB upper bits UB. The second NAND gate 40 ₂ performs the inverted value UB signal UBB, a NAND operation on the basis of the signal PRGPTN00. The third NAND gate 40 ₃ performs a NAND operation on the basis of the outputs of the first and second NAND gates. The fourth NAND gate 40 _3, and the inverted value of the output of the third NAND gate performs a NAND operation on the basis of the output of the second data buffer 34A, and sends the data switching circuit 42 writes the operation result.

  In the write data mask circuit 40, when the data pattern selection signal [1: 0] is “10”), the signal PRGPTN10 is “1”, the signal PRGPTN00 is “0”, and the signal UBB is “1”. The output to the write data switching circuit 42 is masked to “1”. When the data pattern selection signal [1: 0] is “00”, the signal PRGPTN10 is “0”, the signal PRGPTN00 is “1”, and when the signal UBB is “0”, the write data switching circuit 42 is supplied. Mask output to "1". Thereby, for example, when the data pattern selection signal [1: 0] is “10”, the location where the multi-value compression pair is (00) is also “0” in the second data buffer 34A, but the signal UBB is Since it is “1”, the output to the write data switching circuit 42 is masked by “1”. When the data pattern selection signal [1: 0] is other than “10” or “00”, the output data of the second data buffer 34A is output to the write data switching circuit 42 as it is regardless of the value of the signal UBB. Therefore, in the write data mask circuit 40, data is written only when data to be written of any of data (10), (00), and (01) exists in the data held in the second data buffer 34A. “0” is output, and “1” is output when it does not exist. Decoded values of the signal PRGPTN1XB, the signal PRGPTN10, and the signal PRGPTN00 are shown in FIG. That is, the write data mask circuit 40 outputs “0” in the case of a write target bit.

  The write data switching circuit 42 switches between upper bits (first to 64th bits) and lower bits (65th to 124th bits) of the output data (128 bits) of the write data mask circuit 40. When the column address B [0] is “0”, the bit “0” on the lower bit side is set to “1” (the object to be written) on the PRG data bus. Bit) and write. That is, writing is performed only when there is data to be written. The write data switching circuit 42 outputs “1” in the case of a write target bit.

In the verify operation after the end of writing, verify of each level is performed separately in order to determine different threshold levels. A specific example of the sense amplifier data mask circuit 44 is shown in FIG. The sense amplifier data mask circuit 44 includes a NAND gate 44 _1, and the AND gate 44 _2. NAND gate 44 ₁ is provided with a signal PGRTN10, performs a NAND operation on the basis of the signal UBB, it sends the result to the AND gate 44 _2. AND gate 44 _2, the output of NAND gate 44 _1, on the basis of the output of the sense amplifier 14 performs an AND operation, and sends the result to verify data control circuit 38. When the data pattern selection signal [1: 0] is “10”, the signal PRGPTN10 is “1” and the signal UBB is “1” (multi-value compression pair is “00”, “01”). “0” is output regardless of the output of 14. As a result, when the “10” level is verified, it is possible to prevent destruction of data at a location where the multi-value compression pair of the second data buffer 34A is “00”.

  The processing operation of the second data buffer 34A of the present embodiment described above is shown in FIG. 30, and the processing operation of the second data buffer 34 of the first to fourth embodiments is shown in FIG. As can be seen from FIG. 30, in this embodiment, the data sent from the first data buffer 31A is converted by multi-value compression by the data conversion circuit 32A, and 2 bits of the multi-value compression bit pair are compressed to 1 bit. Then, it is sent to the second data buffer 34A. The converted data is latched in the second data buffer 34A, and at the same time, the data is determined. The latched data is sent to the write data output circuit 42 via a write data mask circuit 40 (see FIG. 23) (not shown). On the other hand, after the data is determined in the second data buffer 34A, the determination signal HIT is output based on the determination result and sent to the AAS circuit 35.

  On the other hand, as can be seen from FIG. 31, in the first to fourth embodiments, the data sent from the first data buffer 31 is subjected to multi-value compression and conversion by the data conversion circuit 32, and multi-value compression is performed. The bit pair is sent to the second data buffer 34 without being compressed and remains 2 bits. The converted data is first latched in the second data buffer 34. Thereafter, the latched data is output as data. On the other hand, the latched data is subjected to data determination in the second data buffer 34, and a determination signal HIT is output based on the determination result and sent to the AAS circuit 35.

As described above, in the present embodiment, each data buffer circuit 420 _i (i = 0,...) In the second data buffer 34A is compressed by compressing 2 bits of the multi-value compression pair into 1 bit by the data conversion circuit 32A. .., 15) can be made half the size (256 bits) of each data buffer circuit of the second data buffer 34 of the first to fourth embodiments. Further, in the first to fourth embodiments, one set of first to fourth data determination circuits is provided for each data buffer circuit 420 _i (i = 0,..., 15). In the embodiment, it is used in common. Therefore, the area of the second data buffer of this embodiment can be reduced compared to the first to fourth embodiments.

  As in the first to fourth embodiments, this embodiment is also configured to skip the address to the address where the write target bit exists when there is no write target bit. The write operation time can be shortened as much as possible.

(Application example)
Hereinafter, an example in which the NOR flash memory 100 having the configuration and function described in each of the above embodiments is mounted on a semiconductor chip will be described.

  FIG. 21 is a cross-sectional view showing an example of a semiconductor chip (multi-chip package: MCP) 1000 including a NOR flash memory 100 according to an application example.

  As shown in FIG. 21, a semiconductor chip 1000 includes a NAND flash memory 1002, a spacer 1003, a NOR flash memory 100, a spacer 1004, a PSRAM (Pseudo Static Random Access Memory) 1005, and a controller, which are sequentially stacked on a substrate 1001. 1006 is mounted in the same package.

  The NAND flash memory 1002 has, for example, a plurality of memory cells that can store multi-value data. Further, the semiconductor chip 1000 may be configured to use SDRAM (Synchronous Dynamic Random Access Memory) instead of PSRAM.

  Among the above memories, the NAND flash memory 1002 is used as a data storage memory, for example, depending on the use by the memory system. The NOR flash memory 100 is used as a program storage memory, for example. The PSRAM 1005 is used as a work memory, for example.

  The controller 1006 mainly performs data input / output control and data management for the NAND flash memory 1002. The controller 1006 includes an ECC correction circuit (not shown), adds an error correction code (ECC) when writing data, and analyzes and processes the error correction code when reading data.

  The NAND flash memory 1002, the NOR flash memory 100, the PSRAM 1005, and the controller 1006 are bonded to the substrate 1001 with wires 1007.

  Each solder ball 1008 provided on the back surface of the substrate 1001 is electrically connected to a wire 1007. As the package shape, for example, a surface mount type BGA (Ball Grid Array) in which each solder ball 1008 is two-dimensionally arranged is adopted.

  The ECC correction circuit 11 according to the first embodiment may be provided in the NOR flash memory 100 as described above, or may be provided in the controller 1006. In this case, the NAND flash memory 1002 and the ECC correction circuit may be shared, and the NAND flash memory 1002 and the NOR flash memory 100 may have different ECC correction circuits. Further, the ECC correction circuit 11 may be provided outside the controller 1002 independently.

  Next, a case where the semiconductor chip 1000 is applied to a mobile phone which is an example of an electronic device will be described.

  FIG. 22 is a diagram showing a mobile phone in which the semiconductor chip 1000 is mounted. As shown in FIG. 22, the mobile phone 2000 includes a main body upper part 2002 having a main screen 2001 and a main body lower part 2004 having a keypad 2003. The mobile phone 2000 is equipped with a semiconductor chip 1000.

  A CPU (not shown) mounted on the mobile phone 2000 accesses the semiconductor chip 1000 via an interface (not shown) and transfers data and the like.

The cellular phone 2000 uses, for example, the NAND flash memory 1002 as a user data storage area and the NOR flash memory 100 as a program storage area such as firmware.

  In such a memory system, the NOR flash memory 100 is required to perform a high-speed write operation. On the other hand, the amount of program data to be stored is increasing as the application software becomes more sophisticated.

  As described above, the NOR flash memory 100 according to the application example includes a memory cell capable of storing multi-value data, and when there is no write target bit, the address is the address where the write target bit exists. It is possible to solve both the above-mentioned two problems by being configured to skip to the above.

  Note that the semiconductor chip 1000 can be applied to various electronic devices such as a personal computer, a digital still camera, and a PDA in addition to the mobile phone.

The block diagram which shows the non-volatile semiconductor memory device by 1st Embodiment. The figure which shows a multi-value compression pair. The figure explaining a data pattern selection signal. The figure explaining the data conversion of a data conversion circuit. The block diagram which shows the structure of the specific example of a 2nd data buffer. The figure explaining the relationship between a control signal and an operation mode. The block diagram which shows an automatic address search circuit. FIG. 6 is a timing diagram of a write operation based on an AAS address when there is a write target bit. FIG. 9 is a timing diagram of a write operation based on an AAS address when there is no write target bit. The circuit diagram which shows one specific example of an AAS main circuit. The figure which shows the state which latched the write data in the 2nd data buffer. The figure which shows the state which skipped to the address with the data to write next at the rising edge of the control signal ADDINCEN. The figure which shows the state which did not have the address where write data exists after this, and the end signal END was output at the rising edge of the control signal ADDINCEN. The block diagram which shows the relationship between a verification data control circuit and a 2nd data buffer. FIG. 5 is a circuit diagram showing a specific example of a verify data control circuit. The figure which shows the state of the AAS main circuit at the time of a verify operation | movement. FIG. 6 is a timing chart when a write operation and a verify operation are repeated. The circuit diagram which shows the output stage of the 2nd data buffer in 1st Embodiment. The circuit diagram which shows the output stage of the 2nd data buffer in the modification of 1st Embodiment. The figure which shows the relationship between each page in a write operation and a verify operation, and the data output bus to which the output of a 2nd data buffer is sent when 2 port output control is performed. Sectional drawing which shows an example of the semiconductor chip provided with the NOR type flash memory in the application example. The schematic diagram which shows the mobile telephone which stores the semiconductor chip provided with the NOR type flash memory in the application example. The block diagram which shows the non-volatile semiconductor memory device by 5th Embodiment. The figure explaining the data conversion of the data converter circuit which concerns on 5th Embodiment. The block diagram which shows the structure of the specific example of a 2nd data buffer. FIG. 5 is a circuit diagram showing a specific example of a write data mask circuit. The figure which shows the decoding value of signal PRGPTNN10B, signal PRGPTN1XB, signal PRGPTN10, and signal PRGPTN00. FIG. 3 is a circuit diagram showing a specific example of a write data switching circuit. FIG. 5 is a circuit diagram showing a specific example of a sense amplifier data mask circuit. The figure explaining the processing operation of the 2nd data buffer concerning a 5th embodiment. The figure explaining the processing operation of the 2nd data buffer concerning a 1st thru / or a 4th embodiment.

Explanation of symbols

2 memory block 4 memory cell array 6 memory decoder 12 read sense amplifier circuit 14 automatic operation sense amplifier circuit 20 automatic operation control system 22 command determination circuit 24 address generation circuit 26 automatic operation control circuit 30 data control system 31 first data buffer 31A First data buffer 32 Data conversion circuit 32A Data conversion circuit 33 Input selection circuit 34 Second data buffer 34A Second data buffer 35 Automatic address search circuit (AAS circuit)
36 address selection circuit 37 write data multi-value compression circuit 38 verify data control circuit 39 verify data output decode circuit 40 write data mask circuit 42 write data switching circuit 44 sense amplifier data mask circuit 1000 semiconductor chip 1001 substrate 1002 NAND flash memory 1003 1004 Spacer 1005 PSRAM
1006 Controller 1007 Wire 1008 Solder ball 2000 Mobile phone 2001 Main screen 2002 Main body upper part 2003 Keypad 2004 Lower main body

Claims (9)

A memory cell array having a plurality of nonvolatile memory cells;
An address search circuit that searches for write target data and outputs an address where the write target data exists when writing data to the plurality of nonvolatile memory cells;
A control circuit for controlling to write the write target data in the memory cell according to the address output from the address search circuit;
A non-volatile semiconductor memory device comprising: A data buffer that holds input data and has a determination function for determining whether or not the data to be written exists in the input data;
2. The nonvolatile semiconductor memory device according to claim 1, wherein the address search circuit outputs the address where the write target data exists based on a determination result of the data buffer. A first data buffer for holding input data;
A data conversion circuit for converting input data held in the first data buffer according to the write target data;
A second data buffer that holds the input data converted by the data conversion circuit and has a determination function for determining whether or not the data to be written exists in the held input data; Prepared,
2. The nonvolatile semiconductor memory device according to claim 1, wherein the address search circuit outputs the address where the write target data exists based on a determination result of the second data buffer.   A verify data control circuit for performing a verify determination after the writing; the verify data control circuit inverts the verify data for the data in which the verify determination target bit exists and outputs the inverted data to the data buffer; 4. The nonvolatile semiconductor memory device according to claim 2, wherein a bit that has been passed once by verifying outputs pass data to the data buffer. 5.   The plurality of nonvolatile memory cells can store quaternary level data, and the control circuit has the highest threshold voltage and the lowest threshold voltage among the quaternary level data. 5. The nonvolatile semiconductor memory device according to claim 1, wherein two levels of data excluding data are controlled to be written to the nonvolatile memory cell at the same time. 6. A first data buffer for holding input data;
According to the data to be written, the input data held in the first data buffer is converted by multi-value compression and converted, and the converted data is further compressed in half and the remaining half. A data conversion circuit for outputting the second compressed data;
A second data buffer that holds the first compressed data output from the data conversion circuit and has a determination function for determining whether or not the write target data exists in the first compressed data; Further comprising
2. The nonvolatile semiconductor memory device according to claim 1, wherein the address search circuit outputs the address where the write target data exists based on a determination result of the data buffer. Based on the data pattern signal indicating the type of the write target data, the first compressed data held in the second data buffer, and the second compressed data output from the data conversion circuit, the second data A write data mask circuit that outputs without masking when the first compressed data held in the buffer is the write target data, and masks and outputs when the data is the write target data;
7. The nonvolatile semiconductor memory device according to claim 6, wherein writing is performed based on an output of the write data mask circuit and an address output from the address search circuit. A verify sense amplifier for performing verify read;
Based on the output of the verify sense amplifier, the second compressed data, and the data pattern signal, the verify sense is performed so that verification is not performed only in the case of data that does not have a target bit for verify determination. A sense amplifier data mask circuit for masking the output of the amplifier;
The nonvolatile semiconductor memory device according to claim 6, further comprising:   The second data buffer holds the first compressed data and determines whether the write target data exists in the first compressed data based on the first and second compressed data. 7. A determination signal is sent to the address search circuit based on the determination result and a data pattern signal indicating the type of the write target data to output the address where the write target data exists. The nonvolatile semiconductor memory device according to any one of 1 to 8.

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