JP2010055673A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of accessing memory cells with continuous addresses from the outside when writing of binary data is carried out. <P>SOLUTION: A NOR type flash memory 100 by which data are writable in either one of the multi-valued data or binary data, includes an address conversion circuit 13 for rearranging a part of address bit of the external address at the writing of the binary data. By this arrangement, the writing of data and reading of data at one word unit become possible by giving the continuous external addresses at the writing of the binary data, thereby the NOR type flash memory 100 can be effectively utilized at an SLC mode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device that can be written by switching between multi-value data and binary data.

  In recent years, flash memories using MLC (Multi Level Cell) technology have been mass-produced in order to increase the degree of integration. The same applies to the NOR type flash memory, but in order to apply the MLC technique as the design rule becomes finer, advanced techniques are required to ensure the reliability of the data. Against this background, an MLC NOR type flash memory in which an ECC (Error Correction code) circuit is provided inside the memory has appeared.

  On the other hand, there is a request from the user side to write data to the flash memory in units of words. Therefore, a flash memory that has a multi-value data write function and a binary data write function and can write multi-value data or binary data in the same memory cell area depending on the mode has appeared ( Patent Document 1).

However, in this type of conventional memory, when writing binary data, there is a problem that the user cannot specify consecutive addresses, and it is necessary to specify jump addresses, which increases the burden on the programmer, There was a problem of poor usability.
JP 2005-108303 A

  The present invention provides a nonvolatile semiconductor memory device capable of accessing memory cells with continuous addresses from the outside when binary data is written.

In one embodiment of the present invention, any one of a plurality of memory cells that can read and write data and a predetermined cell region that constitutes a part of the plurality of memory cells, either multi-value data writing or binary data writing Flag storage means for storing flag data indicating whether to perform
When writing of the multi-value data is selected by the flag data, the entire corresponding cell area can be accessed by an external address, and when writing of the binary data is selected by the flag data There is provided a non-volatile semiconductor memory device comprising: an access range setting unit that makes a half of the corresponding cell region accessible by a continuous address range of external addresses.

  According to the present invention, when binary data is written, a memory cell can be accessed from the outside with continuous addresses.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  The nonvolatile semiconductor memory device according to the embodiment of the present invention is, for example, a NOR flash memory, and has a multi-value data (MLC) write function. When writing multi-value data, it is common to provide an ECC circuit for generating parity data so that error correction can be performed in order to improve reliability.

  As for the bit size that can be corrected by the ECC circuit, 1-bit correction is mainly performed in units of a plurality of words because of reliability specifications and chip size. If 1-bit correction is performed in units of 1 word, high reliability can be guaranteed, but the chip size becomes enormous, which is not practical. Therefore, when writing to the NOR flash memory, it is necessary to perform batch writing in units of word areas that can be corrected by the ECC circuit (hereinafter referred to as ECC units or ECC segments). Actually, in order to improve the average writing speed, it is common to perform batch writing in ECC units composed of a plurality of segments, which is called a page program.

  On the other hand, the user side of the memory may handle data in units of words, and in order to use the memory storage area without waste, a function for writing in units of words is required. For this reason, the NOR flash memory according to the present embodiment has a binary data (SLC: Single Level Cell) write function in addition to the MLC write function. When SLC is used, writing is possible in units of one word without using an ECC circuit. Hereinafter, a case where the multi-value data writing function is used is referred to as an MLC mode, and a case where the binary data writing function is used is referred to as an SLC mode.

  Note that whether the MLC mode or the SLC mode is selected can be switched in units of address groups (usually page program units). Which address group in the memory is set to the SLC mode is set by the user (command) on the user side. Therefore, a redundant portion (flag storage means, parity storage means) 1a is provided for each address group in the memory, and flag data indicating either the MLC mode or the SLC mode is stored in the redundant portion 1a.

  When the SLC mode is selected, the address area actually used for data writing is halved. In this case, the valid address and the invalid address appear in half for each ECC unit.

  FIG. 1A is a diagram showing a relationship between an external address and a memory cell when the MLC mode is selected. As shown in the figure, when multi-value data is stored, data at a plurality of addresses is stored in the same memory cell. FIG. 1A shows an example in which the ECC unit is 2N words.

  In FIG. 1A, it is assumed that one word (16 bits) of data is written at one address. Therefore, data is actually written into 16 memory cells with one address, but FIG. 1A shows only one memory cell for simplicity.

  FIG. 1B shows an example where N in FIG. 1A is set to N = 4. This is also the case, and data of two addresses is stored in each memory cell. Therefore, eight addresses are associated with memory cells for four words for each ECC unit.

  FIG. 2A is a diagram showing the relationship between the external address and the memory cell when the SLC mode is selected, and shows an example in which only the address in the first half of the ECC unit is associated with the memory cell as an effective address. . The address in the latter half of the ECC unit is an invalid address and is not used for storage in the memory cell.

  FIG. 2B shows an example in which N in FIG. 2A is set to N = 4. This is also the case, and only the address of the first half of the ECC unit is used for storage in the memory cell.

  As shown in FIGS. 2A and 2B, when the SLC mode is selected, only half of the external address is used for storing the memory cell, and the external address used for storing the memory cell jumps out. Become. For this reason, data cannot be written by designating consecutive addresses from the outside, and there is a problem that the burden on the user side (programmer) is heavy because it is necessary to designate jump addresses.

  1 and 2 show an example of a page program for writing data to a memory cell for each ECC unit which is a page program unit. In a flash memory, data is generally written in a unit larger than the unit of data writing. Erase. A unit of data erasure is called an erase block.

  FIG. 3 is a diagram schematically showing an example of a page program unit and an erase block unit. In FIG. 3, the ECC unit consists of 32 segments, and each segment consists of 8 words. Therefore, the ECC unit is 8 × 32 = 256 words, which corresponds to one page.

  The page program address group has an area of 512 pages = 256 words × 512 = 128 k words, and this area is a unit for erasing data and is an erase block. An area of 64 × 128k words / block = 8M words, which is a collection of 64 erase blocks, corresponds to one bank. The NOR type flash memory has a data capacity of a plurality of banks. For example, the NOR type flash memory of FIG. 3 has 8 banks, and the total data capacity of the memory is 8 × 8 M words / bank = 64 M words = 1 Gbit.

  The data amounts of the page program, erase block, and bank shown in FIG. 3 are merely examples, and various changes can be made.

  The NOR flash memory according to the present embodiment described below performs data writing for each ECC unit consisting of 256 words at the time of data writing, and erases data for each erase block consisting of 128 k words.

  FIG. 4 is a block diagram showing an example of the internal configuration of the NOR flash memory 100. 4 includes a memory cell array 1, a decoder 2, a sense amplifier 3, a control circuit 4, an address buffer 5, an input / output buffer 6, a data latch circuit 7, and a data compression circuit 8. A parity generation circuit 9, a burst circuit 10, an ECC correction circuit 11, a multiplexer 12, and an address conversion circuit 13. Here, the control circuit 4 and the address conversion circuit 13 correspond to access range setting means.

  The memory cell array 1 has a plurality of memory cells arranged in a matrix. The control gate electrodes of the plurality of memory cells arranged in the selected row direction are commonly connected to the word line, and the drain regions of the plurality of memory cells arranged in the selected column direction are common to the bit lines via the bit line contacts. It is connected.

  A group of memory cells connected to one word line includes a plurality of memory cells used as a data area for storing main body data (write data input from the outside), and parity data and flags associated with the main body data. There are a plurality of memory cells used as a parity / flag area in which data is stored. In the present embodiment, it is assumed that the memory cell group connected to one word line forms a unit processed by a single page write operation.

  The decoder 2 performs bit line selection, word line selection, and driving of the memory cell array 1 in accordance with a control signal output from the control circuit 4.

  The sense amplifier 3 is connected to a bit line of the memory cell array 1 and reads and outputs data stored in the memory cell.

  Address buffer 5 receives an external address signal and generates an internal address signal. The internal address signal generated by the address buffer 5 is supplied to the control circuit 4, the data latch circuit 7, and the burst circuit 10.

  The input / output buffer 6 is connected to, for example, a data input / output terminal (not shown) capable of inputting / outputting data of 16 bits (one word) simultaneously in one transfer cycle. The supplied data is supplied to the data latch circuit 7 and the control circuit 4. Further, when reading data, the input / output buffer 6 receives the read data via the burst circuit 10 and outputs the input data to the outside.

  The control circuit 4 receives a chip enable signal CEB, a write enable signal WEB and an output enable signal OEB inputted from the outside, and also receives an internal address signal and a data signal. The control circuit 4 outputs various control signals for controlling the operation of each internal circuit based on these input signals.

  The data latch circuit 7 receives the internal address signal and the input data signal, latches the input data in the area indicated by the internal address signal, and outputs the latched input data to the data compression circuit 8 and the parity generation circuit 9. For example, it is assumed that the data latch circuit 7 can hold at least 256 bits of data.

  The data compression circuit 8 writes the flag data output from the control circuit 4, the main body data output from the data latch circuit 7, and the parity data output from the parity generation circuit 9 when writing multi-value data into the memory cell. Compress the address. Although a detailed description is omitted in this embodiment, an address compression method is used in which data in units of one word input in different transfer cycles is processed as a set (multi-value compression pair).

  The parity generation circuit 9 generates parity data for ECC correction of this data according to the data output from the data latch circuit 7. Parity data is generated in units of 256 words processed by one page write operation, for example.

  The ECC correction circuit 11 corrects the read data output from the sense amplifier 3 based on the parity data, and outputs corrected data (hereinafter referred to as corrected data).

  The multiplexer 12 receives the correction data output from the ECC correction circuit 11 and the flag data. The multiplexer 12 outputs the correction data to the burst circuit 10. Further, the multiplexer 12 outputs the flag data to the burst circuit 10 in response to an input of a control signal that requests output of the flag data output from the control circuit 4.

  The burst circuit 10 continuously outputs addresses of data to be read to the decoder 2 in synchronization with the external clock signal CLK according to the internal address signal. The burst circuit 10 outputs the data signal output from the multiplexer 12 to the input / output buffer 6 in synchronization with the external clock signal CLK (burst read operation).

  In the present embodiment, switching between the MLC mode and the SLC mode can be performed for every 256 words, which is a unit of page program, and parity data and flag data are generated for every 256 words. The flag data includes flag data indicating the MLC mode and flag data indicating the SLC mode, and these are stored in separate memory cells. More specifically, the flag data is defined as (11) in the erased state, (01) in the multi-valued state, (10) in the binary state, (00) in the write-inhibited state, and 2 Stored in one memory cell. When the SLC mode is selected, data ECC correction is not performed and parity data is not required.

  The NOR flash memory 100 of FIG. 4 is characterized in that in the SLC mode, a continuous address is supplied from the outside so that the memory cell can be accessed in units of one word. In order to realize this, the NOR flash memory 100 of FIG. 4 has an address conversion circuit 13. The address conversion circuit 13 generates an internal address by rearranging a part of the bit string of the external address. When the external address is supplied, the memory cell corresponding to the internal address converted by the address conversion circuit 13 is selected.

  5 and 6 are diagrams for explaining the operation of the address conversion circuit 13. FIG. 5A is a diagram showing the relationship between external addresses and internal cells when no address translation is performed, and FIG. 5B is a diagram showing the relationship between external addresses and internal addresses in the case of FIG. 5A. It is. When the address conversion is not performed, the external address and the internal address are the same. However, when the external address is incremented continuously, a valid address that can access the memory cell and an invalid address that cannot access the memory cell alternately appear. More specifically, the external addresses 0h to 3h can access the memory cell, but the subsequent 4h to 7h cannot be accessed, and only the 4-word address can be continuously accessed.

  On the other hand, FIG. 6A shows the relationship between the external address and the internal cell when the address conversion circuit 13 is provided, and FIG. 6B shows the relationship between the external address and the internal address in the case of FIG. It is a figure which shows a relationship. As shown in FIG. 6B, the external address A2-A6 is shifted by 1 bit and assigned to the internal address A3-A7, and the external address A7 (usually 0) becomes the internal address A2. Assigned. As a result, as shown in FIG. 6A, the memory cells can be continuously accessed while the external address is between 0h and 7Fh. 80h to FFh thereafter are invalid addresses that cannot access the memory cells.

  Thus, by providing the address conversion circuit 13, the memory cell area that can be continuously accessed with the external address can be greatly increased, and it becomes easier to specify the address from the outside in the SLC mode, and the NOR flash memory is effective. Can be used.

  FIG. 7 is a circuit diagram showing an example of the internal configuration of the address conversion circuit 13. As illustrated, the address conversion circuit 13 includes first to sixth address selection circuits 13a to 13f that select one of two address bits of an external address. Each of the first to sixth address selection circuits 13a to 13f performs address selection based on flag data (MLC / SLC mode signal).

  The first address selection circuit 13a selects either the external address A2 or A3 and supplies it to the internal address A3. The second address selection circuit 13b selects one of the external addresses A3 and A4 and supplies it to the internal address A4. The third address selection circuit 13c selects one of the external addresses A4 and A5 and supplies it to the internal address A5. The fourth address selection circuit 13d selects one of the external addresses A5 and A6 and supplies it to the internal address A6. The fifth address selection circuit 13e selects one of the external addresses A6 and A7 and supplies it to the internal address A7. The sixth address selection circuit 13f selects one of the external addresses A7 and A2 and supplies it to the internal address A2.

  Each of the first to sixth address selection circuits in FIG. 7 is configured by combining an AND gate, a NOR gate, and an inverter, but the circuit configuration is not limited to that shown in the figure.

  As described above, in the first embodiment, the address conversion circuit 13 for rearranging a part of the address bits of the external address in the SLC mode is provided. Therefore, in the SLC mode, the data is obtained in units of one word by giving continuous external addresses. Writing and data reading are possible, and the NOR flash memory 100 can be effectively used in the SLC mode.

(Second Embodiment)
In the first embodiment, an example has been described in which data can be written with continuous addresses in units of page programs in the SLC mode. However, in the second embodiment described below, data can be written with continuous addresses in units of erase blocks. It is what I did. Below, it demonstrates centering around difference with 1st Embodiment.

  In the second embodiment, the basic operation is the same except that the address range in which data can be written by giving a continuous address from the outside in the SLC mode is different from that in the first embodiment.

  8 and 9 are diagrams for explaining the operation of the address conversion circuit 13 according to the second embodiment. FIG. 8A is a diagram showing the relationship between external addresses and internal cells when no address translation is performed, and FIG. 8B is a diagram showing the relationship between external addresses and internal addresses in the case of FIG. 8A. It is. When address translation is not performed, valid addresses that can access memory cells and invalid addresses that cannot be accessed appear alternately.

  On the other hand, FIG. 9A shows the relationship between the external address and the internal cell when the address conversion circuit 13 is provided, and FIG. 9B shows the relationship between the external address and the internal address in the case of FIG. It is a figure which shows a relationship. As shown in FIG. 9B, the external address A2-A15 is shifted by 1 bit and assigned to the internal address A3-A16, and the external address A16 (usually 0) becomes the internal address A2. Assigned. Thereby, as shown in FIG. 9A, the memory cells can be continuously accessed between the external addresses 0h to FFFFh. Subsequent 10000h to 1FFFFh are invalid addresses that cannot access the memory cells.

  As described above, in the second embodiment, since data can be written from the outside with continuous addresses in units of erase blocks, data can be written with continuous addresses in a wider address space than in the first embodiment. The NOR type flash memory 100 can be used more effectively than in the first embodiment.

(Third embodiment)
There is no reason why the address range in which data is written with continuous addresses in the SLC mode is limited to page program units or erase block units. Therefore, in the third embodiment described below, data can be written at continuous addresses in an arbitrary address range.

  10 and 11 are diagrams for explaining the operation of the address conversion circuit 13 according to the third embodiment. FIG. 10A is a diagram showing the relationship between external addresses and internal cells when no address translation is performed, and FIG. 10B is a diagram showing the relationship between external addresses and internal addresses in the case of FIG. 10A. It is. FIG. 11A is a diagram showing the relationship between external addresses and internal cells when no address translation is performed, and FIG. 11B is a diagram showing the relationship between external addresses and internal addresses in the case of FIG. 11A. It is.

In these drawings, in the SLC mode, an example is shown in which data can be written with continuous addresses in units of an address range of 2 ^{y + 1} words.

  When performing address translation, as shown in FIG. 11B, external addresses A0 to A (x-1) are associated with internal addresses A0 to A (x-1), and external addresses Ax to A (y-1) is shifted bit by bit and associated with internal addresses A (x + 1) to Ay, and external address Ay is associated with internal address Ax.

  Thus, in the SLC mode, data can be written from the outside with continuous addresses in the address range of 0h to (m + 1) N / 2h (where m and N are hexadecimal numbers).

  As described above, in the third embodiment, in the SLC mode, data can be written at a continuous address from the outside in an arbitrary address range in the memory cell array.

(Other embodiments)
The use of the NOR type flash memory 100 described in the above first to third embodiments is not particularly limited, and can be used as a storage device for various electric devices and electronic devices. The NOR flash memory 100 may be housed in the same package as other memories such as a NAND flash memory.

  FIG. 12 is a cross-sectional view showing an example of a semiconductor chip (multi-chip package: MCP) 20 incorporating the NOR flash memory 100 and other memories described in the first to third embodiments. is there.

  As shown in FIG. 12, the semiconductor chip 20 includes a NAND flash memory 22, a spacer 23, a NOR flash memory 100, a spacer 24, a PSRAM (Pseudo Static Random Access Memory) 25, and a controller, which are sequentially stacked on a substrate 21. 26 is mounted in the same package.

  The NAND flash memory 22 has, for example, a plurality of memory cells that can store multi-value data. Further, the semiconductor chip 20 may be configured to use SDRAM (Synchronous Dynamic Random Access Memory) instead of PSRAM.

  Among the above memories, the NAND flash memory 22 is used as a data storage memory, for example, depending on the use by the memory system. The NOR flash memory 100 is used as a program storage memory, for example. The PSRAM 25 is used as a work memory, for example.

  The controller 26 mainly performs data input / output control and data management for the NAND flash memory 22. The controller 26 has an ECC correction circuit (not shown), adds an error correction code (ECC) when writing data, and analyzes and processes the error correction code when reading data.

  The NAND flash memory 22, the NOR flash memory 100, the PSRAM 25, and the controller 26 are bonded to the substrate 21 with wires 27.

  Each solder ball 28 provided on the back surface of the substrate 21 is electrically connected to the wire 27. As the package shape, for example, a surface mount type BGA (Ball Grid Array) in which the solder balls 28 are two-dimensionally arranged is employed.

  The ECC correction circuit 11 according to the first embodiment may be provided in the NOR flash memory 100 as described above, or may be provided in the controller 26. In this case, the NAND flash memory 22 and the ECC correction circuit may be shared, and the NAND flash memory 22 and the NOR flash memory 100 may have different ECC correction circuits. Further, the ECC correction circuit 11 may be provided outside the controller 22 independently.

  Next, a case where the semiconductor chip 20 is applied to a mobile phone which is an example of an electronic device will be described.

  FIG. 13 is a block diagram showing an example of the internal configuration of this type of mobile phone. The mobile phone of FIG. 13 includes an antenna 31, an antenna duplexer 32 that switches between transmission and reception signals, a reception circuit 33 that converts a radio signal into a baseband signal, and a frequency synthesizer 34 that generates a local oscillation signal for transmission and reception. A transmission circuit 35 that modulates the transmission signal to generate a radio signal, a baseband processing unit 36 that generates a reception signal of a predetermined transmission format based on the baseband signal, and the received signal as audio, video, and text data A demultiplexing processing unit 37 that separates the audio data into a digital audio signal, a PCM codec 39 that generates an analog audio signal by PCM decoding the digital audio signal, a speaker 40, and a microphone 41. Video codec 42 for decoding video data into digital video signals , Camera 43, camera control unit 44, control unit 45 for controlling the entire mobile phone, display unit 46, key input unit 47, RAM 48, ROM 49, program storage flash memory 50, and data storage A flash memory 51 and a power supply circuit 52 are provided.

  In FIG. 13, the NOR flash memory 100 described in the first to third embodiments is used for the program storage flash memory 50, and the NAND flash memory 22 is used for the data storage flash memory 51.

  Among the data handled by mobile phones, there is data with a small capacity (in units of several words). When storing such data, the NAND flash memory 22 has to write in units of pages (512 bytes) every time several words of data are written because of the NAND type structure. For this reason, a storage area that is not used is generated, and the time required to complete the writing is also increased. Therefore, in the mobile phone of FIG. 13, data can be written in units of one word in the SLC mode by using a part of the storage area of the NOR flash memory 100 that is originally used for storing programs. Can be used without waste, and high-speed writing is also possible. At this time, with the NOR flash memory 100 described in the first to third embodiments, it is possible to write data by giving continuous addresses from the outside, so it is easy to create a program for several words of data. This reduces the burden on the programmer.

  Based on the above description, those skilled in the art may be able to conceive additional effects and various modifications of the present invention. Accordingly, aspects of the present invention are not limited to the individual embodiments described above. Various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

(A) is a figure which shows the relationship between an external address and memory cell at the time of selecting MLC mode, (b) is a figure which shows the example which set N = 4 to N of FIG. 1 (a). (A) is a figure which shows the relationship between the external address and memory cell at the time of selecting SLC mode, (b) is a figure which shows the example which set N = 4 to N of FIG. 2 (a). The figure which shows typically an example of the unit of a page program, and the unit of an erase block. 1 is a block diagram showing an example of an internal configuration of a NOR flash memory 100. FIG. (A) is a figure which shows the relationship between the external address and internal cell when not performing address conversion, (b) is a figure which shows the relationship between the external address and internal address in the case of Fig.5 (a). FIG. 7A is a diagram showing the relationship between external addresses and internal cells when the address conversion circuit 13 is provided, and FIG. 7B is a diagram showing the relationship between external addresses and internal addresses in the case of FIG. 3 is a circuit diagram showing an example of an internal configuration of an address conversion circuit 13. FIG. (A) is a figure which shows the relationship between the external address and internal cell when not performing address translation, (b) is a figure which shows the relationship between the external address and internal address in the case of Fig.8 (a). (A) is a figure which shows the relationship between an external address and internal cell at the time of providing the address conversion circuit 13, (b) is a figure which shows the relationship between the external address and internal address in the case of Fig.9 (a). (A) is a figure which shows the relationship between the external address and internal cell when not performing address conversion, (b) is a figure which shows the relationship between the external address and internal address in the case of Fig.10 (a). (A) is a figure which shows the relationship between the external address and internal cell when not performing address translation, (b) is a figure which shows the relationship between the external address and internal address in the case of Fig.11 (a). FIG. 4 is a cross-sectional view showing an example of a semiconductor chip 20 incorporating the NOR flash memory 100 described in the first to third embodiments and another memory. The block diagram which shows an example of the internal structure of a mobile telephone.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory cell array 1a Redundant part 4 Control circuit 13 Address conversion circuit 22 NAND type flash memory 100 NOR type flash memory 50 Program storage flash memory 51 Data storage flash memory

Claims (5)

A plurality of memory cells capable of reading and writing data;
Flag storage means for storing flag data indicating whether to write multi-value data or binary data for each predetermined cell region constituting a part of the plurality of memory cells;
When writing of the multi-value data is selected by the flag data, the entire corresponding cell area can be accessed by an external address, and when writing of the binary data is selected by the flag data A non-volatile semiconductor memory device, comprising: an access range setting unit that allows a half of the corresponding cell region to be accessed by a continuous address range of external addresses.   2. The access range setting means includes address conversion means for rearranging at least part of a bit string constituting an external address when writing of the binary data is selected by the flag data. The non-volatile semiconductor memory device described in 1. Parity storage means for storing parity data used for error correction when writing of the multi-value data is selected by the flag data,
3. The nonvolatile semiconductor memory device according to claim 1, wherein the flag storage unit and the parity storage unit are provided in a part of the plurality of memory cells.   The size of the cell area when writing binary data is a page size that is a unit for writing data of multilevel data, or a size of an erase block that is a unit for erasing data of the plurality of memory cells. The nonvolatile semiconductor memory device according to claim 1.   The size of the cell area when binary data is written is an arbitrary size between a page size, which is a unit for writing multi-value data, and all sizes of the plurality of memory cells. The non-volatile semiconductor memory device according to claim 1.

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