JP4599954B2 - Switching regulator and drive control method thereof - Google Patents

Description

  The present invention relates to a switching regulator that converts a DC voltage by a switching operation of a semiconductor switch, and a drive control method for the switching regulator, and more particularly to a switching regulator that can linearly control the drain current of a semiconductor switch that performs a switching operation.

FIG. 5 is a circuit diagram showing a circuit configuration of a conventional switching regulator.
This switching regulator is a step-down switching power supply device including a P-channel type semiconductor switch Q11, an N-channel type semiconductor switch Q12, an output inductor L, and an output capacitor C. The switching regulator is connected to a driver 1, a comparator 2, and an oscillator 3 that generate a predetermined control signal in accordance with the fed back output voltage level. The connection point (node N) of the semiconductor switches Q11 and Q12 of this switching regulator is grounded via a series circuit of an output inductor L and an output capacitor C. The semiconductor switches Q11 and Q12 are alternately turned on and off by the gate control signal from the driver 1, the input power supply voltage Vdd from the power supply terminal 4 is converted into a desired DC voltage, and the output capacitor C and the output inductor L An output voltage Vout having a predetermined magnitude is output from the connection point to the output terminal 5.

  At this time, the source terminal of the semiconductor switch Q11 is connected to the power supply terminal 4 of the switching regulator and the switching operation is performed by the gate control signal. However, the semiconductor switch Q11 is connected to the power supply terminal 4 to which the input power supply voltage Vdd of the semiconductor switch Q11 is applied. Has a parasitic inductor component with a non-negligible size. Therefore, when the semiconductor switch Q11 is switched, a rapid current change is caused in the drain current, and a high-frequency power supply voltage fluctuation occurs in the power supply terminal 4 and the output terminal 5 of the switching regulator.

In conventional switching regulators, in order to suppress such current and voltage fluctuations, a plurality of semiconductor switches are arranged in parallel, and the drain current is linearly increased / decreased by shifting on / off times from each other (for example, Patent Documents) 1) or a method of slowing the change in the drive signal from the driver by using an RC delay or the like to reduce the current change and suppressing the high-frequency power supply voltage fluctuation (for example, see Patent Document 2). Has been.
JP 2002-64972 A ([0038] to [0078], FIGS. 7 to 10) JP 2003-134803 A ([0012] to [0017], FIG. 2)

The conventional switching regulator described above has the following problems.
In the switching power supply circuit of Patent Document 1, since the gate control signal for driving a plurality of semiconductor switches is a digital signal, it contains a high frequency component. Therefore, even if a small size transistor is used for each semiconductor switch, the change in the passing current is not constant, and a high frequency component is included, so that the input / output voltage fluctuation cannot be sufficiently suppressed.

  In order to cope with such a problem, the number of semiconductor switches connected in parallel is increased, and, for example, m semiconductor switches are sequentially turned on and off. However, since the voltage fluctuation at the output node is large at the first time when turned on (through) or at the last time when turned off (shut off), the rate of change of the output current cannot be suppressed to (1 / m). Therefore, even if the number m of semiconductor switches connected in parallel is increased, an effect corresponding to the number of semiconductor switches connected in parallel is not exhibited.

  Moreover, in the switching power supply circuit of Patent Document 1, voltage fluctuations of each semiconductor switch can be reduced by slowing the change in the gate control signal. However, such a gate control signal not only lowers the voltage conversion efficiency in the switching regulator, but also increases the transition time of the semiconductor switch, making switching control and high-speed response in the high frequency range impossible. Is not an effective measure.

  In a switching power supply circuit, when controlling each semiconductor switch, it is generally desirable to use a gate control signal having a constant voltage change that does not include a high-frequency component. However, even with such a gate control signal, each semiconductor switch itself has an abrupt current change characteristic in the vicinity of the threshold value, so that a constant current change corresponding to the above-described constant voltage change can be obtained. As a result, voltage fluctuations occurring at both the input and output points of the semiconductor switch could not be avoided.

  Further, in the switching regulator of Patent Document 2, an RC filter or LC filter is inserted to remove a high frequency component of the gate control signal and suppress a rapid change in the current flowing through the semiconductor switch. However, since the actual output current from the semiconductor switch does not change linearly, there is a problem that the moment when the rate of change of the output current increases cannot be eliminated.

  Furthermore, if it is configured to arrange a large number of circuits in which semiconductor switches and constant current circuits are connected in series, the input / output current change can be made linear, but the power loss in each constant current circuit There was also a problem that it was not realized as a switching power supply.

  The present invention has been made in view of the above points, and a switching regulator that controls the gate voltage of a semiconductor switch to reduce noise so as to obtain an ideal linear output current and its drive control. It aims to provide a method.

In order to solve the above problems, the present invention provides a drive control method for a switching regulator that converts a DC voltage by a switching operation of a semiconductor switch. In this switching regulator drive control method, when switching operation of the semiconductor switch from on to off, the change rate of the gate voltage of the semiconductor switch is switched from off to on in the order of high speed, low speed, ultra low speed, and high speed. During operation, the gate voltage change rate is controlled at different rates in order of high-speed, ultra-low speed, low-speed, and high-speed, and drive control is performed so that the drain current of the semiconductor switch changes linearly. It is characterized by.

The switching regulator of the present invention is connected between a gate terminal of the semiconductor switch and a first power source, and has a first switch means for holding the semiconductor switch in an off state, the gate terminal and a second power source. A second switch means connected between the power source and holding the semiconductor switch in an ON state ; a capacitor having a different capacitance; and a reset switch for resetting the charge amount of the capacitor to an initial value; A plurality of current injection circuits connected to the gate terminal via a reverse current prevention diode to control the amount of charge injected into the gate terminal, capacitors having different capacities, and the charge amount of the capacitor are initially set It consists of a reset switch that resets to a value, and a reverse current prevention diode is connected to the gate terminal. Connected Te, generating a plurality of current discharge circuit for controlling the amount of charge discharged from the gate terminal, a timing signal to the first, second switching means, and said current injection circuit and the current discharge circuit The switching period in the semiconductor switch is set, and the switching period is divided into a plurality of charge injection periods in which charge injection from the current injection circuit has different speeds, or charge discharge from the current emission circuit And a timing setting means for dividing the plurality of charge discharge periods into different charge discharge periods , wherein the semiconductor switch has a charge injection speed to the gate terminal in the current injection circuit and a current discharge circuit in the current discharge circuit. to be switchable switched respectively controlled by the speed of the charge released from the gate terminal And butterflies.

According to the present invention, there is an advantage that the change in the gate voltage can be precisely controlled by configuring the semiconductor switch in the output stage with a MOS transistor.
In addition, by precisely controlling the gate voltage change of the semiconductor switch, the current change (di / dt) flowing through the semiconductor switch can always be kept within a certain range, and the input at the time of switching due to the parasitic inductance (L) can be suppressed. The fluctuation of the output voltage can be made less than or equal to L × (di / dt).

  Furthermore, since the semiconductor switch at the output stage constituted by the MOS transistor becomes a capacitive load, the power consumption required for driving the semiconductor switch can be minimized by controlling the current injection and the current discharge to the gate terminal.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a circuit configuration of a switching regulator according to an embodiment of the present invention.
In the figure, a semiconductor switch Q3 is a P-channel type MOSFET corresponding to the semiconductor switch Q11 of FIG. 5, and its drain terminal is grounded via a diode D1, to which an output inductor L and an output capacitor C are connected. Thus, an asynchronous and step-down switching power supply circuit is configured. That is, one end of the output inductor L is connected to the connection point (node N) of the semiconductor switch Q3 and the diode D1, the other end of the output inductor L is grounded via the output capacitor C, and also to the output terminal 5. It is connected.

  Therefore, when the semiconductor switch Q3 is turned on for a predetermined period, a direct current flows into the output capacitor C from the power supply terminal 4 to which the input power supply voltage Vdd is applied via the semiconductor switch Q3 and the output inductor L. Even when the predetermined output voltage Vout is generated and the semiconductor switch Q3 is subsequently turned off, the output voltage Vout is held at the output terminal 5.

  The transistor Q1 is a P-channel type MOSFET similar to the semiconductor switch Q3, and the power supply terminal 4 to which the input power supply voltage Vdd is applied and the source terminal are connected. The transistor Q1 functions as first switch means for holding the semiconductor switch Q3 in an off state, and its drain terminal is connected to the gate terminal of the semiconductor switch Q3. The transistor Q2 is an N-channel MOSFET, and is provided so as to connect the gate terminal of the semiconductor switch Q3 and the ground, and functions as second switch means for holding the semiconductor switch Q3 in the on state. .

  The switching regulator shown in FIG. 1 further includes a charge control circuit 6, a discharge control circuit 7, and timing pulse generation circuits 8 and 9, and these circuits 6 to 8 are drive circuits corresponding to the driver 1 of FIG. A stepped voltage signal waveform is generated for the gate terminal of the semiconductor switch Q3. Among these, the charge control circuit 6 and the discharge control circuit 7 are respectively composed of three current injection circuits 61 to 63 and three current discharge circuits 71 to 73, all connected to the gate terminal of the semiconductor switch Q3. The gate potential is determined.

  Of the timing setting circuit 10 constituted by the two timing pulse generation circuits 8 and 9, the timing pulse generation circuit 8 supplies timing pulses to the transistor Q1 and the charge control circuit 6, respectively. Supplies timing pulses to the transistor Q2 and the discharge control circuit 7, respectively. In the timing setting circuit 10, the timing pulse generation circuit 8 controls the on / off period of the transistor Q1, and the output signals from the three current injection circuits 61 to 63 are controlled so that the semiconductor switch Q3 is switched. In the turn-off period, a control sequence divided into a plurality of charge injection periods in which charge injection is performed at different speeds is executed. The other timing pulse generation circuit 9 of the timing setting circuit 10 controls the on / off period of the transistor Q2 and also controls the output signals from the three current emission circuits 71 to 73 to control the semiconductor switch Q3. During the turn-on period, the control sequence divided into a plurality of charge discharge periods with different charge discharge speeds is executed.

  FIG. 2A is a circuit diagram showing a specific configuration of the current injection circuit. Here, although the current injection circuit 61 constituting the charge control circuit 6 will be described, the other current injection circuits 62 and 63 are also configured in the same manner as that shown in FIG.

  The current injection circuit 61 includes a buffer circuit DvA connected in series, a capacitor CA, and an N-channel type transistor QA serving as a reset switch. In this current injection circuit 61, the transistor QA is normally turned off, and a node corresponding to the amount of electric charge accumulated in the capacitor CA by the pulse signal SA input from the timing pulse generation circuit 8 to the capacitor CA via the buffer circuit DvA. The voltage VA is determined, and the voltage signal VgA is output to the gate terminal of the semiconductor switch Q3 via the diode DA connected in the forward direction. A one-shot pulse signal SD is input from the timing pulse generation circuit 8 to the gate terminal of the transistor QA. When the transistor QA is turned on by the pulse signal SD, the charge accumulated in the capacitor CA is discharged. The node voltage VA is reset to the ground potential.

  That is, in the current injection circuit 61 of the charge control circuit 6, the magnitude of the node voltage VA at the connection point between the capacitor CA and the diode DA is determined by these pulse signals SA and SD, and the magnitude of the node voltage VA. The timing for outputting the voltage signal VgA according to this is determined. During the turn-off period in the semiconductor switch Q3, the voltage signals VgB and VgC corresponding to the amounts of charge accumulated in the similar capacitors CB and CC from the other current injection circuits 62 and 63 of the charge control circuit 6 are set, respectively. Is output to the gate terminal of the semiconductor switch Q3. Therefore, the current injection circuits 61 to 63 constituting the charge control circuit 6 can control the gate voltage of the semiconductor switch Q3 at different change rates stepwise according to the respective charge injection amounts. In addition, these current injection circuits 61 to 63 have an advantage that the amount of charge injection (electron extraction) can be accurately defined by using the diode DA connected in the forward direction with the capacitor CA.

  FIG. 2B is a circuit diagram showing a specific configuration of the current emission circuit. Here, although the current emission circuit 71 constituting the discharge control circuit 7 will be described, the other current emission circuits 72 and 73 are also configured in the same manner as in FIG.

  The current discharge circuit 71 includes a buffer circuit DvF connected in series, a capacitor CF, and a P-channel type transistor QF serving as a reset switch. In this current emission circuit 71, the transistor QF is normally off and the node voltage VF of the capacitor CF is held at the input power supply voltage Vdd, but is input from the timing pulse generation circuit 9 to the capacitor CF via the buffer circuit DvF. The accumulated signal in the capacitor CF is discharged by the pulse signal SF, and the voltage signal VgF is output to the gate terminal of the semiconductor switch Q3 via the diode DF connected in the reverse direction. The one-shot pulse signal SI is input from the timing pulse generation circuit 9 to the gate terminal of the transistor QF. When the transistor QF is turned on by the pulse signal SI, the capacitor CF is charged with a charge amount, and the node The voltage VF is reset to the input power supply voltage Vdd.

  That is, in the current emission circuit 71 of the discharge control circuit 7, the magnitude of the node voltage VF at the connection point between the capacitor CF and the diode DF is determined by these pulse signals SF and SI, and the magnitude of the node voltage VF is determined. The timing for outputting the voltage signal VgF is determined accordingly. Then, during the turn-on period in the semiconductor switch Q3, voltage signals VgG and VgH corresponding to the charge amounts accumulated in the similar capacitors CG and CH from the other current discharge circuits 72 and 73 of the discharge control circuit 7 are set, respectively. Is output to the gate terminal of the semiconductor switch Q3. Therefore, the current emission circuits 71 to 73 constituting the discharge control circuit 7 can control the gate voltage of the semiconductor switch Q3 at different rates of change in stages according to the respective charge emission rates. Moreover, these current emission circuits 71 to 73 have an advantage that the amount of charge emission (electron injection) can be accurately defined by using the diode DF connected in the reverse direction to the capacitor CF.

Next, a specific control sequence of the gate voltage in the switching regulator described above will be described.
Consider a case where the semiconductor switch Q3 is a P-channel MOSFET, for example, and its gate terminal is controlled by a stepped voltage. By injecting charges into the semiconductor switch Q3 in the on state in a predetermined control sequence, the gate voltage can be turned off while being controlled stepwise with different rates of change.

  First, the gate voltage is increased at a stroke until the saturation current of the semiconductor switch Q3 becomes equal to the output current (first period). Next, in the period in which the drain voltage of the semiconductor switch Q3 suddenly changes, the change in the gate potential is slightly delayed (second period), and after the drain voltage of the semiconductor switch Q3 has dropped to the ground potential level, the gate potential is changed. Increase slowly as much as possible until the threshold voltage is reached (third period). Finally, after the gate potential exceeds the threshold value, the gate potential is raised again at high speed (fourth period), and the semiconductor switch Q3 is turned off. That is, the gate voltage of the semiconductor switch Q3 changes at a high speed during the first period, changes at a low speed during the second period, changes at a very low speed during the third period, and changes during the fourth period. In order to change again at high speed, a series of change rate control sequences are executed in the timing setting circuit 10 to drive and control the switching regulator.

  Next, the intention and purpose of changing the gate voltage at a predetermined speed at each timing by dividing the charge injection period into first to fourth periods by such a series of change rate control sequences will be described. .

  In the first period, the semiconductor switch Q1 operates in the linear region. Since the transistor constituting the semiconductor switch Q1 is large in size and has a sufficient saturation current, a current drawn to the output inductor L can be output even when the gate voltage is increased. In addition, since the on-resistance of the transistor constituting the semiconductor switch Q1 is small and the voltage difference between the source and drain is small, the drain-node voltage Vsw of the semiconductor switch Q1 does not change so much. Therefore, in the first period, although the drain-node voltage Vsw slightly changes, the output current does not decrease, so it can be said that the switching is not strictly performed. In order to change the output current by setting the first period short and using the switching transition time as much as possible, the gate voltage is increased at once.

  In the second period, the semiconductor switch Q1 enters the saturation region. As a result, the source-drain voltage increases. Therefore, the drain-node voltage Vsw changes greatly, but the current change is not large. This is proved also from an actual measurement result in which ringing occurs slightly after the sudden change of the drain node voltage Vsw. Therefore, in the second period, the gate potential may be increased more slowly than in the first period.

In the third period, the semiconductor switch Q1 completely enters the saturation region. This is a period in which the gate voltage of the semiconductor switch Q1 approaches the threshold value V _T and the N-channel parasitic diode is turned on. By taking the third period the longest and slowly changing the gate potential, the current change rate can be suppressed.

In the saturation region of the drain current ID, for example, ID = K (V _GS −V _T ) ²
In the case of a simple quadratic curve, the gate voltage V _GS necessary for making the current change rate dID / dt of the drain current ID constant is:
V _GS = V _T + {(A−B · t) / K} ^1/2 (1)
It becomes. Here, V _GS is a gate-source voltage, t is time, and K, A, and B are constants.

  Therefore, the gate voltage change of the semiconductor switch Q3 is first fast and gradually slows down. Unlike the conventional gate voltage controlled at a constant rate of change, the above-described gate voltage control sequence makes it possible to keep the current rate of change constant.

  In the fourth period, the gate potential is approximately around the threshold value, and the current change is small because the semiconductor switch Q1 is almost off. Therefore, the fourth period may be short, and the gate voltage can be rapidly changed to the input power supply voltage Vdd.

  Next, a description will be given of a charge discharge period in which charges are discharged from the semiconductor switch Q3 in the off state in a predetermined control sequence so that the gate voltage is turned on while being controlled at different rates of change in stages. In the control sequence of the charge discharge period, the gate potential of the semiconductor switch Q3 may be changed by reversing the above-described change rate control sequence.

  That is, first, the gate voltage is rapidly lowered to the threshold value, and the semiconductor switch Q3 is turned on. Next, until the saturation current of the semiconductor switch Q3 becomes equal to the output current, the gate potential is lowered slowly as much as possible to make the gate potential change slightly faster around the point where the saturation current becomes equal to the output current. After the drain voltage becomes sufficiently high, the gate voltage is lowered all at once to achieve a full-on state.

  As described above, in order to control the gate voltage at different rates of change in stages, the charging speed for the gate terminal of the semiconductor switch Q3 is changed from high speed → low speed → ultra low speed → high speed and the discharge speed is high speed → ultra low speed → It is necessary to change in four stages, low speed → high speed. In addition, when the switching frequency is on the order of MHz, a series of change rate control sequences must be completed in about 50 ns.

  Then, the timing pulse generation circuits 8 and 9 for realizing the switching regulator drive control method of the present invention and the signal waveforms generated therein will be described below. FIGS. 3A and 3B are circuit diagrams showing a specific configuration of the timing pulse generation circuit constituting the timing setting circuit. FIG. 4 is a signal waveform diagram showing the clock signals Φ1 and Φ2, the gate potential VE of the semiconductor switch Q3, the pulse width modulation signal PWM, and the timing pulses SA to SJ output from the timing setting circuit 10.

The timing pulse generation circuit 8 shown in FIG. 3A includes a one-shot circuit 81, a delay circuit 82, four AND gates G1 to G4, and an inverter Iv1.
The one-shot circuit 81 includes an inverter type buffer Dv5, a capacitor C5, and an AND gate G5, and a clock signal Φ1 is input from an oscillator 31 corresponding to the oscillator 3 shown in FIG. The clock signal Φ1 is a timing signal having a cycle shown in FIG. 4A, and is supplied to one input terminal of the AND gate G5. The other input terminal of the AND gate G5 is predetermined by a buffer Dv5 and a capacitor C5. A timing signal delayed by time T and held by the capacitor C5 is supplied. Therefore, the one-shot circuit 81 outputs a pulse signal SD having a one-shot high level (H level) period T as shown in FIG.

  The delay circuit 82 includes four cascaded buffers Dv1 to Dv4 and four capacitors C1 to C4, and is a pulse width modulation circuit (hereinafter referred to as a PWM circuit) corresponding to the comparator 2 shown in FIG. .) The pulse width modulation signal PWM from 21 is input to the buffer Dv1. The output terminals of the four buffers Dv1 to Dv4 are grounded via capacitors C1 to C4, respectively, and each connection point is connected to one input terminal of the AND gates G1 to G4. Each of the buffers Dv1 to Dv4 is configured to transfer the pulse width modulation signal PWM with delay times Ta, Tb, Tc, and Te while being sequentially held by the capacitors C1 to C4.

  The other input terminals of the AND gates G1 to G3 are respectively connected to the oscillator 31, the clock signal Φ1 from the oscillator 31 is input, and the other input terminal of the AND gate G4 is connected to the PWM circuit 21. A pulse width modulation signal PWM is input. An inverter Iv1 is connected to the output terminal side of the AND gate G4. Timing pulses SA to SC shown in FIGS. 4E to 4G are output from the AND gates G1 to G3 with respect to the pulse width modulation signal PWM which becomes H level at the timing shown in FIG. From Iv1, a timing pulse SE shown in FIG.

  Next, a control sequence for the charge injection period will be described. The charge control circuit 6 and the transistor Q1 are controlled by the timing pulses SA to SE, the gate voltage of the semiconductor switch Q3 is raised, and the switching operation from the on state to the off state is executed.

  First, the timing pulse SA changes from L level to H level with a delay of time Ta after the pulse width modulation signal PWM becomes H level. As a result, the node voltage VA of the capacitor CA in the current injection circuit 61 starts to change from the L level to the H level. Here, the node voltage VA actually does not completely reach the H level due to the influence of the parasitic capacitance or the like. However, since the capacitance of the capacitor CA is much larger than the parasitic capacitance, the node voltage VA is almost at the H level. Can be considered.

  Since the gate potential VE of the semiconductor switch Q3 in the on state is the ground potential Gnd and positive charges are injected into the gate terminal through the diode DA, the gate potential VE of the semiconductor switch Q3 is equal to the capacitance of the capacitor CA. It changes according to the ratio with the gate capacitance of the semiconductor switch Q3. Therefore, the capacitance of the capacitor CA may be set so that the gate voltage is increased at a stroke until the saturation current of the semiconductor switch Q3 becomes equal to the output current. Thereby, the change of the gate voltage in the first period can be given accurately.

  After the timing pulse SA changes, the timing pulse SB similarly changes from the L level to the H level with a delay of time Tb. As a result, the voltage signal VgB having a magnitude corresponding to the amount of charge defined by the capacitor CB (not shown) is output from the current injection circuit 62, and the gate potential VE changes by a specified amount. However, at this time, the output resistance of the buffer circuit DvB (not shown) in the current injection circuit 62 is raised in order to slightly slow down the voltage change.

  As a result, the source-drain voltage of the semiconductor switch Q3 increases, and the potential change occurs in the second period described above. Subsequently, the timing pulse SC is changed from the L level to the H level with a delay of the time Tc, so that the timing pulse SC is set to be sufficiently longer than the first and second periods and is approximately the same as the switching time. The buffer circuit DvC (not shown) is set to a higher output resistance, and a change in the gate voltage corresponding to the third period described above occurs.

  That is, the node voltage VC in the current injection circuit 63 becomes H level due to the charge of the capacitor CC (not shown), positive charge is injected through the diode DC, and a necessary voltage change in the gate potential VE of the semiconductor switch Q3. Is completed.

  After the change of the timing pulse SC is completed, the timing pulse SE changes to the L level with a delay of time Te. The change in the timing pulse SE turns on the transistor Q1, and the gate potential VE of the semiconductor switch Q3 is fixed at the H level. Thereby, the voltage change in the fourth period is completed. After the gate potential VE is fixed to the H level, the transistors QA to QC of the current injection circuits 61 to 63 are turned on, so that the capacitors CA to CC are reset and the node voltages VA, VB, and VC are set to the L level. The timing pulses SA, SB, and SC are also returned to the L level.

  In the current injection circuits 61 to 63 described above, errors due to various parasitic capacitances and voltage drop corresponding to the diode forward voltage occur in each element constituting the current injection circuits 61 to 63. In practice, however, the capacitance value and the reset level are optimized. You can deal with it.

  In order to switch the semiconductor switch Q3 from the OFF state to the ON state, a control sequence is executed in which the discharge control circuit 7 and the transistor Q2 are controlled by the timing pulses SF to SJ to lower the gate voltage VE of the semiconductor switch Q3. However, in this case, contrary to the above-described control sequence, timing pulses SF to SJ that transition from the H level to the L level are used, and the reset level of the node voltage VF such as the capacitor CF is set as the input power supply voltage Vdd.

  Although the timing setting circuit 10 shown in FIG. 3 generates the timing pulses SA to SJ using the digital circuit elements and the clock signals Φ1 and Φ2, the control sequence is fast and the signal timing can be fixed. Therefore, it is possible to replace it with a delay line or the like. In addition, the gate voltage of the semiconductor switch Q3 is ideally set as shown in the above equation (1). However, even when approximated by a straight line as described above, noise can be suppressed if the change is slow. In order to simplify the explanation, the charge control circuit 6 and the discharge control circuit 7 are constituted by three current injection circuits 61 to 63 and current discharge circuits 71 to 73, respectively. It is also possible to make the gate voltage of the semiconductor switch Q3 pseudo approximate to the above equation (1) by further increasing the number of stages constituting the above.

  As described above, in the switching regulator drive control method of the present invention, the step-like voltage control can be performed by using the switching period to the maximum, so that the low slew rate that uniformly delays the gate potential change as in the conventional case. Unlike the method, there is an advantage that an ideal linear output current can be obtained.

  In the switching regulator according to the present invention, the control sequence for the semiconductor switch Q3 on the power supply terminal 4 side has been described. However, when the synchronous power supply device is configured, the semiconductor switch on the ground side (Q12 in FIG. 5) is used. ) Can be driven by the same control sequence.

  It should be noted that the switching regulator according to the present invention can control either the synchronous or asynchronous system, the step-down type or the step-up type as long as the output transistor is controlled so that the rate of change of the input / output current is constant. Needless to say, it can also be applied to regulators.

It is a circuit diagram which shows the circuit structure of the switching regulator which concerns on embodiment of this invention. (A) is a circuit diagram showing a specific configuration of the current injection circuit, (B) is a circuit diagram showing a specific configuration of the current emission circuit. (A), (B) is a circuit diagram which shows the concrete structure of the timing pulse generation circuit which comprises a timing setting circuit. (A) and (b) are clock signals, (c) is a gate voltage waveform of a semiconductor switch, (d) is a PWM signal, and (e) to (n) are timing pulses SA to SJ output from a timing setting circuit. It is a signal waveform diagram shown. It is a circuit diagram which shows the circuit structure of the conventional switching regulator.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Driver 2 Comparator 3 Oscillator 4 Power supply terminal 5 Output terminal 6 Charge control circuit 7 Discharge control circuit 8, 9 Timing pulse generation circuit 10 Timing setting circuit 61-63 Current injection circuit 71-73 Current discharge circuit C Output capacitor CA, CF Capacitor (capacitor)
D1 diode DA, DF diode DvA, DvF buffer circuit L output inductor Q1 transistor (first switch means)
Q2 transistor (second switch means)
Q3 Semiconductor switch QA transistor (reset switch)
QF transistor (reset switch)

Claims (2)

In a switching regulator drive control method for converting DC voltage by switching operation of a semiconductor switch,
In the switching operation from on to off of the semiconductor switch, the change rate of the gate voltage of the semiconductor switch is changed in the order of high speed, low speed, ultra low speed, and high speed in the switching operation from off to on. Driving control of a switching regulator, characterized in that control is performed so that the drain current of the semiconductor switch changes linearly by controlling at different change rates stepwise in order of high speed, ultra low speed, low speed, and high speed. Method. In a switching regulator that converts DC voltage by switching operation of a semiconductor switch,
  First switch means connected between a gate terminal of the semiconductor switch and a first power supply, and holding the semiconductor switch in an off state;
  A second switch means connected between the gate terminal and a second power supply for holding the semiconductor switch in an ON state;
  Charges that are composed of capacitors having different capacities and a reset switch that resets the charge amount of the capacitors to an initial value, are connected to the gate terminal via a diode for preventing reverse current, and are injected into the gate terminal A plurality of current injection circuits for controlling the amount;
  A capacitor having different capacitances and a reset switch that resets the charge amount of the capacitor to an initial value, and is connected to the gate terminal via a diode for preventing reverse current and discharged from the gate terminal A plurality of current emission circuits for controlling the amount;
  A timing signal to the first and second switch means, the current injection circuit and the current emission circuit is generated to set a switching period in the semiconductor switch, and the switching period is set from the current injection circuit. A timing setting means for dividing the charge injection into a plurality of charge injection periods each having a different speed, or for dividing the charge discharge from the current discharge circuit into a plurality of charge discharge periods each having a different speed;
  With
  The semiconductor switch is switching-controlled to be switchable according to a charge injection speed to the gate terminal in the current injection circuit and a charge discharge speed from the gate terminal in the current discharge circuit, respectively. Switching regulator.

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