JP4595431B2 - Dry etching method and dry etching apparatus - Google Patents

Description

  The present invention relates to dry etching applied to a microfabrication field such as a semiconductor manufacturing mask manufacturing process, a semiconductor manufacturing process, and a display substrate manufacturing process, and in particular, a dry etching that does not destroy a membrane such as an EB mask. The present invention relates to an etching method and a dry etching apparatus.

  In order to increase the density of semiconductor integrated circuits, miniaturization of dimensional width such as device wiring and a method of forming connection holes play a major role. A pattern with a size of 65 nm or less is being put into practical use for these dimensions, but the realization of such a fine pattern is largely due to the development of dry etching technology. Also, in the display field such as a liquid crystal display and a plasma display, the flow of high density, miniaturization, and large diameter is exactly the same as that of a semiconductor integrated circuit. Hereinafter, a dry etching technique in the semiconductor field will be described as an example.

  First, the dry etching technique will be described with reference to FIG. FIG. 1 is an explanatory view showing a dry etching apparatus using a general inductively coupled plasma (ICP) method. A reactive gas is introduced into the vacuum chamber 1 and energy is input by a high-frequency oscillator 2 for generating ICP plasma, whereby the reactive gas is ionized and dissociated to generate plasma 3. The wafer 5 fixed on the cathode stage 4 in the vacuum chamber 1 is etched by radicals and ions generated in the plasma.

The cathode stage is connected to a high frequency oscillator 6 for RF bias control, and the etching characteristics such as vertical etching and etching rate are controlled by controlling the kinetic energy of ions incident on the wafer. There are an electrostatic chuck method and a mechanical chuck method for fixing the wafer to the cathode stage.
Wafer temperature is one of the important parameters because the temperature of the wafer during etching greatly affects the etching characteristics such as processing dimensions and etching depth. Therefore, in order to realize a more precise process, it is generally required to cool the wafer and make the temperature distribution of the wafer uniform. For this reason, various ideas have been made on the cathode stage.

  The first prior art is shown in FIG. As described in Japanese Patent Application Laid-Open Nos. 58-32410 and 60-115226, the first conventional technique is such that the temperature of the stage 13 during etching is set to a certain temperature by a heat exchanger. And is maintained at a set temperature by the chiller piping 15 for heating and cooling. In order to conduct heat conduction between the stage 13 and the wafer 12 efficiently, a gas for heat conduction (a rare gas such as He) is filled between them at a pressure of several Torr, thereby controlling the temperature of the wafer.

  However, in this method, the heat conduction gas leaks in the vicinity of the wafer periphery, but the pressure is low, so even if the heat from the plasma is uniform within the wafer surface, the temperature at the wafer periphery may increase. In a dry etching apparatus that comes into contact with the stage only at the periphery of the wafer, problems such as a high temperature at the center of the wafer occur. Further, when the heat input from the plasma is not uniform, a temperature distribution corresponding to that occurs on the wafer, and the distribution cannot be improved or corrected.

As means for solving this problem, a second prior art is shown in FIG. As described in JP-A-8-191059, the second prior art divides the stage 19 into a plurality of regions and independently controls each of them by independent heaters 16 so that the temperature distribution of the wafer 18 is obtained. It is possible to improve or intentionally have a temperature distribution. In this method, the wafer temperature is controlled by independent control of the heater, but since the heat conduction gas is one system as in the first prior art, the pressure of the heat conduction gas is controlled for each region. I can't.

  Therefore, the material to be etched is an EPL (Electron Projection Lithography) mask, a LEEPL (Low Energy E-beam Proximity Projection Lithography) mask, an EB partial batch exposure mask, an X-ray mask, an IPL (Ion Projection Lithium mask), and an IPL mask. In the case of a membrane mask such as FIG. 4 (FIG. 4), the membrane mask has a membrane region 21 having a film thickness of submicron to several tens of microns and a bulk region 22 other than the membrane region 21 in one wafer. When etching is performed using the first and second conventional techniques, the membrane is destroyed by the differential pressure between the process gas pressure in the vacuum chamber and the gas pressure for heat conduction. Cormorant.

In addition, if the heat conduction gas pressure is reduced or the flow rate is reduced to zero to avoid membrane breakage, the membrane will not break, but the bulk region will also be insufficiently cooled, resulting in insufficient cooling of the entire sample. As a result, the etching characteristics such as the selectivity with the resist are greatly reduced. 4A and 4B are schematic views of a general EB mask, FIG. 4A is a plan view from above of the EB mask, and FIG. 4B is a cross-sectional view taken along line AB in FIG. .
JP 58-32410 A JP-A-60-115226 Japanese Patent Laid-Open No. 8-191059

  In recent years, with the progress of higher integration, miniaturization, and higher performance of semiconductor devices found in VLSI, ULSI, etc., the technical requirements for dry etching technology, which is the main process of semiconductor device manufacturing, have become increasingly severe. However, new dry etching is also used in the manufacture of EB masks such as EPL masks, LEEPL masks, EB partial batch exposure masks, X-ray masks, and IPL masks, which play an important role in lithography technology used in semiconductor device manufacturing. Technology is required.

These EB masks, X-ray masks, IPL masks, and masks for ion implanters have a membrane region with a thickness of submicron to several tens of microns and a bulk region other than that within one mask surface. ing. When microetching the membrane region by dry etching, if dry etching is performed by the first and second conventional techniques, there is a large pressure difference between the process pressure in the vacuum chamber and the pressure due to the heat conduction gas between the stage and the wafer. This will destroy the membrane.
Also, if the pressure of the heat conduction gas is lowered or the flow rate is reduced to zero to avoid the destruction of the membrane, the membrane will not break, but the cooling of the entire EB mask, X-ray mask, and IPL mask will be insufficient. Etching characteristics such as a decrease in selectivity with a resist are greatly deteriorated.

The present invention solves the problems of the prior art as described above, without destroying the membrane during dry etching of the membrane in an EB mask, an X-ray mask, an IPL mask, or an ion implantation apparatus mask. It is another object of the present invention to provide a dry etching method and a dry etching apparatus that do not deteriorate etching characteristics. Further, the present invention is not limited to the EB mask, the X-ray mask, the IPL mask, and the ion implantation apparatus mask, but can be applied to various dry etching such as a display substrate as necessary.

The present invention divides a stage into a peripheral area and a central area in a method of performing dry etching while introducing a heat conduction gas for promoting cooling or heating of the SOI substrate between an 8-inch φ SOI substrate and the stage. The peripheral region is set to a stage temperature of 25 ° C. and a heat conduction gas pressure of 6 Torr, and the central region is set to a stage temperature of 15 ° C. and a heat conduction gas pressure of 2 Torr to perform dry etching. This is a dry etching method.

In a dry etching apparatus that performs dry etching while introducing a heat conduction gas for promoting cooling or heating of the SOI substrate between an 8-inch φ SOI substrate and the stage,
1) A stage divided into a peripheral region and a central region by a partition,
2) A mechanism for setting and maintaining the stage temperature at 25 ° C in the peripheral region and 15 ° C in the central region ,
3) A mechanism for setting and maintaining the heat conduction gas flow rate and pressure at 6 Torr in the peripheral region and 2 Torr in the central region ,
Is a dry etching apparatus characterized by comprising:

  Further, the present invention is the dry etching apparatus according to the above invention, wherein the heat conduction gas is He or Ar.

  The present invention is a dry etching method in which the stage is divided into several regions, and the dry etching is performed by setting the stage temperature, the heat conduction gas flow rate and the pressure for each region. It is possible to perform dry etching with sufficient cooling without destroying a sample such as an EB mask, which is easily broken by the pressure of. Since the pressure and temperature of the heat conduction gas can be controlled for each region of the substrate, etching with favorable etching characteristics such as line width, resist selection ratio, pattern shape and the like can be performed.

  The present invention also includes 1) a stage integrally divided into several regions by a partition, 2) a mechanism for setting and maintaining the stage temperature for each divided stage, and 3) for each divided stage. Since it is a dry etching apparatus equipped with a mechanism for setting and maintaining the heat conduction gas flow rate and pressure, without destroying a sample such as an EB mask that is easily broken by the pressure of the heat conduction gas on the back surface of the substrate, and A dry etching apparatus capable of performing etching with sufficient cooling.

The present invention will be described below based on one embodiment.
5 and 6 are explanatory views of the cathode stage unit 23 of the dry etching apparatus of the present invention. 5 is a plan view from above of the cathode stage unit, and FIG. 6 is a cross-sectional view taken along line XY of FIG.

  As shown in FIGS. 5 and 6, the wafer contact surface of the cathode stage unit 23 is an electrostatic chuck 24, which can attract the wafer by electrostatic force. The electrostatic chuck is divided into blocks 26 a to 26 i by a partition 25. Each divided block includes a chiller pipe for heating and cooling (27a to 27e in FIG. 6) and a heat conduction gas inlet port 28a to 28i. The chiller temperature control and heat conduction are provided for each block. The pressure and flow rate of the working gas can be controlled.

In the example shown in FIG. 5, the cathode stage unit 23 is divided into nine blocks (26a to 26i). However, it is better to arbitrarily design the cathode stage unit 23 according to the structure of the sample to be processed. In addition, if the number of blocks is increased, finer control of the temperature of the sample, the gas pressure and heat flow for heat conduction on the back surface is possible, but a flow controller, pressure gauge, chiller temperature controller, piping, etc. are required for the number of blocks. It becomes.

  In the method of the present invention, the material to be etched, the mask material, and the etching gas are not particularly limited as long as dry etching is possible. The plasma generation method of the etching apparatus includes parallel plate type, capacitive coupling type (CCP), inductive coupling type (ICP), ultra high frequency type (UHF), electron cyclotron resonance type (ECR), microwave type, and helicon wave type. There is no limitation such as surface wave type, and all these plasma generation methods can be used.

<Reference example>
Hereinafter, Example 1 will be described as a reference example with reference to the drawings. A general ICP type dry etching apparatus and a cathode stage unit as a reference example were manufactured. The apparatus will be described with reference to FIGS. 7, 8, and 9. 7 is a schematic view of the entire apparatus, FIG. 8 is a plan view of the cathode stage unit from above, and FIG. 9 is a cross-sectional view taken along line XY of FIG.

  The high frequency oscillator 29 for generating ICP plasma shown in FIG. 7 uses a model number RF-20M (20 MHz, 2 kW) manufactured by PFPP, and the high frequency oscillator 30 for RF bias control is a model number AGC-6B (13 manufactured by ENI). .56 MHz, 600 W). The vacuum chamber 31 is a general vacuum chamber, which has a reaction gas supply port 32 and a reaction gas exhaust port 33. An upper part of the vacuum chamber is a coil 34 of an anode electrode for generating ICP plasma, and a lower part of the RF chamber is RF. A cathode stage unit 35 incorporating a bias cathode electrode is connected.

  The difference from a general ICP type dry etching apparatus is that the cathode stage unit 35 has a function of controlling the temperature, the flow rate of the heat conduction gas, and the pressure for each area of the stage. In this example, helium (He) was used as the heat conduction gas, and pure water was used as the temperature control chiller.

  As shown in FIGS. 8 and 9, the entire surface of the cathode stage unit 35 is an electrostatic chuck 40, and the wafer can be attracted by electrostatic force. In the first embodiment, the electrostatic chuck 40 is divided into the outer peripheral area A, the normal area B, and the central area C by the partition 41. In each region, a heat conduction gas (He) inlet 45 (45A-L, 45A-R, 45A-T, 45A-B, 45B-L, 45B-R, 45B-T, 45B-B, And 45C), and chiller piping 46 for heating and cooling (46A-L, 46A-R, 46A-T, 46A-B, 46B-L, 46B-R, 46B-T, 46B-B, and 46C) are provided. It has been.

Hereinafter, the dry etching method according to the present invention will be described with reference to an example in which dry etching is performed using the present apparatus shown in FIGS. First, as an experimental method, a silicon wafer 47 (8 inches φ) with a thermal oxide film 48 having a thickness of 1000 nm (T1) shown in FIG. 10A is prepared, and dry etching is performed as shown in FIG. 10B. The thermal oxide film 48 was thinned (T2).
The in-plane distribution of the etching rate was determined by measuring the thickness of the oxide film before and after etching with an optical film thickness meter.

As shown in Table 1, four types of conditions for the cathode stage unit were set. Condition 1 is that the stage temperature is 25 ° C. and He cooling is OFF (does not flow) in all regions, Condition 2 is that the stage temperature is 25 ° C. and He pressure is 6 Torr in all regions, and Condition 3 is that the stage temperature is in the region Each time, the temperature was changed by 5 ° C. and the He cooling was changed to 6 Torr in all regions, and in condition 4, the stage temperature was changed to 25 ° C. and the He cooling was changed to 2 Torr in all regions.
Other etching conditions are: plasma source: 500 W, bias power: 100 W, etching gas: CF ₄ = 20 sccm, pressure: fixed at 15 mTorr, and the in-plane distribution of the etching rate of the oxide film using only the conditions of the cathode stage unit as parameters. Was measured.

結果を図１１、図１２に示す。条件１の結果を図１１（ａ）に、条件２の結果を図１１（ｂ）に示してある。図１１（ａ）及び（ｂ）に示すように、条件１、条件２では、各領域毎のステージ温度制御や熱伝導用Ｈｅの圧力制御がされていないため、実際のウェハ上では中心領域Ｃの温度が高く、周辺が低いという温度分布が生じてしまい、その温度分布を反映したエッチングレートの分布が見られる。

The results are shown in FIGS. The result of condition 1 is shown in FIG. 11 (a), and the result of condition 2 is shown in FIG. 11 (b). As shown in FIGS. 11A and 11B, under conditions 1 and 2, stage temperature control for each region and pressure control for heat conduction He are not performed. A temperature distribution occurs in which the temperature is high and the periphery is low, and an etching rate distribution reflecting the temperature distribution is observed.

Further, in condition 3 shown in FIG. 12A, the stage temperature control is performed for each region, so that the in-plane distribution of the etching rate is made uniform. Further, as shown in FIG. 12B, in condition 4, since the pressure control of the heat conduction He is performed for each region, the in-plane distribution of the etching rate is made uniform.
As described above, the pressure control of the heat conduction He for each region has the same effect as the temperature control for each region.

  Next, an example in which an EB mask is manufactured using the second example of the dry etching apparatus of the present invention will be described. The apparatus main body other than the cathode stage unit has the same structure as that of the first embodiment (see FIG. 7). The cathode stage unit divides the electrostatic chuck 51 into the peripheral region D and the central region E by the partition 55 as shown in FIG. 13 so as to fit the membrane region 21 and the bulk region 22 of the EB mask as shown in FIG. did. Each region is provided with a heat conduction gas (He) inlet 54 and heating and cooling chiller piping (not shown) in the same manner as in the first embodiment. Has the function of controlling the gas flow rate and pressure.

In the second embodiment, first, an 8-inch φ SOI substrate is used as the EB mask, and after steps such as photolithography, EB lithography, wet etching, dry etching, and cleaning, as shown in FIG. A bulk region 22 having a thickness of approximately 500 μm and a membrane region 21 having a thickness of approximately 10 μm were formed.
Next, an EB resist 56 was coated (FIG. 14B), and a resist pattern 57 was formed by drawing and development (FIG. 14C). Thereafter, using the dry etching apparatus of the present invention, the main pattern was formed in the membrane region by dry etching under the conditions of the three types of cathode stages (FIG. 14D).

The conditions other than the dry etching cathode stage conditions were fixed at plasma source: 500 W, bias power: 150 W, etching gas: C ₃ F ₈ = 20 sccm, pressure: 10 mTorr, and only the cathode stage conditions were used as parameters. Table 2 shows the three types of stage conditions. Condition 1 has a stage temperature of 25 ° C. and a He cooling pressure of 6 Torr in both the central region E and the peripheral region D, and Condition 2 has a stage temperature of 25 ° C. and a He cooling pressure of 0 Torr (flow rate in both the central region E and the peripheral region D) In the condition 3, the stage temperature was lowered in the central region E, and the He cooling pressure was also reduced in the central region.

これら条件１、２、３でドライエッチングを実施した結果、条件１ではＨｅ冷却圧力により、ドライエッチング中にメンブレン破壊が生じた。条件２ではＨｅ冷却を切っているため、メンブレン破壊は発生しなかったが、メンブレン領域（特にウェハ中心）の温度上昇し、ウェハ中心のエッチングレートが大きいという面内分布が発生した（図１５（ａ）
）。条件３では、メンブレンを破壊することなく、メンブレン部を十分に冷却することが出来るため、エッチングレートの面内分布は非常に均一で良好であった（図１５（ｂ））。その後、レジスト剥離によりＥＢマスクの加工を完了させた（図１４（ｅ））。

As a result of performing dry etching under these conditions 1, 2, and 3, membrane breakage occurred during dry etching under the condition 1 under the He cooling pressure. In condition 2, since the He cooling was turned off, membrane destruction did not occur, but the temperature in the membrane region (particularly the wafer center) increased, and an in-plane distribution in which the etching rate at the wafer center was large occurred (FIG. 15 ( a)
). Under condition 3, since the membrane portion can be sufficiently cooled without destroying the membrane, the in-plane distribution of the etching rate was very uniform and good (FIG. 15B). Thereafter, the processing of the EB mask was completed by removing the resist (FIG. 14E).

It is explanatory drawing which showed the dry etching apparatus by a general inductively coupled plasma (ICP) system. It is explanatory drawing of the stage of the dry etching apparatus in 1st prior art. It is explanatory drawing of the stage of the dry etching apparatus in 2nd prior art. (A) is a top view which illustrates typically the membrane area | region and bulk area | region of a membrane mask. (B) is sectional drawing which illustrates typically the membrane area | region and bulk area | region of a membrane mask. It is a top view of the cathode stage unit of the dry etching apparatus of this invention. FIG. 6 is a cross-sectional view taken along line XY in FIG. 5. It is the schematic of the whole dry etching apparatus of this invention in Example 1,2. 3 is a plan view of a cathode stage unit in Embodiment 1. FIG. FIG. 9 is a cross-sectional view taken along line XY in FIG. 8. (A) is sectional drawing of the silicon wafer with a thermal oxide film before an etching. (B) is sectional drawing of the silicon wafer with a thermal oxide film after an etching. (A) is explanatory drawing of the result of the conditions 1 in Example 1. FIG. (B) is explanatory drawing of the result of the conditions 2 in Example 1. FIG. (A) is explanatory drawing of the result of the conditions 3 in Example 1. FIG. (B) is explanatory drawing of the result of the conditions 4 in Example 1. FIG. 6 is a plan view of a cathode stage unit in Embodiment 2. FIG. (A)-(e) is explanatory drawing of the process in Example 2. FIG. (A) is explanatory drawing of the result of the conditions 2 in Example 2. FIG. (B) is explanatory drawing of the result of the conditions 3 in Example 2. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 31 ... Vacuum chamber 2, 29 ... High frequency oscillator 3 for plasma generation ... Plasma 4 ... Cathode stage 5, 12, 18, 38 ... Wafer 6, 30 ... RF bias Control high frequency oscillator 7 ... blocking capacitors 8, 37, 39 ... matching units 9, 34 ... coils 10, 32 ... reaction gas supply port 11, 33 ... reaction gas exhaust port 13, 19 ... Stages 14, 28a to 28i, 45 ... Heat conduction gas inlets 15, 27a to 27e, 46 ... Heating and cooling chiller piping 16 ... Heaters 17, 25, 41, 55 ... partition 20, 54 ... heat conduction gas inlet 21 ... membrane region 22 ... bulk region 23, 35 ... cathode stage unit 24, 40, 51 ... electrostatic chuck 26a 26i ··· block (area)
36 ... Blocking capacitor 47 ... Silicon wafer 48 before etching 48 ... Thermal oxide film 49 ... Silicon 50 ... Silicon wafer 56 after etching ... EB resist 57 ... Resist pattern A ..Outer peripheral region B ... Normal region C, E ... Central region D ... Peripheral region

Claims (3)

In a method of performing dry etching while introducing a heat conduction gas for promoting cooling or heating of an SOI substrate between an 8-inch φ SOI substrate and the stage, the stage is divided into a square central region, the center The central area is set to a stage temperature of 15 ° C. and a heat conduction gas pressure of 2 Torr, and the peripheral area is set to a stage temperature of 25 ° C. and a heat conduction gas pressure of 6 Torr. Te, dry etching wherein the dry etching is performed. In a dry etching apparatus that performs dry etching while introducing a heat conduction gas for promoting cooling or heating of the SOI substrate between an 8-inch φ SOI substrate and a stage,
1) A stage divided by a partition into a square central region and a peripheral region located around the central region ;
2) a mechanism for setting and maintaining the stage temperature at 15 ° C. in the central region and 25 ° C. in the peripheral region ;
3) a mechanism for setting and maintaining the heat conduction gas flow rate and pressure at 2 Torr in the central region and 6 Torr in the peripheral region ;
A dry etching apparatus comprising:   The dry etching apparatus according to claim 2, wherein the heat conduction gas is He or Ar.

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