JP4592666B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device and a method of manufacturing the semiconductor memory device capable of realizing a high breakdown voltage of a transistor in a high-voltage peripheral circuit to which a high voltage is applied without adding a special process. Is.

  Conventionally, in a nonvolatile semiconductor memory device, a circuit using a high voltage of about 10 V or more (about 10 V to about 20 V) is provided in addition to the 5 V type which is the standard power supply voltage of the current LSI. This is a physical phenomenon that requires a strong electric field, such as channel hot electron injection (CHE injection) or FN (Fowler-Nordheim) tunnel injection, in order to inject or extract charges to the floating gate electrode surrounded by an insulating film. It is because it uses.

Here, the configuration of a DINOR type flash memory which is a kind of semiconductor nonvolatile memory device will be described with reference to FIG. In FIG. 59, reference numerals 101 _{11 to} 101 ₄₂ denote memory cells each having a source region, a drain region, a floating gate electrode, and a control gate electrode. The source region is formed from an n-type diffusion layer. The drain region is formed of an n-type diffusion layer formed separately from the source region. The floating gate electrode is formed on the channel region located between the source region and the drain region via a gate oxide film made of a tunnel oxide film. The control gate electrode is disposed to face the floating gate electrode with an interlayer insulating film interposed therebetween.

  For convenience of explanation, FIG. 59 shows only blocks 102a and 102b in which the erase operation is performed collectively in units of 2 rows and 2 columns in 4 rows and 2 columns. However, in the DINOR type flash memory, a plurality of memory cells 101 arranged in a matrix of a plurality of rows and a plurality of columns constitute a memory cell array. The memory cell array has a plurality of blocks 102 which are batch erase units. Each block 102 has a plurality of rows and a plurality of columns of memory cells 101. As will be described later, a plurality of memory cells 101 constituting each block 102 are one p-type well of a plurality of n-type well regions formed in a p-type well region formed on a semiconductor substrate. It is formed in the region. The memory cell 101 has a configuration in which a substrate potential is independently applied to each block 102 by applying a substrate potential to the n-type well region.

  In addition, the number of the subscript in a code | symbol shows a row and / or a column, and the alphabet shows the distinction of a block unit. Subscripts are omitted when referring generically. The same applies hereinafter.

The word lines 103 _{1 to} 103 ₄ are arranged in corresponding rows and connected to control gate electrodes of a plurality of memory cells 101 arranged in the corresponding rows. The word lines 103 _{1 to} 103 ₄ are composed of a polysilicon layer and a first metal layer. The polysilicon layer is integrally formed with a control gate electrode formed by a second polysilicon layer (the floating gate electrode is formed by the first polysilicon layer). The first metal layer is disposed in parallel above the polysilicon layer. The main bit lines 104 _{1 to} 104 ₂ are arranged in corresponding columns. The main bit lines 104 _{1 to} 104 ₂ are formed by a second metal layer disposed above the word line 103. The sub bit lines 105 _{1a to} 105 _2b are arranged in corresponding columns and for each corresponding block 102. The sub bit lines 105 _{1a to} 105 _2b are connected to the drain regions of the plurality of memory cells 101 in the corresponding block 102 in the corresponding column. The sub bit lines 105 _{1a to} 105 _2b are formed by a third polysilicon layer disposed above the polysilicon layer of the word line 103.

Select gates 106 _{1a to} 106 _2b are provided for each corresponding sub-bit line 104. Select gates 106 _{1a to} 106 _2b are formed of n-channel MOS transistors connected between corresponding sub-bit lines 104 and main bit lines 103 arranged in corresponding columns. The gate electrodes of the select gates 106 _{1a to} 106 _2b are formed of a second polysilicon layer. The source lines 107a to 107b are provided for each corresponding block 102. The source lines 107 a to 107 b are connected to the source regions of the plurality of memory cells 101 in the corresponding block 102. Well potential lines 108a to 108b are provided for the corresponding blocks 102, respectively. Well potential lines 108a to 108b are provided for the corresponding blocks 102, respectively. The well potential lines 108a to 108b are connected to the p-type well region in which the plurality of memory cells 101 are formed in order to give the substrate potential of the plurality of memory cells 101 in the corresponding block 102.

Block select signal lines 109a to 109b are provided for the corresponding blocks 102, respectively. The block select signal lines 109a to 109b are connected to gate electrodes (control electrodes) of a plurality of select gates 106 provided for the corresponding block 102. The input / output line 110 is for transmitting information to be written to the memory cell 101 and reading information stored in the memory cell 101. Transfer gates 111 _{1 to} 111 ₂ are provided for each corresponding main bit line 104. Transfer gates 111 _{1 to} 111 ₂ are formed of n-channel MOS transistors connected between corresponding main bit line 103 and input / output line 110. The gate electrodes of the transfer gates 111 _{1 to} 111 ₂ are formed of a second polysilicon layer. Column select signal lines 112 _{1 to} 112 ₂ are provided for the corresponding transfer gates 111 respectively. The column select signal lines 112 _{1 to} 112 ₂ are connected to the gate electrode (control electrode) of the corresponding transfer gate.

  Row decoder 113 receives a row address signal, a write / erase control signal, a first high potential (for example, 10 V) higher than a power supply potential (for example, 3.3 V), and a negative potential (for example, −8 V). Based on the write / control signal, a desired number of word lines 103 is selected from the plurality of word lines 103 (the number of word lines in a block unit at the time of erasure and one at the time of writing and reading). A selection potential is applied, and the other word lines 103 are maintained at the ground potential. The selection potential is, for example, a negative potential at the time of writing (in this example, the operation of extracting the electrons accumulated in the floating gate electrode is called writing), and the erasing (in this example, the operation of injecting electrons into the floating gate electrode is erased) The first high potential during reading, and the power supply potential during reading.

  Source / well decoder 114 receives a part of a row address signal, a part of a column address signal, a write / erase control signal, and a negative potential (for example, −8 V), and receives one of the write / erase control signal and the row address signal. Based on the part and part of the column address signal, source line 107 and well potential line 108 are set to desired potentials, and other source line 107 and well potential line 108 are set to ground potential. The desired potential is, for example, that all source lines 107 are floated (electrically floating) and all well potential lines 108 are set to the ground potential at the time of writing. Further, all the source lines 107 and all the well potential lines 108 are set to the ground potential at the time of reading. Further, a negative potential is applied to the source line 107 and the well potential line 108 corresponding to the block 102 selected by a part of the row address signal and a part of the column address signal at the time of erasing. The select gate decoder 115 includes a part of the row address signal, a part of the column address signal, a write / erase control signal, and a second high potential (for example, 3.3 V) that is higher than the first high potential (for example, 3.3 V). 6V), one of the plurality of block select signal lines 109 is selected on the basis of part of the row address signal and part of the column address signal, and write / erase control is performed on the selected block select signal line 109. A selection potential is applied based on the signal, and the other block select signal lines 109 are maintained at the ground potential state. The selection potential is, for example, a second high potential during writing, a ground potential during erasing, and a power supply potential during reading.

  Column decoder 116 receives a column address signal, a write / erase control signal, and a second high potential (for example, 6 V) that is higher than the power supply potential (for example, 3.3 V) and lower than the first high potential, and is based on the column address signal. One of the plurality of column select signal lines 112 is selected, a selected potential is applied to the selected column select signal line 112 based on the write / erase control signal, and the other column select signal lines 112 are set to the ground potential state. To maintain. The selection potential is, for example, a second high potential during writing, a ground potential during erasing, and a power supply potential during reading. Address buffer circuit 117 receives an address signal (row address signal and column address signal are input in time series) input to address input pad 118, and receives row decoder 113, source / well decoder 114, select gate decoder 115, and column. An address signal is supplied to the decoder 116.

  Write circuit 119 receives a write / erase control signal, data information, and a second high potential (eg, 6 V) that is higher than the power supply potential (eg, 3.3 V) and lower than the first high potential (eg, 6 V). When the signal indicates the time of writing and the data information input through the input / output pad 121 and the data input / output buffer 120 is programmed, the second high potential is applied to the input / output line 110. Sometimes the output is in a high impedance state. Sense amplifier 122 receives a write / erase control signal, and is activated when the write / erase control signal indicates reading, and applies a low potential (for example, 1.2 V) to input / output line 110 to allow current to flow. The read information from the memory cell 101 selected by amplification is output to the input / output pad 121 via the data input / output buffer 120.

  Second high voltage generation circuit 123 receives a write / erase control signal, and applies a first high potential (for example, 10 V) to row decoder 113 based on this write / erase control signal. The second high voltage generation circuit 124 receives a write / erase control signal, and based on the write / erase control signal, the second high voltage generation circuit 124 applies a second high potential (for example, 6V) to the select gate decoder 115, column decoder 116, and write circuit 119. )give. Negative potential generating circuit 125 receives a write / erase control signal, and applies a negative potential (for example, −8 V) to row decoder 113 and source / well decoder 114 based on the write / erase control signal. The chip 126 includes a row decoder 113, a source / well decoder 114, a select gate decoder 115, a column decoder 116, a write circuit 119, a sense amplifier 122, first and second high voltage generation circuits 123 and 124, and a negative voltage generation circuit 125. Is a write / erase control circuit for supplying a write / erase control signal to. A chip 127 is a chip in the nonvolatile semiconductor memory device.

  Note that row decoder 113, source / well decoder 114, select gate decoder 115, column decoder 116, address buffer circuit 117, write circuit 119, input / output buffer circuit 120, sense amplifier 122, and first and second high voltage generation circuits. 123 and 124, negative voltage generation circuit 125, and write / erase control circuit 126 write information to memory cell 101 of the memory cell array, read information stored in memory cell 101, and information stored in memory cell 1 Peripheral circuit for erasing the transistor, each having a plurality of n-channel MOS transistors and a plurality of p-channel MOS transistors, and their gate electrodes are formed by a second polysilicon layer Has been.

  Next, erase operation, write operation and read operation of the flash memory will be described with reference to FIG. In this example, the erase operation is an operation of injecting electrons into the floating gate electrode. In this example, the writing operation is an operation for extracting electrons accumulated in the floating gate electrode.

(Erase operation)
In this embodiment is what is collectively erased in units of blocks, collectively erase the memory cell 101 _11, 101 _12, 101 _21, 101 ₂₂ of the block 102a, a memory cell 101 ₃₁ other block 102b, 101 _32, 101 ₄₁ and 101 ₄₂ are not deleted.

  A signal for instructing batch erase from the outside is input to the write / erase control circuit 126. Then, the write / erase control circuit 126 sends a write / erase signal indicating erasure to the row decoder 113, source / well decoder 114, select gate decoder 115, column decoder 116, write circuit 119, sense amplifier 122, first and This is applied to second high voltage generation circuits 123 and 124 and negative voltage generation circuit 125 so that they can be erased collectively.

  On the other hand, an address signal is input to the address buffer circuit 117 via the address input pad 118. In this case, the address signal is a row address signal and a column address signal input in time series, which means that the block 102a is selected.

Upon receiving a write / erase signal indicating erasure from the write / erase control circuit 126 and an address signal from the address buffer 117, the row decoder 113 receives the memory cells 101 ₁₁ , 101 ₁₂ , 101 ₂₁ , the word line 103 _1, 103 ₂ are connected to the 101 ₂₂ providing a first high potential from the first high-voltage generating circuit 123 (e.g. 10V), the memory cell 101 ₃₁ of block 102b is not selected, 101 _32, 101 _41, 101 ₄₂ connected to the word line 103 _3, 103 ₄ of the potential is maintained at ground potential.

The source / well decoder 114 that has received a write / erase signal indicating erasure from the write / erase control circuit 126 and an address signal from the address buffer 117 also selects the memory cells 101 ₁₁ and 101 _{12 of} the block 102a to be selected. , 101 ₂₁ , 101 ₂₂ are supplied with a negative potential (for example, −8 V) from the negative voltage generation circuit 125 to the source line 107a, and the memory cells 101 ₃₁ , 101 ₃₂ , 101 ₄₁ , 101 ₄₂ of the unselected block 102b are supplied to the source line 107a. while maintaining the potential of the source line 107b is connected to the ground potential, the memory cell 101 _11, 101 _12, 101 _21, 101 ₂₂ negative voltage generating circuit to the well potential line 108a connected to the substrate 125 of block 102a for selecting A negative voltage (for example, -8V) is applied to the memory cell of the unselected block 102b. 101 _31, 101 _32, 101 _41, 101 ₄₂ potential wells potential line 108b connected to the substrate to ground potential. Here, the substrate of the memory cell 101 _11, 101 _12, 101 _21, 101 ₂₂ of block 102a for selecting a second well region 304a shown in FIG. 61. Further, the substrate of the memory cell 101 _31, 101 _32, 101 _41, 101 ₄₂ of block 102b is not selected, a second well region 304b shown in FIG. 61.

Further, the select gate decoder 115 receiving the write / erase signal indicating erasure from the write / erase control circuit 126 and the address signal from the address buffer 117 grounds the potentials of all the block select signal lines 109a and 109b. In order to maintain the potential, select gates 106 _{1a to} 106 _2b maintain a non-conductive state. The main bit lines 104 ₁ and 104 ₂ and the plurality of bit lines 105 _{1a to} 105 _2b are electrically disconnected. Further, the sub bit lines 105 _{1a to} 105 _2b are in an electrically floating state (floating).

Further, the column decoder that receives the write / erase signal indicating erasure from the write / erase control circuit 126 and the address signal from the address buffer 117 sets the potentials of all the column select signal lines 112 ₁ and 112 ₂ . In order to maintain the ground potential, the transfer gates 111 _{1 to} 111 ₂ maintain a non-conductive state. Further, the input / output line 110 and the main bit lines 104 ₁ and 104 ₂ are electrically disconnected. The main bit lines 104 ₁ and 104 ₂ are in an electrically floating state (floating).

  The write circuit 119 that has received a write / erase signal indicating erasure from the write / erase control circuit 126 has its output in a high impedance state. The sense amplifier 122 is in an inactive state.

Accordingly, the memory cell 101 _11, 101 _12, 101 _21, 101 ₂₂ of the block 102a to be selected, the control gate electrode and the first high potential (for example 10V), the source region a negative potential (e.g. -8 V), Since the drain region is floated and the substrate (well region 304a in FIG. 61) is set to a negative potential (for example, −8V), the substrate is located between the source region and the control gate electrode and between the source region and the drain region. Since a high electric field is applied between the surface region, that is, the channel region and the control gate electrode, the gate oxidation is located from the channel region and the source region to the floating gate electrode, directly below the floating gate electrode and on the channel region and the source region. Electrons are injected through the film by tunneling.

  As a result, electrons are accumulated in the floating gate, and the memory cell is erased by increasing the threshold value of the memory cell.

On the other hand, in the memory cell 101 _31, 101 _32, 101 _41, 101 ₄₂ of the block 102b not selected, since the control gate electrode to the ground potential, the source region is ground potential, the drain region is in a floating, the control gates A high electric field is not generated between the electrode and the source region, drain region, and channel region, and electrons are not injected into the floating gate electrode. Further, there is no extraction of electrons accumulated in the floating gate electrode.

In this way, batch erasure is performed for each block.
(Write operation)
Writing information to the memory cell 101 ₁₁ of the block 102a (program), the memory cell 101 _31, 101 _32, 101 _41, 101 ₄₂ of the other memory cells 101 _12, 101 _21, 101 ₂₂ and other blocks 102b Will not write any information.

  When a signal for instructing writing from the outside is input to the write / erase control circuit 126, the write / erase control circuit 126 sends a write / erase signal indicating writing to the row decoder 113 and the source / well. The decoder 114, the select gate decoder 115, the column decoder 116, the write circuit 119, the sense amplifier 122, the first and second high voltage generation circuits 123 and 124, and the negative voltage generation circuit 125 are supplied to these circuits for writing. State.

On the other hand, an address signal is input to the address buffer circuit 117 via the address input pad 118. In this case, a row address signal and column address signal input to the time series, which means that the address signal for selecting a memory cell 101 _11.

The row decoder 113 receives an address signal from the write / erase signal and the address buffer 117 refers to the write from the write / erase control circuit 126 is connected to the memory cell 101 ₁₁ to select on the basis of a row address signal that the word line 103 ₁ giving a negative voltage (e.g., -8 V) from the negative voltage generating circuit 125 maintains the rest of the word lines 103 _2, 103 _3, 103 ₄ all potential to the ground potential.

  In addition, the source / well decoder 114 receiving the write / erase signal indicating writing from the write / erase control circuit 126 and the address signal from the address buffer 117 sets all the source lines 107a and 107b in a floating state. The potentials of well potential lines 108a and 108b connected to all the memory cell substrates are maintained at the ground potential. Here, all the memory cell substrates are the second well regions 304a and 304b shown in FIG.

Further, the select gate decoder 115 receiving the write / erase signal indicating writing from the write / erase control circuit 126 and the address signal from the address buffer 117 receives a part of the row address signal and one of the column address signals. giving a second high potential from the second high voltage generation circuit 124 (e.g., 6V) to a block select signal line 109a to the memory cell 101 ₁₁ corresponding to the block existing selected based on the parts, the remaining block select signals The potential of the line 109b is maintained at the ground potential. As a result, the select gates 106 _1a and 106 _2a connected to the block select signal line 109a become conductive, and the main bit lines 104 ₁ and 104 ₂ and the sub bit lines 105 _1a and 105 _2a are electrically connected, The potentials of the main bit lines 104 ₁ and 104 ₂ are transmitted to the sub bit lines 105 _1a and 105 _2a . The select gates 106 _1b and 106 _2b connected to the block select signal line 109b maintain a non-conductive state, and the main bit lines 104 ₁ and 104 ₂ and the sub bit lines 105 _1b and 105 _2b are not electrically connected. In this state, the sub bit lines 105 _1b and 105 _2b are in an electrically floating state (floating).

Furthermore, the column decoder which receives the address signal from the write / erase signal and the address buffer 117 refers to the write from the write / erase control circuit 126, the memory cell 101 ₁₁ selected based on the column address signal A second high potential (for example, 6V) from the second high voltage generation circuit 124 is applied to the column select signal line 112 ₁ connected to the transfer gate 111 ₁ connected to the main bit line 104 ₁ arranged in the arranged column. ) gives, to maintain the potential of the rest of the column select signal line 112 ₂ to the ground potential. As a result, the transfer gate 111 ₁ connected to the column select signal line 112 ₁ becomes conductive, the input / output line 110 and the main bit lines 104 ₁ and 104 ₂ become electrically connected, and the main bit line 104 ₁ The potential of the input / output line 110 is transmitted to. Further, the transfer gate 111 ₂ connected to the column select signal line 112 ₂ maintains a non-conductive state, and is electrically connected to the input / output line 110 and the main bit line 104 _2, and the main bit line 104 ₂ is electrically connected. It is in a floating state (floating).

  The write circuit 119 that has received a write / erase signal indicating writing from the write / erase control circuit 126 performs basic processing based on information input from the input / output pad 121 via the data input / output buffer 120. A second high potential (for example, 6 V) from second high voltage generation circuit 124 is applied to input / output line 110.

  The sense amplifier 122 that has received a write / erase signal indicating writing from the write / erase control circuit 126 is in an inactive state.

Accordingly, the memory cell 101 ₁₁ to be selected, the control gate electrode a negative potential (e.g. -8 V), the source region is floated, the drain region is the second high potential (for example 6V), the substrate (a second well Since the region 304a) is set to the ground potential, a high electric field is applied between the drain region and the control gate electrode, so that the electrons accumulated in the floating gate electrode are located immediately below the floating gate electrode. The drain electrode is extracted by a tunnel phenomenon through the gate oxide film.

Further, the word lines 103 ₁ non-selected memory cell 101 ₁₂ connected to the the control gate electrode a negative potential (e.g. -8 V), the source region is floated, the drain region into the floating substrate (in FIG. 61 Since the second well region 304a) is at the ground potential, no high electric field is generated between the control gate electrode and the source region, drain region, and channel region, and electrons accumulated in the floating gate electrode are extracted. In addition, no electrons are injected into the floating gate electrode.

Further, the control gate electrode is a ground potential in the memory cell 101 _21, 101 ₂₂ unselected connected to the word line 103 _2, the source region is floated, the drain region into the floating substrate (the second 61 Since the well region 304a) is at the ground potential, a high electric field is not generated between the control gate electrode and the source region, drain region, and channel region, and electrons accumulated in the floating gate electrode are not extracted. In addition, no electrons are injected into the floating gate electrode.

Furthermore, in the non-selected memory cells 101 ₃₁ , 101 ₃₂ , 101 ₄₁ , 101 ₄₂ connected to the word lines 103 ₃ , 103 ₄ , the control gate electrode is at the ground potential, the source region is floating, and the drain region is Since the substrate (the second well region 304a in FIG. 61) is set to the ground potential in a floating state, a high electric field is not generated between the control gate electrode and the source region, the drain region, and the channel region. The electrons stored in the substrate are not extracted, and the electrons are not injected into the floating gate electrode.

In this way, only for one memory cell 101 _11, which is selected based on the row address signal and column address signal input from the outside, withdrawing the electrons accumulated in the floating gate electrode on the drain electrode side It can be written.

(Read operation)
Reading the information stored on the memory cell 101 ₁₁ block 102a, the memory cell 101 _31, 101 _32, 101 _41, 101 ₄₂ of the other memory cells 101 _12, 101 _21, 101 ₂₂ and other blocks 102b The stored information is not read out.

  When a signal for instructing reading from the outside is input to the write / erase control circuit 126, the write / erase control circuit 126 sends a write / erase signal meaning reading to the row decoder 113 and the source / well decoder 114. And select gate decoder 115, column decoder 116, write circuit 119, sense amplifier 122, first and second high voltage generation circuits 123 and 124, and negative voltage generation circuit 125, so that these circuits can be read. Eggplant.

On the other hand, an address signal is input to the address buffer circuit 117 via the address input pad 118. In this case, the address signal is a row address signal and column address signal input to the time series, which means that selects the memory cell 101 _11.

The row decoder 113 receives an address signal from the write / erase signal and the address buffer 117 refers to the read from the write / erase control circuit 126 is connected to the memory cell 101 ₁₁ to select on the basis of a row address signal the word line 103 ₁ giving power source potential (e.g. 3.3V), maintaining the rest of the word lines 103 _2, 103 _3, 103 ₄ all potential to the ground potential.

  The source / well decoder 114 that has received a write / erase signal indicating reading from the write / erase control circuit 126 and an address signal from the address buffer 117 receives all the source lines 107a and 107b and all the memory cells. The potentials of the well potential lines 108a and 108b connected to the substrate are maintained at the ground potential. Here, all the memory cell substrates are the second well regions 304a and 304b shown in FIG.

Further, the select gate decoder 115 receiving the write / erase signal indicating reading from the write / erase control circuit 126 and the address signal from the address buffer 117 outputs a part of the row address signal and a part of the column address. based on, given the power potential (eg, 3.3V) to a block select signal line 109a corresponding to the block in which the memory cell 101 ₁₁ to select present, to maintain the potential of the rest of the block select signal line 109b to a ground potential. As a result, the select gates 106 _1a and 106 _2a connected to the block select signal line 109a become conductive, and the main bit lines 104 ₁ and 104 ₂ and the sub bit lines 105 _1a and 105 _2a are electrically connected. . The select gates 106 _1b and 106 _2b connected to the block select signal line 109b maintain a non-conductive state, and the main bit lines 104 ₁ and 104 ₂ and the sub bit lines 105 _1b and 105 _2b are not electrically connected. In this state, the sub bit lines 105 _1b and 105 _2b are in an electrically floating state (floating).

Furthermore, the write / column decoder which receives the address signal from the write / erase signal and the address buffer 117 refers to the read from the erase control circuit 126, the memory cell 101 ₁₁ selected based on the column address signal is located A power supply potential is applied to the column select signal line 112 ₁ connected to the transfer gate 111 ₁ connected to the main bit line 104 ₁ arranged in the selected column, and the potential of the remaining column select signal line 112 ₂ is set to the ground potential. maintain. As a result, the transfer gate 111 ₁ connected to the column select signal line 112 ₁ becomes conductive, and the input / output line 110 and the main bit lines 104 ₁ and 104 ₂ are electrically connected. Further, the transfer gate 111 ₂ connected to the column select signal line 112 ₂ is kept in a non-conductive state, the input / output line 110 and the main bit line 104 ₂ are electrically disconnected, and the main bit line 104 ₂ It is in an electrically floating state (floating).

  Further, the write circuit 119 that has received a write / erase signal that means reading from the write / erase control circuit 126 does not affect the input / output line 110 because its output is brought into a high impedance state. .

  The sense amplifier 122 that has received a write / erase signal that means reading from the write / erase control circuit 126 is activated, applies a low potential (eg, 1.2 V) to the input / output line 110, and the input / output line 110. Is detected, and the detected information is amplified and output to the input / output pad via the data input / output buffer 120 as read information.

Therefore, when the memory cell 101 ₁₁ to select is being written information, because the threshold voltage of the memory cell 101 ₁₁ is low, by the given power supply potential to the word line 103 _1, memory cell 101 ₁₁ is in a conducting state. Here, a case where electrons accumulated in the floating gate electrode is drawn from the case where the memory cell 101 ₁₁ to select is written information. Therefore, when a low potential is applied to the input / output line 110 from the sense amplifier 122, the source line 107a through the transfer gate 111 ₁ , the main bit line 104 ₁ , the select gate 106 _1a , the sub bit line 105 _1a and the memory cell 101 ₁₁ The sense amplifier 122 senses this and outputs it to the data input / output buffer 120 as read information “1”.

On the other hand, if the information in the memory cell 101 ₁₁ to select is not written, because the threshold voltage of the memory cell 101 ₁₁ is high, even given the power supply potential to the word line 103 _1, memory cell 101 ₁₁ remains non-conductive. Here, the case where information in the memory cell 101 ₁₁ to select is not written a case where electrons in the floating gate electrode are accumulated. Therefore, even when a low potential is applied from the sense amplifier 122 to the input / output line 110, a current does not flow through the source line 107a. Therefore, no current flows, and the sense amplifier 122 senses the read information “ 0 ”is output to the data input / output buffer 120.

At this time, since all the remaining word lines 3 _{2-3 4} memory cell 101 ₁₁ to select is not connected is a ground potential, word lines ₁₀₃₂ 103 ₄ to the memory cells connected to 101 ₂₁ ~ Since all of the 101 ₄₂ are maintained in the non-conductive state regardless of the stored information, there is no path for current to flow through these memory cells 101 _{21 to} 101 ₄₂ . The remaining memory cells 101 ₁₂ connected to the word line 103 ₁ to which the memory cell 101 _{11 to} be selected is connected become conductive or non-conductive depending on the stored information. However, these memory cells 101 ₁₂ because There have the main bit line 104 ₂ is connected is electrically disconnected from the output line 110 by the transfer gate 111 _2, no current flows pathway occurs through the memory cells 101 ₁₂ .

In this way, only for one memory cell 101 _11, which is selected based on the row address signal and column address signal input from the outside, sense amplifier 122 whether or not a current flows on the basis of the stored information because but detectable, but which can be read the information stored in the memory cell 101 _11.

  As described above, in the DINOR type flash memory, when erasing a plurality of memory cells in a block unit, the back gate (Vbb) voltage is applied to the well region where the memory cells are formed. In order to electrically insulate the well region from the semiconductor substrate, it is necessary to adopt a triple well structure in which the well region is provided so as to further surround the well region. The triple well structure here is the relationship between 303 and 304a or the relationship between 303 and 304b in FIG.

  In order to form this triple well structure, a method currently used is to form a well by high-energy ion implantation. Using this technique has the advantage that the well depth, well concentration, and well injection range can be easily controlled. Further, as described above, a high voltage is required for the operation of a nonvolatile semiconductor memory device such as a flash memory. Therefore, a circuit that operates at a high voltage is provided in the peripheral circuit. Such a circuit operating at a high voltage is referred to as a “high voltage peripheral circuit” in this specification. In the flash memory, the high voltage peripheral circuit is mainly used when a high voltage is applied to the memory cell such as a write or erase operation.

  On the other hand, the peripheral circuit is also provided with a circuit that operates at a normal low voltage (for example, a voltage of about 5 V). This peripheral circuit operating at a low voltage is referred to as a “low voltage peripheral circuit”. As described above, there are two types of peripheral circuits, a high voltage peripheral circuit and a low voltage peripheral circuit.

  Conventionally, an LDD (Lightly Doped Drain) type transistor as shown in FIG. 60 has generally been used as a basic element of a peripheral circuit. FIG. 60 shows an example of an LDD transistor that has been conventionally used as a basic element of a peripheral circuit. Referring to FIG. 60, n-type low-concentration impurity regions 206a and 207a are formed on the main surface of p-type semiconductor substrate 201 at a predetermined interval so as to define channel region 205. A gate electrode 204 is formed on the channel region 205 with a gate insulating film 202 interposed therebetween. Further, the main surface of the p-type semiconductor substrate 201 has an end portion at a position farther from the gate electrode 204 than the end portions of the n-type low-concentration impurity regions 206a and 207a, and in a direction away from the gate electrode 204. Extending n-type high concentration impurity regions 206b and 207b are formed.

  An n-type drain region 206 is formed from the n-type high-concentration impurity region 206b and the n-type low-concentration impurity region 206a. An n-type source region 207 is formed from the n-type low concentration impurity region 207a and the n-type high concentration impurity region 207b. An interlayer insulating film 209 is formed on the p-type semiconductor substrate 201, and a contact hole is provided in a portion of the interlayer insulating film 209 located on the n-type drain region 206. A wiring layer 211 is formed from the inner surface of the contact hole to the interlayer insulating film 209.

  As described above, an attempt has been made to secure a high breakdown voltage by using an LDD transistor as a basic element of a peripheral circuit. However, with the recent miniaturization of elements, a high breakdown voltage is ensured even if an LDD transistor is used. It has become difficult. Here, the breakdown voltage of the transistor will be described.

The breakdown voltage of a transistor is generally called an off-breakdown voltage and what is called an on-breakdown voltage. The off breakdown voltage is the source and drain breakdown voltage (BV _DS0 ) when the voltage applied to the gate electrode is 0 V, and the on breakdown voltage is the source when the voltage applied to the gate electrode is changed, This is the minimum value of the breakdown voltage between drains (BV _DS ). In a normal transistor, since BV _DS ≧ BV _DS0 , the operating voltage (between source and drain) V _DS of the transistor must satisfy at least the following condition.

V _DS > BV _DS
By the way, the breakdown voltage between the source and drain during the operation of the transistor is E. Sun, J. Moll, J. Berger, and B. Alders, “Breakdown Mechanism in Short-Channel MOSTransistors,” IEEE Tech Dig, Int. Electron Device Meet. , Washington DC 1978, p.478. This is a kind of parasitic bipolar effect, as analyzed by its mechanism. FIG. 62 is an explanatory diagram for explaining the parasitic bipolar effect. In the short channel MOSFET, when the drain voltage is increased, the electric field in the channel direction is remarkably increased near the drain, and avalanche breakdown occurs. As a result, a large number of electron-hole pairs are generated.

Of the generated carriers, holes flow to the p-type silicon substrate 401 side as shown in FIG. 62 and become a substrate current (I _sub ), and some of them flow into the n-type source region 403. By the hole current flowing into the n-type source region 403, the voltage in the vicinity of the n-type source region 403 is pushed down, and when it becomes higher than the built-in potential of the pn junction between the source region and the substrate, the forward direction of the pn junction between the source region and the substrate Current begins to flow.

  That is, electrons flow from the n-type source region 403 into the p-type silicon substrate 401. As a result, parasitic bipolar transistor operation consisting of source-substrate-drain occurs. This is a breakdown voltage drop phenomenon of the MOS transistor. In FIG. 62, a gate electrode 305 is formed on the channel region with a gate insulating film 404 interposed therebetween. A source region 303 and a drain region 302 are formed so as to define a channel region.

The following formula can be given as a cause of the above-mentioned pressure drop.
I _H × R _sub > V _build-in
In the above equation, I _H represents the current flowing into the source region, and R _sub represents the resistance along the path through which the hole current flows between the substrate and the source region. V _build-in indicates the built-in potential of the pn junction between the source region and the substrate.

From the above description, it can be said that it is important to reduce the hole current generated by the avalanche breakdown in order to improve the breakdown voltage of the transistor. The substrate current (I _sub ) comprising the majority of the generated Hall current is a direct barometer of the avalanche breakdown phenomenon. It is also an important parameter used to predict hot carrier degradation. This substrate current strongly depends on the maximum electric field strength in the channel direction near the drain region, and is generally expressed by the following equation.

I _sub ∝Id ・ Em ^{n + 1}
In the above equation, Id represents the drain current, and Em represents the maximum electric field strength in the channel direction. Further, n≈7. Therefore, from the above equation, it can be said that the maximum electric field strength Em needs to be reduced in order to reduce the substrate current (hole current).

  One method for reducing the maximum electric field intensity Em is to increase the width of the low-concentration impurity region in the LDD transistor. As a result, the depletion layer can be extended sufficiently even in the low-concentration impurity region, and the electric field strength in that portion can be reduced. FIG. 63A is a diagram showing the relationship between the low-concentration impurity region width and the electric field strength depending on the position in the channel direction, which is disclosed in Koyanagi, Kaneko, Shimizu, Proceedings of the Japan Society of Applied Physics (Autumn 1983).

In FIG. 63A, L _SW indicates the width of the low concentration impurity region in the channel length direction. As shown in FIG. 63A, it can be seen that by increasing the low-concentration impurity region width, the maximum value of the channel horizontal electric field ε _Y is reduced in this case. That is, the maximum electric field strength is reduced. Note that FIG. 63B shows the relationship between the breakdown voltage between the source and drain of the transistor and the concentration (/ cm ³ ) of the drain region. Generally, when the concentration of the drain region is lowered, the distance between the source and drain is reduced. It can be seen that the breakdown voltage of the region is improved.

As described above, in order to improve the breakdown voltage BV _DS of the transistor, it is necessary to suppress the parasitic bipolar effect that determines the breakdown voltage. For this purpose, the hole current must be reduced. For that purpose, it is necessary to keep the maximum electric field strength Em small. As one method for that purpose, it can be said that it is effective to reduce the concentration of the low concentration impurity region of the LDD transistor.

  Further, as shown in FIG. 63B, it can be seen that the breakdown voltage can be controlled by controlling the concentration of the low concentration impurity region.

  As another method for suppressing the maximum electric field strength Em, it is effective to increase the gate oxide film thickness.

  However, as described above, when the concentration of the low-concentration impurity region in the vicinity of the drain region is uniformly reduced and the gate oxide film thickness is increased so that the source-drain breakdown voltage can be sufficiently secured in the peripheral circuit, Such a problem will occur.

  FIG. 63C is a diagram showing the relationship between the drain current Id (mA) and the impurity concentration in the low-concentration impurity region. Since the resistance of the low concentration impurity region is relatively high, reducing the concentration of the low concentration impurity region increases the resistance value of that portion. Accordingly, as shown in FIG. 63C, the drain current is reduced by reducing the concentration of the low-concentration impurity region.

  FIG. 63D is a diagram showing the relationship between the drain current Id (mA) and the gate oxide film thickness (Å). When the gate oxide film is thickened, the channel direction electric field is relaxed, so that the drain current also decreases as shown in FIG.

  That is, the operation speed is reduced. As a result, there arises a problem that the driving capability of the transistor is deteriorated. This problem greatly affects the reading time. That is, reducing the concentration of the low-concentration impurity region in the vicinity of the drain region or increasing the gate oxide film thickness uniformly in the low-voltage peripheral circuit and the high-voltage peripheral circuit results in degradation of performance such as read speed. End up. On the other hand, it can be said that the writing operation and the erasing operation do not depend so much on the driving ability of the transistors used in the peripheral circuits because most of the time required for the injection or extraction of electrons occupies.

  The present invention has been made to solve the above-described problems, and one object of the present invention is to drive the transistors in the low voltage peripheral circuit without impairing the high breakdown voltage of the transistors in the high voltage peripheral circuit. It is an object of the present invention to provide a semiconductor memory device capable of ensuring the capability.

  Another object of the present invention is to provide a semiconductor memory device capable of securing a higher breakdown voltage by forming a high voltage peripheral circuit transistor using a triple well.

  Another object of the present invention is to provide a semiconductor memory device in which the breakdown voltage can be easily controlled by forming a high voltage peripheral circuit transistor using an injection well.

  Another object of the present invention is to provide a semiconductor memory device capable of avoiding a significant decrease in current driving capability accompanying an increase in breakdown voltage of a transistor in a high voltage peripheral circuit without impairing an increase in breakdown voltage of the transistor in the high voltage peripheral circuit. Is to provide.

  Another object of the present invention is to provide a semiconductor capable of increasing the breakdown voltage of a transistor in a high-voltage peripheral circuit and improving the driving capability of the transistor in a low-voltage peripheral circuit without adding an extra step to the conventional manufacturing process. A method for manufacturing a storage device is provided.

  The semiconductor memory device has a memory cell array for storing information and a peripheral circuit region for controlling the operation of the memory cell array, and the peripheral circuit region has first and second voltages to which a relatively high voltage is applied. A semiconductor memory device including a high voltage peripheral circuit and a low voltage peripheral circuit to which a relatively low voltage is applied, wherein the first high voltage peripheral circuit includes a first conductivity type semiconductor substrate and a semiconductor substrate. A first semiconductor well region of a second conductivity type formed by being embedded, and a second conductivity type second region formed on and in contact with the first semiconductor well region and spaced apart from each other A third semiconductor well region is formed on and in contact with the first semiconductor well region, and is formed adjacent to each other between the second and third semiconductor well regions, and further spaced apart from each other. 4th and 5th half of the first conductivity type A body well region, a sixth semiconductor well region of the second conductivity type formed adjacent to and between the fourth and fifth semiconductor well regions and in contact with the first semiconductor well region; , A first gate electrode formed on the fourth, fifth and sixth semiconductor well regions with a gate insulating film interposed therebetween, on both sides of the first gate electrode, A pair of high-concentration impurity regions of the first conductivity type formed in the semiconductor well region and having an impurity concentration higher than that of the fourth and fifth semiconductor well regions, and the second high-voltage peripheral circuit includes: A first conductive type semiconductor substrate; second conductive type seventh and eighth semiconductor well regions formed at a distance from each other in the semiconductor substrate; seventh and eighth semiconductor well regions; and a semiconductor substrate. Formed with a gate insulating film interposed between the second region and the second region. A pair of gate electrodes formed on the opposite sides of the gate electrode and the second gate electrode, respectively, in the seventh and eighth semiconductor well regions, and having a higher impurity concentration than the seventh and eighth semiconductor well regions. And a high concentration impurity region of the second conductivity type.

  A method for manufacturing a semiconductor memory device includes a memory cell array for storing information, and a peripheral circuit region for controlling the operation of the memory cell array. The peripheral circuit region has first and second voltages to which a relatively high voltage is applied. A method of manufacturing a semiconductor memory device including a second high-voltage peripheral circuit and a low-voltage peripheral circuit to which a relatively low voltage is applied, the first conductivity including a formation region of the first high-voltage peripheral circuit A step of forming a first semiconductor well region in the semiconductor substrate by implanting impurity ions of a second conductivity type into the semiconductor substrate of a type at a first implantation depth, and shallower than the first implantation depth. Step of forming second and third semiconductor well regions spaced apart from each other so as to be in contact with the first semiconductor well region by implanting impurity ions of the second conductivity type at the second implantation depth And at the second implantation depth Forming a fourth and fifth semiconductor well regions spaced apart from each other between the second and third semiconductor well regions by implanting impurity ions of one conductivity type; Implanting second conductivity type impurity ions at an implantation depth of 2 to form a sixth semiconductor well region adjacently between the fourth and fifth semiconductor well regions; Forming a first gate electrode with a gate insulating film interposed between the fifth and sixth semiconductor well regions, and a first conductivity type impurity ion at a third implantation depth shallower than the second implantation depth. Forming a pair of first-conductivity type high-concentration impurity regions having an impurity concentration higher than that of the fourth and fifth semiconductor wells on both sides of the first gate electrode, Forming a third semiconductor well region and 7th and 8th semiconductor wells are implanted into the semiconductor substrate by implanting the second conductivity type impurity ions at the second implantation depth into the first conductivity type semiconductor substrate including the high voltage peripheral circuit formation region. Forming a region at a distance from each other; forming a first gate electrode; and forming a second gate by interposing a gate insulating film on the seventh and eighth semiconductor well regions and the semiconductor substrate region A step of forming an electrode, and impurity ions of the second conductivity type at a third implantation depth shallower than the second implantation depth in each of the first and second semiconductor well regions on both sides of the second gate electrode. Forming a pair of high-concentration impurity regions of the second conductivity type having an impurity concentration higher than that of the seventh and eighth semiconductor well regions by implantation.

(Embodiment 1)
An embodiment of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below with reference to FIGS.

  FIG. 1A is a cross-sectional view of the semiconductor memory device according to the first embodiment of the present invention. In the drawing, the left side 51-54 shows the peripheral circuit region, and the right side 55 shows the memory cell region.

  The structure of the high voltage transistors 45 and 46 in the present invention shown in FIG.

  In the pMOS high voltage transistor 45, a bottom n well 8, an n well 11 and a p well 16 are formed on a silicon substrate 1. The p-well 16 is on the bottom n-well 8, and the p-well 16 serves as a source / drain and defines a channel region. The n well 11 is also formed on the bottom n well 8 and adjacent to the p well 16.

  In the nMOS high voltage transistor 46, the source / drain 12 is formed in the n well on the main surface of the silicon substrate 1 to define the channel region.

In any of the high voltage transistors 45 and 46, the gate electrode 24 is formed on the channel region via the silicon oxide film 21. Here, the concentration of the n well and the p well is desirably about 10 ¹³ / cm ² . The well implanted as the source / drain of the high voltage transistor in the present invention always has its gate side end positioned below the gate electrode 24.

  A side wall insulating film 29 is formed on the side wall of the gate electrode 24. A high concentration impurity region having an end portion is formed at a position separated from the end of the gate electrode 24 by the width of the sidewall insulating film 29. A silicon oxide film 36, a silicon nitride film 35, and a smooth coat film 34 are formed on the gate electrode 24, respectively. A contact hole 37 is formed in these layers, and an aluminum wiring 40 is formed in a predetermined shape from the inner surface of the contact hole to the smooth coat film 34. A smooth coat film 41 is further formed on the aluminum wiring film 40 and the smooth coat film 34. The smooth coat film 41 is also provided with a contact hole 42 at a predetermined position, and an aluminum wiring layer 43 is formed from the inner surface of the contact hole 42 over the smooth coat film 41.

  1B and 1C are plan views of the pMOS high voltage transistor 45 and the nMOS high voltage transistor 46. FIG.

  An embodiment of a method for manufacturing a semiconductor memory device according to the present invention will be described with reference to FIGS.

  As shown in FIG. 2, a silicon oxide film 2 is formed on the main surface of a p-type <100> silicon substrate 1. Next, a polycrystalline silicon film 3 is formed on the silicon oxide film 2. Further, a silicon nitride film 4 is formed on the polycrystalline silicon film 3 by a low pressure CVD (Chemical Vapor Deposition) method. Then, a resist 5 is formed on the silicon nitride film 4, and the resist 5 in a region where a field oxide film is to be formed is removed by ordinary photolithography. At this time, the region where the field oxide film is to be formed is a region for isolating elements.

  As shown in FIG. 3, the silicon nitride film 4 in the region where the field oxide film is to be formed is removed, and a field oxide film 6 is formed using the silicon nitride film 4 as a mask. Then, the silicon nitride film 4 and the polycrystalline silicon film 3 are removed. Resist 7 is formed on the entire main surface of silicon substrate 1 and only the memory cell region 55 and the pMOS high voltage transistor region 51 are removed.

  As shown in FIG. 4, phosphorus is ion-implanted to form a bottom n-well 8. Then, the resist 7 is removed. A resist 9 is formed on the entire main surface of the silicon substrate 1, and in the pMOS low voltage transistor region 53 and the pMOS high voltage transistor region 51, a region other than the source / drain region, a source / drain region of the nMOS high voltage peripheral transistor region 52, The resist in the well region of the memory cell region 55 is removed.

  As shown in FIG. 5, phosphorus for n well is ion-implanted using a resist as a mask. Then, the resist 9 is removed. Resist 14 is formed on the entire main surface of silicon substrate 1, and the resist in the nMOS low voltage transistor region 54, the source / drain region of pMOS high voltage peripheral transistor region 51, and the memory cell region 55 in which the memory cells are formed is removed. To do.

  As shown in FIG. 6, boron for the p-well is ion-implanted using the resist as a mask. Then, the resist 14 is removed. A tunnel oxide film layer 56, a floating gate layer 57, and an interlayer insulating film layer 58 are formed on the entire silicon substrate 1. These three layers are subjected to predetermined patterning to leave the tunnel oxide film layer 56, the floating gate layer 57, and the interlayer insulating film layer 58 only in the memory cell region 55. Thereafter, a silicon oxide film 21 is formed on the entire main surface of the silicon substrate 1. A polycrystalline silicon film 22 is formed on the silicon oxide film 21. The polycrystalline silicon film 22 serves as a control gate in the memory cell region 55 and a gate electrode in the peripheral regions 51 to 54. A resist 23 is formed on the polycrystalline silicon film 22, and a predetermined pattern is applied.

  As shown in FIG. 7, in the peripheral circuit regions 51 to 54, the polycrystalline silicon film 22 is removed by etching using the resist 23 as a mask to form a gate electrode. Further, in the memory cell region 55, the polysilicon film 22, the interlayer insulating film layer 58, the floating gate layer 57, and the tunnel oxide film layer 56 are removed by etching using the resist 23 as a mask, and the tunnel oxide film 18, the floating gate 19, and the interlayer insulating film are removed. A film 20 and a control gate 24 are formed. After forming the source / drain of the memory cell, a resist 25 is formed on the entire main surface of the silicon substrate 1. The resist 25 is subjected to predetermined patterning, and only the nMOS low voltage transistor region 54 is removed.

  As shown in FIG. 8, phosphorus is ion-implanted using the resist 25 and the gate electrode 24 as a mask to form an n-type low concentration impurity layer 26. Resist 27 is formed on the entire main surface of silicon substrate 1. The resist 27 is subjected to predetermined patterning, and only the pMOS low voltage transistor region 53 is removed.

  As shown in FIG. 9, boron is ion-implanted using resist 27 and gate electrode 24 as a mask to form p-type low-concentration impurity layer 28. Then, the resist 27 is removed. After the silicon oxide film is formed on the main surface of the silicon substrate 1 by the CVD method, the sidewall insulating film 29 is formed by the oxide film anisotropic etching.

  As shown in FIG. 10, after a resist 30 is formed on the entire main surface of the silicon substrate 1, predetermined patterning is performed, and the resist is removed only in the memory cell region 55, the nMOS low voltage transistor region 54, and the nMOS high voltage transistor region 52. .

  As shown in FIG. 11, arsenic is ion-implanted using the resist 30, the gate electrode 24, and the sidewall insulating film 29 as a mask to form source / drain n-type high concentration impurity regions 31. After the resist 32 is formed on the entire main surface of the silicon substrate 1, predetermined patterning is performed to remove only the pMOS low-voltage peripheral circuit region 53 and the pMOS high-voltage transistor region 51.

  As shown in FIG. 12, boron is ion-implanted into the resist 30 using the gate electrode 24 and the sidewall insulating film 29 as a mask to form a source / drain p-type high concentration impurity region 33. Further, a smooth coat film 34, a silicon nitride film 35, and a silicon oxide film 36 are formed.

  As shown in FIG. 13, a contact hole 37 is formed. A resist 38 is formed on the entire main surface of the silicon substrate 1 and then subjected to predetermined patterning, and only the nMOS low voltage transistor region 54, the nMOS high voltage transistor region 52, and the memory cell region 55 are removed. Then, phosphorus is ion-implanted to make ohmic contact.

  As shown in FIG. 14, after a resist 39 is formed on the entire main surface of the silicon substrate 1, predetermined patterning is performed, and only the pMOS low voltage transistor region 53 and the pMOS high voltage transistor region 51 are removed. Then, boron is ion-implanted to make ohmic contact.

  As shown in FIG. 15, an aluminum wiring film 40 is formed on the smooth coat film 34 by sputtering, and the aluminum wiring film 40, the source and drain regions in the memory cell region 55, and the aluminum wiring film through the contact holes 37. 40 and the source and drain regions of the peripheral transistor regions 51 to 54 are electrically connected. Then, predetermined patterning is performed on the aluminum wiring film 40.

  As shown in FIG. 1, a smooth coat film 41 is formed on the entire main surface of the silicon substrate 1. A through hole 42 is formed in the smooth coat film 41. Then, an aluminum wiring film 43 is formed on the smooth coat film 41. The aluminum wiring film 43 and the aluminum wiring film 40 are electrically connected through a through hole.

Thus, the semiconductor memory device illustrated in FIG. 1A is completed.
In the semiconductor memory device manufactured according to the first embodiment, since the wide low concentration impurity region exists on the drain side, the electric field strength on the drain side can be reduced. Therefore, the channel direction electric field in the vicinity of the drain side can be relaxed, and the withstand voltage of the transistor can be improved. In the high voltage transistor regions 51 and 52, the drain side well is an injection well. Therefore, it is easy to control the concentration and depth. As a result, it is easy to control the breakdown voltage of the transistor. Further, if the wafer process is performed in accordance with Embodiment Mode 1, a high voltage transistor can be manufactured without increasing the number of masks and processes and without reducing the driving capability of the low voltage transistor.

(Embodiment 2)
An embodiment of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below.

  In the manufacturing process of the semiconductor memory device according to the first embodiment, only the manufacturing process different from the first embodiment is shown. In the step of FIG. 5 of the first embodiment, as shown in FIG. 16, a resist is formed on the entire pMOS high voltage transistor region 51, and a p well region is not formed as a source / drain region of the pMOS high voltage transistor. Source / drain regions having the same concentration as the silicon substrate 1 are formed. A pMOS high voltage transistor 61 formed according to this embodiment is shown in FIG. Other manufacturing steps are the same as those in the first embodiment.

  The structure of the pMOS high voltage transistor 61 in the present invention shown in FIG. 17 will be described. In the pMOS high voltage transistor 61, a bottom n well 8 and an n well 11 are formed on a silicon substrate 1. The region of the substrate 1 becomes the source / drain and defines the channel region. The n-well 11 is on the bottom n-well 8. A p-type high concentration impurity region 33 having an end portion is formed at a position separated from the end edge of the gate electrode 24 by the width of the sidewall insulating film 29.

(Embodiment 3)
An embodiment of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below.

  In the manufacturing process of the semiconductor memory device according to the first embodiment, only the manufacturing process different from the first embodiment is shown. In the step of FIG. 4 of the first embodiment, as shown in FIG. 18, the resist 9 is removed so as to sandwich the drain region of the pMOS high voltage transistor region 51, and impurity implantation for forming an n well is performed in this region. . In the step of FIG. 5 of the first embodiment, as shown in FIG. 19, the resist 14 is removed only in the drain region of the pMOS high voltage transistor 51, and impurity implantation for forming a p-well is performed in this region. In the step of FIG. 8 of the first embodiment, as shown in FIG. 20, the resist 27 is also removed from the source region of the pMOS high voltage transistor region 51 to form a low concentration impurity region. A pMOS high voltage transistor 62 formed according to this embodiment is shown in FIG. Other manufacturing steps are the same as those in the first embodiment.

  The structure of the pMOS high voltage transistor 62 in the present invention shown in FIG. 21 will be described. In the pMOS high voltage transistor 62, a bottom n well 8, an n well 10, and a p well 16 are formed on a silicon substrate 1. This p-well 16 is on the bottom n-well 8. The n well 10 is also formed on the bottom n well 8 and adjacent to the p well 16. A p-type high concentration impurity region 33 having an end portion is formed at a position separated from the end edge of the gate electrode 24 by the width of the sidewall insulating film 29. A p-type low concentration impurity region 28 is formed so as to be in contact with one of the high concentration impurity regions and extend toward the gate electrode.

(Embodiment 4)
An embodiment of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below.

  In the manufacturing process of the semiconductor memory device according to the first embodiment, only the manufacturing process different from the first embodiment is shown. In the step of FIG. 4 of the first embodiment, as shown in FIG. 22, the resist 9 is removed so as to sandwich the drain region of the pMOS high voltage transistor region 51, and impurity implantation for forming an n well is performed in this region. Do. In the process of FIG. 5 of the first embodiment, as shown in FIG. 23, the resist 14 in the pMOS high voltage transistor region 51 is not removed, and the impurity concentration in the drain region of the pMOS high voltage transistor region 51 is the same as that of the silicon substrate 1. To be equal. In the step of FIG. 8 of the first embodiment, as shown in FIG. 24, the resist 27 is also removed from the source region of the pMOS high voltage transistor region 51 to form a low concentration impurity region. A pMOS high voltage transistor 63 formed according to this embodiment is shown in FIG. Other manufacturing steps are the same as those in the first embodiment.

  The structure of the pMOS high voltage transistor 63 in the present invention shown in FIG. 25 will be described. In the pMOS high voltage transistor 63, a bottom n well 8 and an n well 10 are formed on a silicon substrate 1. The n-well 10 is on the bottom n-well 8. A p-type high concentration impurity region 33 having an end portion is formed at a position separated from the end of the gate electrode 24 by the width of the sidewall insulating film 29. A p-type low concentration impurity region 28 is formed so as to be in contact with one of the high concentration impurity regions and extend toward the gate electrode.

(Embodiment 5)
An embodiment of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below.

  In the manufacturing process of the semiconductor memory device according to the first embodiment, only the manufacturing process different from the first embodiment is shown. In the step of FIG. 4 of the first embodiment, as shown in FIG. 26, only the drain region of the resist 9 on the nMOS high voltage transistor region 52 is removed, and impurity implantation for forming an n well is performed in this region. In the step of FIG. 7 of the first embodiment, as shown in FIG. 27, the resist 25 is also removed from the source region of the nMOS high voltage transistor region 52 to form a low concentration impurity region.

  An nMOS high voltage transistor 64 formed according to this embodiment is shown in FIG. Other manufacturing steps are the same as those in the first embodiment.

  The structure of the nMOS high voltage transistor 64 in the present invention shown in FIG. 28 will be described. In the nMOS high voltage transistor 64, an n well 12 is formed in the silicon substrate 1. Further, an n-type high concentration impurity region 31 having an end portion at a position separated from the end of the gate electrode 24 by the width of the sidewall insulating film 29 is formed. An n-type low-concentration impurity region 26 is formed so as to be in contact with one of the high-concentration impurity regions and extend toward the gate electrode.

(Embodiment 6)
An embodiment of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below.

  In the manufacturing process of the semiconductor memory device according to the first embodiment, only the manufacturing process different from the first embodiment is shown. In the step of FIG. 4 of the first embodiment, as shown in FIG. 29, the resist 9 is removed only in the drain region of the nMOS high voltage transistor region 52, and impurity implantation for forming an n well is performed in this region. Then, in the step of FIG. 5 of the first embodiment, as shown in FIG. 30, the resist 14 is removed only in the source and channel regions of the nMOS high voltage transistor region 52 and impurity implantation for forming a p-well is performed. In the step of FIG. 7 of the first embodiment, as shown in FIG. 31, the resist 25 is also removed from the source region of the nMOS high voltage transistor region 52 to form a low concentration impurity region. An nMOS high voltage transistor 65 formed according to this embodiment is shown in FIG. Other manufacturing steps are the same as those in the first embodiment.

  Here, the structure of the nMOS high voltage transistor 65 of the present invention shown in FIG. 32 will be described.

  In the nMOS high voltage transistor 65, an n well 12 and a p well 44 are formed in the silicon substrate 1. The n well 12 and the p well 44 are adjacent to each other. A high concentration impurity region 31 having an end portion is formed at a position separated from the end of the gate electrode 24 by the width of the sidewall insulating film 29. An n-type low-concentration impurity region 26 is formed so as to be in contact with one of the n-type high-concentration impurity regions 31 and extend toward the gate electrode.

(Embodiment 7)
An embodiment of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below.

  In the manufacturing process of the semiconductor memory device according to the first embodiment, only the manufacturing process different from the first embodiment is shown. In the step of FIG. 2 of the first embodiment, as shown in FIG. 33, the resist 5 in the gate side end region of the drain of the pMOS high voltage transistor region 51 is also removed to form a field oxide film. A pMOS high voltage transistor 66 formed in accordance with this embodiment is shown in FIG. Other manufacturing steps are the same as those in the first embodiment.

  Here, the structure of the pMOS high voltage transistor 66 of the present invention shown in FIG. 34 will be described. In the pMOS high voltage transistor 66, a bottom n well 8, an n well 11, and a p well 16 are formed on a silicon substrate 1. This p-well 16 is on the bottom n-well 8. The p-well 16 becomes a source / drain region and defines a channel region. The n well 11 is also formed on the bottom n well 8 and adjacent to the p well 16. A p-type high concentration impurity region 33 having an end portion is formed at a position separated from the end of the gate electrode 24 by the width of the sidewall insulating film 29. Further, the thickness of the gate oxide film on the drain side is thicker than the thickness of the central portion of the gate oxide film.

  In the semiconductor memory device manufactured according to the seventh embodiment, since the wide low concentration region exists on the drain side, the electric field strength on the drain side can be reduced. Accordingly, the breakdown voltage of the transistor can be improved. Further, the thickness of the gate oxide film on the drain side is larger than the thickness of the central portion of the gate oxide film. Therefore, the withstand voltage is improved because only the electric field in the channel direction on the drain side is relaxed. The well on the drain side is an injection well. Therefore, since the concentration and depth can be easily controlled, the breakdown voltage can be easily controlled. Further, if the wafer process is performed in accordance with Embodiment 7, a high voltage transistor can be manufactured without increasing the number of masks and processes and without reducing the driving capability of the low voltage transistor.

(Embodiment 8)
An embodiment of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below.

  In the manufacturing process of the semiconductor memory device according to the first embodiment, only the manufacturing process different from the first embodiment is shown. In the step of FIG. 2 of the first embodiment, as shown in FIG. 35, the resist 5 in the gate side end region of the drain of the nMOS high voltage transistor region 52 is removed, and a field oxide film is formed. An nMOS high voltage transistor 67 formed according to this embodiment is shown in FIG. Other manufacturing steps are the same as those in the first embodiment.

  Here, the structure of the nMOS high voltage transistor 67 of the present invention shown in FIG. 36 will be described. In the nMOS high voltage transistor 67, the source / drain 12 is formed in the n well on the main surface of the silicon substrate 1 to define the channel region. Further, an n-type high concentration impurity region 31 having an end portion at a position separated from the end of the gate electrode 24 by the width of the sidewall insulating film 29 is formed. The thickness of the gate oxide film on the drain side is thicker than the thickness of the central portion of the gate oxide film.

(Embodiment 9)
An embodiment of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below.

  In the manufacturing process of the semiconductor memory device according to the first embodiment, only the manufacturing process different from the first embodiment is shown. In the step of FIG. 2 of the first embodiment, as shown in FIG. 37, the resist 5 in the gate side end region of the drain of the pMOS high voltage transistor region 51 is also removed to form a field oxide film. In the step of FIG. 5 of the first embodiment, as shown in FIG. 38, a resist is formed on the entire pMOS high voltage transistor region 51, a p well is not formed as a source / drain region of the pMOS high voltage transistor, and silicon Source / drain regions having the same concentration as the substrate 1 are formed. A pMOS high voltage transistor 68 formed in accordance with this embodiment is shown in FIG. Other manufacturing steps are the same as those in the first embodiment.

  Here, the structure of the pMOS high voltage transistor 68 of the present invention shown in FIG. 39 will be described. In the pMOS high voltage transistor 68, a bottom n well 8 and an n well 11 are formed on a silicon substrate 1. The n-well 11 is on the bottom n-well 8. A p-type high concentration impurity region 33 having an end portion is formed at a position separated from the end of the gate electrode 24 by the width of the sidewall insulating film 29. Further, the thickness of the gate oxide film on the drain side is thicker than the thickness of the central portion of the gate oxide film.

(Embodiment 10)
An embodiment of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below.

  In the manufacturing process of the semiconductor memory device according to the first embodiment, only the manufacturing process different from the first embodiment is shown. In the step of FIG. 2 of the first embodiment, as shown in FIG. 40, the resist 5 in the gate side end region of the drain of the pMOS high voltage transistor region 51 is also removed, and a field oxide film is formed. In the step of FIG. 4 of the first embodiment, as shown in FIG. 41, the resist 9 is removed so as to sandwich the drain region of the pMOS high voltage transistor region 51, and impurity implantation for forming an n well is performed in this region. Do. Then, in the step of FIG. 5 of the first embodiment, as shown in FIG. 42, the resist 14 is removed only in the drain region of the pMOS high voltage transistor, and impurity implantation for forming a p-well is performed in this region. In the step of FIG. 8 of the first embodiment, as shown in FIG. 43, the resist 27 is also removed from the source region of the pMOS high voltage transistor to form a low concentration impurity region. A pMOS high voltage transistor 69 formed according to this embodiment is shown in FIG. Other manufacturing steps are the same as those in the first embodiment.

  Here, the structure of the pMOS high voltage transistor 69 of the present invention shown in FIG. 44 will be described. In the pMOS high voltage transistor 69, a bottom n well 8, an n well 10, and a p well 16 are formed in a silicon substrate 1. This p-well 16 is on the bottom n-well 8. The n well 10 is also formed on the bottom n well 8 and adjacent to the p well 16. A p-type high concentration impurity region 33 having an end portion is formed at a position separated from the end of the gate electrode 24 by the width of the sidewall insulating film 29. A p-type low-concentration impurity region 28 is formed so as to contact one of the p-type high-concentration impurity regions 33 and extend toward the gate electrode. Further, the thickness of the gate oxide film on the drain side is thicker than the thickness of the central portion of the gate oxide film.

(Embodiment 11)
An embodiment of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below.

  In the manufacturing process of the semiconductor memory device according to the first embodiment, only the manufacturing process different from the first embodiment is shown. In the step of FIG. 2 of the first embodiment, as shown in FIG. 45, the resist 5 in the gate side end region of the drain of the pMOS high voltage transistor region 51 is also removed to form a field oxide film. In the step of FIG. 4 of the first embodiment, as shown in FIG. 46, the resist 9 is removed so as to sandwich the drain region of the pMOS high voltage transistor region 51, and impurity implantation for forming an n well is performed in this region. Do. In the step of FIG. 5 of the first embodiment, as shown in FIG. 47, the resist 14 in the pMOS high voltage transistor region 51 is not removed, and the impurity concentration in the drain region of the pMOS high voltage transistor is equal to that of the silicon substrate 1. To be. In the step of FIG. 8 of the first embodiment, as shown in FIG. 48, the resist 27 is also removed from the source region of the pMOS high voltage transistor region 51 to form a low concentration impurity region. A pMOS high voltage transistor 70 formed in accordance with this embodiment is shown in FIG. Other manufacturing steps are the same as those in the first embodiment.

  Here, the structure of the pMOS high voltage transistor 70 of the present invention shown in FIG. 49 will be described. In the pMOS high-voltage transistor 70, a bottom n-well 8 and an n-well 10 are formed on a silicon substrate 1. The n-well 10 is on the bottom n-well 8 and is formed at a distance from each other. A p-type high concentration impurity region 33 having an end portion is formed at a position separated from the end of the gate electrode 24 by the width of the sidewall insulating film 29. A p-type low-concentration impurity region 28 is formed so as to contact one of the p-type high-concentration impurity regions 33 and extend toward the gate electrode. Further, the thickness of the gate oxide film on the drain side is larger than the thickness of the central portion of the gate oxide film.

(Embodiment 12)
An embodiment of a semiconductor memory device and its manufacturing method according to the present invention will be described below.

  In the manufacturing process of the semiconductor memory device according to the first embodiment, only the manufacturing process different from the first embodiment is shown. In the step of FIG. 2 of the first embodiment, as shown in FIG. 50, the resist 5 in the gate side end region of the drain of the nMOS high voltage transistor region 52 is also removed, and a field oxide film is formed. In the step of FIG. 4 of the first embodiment, as shown in FIG. 51, only the drain region of the resist 9 on the nMOS high voltage transistor region 52 is removed, and impurity implantation for forming an n well is performed in this region. In the step of FIG. 7 of the first embodiment, as shown in FIG. 52, the resist 25 is also removed from the source region of the nMOS high voltage transistor region 52 to form a low concentration impurity region. An nMOS high voltage transistor 71 formed according to this embodiment is shown in FIG. Other manufacturing steps are the same as those in the first embodiment.

  Here, the structure of the nMOS high voltage transistor 71 of the present invention shown in FIG. 53 will be described. In the nMOS high voltage transistor 71, an n well 12 is formed in the silicon substrate 1. Further, an n-type high concentration impurity region 31 having an end portion at a position separated from the end of the gate electrode 24 by the width of the sidewall insulating film 29 is formed. An n-type low-concentration impurity region 26 is formed so as to be in contact with one of the n-type high-concentration impurity regions 31 and extend toward the gate electrode. Further, the thickness of the gate oxide film on the drain side is thicker than the thickness of the central portion of the gate oxide film.

(Embodiment 13)
An embodiment of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below.

  In the manufacturing process of the semiconductor memory device according to the first embodiment, only the manufacturing process different from the first embodiment is shown. In the step of FIG. 2 of the first embodiment, as shown in FIG. 54, the resist 5 in the gate side end region of the drain of the nMOS high voltage transistor region 52 is also removed, and a field oxide film is formed. In the step of FIG. 4 of the first embodiment, as shown in FIG. 55, the resist 9 is removed only in the drain region of the nMOS high voltage transistor, and impurity implantation is performed to form an n well in this region. Then, in the step of FIG. 5 of the first embodiment, as shown in FIG. 56, the resist 14 is removed only in the source and channel regions of the nMOS high voltage transistor region, and impurity implantation for forming a p-well is performed. In the step of FIG. 7 of the first embodiment, as shown in FIG. 57, the resist 25 is also removed from the source region of the nMOS high voltage transistor region 52 to form a low concentration impurity region. An nMOS high voltage transistor 72 formed in accordance with this embodiment is shown in FIG. Other manufacturing steps are the same as those in the first embodiment.

  Here, the structure of the nMOS high voltage transistor 72 of the present invention shown in FIG. 58 will be described. In the nMOS high voltage transistor 72, an n well 12 and a p well 44 are formed adjacent to each other on the silicon substrate 1. Further, an n-type high concentration impurity region 31 having an end portion at a position separated from the end of the gate electrode 24 by the width of the sidewall insulating film 29 is formed. An n-type low-concentration impurity region 26 is formed so as to be in contact with one of the n-type high-concentration impurity regions 31 and extend toward the gate electrode.

  The semiconductor memory device includes a semiconductor substrate, first to sixth semiconductor well regions, a pair of high-concentration impurity regions, and a gate electrode. The first semiconductor well region is of the second conductivity type and is formed embedded in the semiconductor substrate. The second and third semiconductor well regions are of the second conductivity type, are formed on and in contact with the first semiconductor well region, and are formed at a distance from each other. The fourth and fifth semiconductor well regions are of the first conductivity type, are formed on and in contact with the first semiconductor well region, and are adjacent to each other between the second and third semiconductor well regions. Formed, and spaced apart from each other. The sixth semiconductor well region is of the second conductivity type and is formed adjacent to and between the fourth and fifth semiconductor well regions and in contact with the first semiconductor well region. The gate electrode is formed on the fourth, fifth and sixth semiconductor well regions with a gate insulating film interposed. The pair of high-concentration impurity regions are of the first conductivity type, are formed on both sides of the gate electrode and in the fourth and fifth semiconductor well regions, respectively, and are more than the fourth and fifth semiconductor well regions. Has a high impurity concentration.

  The semiconductor memory device includes a semiconductor substrate, first and second semiconductor well regions, a gate electrode, and a pair of high-concentration impurity regions. The semiconductor substrate is of the first conductivity type. The first and second semiconductor well regions are of the second conductivity type and are formed at a distance from each other in the semiconductor substrate. The gate electrode is formed on the first and second semiconductor well regions and the semiconductor substrate region with a gate insulating film interposed therebetween. The pair of high-concentration impurity regions are of the second conductivity type, are formed on both sides of the gate insulating film and in the first and second semiconductor well regions, respectively, and more than the first and second semiconductor well regions Has a high impurity concentration.

  The semiconductor memory device includes a semiconductor substrate, first to fourth semiconductor well regions, a gate electrode, and a pair of high-concentration impurity regions. The semiconductor substrate is of the first conductivity type. The first semiconductor well region is of the second conductivity type and is formed embedded in the semiconductor substrate. The second and third semiconductor well regions are of the second conductivity type, are formed on and in contact with the first semiconductor well region, and are formed at a distance from each other. The fourth semiconductor well region is of the second conductivity type, is formed between the second and third semiconductor well regions, and is formed on and in contact with the first semiconductor well region. The gate electrode is formed on the semiconductor substrate region on both sides of the fourth semiconductor well region and the fourth semiconductor well region with a gate insulating film interposed therebetween. The pair of high-concentration impurity regions are of the first conductivity type, are formed in the semiconductor substrate on both sides of the gate electrode, and have a higher impurity concentration than the semiconductor substrate.

  The semiconductor memory device includes a semiconductor substrate, first to fourth semiconductor well regions, a gate electrode, a pair of high concentration impurity regions, and a low concentration impurity region. The semiconductor substrate is of the first conductivity type. The first semiconductor well region is of the second conductivity type and is formed embedded in the semiconductor substrate. The second and third semiconductor well regions are of the second conductivity type, are formed on and in contact with the first semiconductor well region, and are formed at a distance from each other. The fourth semiconductor well region is of the first conductivity type, is formed on and in contact with the first semiconductor well region, and is formed adjacent to between the second and third semiconductor well regions. The gate electrode is formed on the second and fourth semiconductor well regions with a gate insulating film interposed. The pair of high-concentration impurity regions are of the first conductivity type, are formed on both sides of the gate electrode and in the second semiconductor well region, and have a higher impurity concentration than the fourth semiconductor well region. The low-concentration impurity region is of the first conductivity type, is formed so as to contact one of the high-concentration impurity regions formed in the second semiconductor well region and extend toward the gate electrode side, and is higher than the high-concentration impurity region. Has a low impurity concentration.

  The semiconductor memory device includes a semiconductor substrate, first to third semiconductor well regions, a gate electrode, a pair of high concentration impurity regions, and a low concentration impurity region. The semiconductor substrate is of the first conductivity type. The first semiconductor well region is of the second conductivity type and is formed embedded in the semiconductor substrate. The second and third semiconductor well regions are of the second conductivity type, are formed on and in contact with the first semiconductor well region, and are formed at a distance from each other. The gate electrode is formed on a region of the semiconductor substrate between the second and third semiconductor well regions and on the second semiconductor well region with a gate insulating film interposed. The pair of high-concentration impurity regions are of the first conductivity type and are formed on both sides of the gate electrode in the region of the semiconductor substrate between the second and third semiconductor well regions and in the second semiconductor well region, respectively. Is done. The low-concentration impurity region is of the first conductivity type, is formed so as to contact one of the high-concentration impurity regions formed in the second semiconductor well region and extend toward the gate electrode side, and is higher than the high-concentration impurity region. Has a low impurity concentration.

  The semiconductor memory device includes a semiconductor substrate, a semiconductor well region, a gate electrode, a pair of high concentration impurity regions, and a low concentration impurity region. The semiconductor substrate is of the first conductivity type. The semiconductor well region is of the second conductivity type and is formed in the semiconductor substrate. The gate electrode is formed on the semiconductor well region and the adjacent semiconductor substrate region with a gate insulating film interposed. The pair of high-concentration impurity regions are of the second conductivity type, and are formed on both sides of the gate electrode, in the semiconductor substrate and in the semiconductor well region, respectively. The low-concentration impurity region is of the second conductivity type, is formed to contact one of the high-concentration impurity regions formed in the semiconductor substrate and extend to the gate electrode side, and has an impurity concentration lower than that of the high-concentration impurity region. Have.

  The semiconductor memory device includes a semiconductor substrate, first and second semiconductor well regions, a gate electrode, a pair of high concentration impurity regions, and a low concentration impurity region. The semiconductor substrate is of the first conductivity type. The first semiconductor well region is of the second conductivity type and is formed on the semiconductor substrate. The second semiconductor well region is of the first conductivity type, is formed in the semiconductor substrate, and is formed adjacent to the first semiconductor well region. The gate electrode is formed on the first and second semiconductor well regions with a gate insulating film interposed. The pair of high-concentration impurity regions are of the second conductivity type, and are formed in the first and second semiconductor well regions on both sides of the gate electrode, respectively. The low-concentration impurity region is of the second conductivity type, is formed to be in contact with one of the high-concentration impurity regions formed in the second semiconductor well region and extend to the gate electrode side, and more than the high-concentration impurity region Has a low impurity concentration.

  In the semiconductor memory device, the thickness of the end portion on the drain side of the gate insulating film of the semiconductor memory device is larger than the thickness of the central portion of the gate insulating film.

  The semiconductor memory device manufacturing method includes the following steps (a) to (f). (A) Impurity ions of a second conductivity type are implanted at a first implantation depth into a first conductivity type semiconductor substrate including a region for forming a high-voltage peripheral circuit, thereby forming a first semiconductor well region inside the semiconductor substrate. Forming step. (B) Second and third semiconductors are in contact with the first semiconductor well region by implanting second conductivity type impurity ions at a second implantation depth shallower than the first implantation depth. Forming a well region at a distance from each other; (C) Implanting first conductivity type impurity ions at the second implantation depth allows the fourth and fifth semiconductor well regions to be adjacent to each other between the second and third semiconductor well regions. Forming at a distance from each other; (D) A step of forming a sixth semiconductor well region adjacently between the fourth and fifth semiconductor well regions by implanting impurity ions of the second conductivity type at the second implantation depth. (E) forming a gate electrode on the fourth, fifth and sixth semiconductor well regions with a gate insulating film interposed; (F) A pair of impurity ions having a higher impurity concentration than the fourth and fifth semiconductor well regions by implanting the first conductivity type impurity ions at a third implantation depth shallower than the second implantation depth. Forming a first conductivity type high concentration impurity region on both sides of the gate electrode;

  The method for manufacturing a semiconductor memory device includes the following steps (a) to (c). (A) Impurity ions of a second conductivity type are implanted at a first implantation depth into a first conductivity type semiconductor substrate including a region where a high voltage peripheral circuit is formed. Forming the semiconductor well regions at a distance from each other. (B) forming a gate electrode over the first and second semiconductor well regions and the semiconductor substrate region with a gate insulating film interposed; (C) First impurity ions of a second conductivity type are implanted into the first and second semiconductor well regions on both sides of the gate electrode at a second implantation depth shallower than the first implantation depth. Forming a pair of second conductivity type high concentration impurity regions having an impurity concentration higher than that of the second semiconductor well region.

  The method for manufacturing a semiconductor memory device includes the following steps (a) to (e). (A) Impurity ions of a second conductivity type are implanted at a first implantation depth into a first conductivity type semiconductor substrate including a region where a high voltage peripheral circuit is formed, thereby providing a first semiconductor well inside the semiconductor substrate. Forming a region; (B) Second and third semiconductors are in contact with the first semiconductor well region by implanting second conductivity type impurity ions at a second implantation depth shallower than the first implantation depth. Forming a well region at a distance from each other; (C) Implanting impurity ions of the second conductivity type at the second implantation depth so that the fourth semiconductor well region is located above the first semiconductor well region between the second and third semiconductor well regions. Forming so as to be in contact with. (D) A step of forming a gate electrode with a gate insulating film interposed between the fourth semiconductor well region and the regions of the semiconductor substrate on both sides of the fourth semiconductor well region. (E) A pair of first conductivity having a higher impurity concentration than the semiconductor substrate by implanting impurity ions of the first conductivity type into the semiconductor substrate at a third implantation depth shallower than the second implantation depth. Forming a high concentration impurity region of the mold on both sides of the gate electrode;

  The method for manufacturing a semiconductor memory device includes the steps (a) to (f). (A) Impurity ions of a second conductivity type are implanted at a first implantation depth into a first conductivity type semiconductor substrate including a region where a high voltage peripheral circuit is formed, thereby providing a first semiconductor well inside the semiconductor substrate. Forming a region; (B) Second and third semiconductors are in contact with the first semiconductor well region by implanting second conductivity type impurity ions at a second implantation depth shallower than the first implantation depth. Forming a well region at a distance from each other; (C) A step of forming a fourth semiconductor well region adjacently between the second and third semiconductor well regions by implanting impurity ions of the first conductivity type at the second implantation depth. (D) forming a gate electrode on the second and fourth semiconductor well regions with a gate insulating film interposed; (E) Implanting the first conductivity type impurity ions at a third implantation depth shallower than the second implantation depth makes it possible to form a pair of first conductivity type high concentration impurity regions on both sides of the gate electrode. Forming each in the second and fourth semiconductor well regions. (F) a low-conductivity first conductivity type having a lower impurity concentration than the high-concentration impurity region so as to be in contact with one of the high-concentration impurity regions to be formed in the second semiconductor well region and to extend toward the gate electrode; Forming a concentration impurity region;

  The method for manufacturing a semiconductor memory device includes the steps (a) to (e). (A) Impurity ions of a second conductivity type are implanted at a first implantation depth into a first conductivity type semiconductor substrate including a region where a high voltage peripheral circuit is formed, thereby providing a first semiconductor well inside the semiconductor substrate. Forming a region; (B) Second and third semiconductors are in contact with the first semiconductor well region by implanting second conductivity type impurity ions at a second implantation depth shallower than the first implantation depth. Forming a well region at a distance from each other; (C) forming a gate electrode with a gate insulating film interposed between the region of the semiconductor substrate between the second and third semiconductor well regions and the second semiconductor well region; (D) Implanting the first conductivity type impurity ions at a third implantation depth shallower than the second implantation depth allows a pair of first conductivity type high concentration impurity regions to be formed on both sides of the gate electrode and Forming in the region of the semiconductor substrate between the second and third semiconductor well regions and in the second semiconductor well region, respectively. (E) a low concentration of the first conductivity type having an impurity concentration lower than that of the high concentration impurity region so as to be in contact with one of the high concentration impurity regions to be formed in the second semiconductor well region and extend toward the gate electrode side; Forming impurity regions;

  The method for manufacturing a semiconductor memory device includes the steps (a) to (d). (A) Impurity ions of a second conductivity type are implanted at a first implantation depth into a first conductivity type semiconductor substrate including a high voltage peripheral circuit formation region, thereby forming a semiconductor well region in the semiconductor substrate. Process. (B) A step of forming a gate electrode over the semiconductor well region and the region of the semiconductor substrate adjacent thereto by interposing a gate insulating film. (C) Implanting second conductivity type impurity ions at a second implantation depth shallower than the first implantation depth, thereby forming a pair of second conductivity type high concentration impurity regions on both sides of the gate electrode and Forming each of the semiconductor well region and the semiconductor substrate; (D) The second conductivity type low-concentration impurity region extending toward the gate electrode in contact with one of the high-concentration impurity regions formed in the semiconductor substrate and having an impurity concentration lower than that of the high-concentration impurity region. Forming inside.

  The method for manufacturing a semiconductor memory device includes the steps (a) to (e). (A) Impurity ions of a second conductivity type are implanted at a first implantation depth into a first conductivity type semiconductor substrate including a region where a high voltage peripheral circuit is formed, thereby forming a first semiconductor well region in the semiconductor substrate. Forming step. (B) A step of forming a second semiconductor well region adjacent to the first semiconductor well region by implanting first conductivity type impurity ions at a first implantation depth. (C) forming a gate electrode on the first and second semiconductor well regions with a gate insulating film interposed; (D) Implanting the second conductivity type impurity ions at a second implantation depth shallower than the first implantation depth makes it possible to form a pair of second conductivity type high concentration impurity regions on both sides of the gate electrode and Forming each in the first and second semiconductor well regions; (E) a second-conductivity-type low-concentration impurity having an impurity concentration lower than that of the high-concentration impurity region and extending toward the gate electrode while being in contact with one of the high-concentration impurity regions formed in the second semiconductor well region Forming a region;

  The manufacturing method of a semiconductor memory device adds the following steps to the manufacturing method of the semiconductor memory device. Forming an insulating film on a portion of the gate insulating film which is to be the drain side end; In the semiconductor memory device, since a wide low concentration layer exists on the drain side, the electric field strength on the drain side can be reduced. The well on the drain side is an injection well. Therefore, it is easy to control the concentration and depth.

  In the semiconductor memory device, since a wide low concentration layer exists on the drain side, the electric field strength on the drain side can be reduced. Further, when the entire gate oxide film is thickened, the drain current is reduced. However, since the gate oxide film on the drain side is thicker than the central part of the gate oxide film, the electric field strength on the drain side can be reduced without reducing the drain current more than necessary. The well on the drain side is an injection well. Therefore, it is easy to control the concentration and depth.

  The method for manufacturing a semiconductor memory device includes a step of forming a wide low concentration diffusion layer on the drain side. Therefore, the electric field strength on the drain side can be reduced. Further, the source and drain of the high voltage transistor regions 51 and 52 are formed in the same process as the wells of the low voltage transistor regions 53 and 54. Therefore, it is possible to manufacture a high voltage transistor without reducing the driving capability of the low voltage transistor without increasing the number of masks and processes. Also, a step of forming a drain side well by implantation is provided. Therefore, it is easy to control the concentration and depth.

  The method for manufacturing a semiconductor memory device includes a step of forming a wide low concentration diffusion layer on the drain side. Therefore, the electric field strength on the drain side can be reduced. In addition, the method includes a step of increasing the thickness of the gate oxide film on the drain side as compared with the central portion of the gate oxide film. Therefore, the electric field strength on the drain side can be reduced. Further, it is possible to make a high voltage transistor without reducing the driving capability of the low voltage transistor without increasing the number of masks and processes. Also, a step of forming a drain side well by implantation is provided. Therefore, it is easy to control the concentration and depth.

  In the semiconductor memory device, the withstand voltage of the transistor can be improved due to the above-described operation. In addition, the breakdown voltage of the transistor can be easily controlled.

  In the semiconductor memory device, the breakdown voltage of the transistor can be improved due to the above-described action. Also, the breakdown voltage is easy to control.

  In the method for manufacturing a semiconductor memory device, the breakdown voltage of the transistor can be improved due to the above-described operation. In addition, a high voltage transistor can be manufactured without increasing the number of masks and processes and without reducing the driving capability of the low voltage transistor. Also, the breakdown voltage is easy to control.

  In the method for manufacturing a semiconductor memory device, the breakdown voltage of the transistor can be improved due to the above-described operation. A high breakdown voltage transistor can be manufactured without increasing the mask or process of the gate insulating film on the drain side and without lowering the driving capability of the low voltage transistor. Also, the breakdown voltage is easy to control.

(A) is sectional drawing of Embodiment 1 of the semiconductor memory device of this invention, (B) is a top view of the PMOS high voltage transistor area | region 51 in (A), (C) is in (A). 3 is a plan view of an NMOS high voltage transistor region 52. FIG. It is sectional drawing which shows the 1st process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 2nd process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 3rd process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 4th process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 5th process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 6th process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 7th process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 8th process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 9th process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 10th process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 11th process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 12th process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 13th process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 14th process of Embodiment 1 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 4th process of Embodiment 2 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows Embodiment 2 of the semiconductor memory device of this invention. It is sectional drawing which shows the 3rd process of Embodiment 3 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 4th process of Embodiment 3 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 7th process of Embodiment 3 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows Embodiment 3 of the semiconductor memory device of this invention. It is sectional drawing which shows the 3rd process of Embodiment 4 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 4th process of Embodiment 4 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 7th process of Embodiment 4 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows Embodiment 4 of the semiconductor memory device of this invention. It is sectional drawing which shows the 3rd process of Embodiment 5 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 6th process of Embodiment 5 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows Embodiment 5 of the semiconductor memory device of this invention. It is sectional drawing which shows the 3rd process of Embodiment 6 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 4th process of Embodiment 6 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 6th process of Embodiment 6 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows Embodiment 6 of the semiconductor memory device of this invention. It is sectional drawing which shows the 1st process of Embodiment 7 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows Embodiment 7 of the semiconductor memory device of this invention. It is sectional drawing which shows the 1st process of Embodiment 8 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows Embodiment 8 of the semiconductor memory device of this invention. It is sectional drawing which shows the 1st process of Embodiment 9 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 4th process of Embodiment 9 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows Embodiment 9 of the semiconductor memory device of this invention. It is sectional drawing which shows the 1st process of Embodiment 10 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 3rd process of Embodiment 10 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 4th process of Embodiment 10 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 7th process of Embodiment 10 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows Embodiment 10 of the semiconductor memory device of this invention. It is sectional drawing which shows the 1st process of Embodiment 11 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 3rd process of Embodiment 11 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 4th process of Embodiment 11 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 7th process of Embodiment 11 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows Embodiment 11 of the semiconductor memory device of this invention. It is sectional drawing which shows the 1st process of Embodiment 12 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 3rd process of Embodiment 12 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 6th process of Embodiment 12 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows Embodiment 12 of the semiconductor memory device of this invention. It is sectional drawing which shows the 1st process of Embodiment 13 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 3rd process of Embodiment 13 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 4th process of Embodiment 13 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows the 6th process of Embodiment 13 of the manufacturing method of the semiconductor memory device of this invention. It is sectional drawing which shows Embodiment 13 of the semiconductor memory device of this invention. It is a block diagram of a conventional DINOR type flash memory. It is sectional drawing which shows the LDD type transistor formed in the peripheral circuit area | region of the conventional semiconductor memory device. It is sectional drawing of the conventional DINOR type | mold flash memory. It is sectional drawing of the transistor for demonstrating a parasitic bipolar effect. (A) is a figure which shows the relationship between the position of the channel direction of a transistor, and the electric field strength of a channel horizontal direction, (B) is the drain region density | concentration (/ cm < ³ >) of a transistor, and source-drain breakdown voltage (V). (C) is a diagram showing the relationship between the low concentration impurity region (μm) of the LDD transistor and the drain current (mA), and (D) is the gate oxide film of the transistor It is a figure which shows the relationship between thickness (Å) and drain current (mA).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Silicon substrate, 6 field oxide film, 8 bottom n well, 10-13 n well, 15-17, 44 p well, 21 silicon oxide film, 24 gate electrode, 26 n-type low concentration impurity region, 28 p type low concentration Impurity region, 29 sidewall insulating film, 31 n-type high concentration impurity region, 33 p type high concentration impurity region, 45, 61, 62, 63, 66, 68, 69, 70 pMOS high voltage transistor, 46, 64, 65 67, 71, 72 nMOS high voltage transistor, 47 pMOS low voltage transistor, 48 nMOS low voltage transistor, 49 memory cell, 51 pMOS high voltage transistor region, 52 nMOS high voltage transistor region, 53 pMOS low voltage transistor region, 54 nMOS Low voltage transistor area, 55 memory Le area.

Claims (2)

A memory cell array for storing information; and a peripheral circuit region for controlling an operation of the memory cell array, wherein the peripheral circuit region includes first and second high-voltage peripherals to which a relatively high voltage is applied. A semiconductor memory device including a circuit and a low-voltage peripheral circuit to which a relatively low voltage is applied,
The first high voltage peripheral circuit is:
A first conductivity type semiconductor substrate;
A first semiconductor well region of a second conductivity type embedded in the semiconductor substrate;
A second conductivity type second and third semiconductor well region formed on and in contact with the first semiconductor well region;
A first conductivity type formed on and in contact with the first semiconductor well region and adjacent to each other between the second and third semiconductor well regions and further spaced apart from each other. The fourth and fifth semiconductor well regions of
A sixth semiconductor well region of a second conductivity type formed adjacent to and between the fourth and fifth semiconductor well regions and in contact with the first semiconductor well region;
A first gate electrode formed on the fourth, fifth and sixth semiconductor well regions with a gate insulating film interposed therebetween;
A pair of first electrodes on both sides of the first gate electrode and formed in the fourth and fifth semiconductor well regions, respectively, and having a higher impurity concentration than the fourth and fifth semiconductor well regions. A high conductivity impurity region of one conductivity type,
The second high voltage peripheral circuit is:
A semiconductor substrate of the first conductivity type;
A second conductivity type seventh and eighth semiconductor well regions formed at a distance from each other in the semiconductor substrate;
A second gate electrode formed by interposing a gate insulating film on the seventh and eighth semiconductor well regions and the region of the semiconductor substrate;
A pair of first electrodes on both sides of the second gate electrode and formed in the seventh and eighth semiconductor well regions, respectively, and having a higher impurity concentration than the seventh and eighth semiconductor well regions. A semiconductor memory device comprising a two-conductivity type high concentration impurity region. A memory cell array for storing information; and a peripheral circuit region for controlling an operation of the memory cell array, wherein the peripheral circuit region includes first and second high-voltage peripherals to which a relatively high voltage is applied. A method of manufacturing a semiconductor memory device including a circuit and a low voltage peripheral circuit to which a relatively low voltage is applied,
By implanting second conductivity type impurity ions at a first implantation depth into the first conductivity type semiconductor substrate including the region where the first high-voltage peripheral circuit is formed, the first conductivity type is introduced into the semiconductor substrate. Forming a semiconductor well region;
Second and third semiconductor wells are in contact with the first semiconductor well region by implanting second conductivity type impurity ions at a second implantation depth shallower than the first implantation depth. Forming regions at a distance from each other;
By implanting impurity ions of the first conductivity type at the second implantation depth, the fourth and fifth semiconductor well regions are adjacent to each other between the second and third semiconductor well regions, respectively. Forming at a distance;
Forming a sixth semiconductor well region adjacently between the fourth and fifth semiconductor well regions by implanting second conductivity type impurity ions at the second implantation depth;
Forming a first gate electrode with a gate insulating film interposed on the fourth, fifth and sixth semiconductor well regions;
By implanting impurity ions of the first conductivity type at a third implantation depth shallower than the second implantation depth, a pair of first electrodes having an impurity concentration higher than that of the fourth and fifth semiconductor wells. Forming a conductive type high concentration impurity region on both sides of the first gate electrode;
The second and third semiconductor well regions are formed, and the second conductivity type impurity is implanted into the first conductivity type semiconductor substrate including the second high voltage peripheral circuit formation region at a second implantation depth. Forming seventh and eighth semiconductor well regions at a distance from each other in the semiconductor substrate by implanting ions;
Forming a first gate electrode and forming a second gate electrode with a gate insulating film interposed between the seventh and eighth semiconductor well regions and the semiconductor substrate region;
Implanting impurity ions of the second conductivity type at a third implantation depth shallower than the second implantation depth into each of the first and second semiconductor well regions on both sides of the second gate electrode. And a step of forming a pair of second-conductivity type high-concentration impurity regions having a higher impurity concentration than the seventh and eighth semiconductor well regions.

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